tlb.cc revision 7606
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 506019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 516019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 526019Shines@cs.fsu.edu#include "base/inifile.hh" 536019Shines@cs.fsu.edu#include "base/str.hh" 546019Shines@cs.fsu.edu#include "base/trace.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 566116Snate@binkert.org#include "mem/page_table.hh" 576116Snate@binkert.org#include "params/ArmTLB.hh" 586019Shines@cs.fsu.edu#include "sim/process.hh" 596019Shines@cs.fsu.edu 607406SAli.Saidi@ARM.com#if FULL_SYSTEM 617406SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 627406SAli.Saidi@ARM.com#endif 637406SAli.Saidi@ARM.com 646019Shines@cs.fsu.eduusing namespace std; 656019Shines@cs.fsu.eduusing namespace ArmISA; 666019Shines@cs.fsu.edu 676019Shines@cs.fsu.eduTLB::TLB(const Params *p) 686019Shines@cs.fsu.edu : BaseTLB(p), size(p->size), nlu(0) 697404SAli.Saidi@ARM.com#if FULL_SYSTEM 707404SAli.Saidi@ARM.com , tableWalker(p->walker) 717404SAli.Saidi@ARM.com#endif 726019Shines@cs.fsu.edu{ 737404SAli.Saidi@ARM.com table = new TlbEntry[size]; 747404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 757399SAli.Saidi@ARM.com 767406SAli.Saidi@ARM.com#if FULL_SYSTEM 777404SAli.Saidi@ARM.com tableWalker->setTlb(this); 787406SAli.Saidi@ARM.com#endif 796019Shines@cs.fsu.edu} 806019Shines@cs.fsu.edu 816019Shines@cs.fsu.eduTLB::~TLB() 826019Shines@cs.fsu.edu{ 836019Shines@cs.fsu.edu if (table) 846019Shines@cs.fsu.edu delete [] table; 856019Shines@cs.fsu.edu} 866019Shines@cs.fsu.edu 877404SAli.Saidi@ARM.comTlbEntry* 887404SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid) 896019Shines@cs.fsu.edu{ 907404SAli.Saidi@ARM.com // XXX This should either turn into a TlbMap or add caching 917404SAli.Saidi@ARM.com 927404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 937404SAli.Saidi@ARM.com 947404SAli.Saidi@ARM.com // Do some kind of caching, fast indexing, anything 957404SAli.Saidi@ARM.com 967404SAli.Saidi@ARM.com int x = 0; 977404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 987404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 997404SAli.Saidi@ARM.com retval = &table[x]; 1007404SAli.Saidi@ARM.com if (x == nlu) 1017404SAli.Saidi@ARM.com nextnlu(); 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.com break; 1047404SAli.Saidi@ARM.com } 1057404SAli.Saidi@ARM.com x++; 1067404SAli.Saidi@ARM.com } 1077404SAli.Saidi@ARM.com 1087404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1097404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1107404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1117404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1127404SAli.Saidi@ARM.com ; 1137404SAli.Saidi@ARM.com return retval; 1146019Shines@cs.fsu.edu} 1156019Shines@cs.fsu.edu 1166019Shines@cs.fsu.edu// insert a new TLB entry 1176019Shines@cs.fsu.eduvoid 1187404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1196019Shines@cs.fsu.edu{ 1207404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1217404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1227404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1237404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1247404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1257404SAli.Saidi@ARM.com 1267404SAli.Saidi@ARM.com if (table[nlu].valid) 1277404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1287404SAli.Saidi@ARM.com table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N, 1297404SAli.Saidi@ARM.com table[nlu].size, table[nlu].ap); 1307404SAli.Saidi@ARM.com 1317404SAli.Saidi@ARM.com // XXX Update caching, lookup table etc 1327404SAli.Saidi@ARM.com table[nlu] = entry; 1337404SAli.Saidi@ARM.com 1347404SAli.Saidi@ARM.com // XXX Figure out how entries are generally inserted in ARM 1357404SAli.Saidi@ARM.com nextnlu(); 1366019Shines@cs.fsu.edu} 1376019Shines@cs.fsu.edu 1386019Shines@cs.fsu.eduvoid 1397404SAli.Saidi@ARM.comTLB::printTlb() 1407404SAli.Saidi@ARM.com{ 1417404SAli.Saidi@ARM.com int x = 0; 1427404SAli.Saidi@ARM.com TlbEntry *te; 1437404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1447404SAli.Saidi@ARM.com while (x < size) { 1457404SAli.Saidi@ARM.com te = &table[x]; 1467404SAli.Saidi@ARM.com if (te->valid) 1477404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1487404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1497404SAli.Saidi@ARM.com x++; 1507404SAli.Saidi@ARM.com } 1517404SAli.Saidi@ARM.com} 1527404SAli.Saidi@ARM.com 1537404SAli.Saidi@ARM.com 1547404SAli.Saidi@ARM.comvoid 1556019Shines@cs.fsu.eduTLB::flushAll() 1566019Shines@cs.fsu.edu{ 1577404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1587404SAli.Saidi@ARM.com int x = 0; 1597404SAli.Saidi@ARM.com TlbEntry *te; 1607404SAli.Saidi@ARM.com while (x < size) { 1617404SAli.Saidi@ARM.com te = &table[x]; 1627404SAli.Saidi@ARM.com if (te->valid) 1637404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1647404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1657404SAli.Saidi@ARM.com x++; 1667404SAli.Saidi@ARM.com } 1677404SAli.Saidi@ARM.com 1687404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 1696019Shines@cs.fsu.edu nlu = 0; 1706019Shines@cs.fsu.edu} 1716019Shines@cs.fsu.edu 1727404SAli.Saidi@ARM.com 1737404SAli.Saidi@ARM.comvoid 1747404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 1757404SAli.Saidi@ARM.com{ 1767404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 1777404SAli.Saidi@ARM.com TlbEntry *te; 1787404SAli.Saidi@ARM.com 1797404SAli.Saidi@ARM.com te = lookup(mva, asn); 1807404SAli.Saidi@ARM.com while (te != NULL) { 1817404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1827404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1837404SAli.Saidi@ARM.com te->valid = false; 1847404SAli.Saidi@ARM.com te = lookup(mva,asn); 1857404SAli.Saidi@ARM.com } 1867404SAli.Saidi@ARM.com} 1877404SAli.Saidi@ARM.com 1887404SAli.Saidi@ARM.comvoid 1897404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 1907404SAli.Saidi@ARM.com{ 1917404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 1927404SAli.Saidi@ARM.com 1937404SAli.Saidi@ARM.com int x = 0; 1947404SAli.Saidi@ARM.com TlbEntry *te; 1957404SAli.Saidi@ARM.com 1967404SAli.Saidi@ARM.com while (x < size) { 1977404SAli.Saidi@ARM.com te = &table[x]; 1987404SAli.Saidi@ARM.com if (te->asid == asn) { 1997404SAli.Saidi@ARM.com te->valid = false; 2007404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2017404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2027404SAli.Saidi@ARM.com } 2037404SAli.Saidi@ARM.com x++; 2047404SAli.Saidi@ARM.com } 2057404SAli.Saidi@ARM.com} 2067404SAli.Saidi@ARM.com 2077404SAli.Saidi@ARM.comvoid 2087404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2097404SAli.Saidi@ARM.com{ 2107404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2117404SAli.Saidi@ARM.com 2127404SAli.Saidi@ARM.com int x = 0; 2137404SAli.Saidi@ARM.com TlbEntry *te; 2147404SAli.Saidi@ARM.com 2157404SAli.Saidi@ARM.com while (x < size) { 2167404SAli.Saidi@ARM.com te = &table[x]; 2177404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2187404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2197404SAli.Saidi@ARM.com te->valid = false; 2207404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2217404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2227404SAli.Saidi@ARM.com } 2237404SAli.Saidi@ARM.com x++; 2247404SAli.Saidi@ARM.com } 2257404SAli.Saidi@ARM.com} 2267404SAli.Saidi@ARM.com 2276019Shines@cs.fsu.eduvoid 2286019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2296019Shines@cs.fsu.edu{ 2307404SAli.Saidi@ARM.com panic("Implement Serialize\n"); 2316019Shines@cs.fsu.edu} 2326019Shines@cs.fsu.edu 2336019Shines@cs.fsu.eduvoid 2346019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2356019Shines@cs.fsu.edu{ 2366019Shines@cs.fsu.edu 2377399SAli.Saidi@ARM.com panic("Need to properly unserialize TLB\n"); 2386019Shines@cs.fsu.edu} 2396019Shines@cs.fsu.edu 2406019Shines@cs.fsu.eduvoid 2416019Shines@cs.fsu.eduTLB::regStats() 2426019Shines@cs.fsu.edu{ 2436019Shines@cs.fsu.edu read_hits 2446019Shines@cs.fsu.edu .name(name() + ".read_hits") 2456019Shines@cs.fsu.edu .desc("DTB read hits") 2466019Shines@cs.fsu.edu ; 2476019Shines@cs.fsu.edu 2486019Shines@cs.fsu.edu read_misses 2496019Shines@cs.fsu.edu .name(name() + ".read_misses") 2506019Shines@cs.fsu.edu .desc("DTB read misses") 2516019Shines@cs.fsu.edu ; 2526019Shines@cs.fsu.edu 2536019Shines@cs.fsu.edu 2546019Shines@cs.fsu.edu read_accesses 2556019Shines@cs.fsu.edu .name(name() + ".read_accesses") 2566019Shines@cs.fsu.edu .desc("DTB read accesses") 2576019Shines@cs.fsu.edu ; 2586019Shines@cs.fsu.edu 2596019Shines@cs.fsu.edu write_hits 2606019Shines@cs.fsu.edu .name(name() + ".write_hits") 2616019Shines@cs.fsu.edu .desc("DTB write hits") 2626019Shines@cs.fsu.edu ; 2636019Shines@cs.fsu.edu 2646019Shines@cs.fsu.edu write_misses 2656019Shines@cs.fsu.edu .name(name() + ".write_misses") 2666019Shines@cs.fsu.edu .desc("DTB write misses") 2676019Shines@cs.fsu.edu ; 2686019Shines@cs.fsu.edu 2696019Shines@cs.fsu.edu 2706019Shines@cs.fsu.edu write_accesses 2716019Shines@cs.fsu.edu .name(name() + ".write_accesses") 2726019Shines@cs.fsu.edu .desc("DTB write accesses") 2736019Shines@cs.fsu.edu ; 2746019Shines@cs.fsu.edu 2756019Shines@cs.fsu.edu hits 2766019Shines@cs.fsu.edu .name(name() + ".hits") 2776019Shines@cs.fsu.edu .desc("DTB hits") 2786019Shines@cs.fsu.edu ; 2796019Shines@cs.fsu.edu 2806019Shines@cs.fsu.edu misses 2816019Shines@cs.fsu.edu .name(name() + ".misses") 2826019Shines@cs.fsu.edu .desc("DTB misses") 2836019Shines@cs.fsu.edu ; 2846019Shines@cs.fsu.edu 2856019Shines@cs.fsu.edu accesses 2866019Shines@cs.fsu.edu .name(name() + ".accesses") 2876019Shines@cs.fsu.edu .desc("DTB accesses") 2886019Shines@cs.fsu.edu ; 2896019Shines@cs.fsu.edu 2906019Shines@cs.fsu.edu hits = read_hits + write_hits; 2916019Shines@cs.fsu.edu misses = read_misses + write_misses; 2926019Shines@cs.fsu.edu accesses = read_accesses + write_accesses; 2936019Shines@cs.fsu.edu} 2946019Shines@cs.fsu.edu 2957404SAli.Saidi@ARM.com#if !FULL_SYSTEM 2967404SAli.Saidi@ARM.comFault 2977404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 2987404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 2997404SAli.Saidi@ARM.com{ 3007404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 3017093Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr() & ~PcModeMask; 3027294Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3037294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 3047294Sgblack@eecs.umich.edu 3057404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 3067404SAli.Saidi@ARM.com bool is_write = (mode == Write); 3077404SAli.Saidi@ARM.com 3087404SAli.Saidi@ARM.com if (!is_fetch) { 3097294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 3107404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 3117404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 3127404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 3137294Sgblack@eecs.umich.edu } 3147294Sgblack@eecs.umich.edu } 3157294Sgblack@eecs.umich.edu } 3166019Shines@cs.fsu.edu 3177093Sgblack@eecs.umich.edu Addr paddr; 3187404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 3197404SAli.Saidi@ARM.com 3207093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 3217093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 3227093Sgblack@eecs.umich.edu req->setPaddr(paddr); 3236019Shines@cs.fsu.edu 3246019Shines@cs.fsu.edu return NoFault; 3257404SAli.Saidi@ARM.com} 3267404SAli.Saidi@ARM.com 3277404SAli.Saidi@ARM.com#else // FULL_SYSTEM 3287404SAli.Saidi@ARM.com 3297404SAli.Saidi@ARM.comFault 3307406SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 3317406SAli.Saidi@ARM.com{ 3327406SAli.Saidi@ARM.com return NoFault; 3337406SAli.Saidi@ARM.com} 3347406SAli.Saidi@ARM.com 3357406SAli.Saidi@ARM.comFault 3367406SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 3377406SAli.Saidi@ARM.com bool is_write, uint8_t domain, bool sNp) 3387406SAli.Saidi@ARM.com{ 3397406SAli.Saidi@ARM.com return NoFault; 3407406SAli.Saidi@ARM.com} 3417406SAli.Saidi@ARM.com 3427406SAli.Saidi@ARM.comFault 3437404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 3447404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 3457404SAli.Saidi@ARM.com{ 3467404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 3477404SAli.Saidi@ARM.com Addr vaddr = req->getVaddr() & ~PcModeMask; 3487404SAli.Saidi@ARM.com SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3497404SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 3507404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 3517404SAli.Saidi@ARM.com 3527404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 3537404SAli.Saidi@ARM.com bool is_write = (mode == Write); 3547404SAli.Saidi@ARM.com bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 3557404SAli.Saidi@ARM.com 3567404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 3577404SAli.Saidi@ARM.com & UserMode); 3587603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 3597603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 3607603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 3617603SGene.Wu@arm.com if (flags & Clrex){ 3627603SGene.Wu@arm.com req->setPaddr(0); 3637606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 3647603SGene.Wu@arm.com return NoFault; 3657603SGene.Wu@arm.com } 3667404SAli.Saidi@ARM.com if (!is_fetch) { 3677404SAli.Saidi@ARM.com assert(flags & MustBeOne); 3687404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 3697404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 3707404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 3717404SAli.Saidi@ARM.com } 3727404SAli.Saidi@ARM.com } 3737404SAli.Saidi@ARM.com } 3747404SAli.Saidi@ARM.com 3757404SAli.Saidi@ARM.com uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 3767404SAli.Saidi@ARM.com Fault fault; 3777404SAli.Saidi@ARM.com 3787404SAli.Saidi@ARM.com 3796757SAli.Saidi@ARM.com if (!sctlr.m) { 3807093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3817404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 3827404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 3837404SAli.Saidi@ARM.com } else { 3847404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3857404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3867404SAli.Saidi@ARM.com 3877404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 3887404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 3897404SAli.Saidi@ARM.com } 3907436Sdam.sunwoo@arm.com 3917436Sdam.sunwoo@arm.com // Set memory attributes 3927436Sdam.sunwoo@arm.com TlbEntry temp_te; 3937439Sdam.sunwoo@arm.com tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 3947436Sdam.sunwoo@arm.com temp_te.shareable = true; 3957436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 3967436Sdam.sunwoo@arm.com %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 3977436Sdam.sunwoo@arm.com temp_te.innerAttrs, temp_te.outerAttrs); 3987436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 3997436Sdam.sunwoo@arm.com 4007404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 4017404SAli.Saidi@ARM.com } 4027404SAli.Saidi@ARM.com 4037404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 4047404SAli.Saidi@ARM.com // Translation enabled 4057404SAli.Saidi@ARM.com 4067404SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, context_id); 4077404SAli.Saidi@ARM.com if (te == NULL) { 4087404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 4097404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 4107404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 4117404SAli.Saidi@ARM.com vaddr, context_id); 4127404SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, context_id, mode, translation, 4137404SAli.Saidi@ARM.com timing); 4147437Sdam.sunwoo@arm.com if (timing) { 4157404SAli.Saidi@ARM.com delay = true; 4167437Sdam.sunwoo@arm.com // for timing mode, return and wait for table walk 4177437Sdam.sunwoo@arm.com return fault; 4187437Sdam.sunwoo@arm.com } 4197404SAli.Saidi@ARM.com if (fault) 4207404SAli.Saidi@ARM.com return fault; 4217404SAli.Saidi@ARM.com 4227404SAli.Saidi@ARM.com te = lookup(vaddr, context_id); 4237404SAli.Saidi@ARM.com if (!te) 4247404SAli.Saidi@ARM.com printTlb(); 4257404SAli.Saidi@ARM.com assert(te); 4267404SAli.Saidi@ARM.com } 4277404SAli.Saidi@ARM.com 4287436Sdam.sunwoo@arm.com // Set memory attributes 4297436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, 4307436Sdam.sunwoo@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 4317436Sdam.sunwoo@arm.com outerAttrs: %d\n", 4327436Sdam.sunwoo@arm.com te->shareable, te->innerAttrs, te->outerAttrs); 4337436Sdam.sunwoo@arm.com setAttr(te->attributes); 4347606SGene.Wu@arm.com if (te->nonCacheable) 4357606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4367404SAli.Saidi@ARM.com uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 4377404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 4387404SAli.Saidi@ARM.com case 0: 4397404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 4407404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 4417404SAli.Saidi@ARM.com if (is_fetch) 4427404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 4437404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 4447404SAli.Saidi@ARM.com else 4457404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 4467404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 4477404SAli.Saidi@ARM.com case 1: 4487404SAli.Saidi@ARM.com // Continue with permissions check 4497404SAli.Saidi@ARM.com break; 4507404SAli.Saidi@ARM.com case 2: 4517404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 4527404SAli.Saidi@ARM.com case 3: 4537404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 4547404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 4557404SAli.Saidi@ARM.com if (fault) 4567404SAli.Saidi@ARM.com return fault; 4576757SAli.Saidi@ARM.com return NoFault; 4586757SAli.Saidi@ARM.com } 4597404SAli.Saidi@ARM.com 4607404SAli.Saidi@ARM.com uint8_t ap = te->ap; 4617404SAli.Saidi@ARM.com 4627404SAli.Saidi@ARM.com if (sctlr.afe == 1) 4637404SAli.Saidi@ARM.com ap |= 1; 4647404SAli.Saidi@ARM.com 4657404SAli.Saidi@ARM.com bool abt; 4667404SAli.Saidi@ARM.com 4677406SAli.Saidi@ARM.com /* if (!sctlr.xp) 4687406SAli.Saidi@ARM.com ap &= 0x3; 4697406SAli.Saidi@ARM.com*/ 4707404SAli.Saidi@ARM.com switch (ap) { 4717404SAli.Saidi@ARM.com case 0: 4727406SAli.Saidi@ARM.com DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 4737406SAli.Saidi@ARM.com if (!sctlr.xp) { 4747406SAli.Saidi@ARM.com switch ((int)sctlr.rs) { 4757406SAli.Saidi@ARM.com case 2: 4767406SAli.Saidi@ARM.com abt = is_write; 4777406SAli.Saidi@ARM.com break; 4787406SAli.Saidi@ARM.com case 1: 4797406SAli.Saidi@ARM.com abt = is_write || !is_priv; 4807406SAli.Saidi@ARM.com break; 4817406SAli.Saidi@ARM.com case 0: 4827406SAli.Saidi@ARM.com case 3: 4837406SAli.Saidi@ARM.com default: 4847406SAli.Saidi@ARM.com abt = true; 4857406SAli.Saidi@ARM.com break; 4867406SAli.Saidi@ARM.com } 4877406SAli.Saidi@ARM.com } else { 4887406SAli.Saidi@ARM.com abt = true; 4897406SAli.Saidi@ARM.com } 4907404SAli.Saidi@ARM.com break; 4917404SAli.Saidi@ARM.com case 1: 4927404SAli.Saidi@ARM.com abt = !is_priv; 4937404SAli.Saidi@ARM.com break; 4947404SAli.Saidi@ARM.com case 2: 4957404SAli.Saidi@ARM.com abt = !is_priv && is_write; 4967404SAli.Saidi@ARM.com break; 4977404SAli.Saidi@ARM.com case 3: 4987404SAli.Saidi@ARM.com abt = false; 4997404SAli.Saidi@ARM.com break; 5007404SAli.Saidi@ARM.com case 4: 5017404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 5027404SAli.Saidi@ARM.com case 5: 5037404SAli.Saidi@ARM.com abt = !is_priv || is_write; 5047404SAli.Saidi@ARM.com break; 5057404SAli.Saidi@ARM.com case 6: 5067404SAli.Saidi@ARM.com case 7: 5077404SAli.Saidi@ARM.com abt = is_write; 5087404SAli.Saidi@ARM.com break; 5097404SAli.Saidi@ARM.com default: 5107404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 5117404SAli.Saidi@ARM.com } 5127404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 5137404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 5147404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 5157404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 5167404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 5177404SAli.Saidi@ARM.com ArmFault::Permission1)); 5187404SAli.Saidi@ARM.com } else if (abt) { 5197404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 5207404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 5217404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 5227404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 5237404SAli.Saidi@ARM.com ArmFault::Permission1)); 5247404SAli.Saidi@ARM.com } 5257404SAli.Saidi@ARM.com 5267404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 5277404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 5287404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 5297404SAli.Saidi@ARM.com if (fault) 5307404SAli.Saidi@ARM.com return fault; 5317404SAli.Saidi@ARM.com 5326757SAli.Saidi@ARM.com return NoFault; 5337404SAli.Saidi@ARM.com} 5346757SAli.Saidi@ARM.com 5356019Shines@cs.fsu.edu#endif 5367404SAli.Saidi@ARM.com 5377404SAli.Saidi@ARM.comFault 5387404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5397404SAli.Saidi@ARM.com{ 5407404SAli.Saidi@ARM.com bool delay = false; 5417404SAli.Saidi@ARM.com Fault fault; 5427404SAli.Saidi@ARM.com#if FULL_SYSTEM 5437404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, NULL, delay, false); 5447404SAli.Saidi@ARM.com#else 5457404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, NULL, delay, false); 5467404SAli.Saidi@ARM.com#endif 5477404SAli.Saidi@ARM.com assert(!delay); 5487404SAli.Saidi@ARM.com return fault; 5496019Shines@cs.fsu.edu} 5506019Shines@cs.fsu.edu 5517404SAli.Saidi@ARM.comFault 5526116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5536116Snate@binkert.org Translation *translation, Mode mode) 5546020Sgblack@eecs.umich.edu{ 5556020Sgblack@eecs.umich.edu assert(translation); 5567404SAli.Saidi@ARM.com bool delay = false; 5577404SAli.Saidi@ARM.com Fault fault; 5587404SAli.Saidi@ARM.com#if FULL_SYSTEM 5597404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, translation, delay, true); 5607404SAli.Saidi@ARM.com#else 5617404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, translation, delay, true); 5627404SAli.Saidi@ARM.com#endif 5637404SAli.Saidi@ARM.com if (!delay) 5647404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 5657404SAli.Saidi@ARM.com return fault; 5666020Sgblack@eecs.umich.edu} 5676020Sgblack@eecs.umich.edu 5686116Snate@binkert.orgArmISA::TLB * 5696116Snate@binkert.orgArmTLBParams::create() 5706019Shines@cs.fsu.edu{ 5716116Snate@binkert.org return new ArmISA::TLB(this); 5726019Shines@cs.fsu.edu} 573