tlb.cc revision 7404
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 507404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 516019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 526019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 536019Shines@cs.fsu.edu#include "base/inifile.hh" 546019Shines@cs.fsu.edu#include "base/str.hh" 556019Shines@cs.fsu.edu#include "base/trace.hh" 566019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 576116Snate@binkert.org#include "mem/page_table.hh" 586116Snate@binkert.org#include "params/ArmTLB.hh" 596019Shines@cs.fsu.edu#include "sim/process.hh" 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.eduusing namespace std; 626019Shines@cs.fsu.eduusing namespace ArmISA; 636019Shines@cs.fsu.edu 646019Shines@cs.fsu.eduTLB::TLB(const Params *p) 656019Shines@cs.fsu.edu : BaseTLB(p), size(p->size), nlu(0) 667404SAli.Saidi@ARM.com#if FULL_SYSTEM 677404SAli.Saidi@ARM.com , tableWalker(p->walker) 687404SAli.Saidi@ARM.com#endif 696019Shines@cs.fsu.edu{ 707404SAli.Saidi@ARM.com table = new TlbEntry[size]; 717404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 727399SAli.Saidi@ARM.com 737404SAli.Saidi@ARM.com tableWalker->setTlb(this); 746019Shines@cs.fsu.edu} 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.eduTLB::~TLB() 776019Shines@cs.fsu.edu{ 786019Shines@cs.fsu.edu if (table) 796019Shines@cs.fsu.edu delete [] table; 806019Shines@cs.fsu.edu} 816019Shines@cs.fsu.edu 827404SAli.Saidi@ARM.comTlbEntry* 837404SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid) 846019Shines@cs.fsu.edu{ 857404SAli.Saidi@ARM.com // XXX This should either turn into a TlbMap or add caching 867404SAli.Saidi@ARM.com 877404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 887404SAli.Saidi@ARM.com 897404SAli.Saidi@ARM.com // Do some kind of caching, fast indexing, anything 907404SAli.Saidi@ARM.com 917404SAli.Saidi@ARM.com int x = 0; 927404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 937404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 947404SAli.Saidi@ARM.com retval = &table[x]; 957404SAli.Saidi@ARM.com if (x == nlu) 967404SAli.Saidi@ARM.com nextnlu(); 977404SAli.Saidi@ARM.com 987404SAli.Saidi@ARM.com break; 997404SAli.Saidi@ARM.com } 1007404SAli.Saidi@ARM.com x++; 1017404SAli.Saidi@ARM.com } 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1047404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1057404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1067404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1077404SAli.Saidi@ARM.com ; 1087404SAli.Saidi@ARM.com return retval; 1096019Shines@cs.fsu.edu} 1106019Shines@cs.fsu.edu 1116019Shines@cs.fsu.edu// insert a new TLB entry 1126019Shines@cs.fsu.eduvoid 1137404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1146019Shines@cs.fsu.edu{ 1157404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1167404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1177404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1187404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1197404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1207404SAli.Saidi@ARM.com 1217404SAli.Saidi@ARM.com if (table[nlu].valid) 1227404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1237404SAli.Saidi@ARM.com table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N, 1247404SAli.Saidi@ARM.com table[nlu].size, table[nlu].ap); 1257404SAli.Saidi@ARM.com 1267404SAli.Saidi@ARM.com // XXX Update caching, lookup table etc 1277404SAli.Saidi@ARM.com table[nlu] = entry; 1287404SAli.Saidi@ARM.com 1297404SAli.Saidi@ARM.com // XXX Figure out how entries are generally inserted in ARM 1307404SAli.Saidi@ARM.com nextnlu(); 1316019Shines@cs.fsu.edu} 1326019Shines@cs.fsu.edu 1336019Shines@cs.fsu.eduvoid 1347404SAli.Saidi@ARM.comTLB::printTlb() 1357404SAli.Saidi@ARM.com{ 1367404SAli.Saidi@ARM.com int x = 0; 1377404SAli.Saidi@ARM.com TlbEntry *te; 1387404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1397404SAli.Saidi@ARM.com while (x < size) { 1407404SAli.Saidi@ARM.com te = &table[x]; 1417404SAli.Saidi@ARM.com if (te->valid) 1427404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1437404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1447404SAli.Saidi@ARM.com x++; 1457404SAli.Saidi@ARM.com } 1467404SAli.Saidi@ARM.com} 1477404SAli.Saidi@ARM.com 1487404SAli.Saidi@ARM.com 1497404SAli.Saidi@ARM.comvoid 1506019Shines@cs.fsu.eduTLB::flushAll() 1516019Shines@cs.fsu.edu{ 1527404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1537404SAli.Saidi@ARM.com int x = 0; 1547404SAli.Saidi@ARM.com TlbEntry *te; 1557404SAli.Saidi@ARM.com while (x < size) { 1567404SAli.Saidi@ARM.com te = &table[x]; 1577404SAli.Saidi@ARM.com if (te->valid) 1587404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1597404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1607404SAli.Saidi@ARM.com x++; 1617404SAli.Saidi@ARM.com } 1627404SAli.Saidi@ARM.com 1637404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 1646019Shines@cs.fsu.edu nlu = 0; 1656019Shines@cs.fsu.edu} 1666019Shines@cs.fsu.edu 1677404SAli.Saidi@ARM.com 1687404SAli.Saidi@ARM.comvoid 1697404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 1707404SAli.Saidi@ARM.com{ 1717404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 1727404SAli.Saidi@ARM.com TlbEntry *te; 1737404SAli.Saidi@ARM.com 1747404SAli.Saidi@ARM.com te = lookup(mva, asn); 1757404SAli.Saidi@ARM.com while (te != NULL) { 1767404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1777404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1787404SAli.Saidi@ARM.com te->valid = false; 1797404SAli.Saidi@ARM.com te = lookup(mva,asn); 1807404SAli.Saidi@ARM.com } 1817404SAli.Saidi@ARM.com} 1827404SAli.Saidi@ARM.com 1837404SAli.Saidi@ARM.comvoid 1847404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 1857404SAli.Saidi@ARM.com{ 1867404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 1877404SAli.Saidi@ARM.com 1887404SAli.Saidi@ARM.com int x = 0; 1897404SAli.Saidi@ARM.com TlbEntry *te; 1907404SAli.Saidi@ARM.com 1917404SAli.Saidi@ARM.com while (x < size) { 1927404SAli.Saidi@ARM.com te = &table[x]; 1937404SAli.Saidi@ARM.com if (te->asid == asn) { 1947404SAli.Saidi@ARM.com te->valid = false; 1957404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1967404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1977404SAli.Saidi@ARM.com } 1987404SAli.Saidi@ARM.com x++; 1997404SAli.Saidi@ARM.com } 2007404SAli.Saidi@ARM.com} 2017404SAli.Saidi@ARM.com 2027404SAli.Saidi@ARM.comvoid 2037404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2047404SAli.Saidi@ARM.com{ 2057404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2067404SAli.Saidi@ARM.com 2077404SAli.Saidi@ARM.com int x = 0; 2087404SAli.Saidi@ARM.com TlbEntry *te; 2097404SAli.Saidi@ARM.com 2107404SAli.Saidi@ARM.com while (x < size) { 2117404SAli.Saidi@ARM.com te = &table[x]; 2127404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2137404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2147404SAli.Saidi@ARM.com te->valid = false; 2157404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2167404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2177404SAli.Saidi@ARM.com } 2187404SAli.Saidi@ARM.com x++; 2197404SAli.Saidi@ARM.com } 2207404SAli.Saidi@ARM.com} 2217404SAli.Saidi@ARM.com 2226019Shines@cs.fsu.eduvoid 2236019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2246019Shines@cs.fsu.edu{ 2257404SAli.Saidi@ARM.com panic("Implement Serialize\n"); 2266019Shines@cs.fsu.edu} 2276019Shines@cs.fsu.edu 2286019Shines@cs.fsu.eduvoid 2296019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2306019Shines@cs.fsu.edu{ 2316019Shines@cs.fsu.edu 2327399SAli.Saidi@ARM.com panic("Need to properly unserialize TLB\n"); 2336019Shines@cs.fsu.edu} 2346019Shines@cs.fsu.edu 2356019Shines@cs.fsu.eduvoid 2366019Shines@cs.fsu.eduTLB::regStats() 2376019Shines@cs.fsu.edu{ 2386019Shines@cs.fsu.edu read_hits 2396019Shines@cs.fsu.edu .name(name() + ".read_hits") 2406019Shines@cs.fsu.edu .desc("DTB read hits") 2416019Shines@cs.fsu.edu ; 2426019Shines@cs.fsu.edu 2436019Shines@cs.fsu.edu read_misses 2446019Shines@cs.fsu.edu .name(name() + ".read_misses") 2456019Shines@cs.fsu.edu .desc("DTB read misses") 2466019Shines@cs.fsu.edu ; 2476019Shines@cs.fsu.edu 2486019Shines@cs.fsu.edu 2496019Shines@cs.fsu.edu read_accesses 2506019Shines@cs.fsu.edu .name(name() + ".read_accesses") 2516019Shines@cs.fsu.edu .desc("DTB read accesses") 2526019Shines@cs.fsu.edu ; 2536019Shines@cs.fsu.edu 2546019Shines@cs.fsu.edu write_hits 2556019Shines@cs.fsu.edu .name(name() + ".write_hits") 2566019Shines@cs.fsu.edu .desc("DTB write hits") 2576019Shines@cs.fsu.edu ; 2586019Shines@cs.fsu.edu 2596019Shines@cs.fsu.edu write_misses 2606019Shines@cs.fsu.edu .name(name() + ".write_misses") 2616019Shines@cs.fsu.edu .desc("DTB write misses") 2626019Shines@cs.fsu.edu ; 2636019Shines@cs.fsu.edu 2646019Shines@cs.fsu.edu 2656019Shines@cs.fsu.edu write_accesses 2666019Shines@cs.fsu.edu .name(name() + ".write_accesses") 2676019Shines@cs.fsu.edu .desc("DTB write accesses") 2686019Shines@cs.fsu.edu ; 2696019Shines@cs.fsu.edu 2706019Shines@cs.fsu.edu hits 2716019Shines@cs.fsu.edu .name(name() + ".hits") 2726019Shines@cs.fsu.edu .desc("DTB hits") 2736019Shines@cs.fsu.edu ; 2746019Shines@cs.fsu.edu 2756019Shines@cs.fsu.edu misses 2766019Shines@cs.fsu.edu .name(name() + ".misses") 2776019Shines@cs.fsu.edu .desc("DTB misses") 2786019Shines@cs.fsu.edu ; 2796019Shines@cs.fsu.edu 2806019Shines@cs.fsu.edu invalids 2816019Shines@cs.fsu.edu .name(name() + ".invalids") 2826019Shines@cs.fsu.edu .desc("DTB access violations") 2836019Shines@cs.fsu.edu ; 2846019Shines@cs.fsu.edu 2856019Shines@cs.fsu.edu accesses 2866019Shines@cs.fsu.edu .name(name() + ".accesses") 2876019Shines@cs.fsu.edu .desc("DTB accesses") 2886019Shines@cs.fsu.edu ; 2896019Shines@cs.fsu.edu 2906019Shines@cs.fsu.edu hits = read_hits + write_hits; 2916019Shines@cs.fsu.edu misses = read_misses + write_misses; 2926019Shines@cs.fsu.edu accesses = read_accesses + write_accesses; 2936019Shines@cs.fsu.edu} 2946019Shines@cs.fsu.edu 2956019Shines@cs.fsu.eduFault 2967404SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 2976019Shines@cs.fsu.edu{ 2987404SAli.Saidi@ARM.com return NoFault; 2997404SAli.Saidi@ARM.com} 3007404SAli.Saidi@ARM.com 3017404SAli.Saidi@ARM.comFault 3027404SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 3037404SAli.Saidi@ARM.com uint8_t domain, bool sNp) 3047404SAli.Saidi@ARM.com{ 3057404SAli.Saidi@ARM.com return NoFault; 3067404SAli.Saidi@ARM.com} 3077404SAli.Saidi@ARM.com 3087404SAli.Saidi@ARM.com#if !FULL_SYSTEM 3097404SAli.Saidi@ARM.comFault 3107404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 3117404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 3127404SAli.Saidi@ARM.com{ 3137404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 3147093Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr() & ~PcModeMask; 3157294Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3167294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 3177294Sgblack@eecs.umich.edu 3187404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 3197404SAli.Saidi@ARM.com bool is_write = (mode == Write); 3207404SAli.Saidi@ARM.com 3217404SAli.Saidi@ARM.com if (!is_fetch) { 3227294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 3237404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 3247404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 3257404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 3267294Sgblack@eecs.umich.edu } 3277294Sgblack@eecs.umich.edu } 3287294Sgblack@eecs.umich.edu } 3296019Shines@cs.fsu.edu 3307093Sgblack@eecs.umich.edu Addr paddr; 3317404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 3327404SAli.Saidi@ARM.com 3337093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 3347093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 3357093Sgblack@eecs.umich.edu req->setPaddr(paddr); 3366019Shines@cs.fsu.edu 3376019Shines@cs.fsu.edu return NoFault; 3387404SAli.Saidi@ARM.com} 3397404SAli.Saidi@ARM.com 3407404SAli.Saidi@ARM.com#else // FULL_SYSTEM 3417404SAli.Saidi@ARM.com 3427404SAli.Saidi@ARM.comFault 3437404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 3447404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 3457404SAli.Saidi@ARM.com{ 3467404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 3477404SAli.Saidi@ARM.com Addr vaddr = req->getVaddr() & ~PcModeMask; 3487404SAli.Saidi@ARM.com SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3497404SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 3507404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 3517404SAli.Saidi@ARM.com 3527404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 3537404SAli.Saidi@ARM.com bool is_write = (mode == Write); 3547404SAli.Saidi@ARM.com bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 3557404SAli.Saidi@ARM.com 3567404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 3577404SAli.Saidi@ARM.com & UserMode); 3587404SAli.Saidi@ARM.com if (!is_fetch) { 3597404SAli.Saidi@ARM.com assert(flags & MustBeOne); 3607404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 3617404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 3627404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 3637404SAli.Saidi@ARM.com } 3647404SAli.Saidi@ARM.com } 3657404SAli.Saidi@ARM.com } 3667404SAli.Saidi@ARM.com 3677404SAli.Saidi@ARM.com uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 3687404SAli.Saidi@ARM.com Fault fault; 3697404SAli.Saidi@ARM.com 3707404SAli.Saidi@ARM.com 3716757SAli.Saidi@ARM.com if (!sctlr.m) { 3727093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3737404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 3747404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 3757404SAli.Saidi@ARM.com } else { 3767404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3777404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3787404SAli.Saidi@ARM.com 3797404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 3807404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 3817404SAli.Saidi@ARM.com } 3827404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 3837404SAli.Saidi@ARM.com } 3847404SAli.Saidi@ARM.com 3857404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 3867404SAli.Saidi@ARM.com // Translation enabled 3877404SAli.Saidi@ARM.com 3887404SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, context_id); 3897404SAli.Saidi@ARM.com if (te == NULL) { 3907404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 3917404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 3927404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 3937404SAli.Saidi@ARM.com vaddr, context_id); 3947404SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, context_id, mode, translation, 3957404SAli.Saidi@ARM.com timing); 3967404SAli.Saidi@ARM.com if (timing) 3977404SAli.Saidi@ARM.com delay = true; 3987404SAli.Saidi@ARM.com if (fault) 3997404SAli.Saidi@ARM.com return fault; 4007404SAli.Saidi@ARM.com 4017404SAli.Saidi@ARM.com te = lookup(vaddr, context_id); 4027404SAli.Saidi@ARM.com if (!te) 4037404SAli.Saidi@ARM.com printTlb(); 4047404SAli.Saidi@ARM.com assert(te); 4057404SAli.Saidi@ARM.com } 4067404SAli.Saidi@ARM.com 4077404SAli.Saidi@ARM.com uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 4087404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 4097404SAli.Saidi@ARM.com case 0: 4107404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 4117404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 4127404SAli.Saidi@ARM.com if (is_fetch) 4137404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 4147404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 4157404SAli.Saidi@ARM.com else 4167404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 4177404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 4187404SAli.Saidi@ARM.com case 1: 4197404SAli.Saidi@ARM.com // Continue with permissions check 4207404SAli.Saidi@ARM.com break; 4217404SAli.Saidi@ARM.com case 2: 4227404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 4237404SAli.Saidi@ARM.com case 3: 4247404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 4257404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 4267404SAli.Saidi@ARM.com if (fault) 4277404SAli.Saidi@ARM.com return fault; 4286757SAli.Saidi@ARM.com return NoFault; 4296757SAli.Saidi@ARM.com } 4307404SAli.Saidi@ARM.com 4317404SAli.Saidi@ARM.com uint8_t ap = te->ap; 4327404SAli.Saidi@ARM.com 4337404SAli.Saidi@ARM.com if (sctlr.afe == 1) 4347404SAli.Saidi@ARM.com ap |= 1; 4357404SAli.Saidi@ARM.com 4367404SAli.Saidi@ARM.com bool abt; 4377404SAli.Saidi@ARM.com 4387404SAli.Saidi@ARM.com switch (ap) { 4397404SAli.Saidi@ARM.com case 0: 4407404SAli.Saidi@ARM.com abt = true; 4417404SAli.Saidi@ARM.com break; 4427404SAli.Saidi@ARM.com case 1: 4437404SAli.Saidi@ARM.com abt = !is_priv; 4447404SAli.Saidi@ARM.com break; 4457404SAli.Saidi@ARM.com case 2: 4467404SAli.Saidi@ARM.com abt = !is_priv && is_write; 4477404SAli.Saidi@ARM.com break; 4487404SAli.Saidi@ARM.com case 3: 4497404SAli.Saidi@ARM.com abt = false; 4507404SAli.Saidi@ARM.com break; 4517404SAli.Saidi@ARM.com case 4: 4527404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 4537404SAli.Saidi@ARM.com case 5: 4547404SAli.Saidi@ARM.com abt = !is_priv || is_write; 4557404SAli.Saidi@ARM.com break; 4567404SAli.Saidi@ARM.com case 6: 4577404SAli.Saidi@ARM.com case 7: 4587404SAli.Saidi@ARM.com abt = is_write; 4597404SAli.Saidi@ARM.com break; 4607404SAli.Saidi@ARM.com default: 4617404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 4627404SAli.Saidi@ARM.com } 4637404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 4647404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 4657404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 4667404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 4677404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 4687404SAli.Saidi@ARM.com ArmFault::Permission1)); 4697404SAli.Saidi@ARM.com } else if (abt) { 4707404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 4717404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 4727404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 4737404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 4747404SAli.Saidi@ARM.com ArmFault::Permission1)); 4757404SAli.Saidi@ARM.com } 4767404SAli.Saidi@ARM.com 4777404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 4787404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 4797404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 4807404SAli.Saidi@ARM.com if (fault) 4817404SAli.Saidi@ARM.com return fault; 4827404SAli.Saidi@ARM.com 4836757SAli.Saidi@ARM.com return NoFault; 4847404SAli.Saidi@ARM.com} 4856757SAli.Saidi@ARM.com 4866019Shines@cs.fsu.edu#endif 4877404SAli.Saidi@ARM.com 4887404SAli.Saidi@ARM.comFault 4897404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 4907404SAli.Saidi@ARM.com{ 4917404SAli.Saidi@ARM.com bool delay = false; 4927404SAli.Saidi@ARM.com Fault fault; 4937404SAli.Saidi@ARM.com#if FULL_SYSTEM 4947404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, NULL, delay, false); 4957404SAli.Saidi@ARM.com#else 4967404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, NULL, delay, false); 4977404SAli.Saidi@ARM.com#endif 4987404SAli.Saidi@ARM.com assert(!delay); 4997404SAli.Saidi@ARM.com return fault; 5006019Shines@cs.fsu.edu} 5016019Shines@cs.fsu.edu 5027404SAli.Saidi@ARM.comFault 5036116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5046116Snate@binkert.org Translation *translation, Mode mode) 5056020Sgblack@eecs.umich.edu{ 5066020Sgblack@eecs.umich.edu assert(translation); 5077404SAli.Saidi@ARM.com bool delay = false; 5087404SAli.Saidi@ARM.com Fault fault; 5097404SAli.Saidi@ARM.com#if FULL_SYSTEM 5107404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, translation, delay, true); 5117404SAli.Saidi@ARM.com#else 5127404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, translation, delay, true); 5137404SAli.Saidi@ARM.com#endif 5147404SAli.Saidi@ARM.com if (!delay) 5157404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 5167404SAli.Saidi@ARM.com return fault; 5176020Sgblack@eecs.umich.edu} 5186020Sgblack@eecs.umich.edu 5196116Snate@binkert.orgArmISA::TLB * 5206116Snate@binkert.orgArmTLBParams::create() 5216019Shines@cs.fsu.edu{ 5226116Snate@binkert.org return new ArmISA::TLB(this); 5236019Shines@cs.fsu.edu} 524