tlb.cc revision 6019 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Nathan Binkert
31 *          Steve Reinhardt
32 *          Stephen Hines
33 */
34
35#include <string>
36#include <vector>
37
38#include "arch/arm/pagetable.hh"
39#include "arch/arm/tlb.hh"
40#include "arch/arm/faults.hh"
41#include "arch/arm/utility.hh"
42#include "base/inifile.hh"
43#include "base/str.hh"
44#include "base/trace.hh"
45#include "cpu/thread_context.hh"
46#include "sim/process.hh"
47#include "mem/page_table.hh"
48#include "params/ArmDTB.hh"
49#include "params/ArmITB.hh"
50#include "params/ArmTLB.hh"
51#include "params/ArmUTB.hh"
52
53
54using namespace std;
55using namespace ArmISA;
56
57///////////////////////////////////////////////////////////////////////
58//
59//  ARM TLB
60//
61
62#define MODE2MASK(X)			(1 << (X))
63
64TLB::TLB(const Params *p)
65    : BaseTLB(p), size(p->size), nlu(0)
66{
67    table = new ArmISA::PTE[size];
68    memset(table, 0, sizeof(ArmISA::PTE[size]));
69    smallPages=0;
70}
71
72TLB::~TLB()
73{
74    if (table)
75        delete [] table;
76}
77
78// look up an entry in the TLB
79ArmISA::PTE *
80TLB::lookup(Addr vpn, uint8_t asn) const
81{
82    // assume not found...
83    ArmISA::PTE *retval = NULL;
84    PageTable::const_iterator i = lookupTable.find(vpn);
85    if (i != lookupTable.end()) {
86        while (i->first == vpn) {
87            int index = i->second;
88            ArmISA::PTE *pte = &table[index];
89
90            /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
91            Addr Mask = pte->Mask;
92            Addr InvMask = ~Mask;
93            Addr VPN  = pte->VPN;
94            //	    warn("Valid: %d - %d\n",pte->V0,pte->V1);
95            if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G  || (asn == pte->asid)))
96              { // We have a VPN + ASID Match
97                retval = pte;
98                break;
99              }
100            ++i;
101        }
102    }
103
104    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
105            retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
106    return retval;
107}
108
109ArmISA::PTE* TLB::getEntry(unsigned Index) const
110{
111    // Make sure that Index is valid
112    assert(Index<size);
113    return &table[Index];
114}
115
116int TLB::probeEntry(Addr vpn,uint8_t asn) const
117{
118    // assume not found...
119    ArmISA::PTE *retval = NULL;
120    int Ind=-1;
121    PageTable::const_iterator i = lookupTable.find(vpn);
122    if (i != lookupTable.end()) {
123        while (i->first == vpn) {
124            int index = i->second;
125            ArmISA::PTE *pte = &table[index];
126
127            /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
128            Addr Mask = pte->Mask;
129            Addr InvMask = ~Mask;
130            Addr VPN  = pte->VPN;
131            if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G  || (asn == pte->asid)))
132              { // We have a VPN + ASID Match
133                retval = pte;
134                Ind = index;
135                break;
136              }
137
138            ++i;
139        }
140    }
141    DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
142    return Ind;
143}
144Fault inline
145TLB::checkCacheability(RequestPtr &req)
146{
147  Addr VAddrUncacheable = 0xA0000000;
148  // In ARM, cacheability is controlled by certain bits of the virtual address
149  // or by the TLB entry
150  if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151    // mark request as uncacheable
152    req->setFlags(req->getFlags() | UNCACHEABLE);
153  }
154  return NoFault;
155}
156void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
157{
158  smallPages=_smallPages;
159  if(Index > size){
160    warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
161  } else {
162    // Update TLB
163    DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
164            ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
165    if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
166      PageTable::iterator i = lookupTable.find(table[Index].VPN);
167      lookupTable.erase(i);
168    }
169    table[Index]=pte;
170    // Update fast lookup table
171    lookupTable.insert(make_pair(table[Index].VPN, Index));
172    //    int TestIndex=probeEntry(pte.VPN,pte.asid);
173    //    warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
174  }
175
176}
177
178// insert a new TLB entry
179void
180TLB::insert(Addr addr, ArmISA::PTE &pte)
181{
182  fatal("TLB Insert not yet implemented\n");
183}
184
185void
186TLB::flushAll()
187{
188    DPRINTF(TLB, "flushAll\n");
189    memset(table, 0, sizeof(ArmISA::PTE[size]));
190    lookupTable.clear();
191    nlu = 0;
192}
193
194void
195TLB::serialize(ostream &os)
196{
197    SERIALIZE_SCALAR(size);
198    SERIALIZE_SCALAR(nlu);
199
200    for (int i = 0; i < size; i++) {
201        nameOut(os, csprintf("%s.PTE%d", name(), i));
202        table[i].serialize(os);
203    }
204}
205
206void
207TLB::unserialize(Checkpoint *cp, const string &section)
208{
209    UNSERIALIZE_SCALAR(size);
210    UNSERIALIZE_SCALAR(nlu);
211
212    for (int i = 0; i < size; i++) {
213        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
214        if (table[i].V0 || table[i].V1) {
215            lookupTable.insert(make_pair(table[i].VPN, i));
216        }
217    }
218}
219
220void
221TLB::regStats()
222{
223    read_hits
224        .name(name() + ".read_hits")
225        .desc("DTB read hits")
226        ;
227
228    read_misses
229        .name(name() + ".read_misses")
230        .desc("DTB read misses")
231        ;
232
233
234    read_accesses
235        .name(name() + ".read_accesses")
236        .desc("DTB read accesses")
237        ;
238
239    write_hits
240        .name(name() + ".write_hits")
241        .desc("DTB write hits")
242        ;
243
244    write_misses
245        .name(name() + ".write_misses")
246        .desc("DTB write misses")
247        ;
248
249
250    write_accesses
251        .name(name() + ".write_accesses")
252        .desc("DTB write accesses")
253        ;
254
255    hits
256        .name(name() + ".hits")
257        .desc("DTB hits")
258        ;
259
260    misses
261        .name(name() + ".misses")
262        .desc("DTB misses")
263        ;
264
265    invalids
266        .name(name() + ".invalids")
267        .desc("DTB access violations")
268        ;
269
270    accesses
271        .name(name() + ".accesses")
272        .desc("DTB accesses")
273        ;
274
275    hits = read_hits + write_hits;
276    misses = read_misses + write_misses;
277    accesses = read_accesses + write_accesses;
278}
279
280Fault
281ITB::translate(RequestPtr &req, ThreadContext *tc)
282{
283#if !FULL_SYSTEM
284    Process * p = tc->getProcessPtr();
285
286    Fault fault = p->pTable->translate(req);
287    if(fault != NoFault)
288        return fault;
289
290    return NoFault;
291#else
292  fatal("ITB translate not yet implemented\n");
293#endif
294}
295
296Fault
297DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
298{
299#if !FULL_SYSTEM
300    Process * p = tc->getProcessPtr();
301
302    Fault fault = p->pTable->translate(req);
303    if(fault != NoFault)
304        return fault;
305
306    return NoFault;
307#else
308  fatal("DTB translate not yet implemented\n");
309#endif
310}
311
312///////////////////////////////////////////////////////////////////////
313//
314//  Arm ITB
315//
316ITB::ITB(const Params *p)
317    : TLB(p)
318{}
319
320
321///////////////////////////////////////////////////////////////////////
322//
323//  Arm DTB
324//
325DTB::DTB(const Params *p)
326    : TLB(p)
327{}
328
329///////////////////////////////////////////////////////////////////////
330//
331//  Arm UTB
332//
333UTB::UTB(const Params *p)
334    : ITB(p), DTB(p)
335{}
336
337ArmISA::PTE &
338TLB::index(bool advance)
339{
340    ArmISA::PTE *pte = &table[nlu];
341
342    if (advance)
343        nextnlu();
344
345    return *pte;
346}
347
348ArmISA::ITB *
349ArmITBParams::create()
350{
351    return new ArmISA::ITB(this);
352}
353
354ArmISA::DTB *
355ArmDTBParams::create()
356{
357    return new ArmISA::DTB(this);
358}
359
360ArmISA::UTB *
361ArmUTBParams::create()
362{
363    return new ArmISA::UTB(this);
364}
365