tlb.cc revision 14278
16019Shines@cs.fsu.edu/* 213882Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2013, 2016-2019 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 4510873Sandreas.sandberg@arm.com#include "arch/arm/tlb.hh" 4610873Sandreas.sandberg@arm.com 4710474Sandreas.hansson@arm.com#include <memory> 486019Shines@cs.fsu.edu#include <string> 496019Shines@cs.fsu.edu#include <vector> 506019Shines@cs.fsu.edu 516116Snate@binkert.org#include "arch/arm/faults.hh" 526019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 5311793Sbrandon.potter@amd.com#include "arch/arm/stage2_lookup.hh" 5411793Sbrandon.potter@amd.com#include "arch/arm/stage2_mmu.hh" 558782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 568756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 576019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 5812005Sandreas.sandberg@arm.com#include "arch/generic/mmapped_ipr.hh" 596019Shines@cs.fsu.edu#include "base/inifile.hh" 606019Shines@cs.fsu.edu#include "base/str.hh" 616019Shines@cs.fsu.edu#include "base/trace.hh" 6210024Sdam.sunwoo@arm.com#include "cpu/base.hh" 636019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 648232Snate@binkert.org#include "debug/Checkpoint.hh" 658232Snate@binkert.org#include "debug/TLB.hh" 668232Snate@binkert.org#include "debug/TLBVerbose.hh" 676116Snate@binkert.org#include "mem/page_table.hh" 6811608Snikos.nikoleris@arm.com#include "mem/request.hh" 696116Snate@binkert.org#include "params/ArmTLB.hh" 708756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 716019Shines@cs.fsu.edu#include "sim/process.hh" 726019Shines@cs.fsu.edu 736019Shines@cs.fsu.eduusing namespace std; 746019Shines@cs.fsu.eduusing namespace ArmISA; 756019Shines@cs.fsu.edu 7610037SARM gem5 DevelopersTLB::TLB(const ArmTLBParams *p) 7710037SARM gem5 Developers : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 7813374Sanouk.vanlaer@arm.com isStage2(p->is_stage2), stage2Req(false), stage2DescReq(false), _attr(0), 7910418Sandreas.hansson@arm.com directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 8011395Sandreas.sandberg@arm.com stage2Mmu(NULL), test(nullptr), rangeMRU(1), 8110537Sandreas.hansson@arm.com aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), 8213453Srekai.gonzalezalberquilla@arm.com isHyp(false), asid(0), vmid(0), hcr(0), dacr(0), 8311152Smitch.hayenga@arm.com miscRegValid(false), miscRegContext(0), curTranType(NormalTran) 846019Shines@cs.fsu.edu{ 8512005Sandreas.sandberg@arm.com const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys); 8612005Sandreas.sandberg@arm.com 8710037SARM gem5 Developers tableWalker->setTlb(this); 887399SAli.Saidi@ARM.com 8910037SARM gem5 Developers // Cache system-level properties 9010037SARM gem5 Developers haveLPAE = tableWalker->haveLPAE(); 9110037SARM gem5 Developers haveVirtualization = tableWalker->haveVirtualization(); 9210037SARM gem5 Developers haveLargeAsid64 = tableWalker->haveLargeAsid64(); 9312005Sandreas.sandberg@arm.com 9412005Sandreas.sandberg@arm.com if (sys) 9512005Sandreas.sandberg@arm.com m5opRange = sys->m5opRange(); 966019Shines@cs.fsu.edu} 976019Shines@cs.fsu.edu 986019Shines@cs.fsu.eduTLB::~TLB() 996019Shines@cs.fsu.edu{ 10010037SARM gem5 Developers delete[] table; 10110037SARM gem5 Developers} 10210037SARM gem5 Developers 10310037SARM gem5 Developersvoid 10410037SARM gem5 DevelopersTLB::init() 10510037SARM gem5 Developers{ 10610037SARM gem5 Developers if (stage2Mmu && !isStage2) 10710037SARM gem5 Developers stage2Tlb = stage2Mmu->stage2Tlb(); 10810037SARM gem5 Developers} 10910037SARM gem5 Developers 11010037SARM gem5 Developersvoid 11110717Sandreas.hansson@arm.comTLB::setMMU(Stage2MMU *m, MasterID master_id) 11210037SARM gem5 Developers{ 11310037SARM gem5 Developers stage2Mmu = m; 11410717Sandreas.hansson@arm.com tableWalker->setMMU(m, master_id); 1156019Shines@cs.fsu.edu} 1166019Shines@cs.fsu.edu 1177694SAli.Saidi@ARM.combool 1187694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 1197694SAli.Saidi@ARM.com{ 12010037SARM gem5 Developers updateMiscReg(tc); 12110037SARM gem5 Developers 12210037SARM gem5 Developers if (directToStage2) { 12310037SARM gem5 Developers assert(stage2Tlb); 12410037SARM gem5 Developers return stage2Tlb->translateFunctional(tc, va, pa); 12510037SARM gem5 Developers } 12610037SARM gem5 Developers 12710037SARM gem5 Developers TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 12810037SARM gem5 Developers aarch64 ? aarch64EL : EL1); 1297694SAli.Saidi@ARM.com if (!e) 1307694SAli.Saidi@ARM.com return false; 1317694SAli.Saidi@ARM.com pa = e->pAddr(va); 1327694SAli.Saidi@ARM.com return true; 1337694SAli.Saidi@ARM.com} 1347694SAli.Saidi@ARM.com 1359738Sandreas@sandberg.pp.seFault 13612749Sgiacomo.travaglini@arm.comTLB::finalizePhysical(const RequestPtr &req, 13712749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const 1389738Sandreas@sandberg.pp.se{ 13912005Sandreas.sandberg@arm.com const Addr paddr = req->getPaddr(); 14012005Sandreas.sandberg@arm.com 14112005Sandreas.sandberg@arm.com if (m5opRange.contains(paddr)) { 14212005Sandreas.sandberg@arm.com req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); 14312005Sandreas.sandberg@arm.com req->setPaddr(GenericISA::iprAddressPseudoInst( 14412005Sandreas.sandberg@arm.com (paddr >> 8) & 0xFF, 14512005Sandreas.sandberg@arm.com paddr & 0xFF)); 14612005Sandreas.sandberg@arm.com } 14712005Sandreas.sandberg@arm.com 1489738Sandreas@sandberg.pp.se return NoFault; 1499738Sandreas@sandberg.pp.se} 1509738Sandreas@sandberg.pp.se 1517404SAli.Saidi@ARM.comTlbEntry* 15210037SARM gem5 DevelopersTLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 15314088Sgiacomo.travaglini@arm.com bool functional, bool ignore_asn, ExceptionLevel target_el) 1546019Shines@cs.fsu.edu{ 1557404SAli.Saidi@ARM.com 1567404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1577404SAli.Saidi@ARM.com 15810037SARM gem5 Developers // Maintaining LRU array 1597404SAli.Saidi@ARM.com int x = 0; 1607404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 16110037SARM gem5 Developers if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 16210037SARM gem5 Developers target_el)) || 16310037SARM gem5 Developers (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 16410037SARM gem5 Developers // We only move the hit entry ahead when the position is higher 16510037SARM gem5 Developers // than rangeMRU 1669535Smrinmoy.ghosh@arm.com if (x > rangeMRU && !functional) { 1677697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 16811321Ssteve.reinhardt@amd.com for (int i = x; i > 0; i--) 16910037SARM gem5 Developers table[i] = table[i - 1]; 1707697SAli.Saidi@ARM.com table[0] = tmp_entry; 1717697SAli.Saidi@ARM.com retval = &table[0]; 1727697SAli.Saidi@ARM.com } else { 1737697SAli.Saidi@ARM.com retval = &table[x]; 1747697SAli.Saidi@ARM.com } 1757404SAli.Saidi@ARM.com break; 1767404SAli.Saidi@ARM.com } 17710037SARM gem5 Developers ++x; 1787404SAli.Saidi@ARM.com } 1797404SAli.Saidi@ARM.com 18010037SARM gem5 Developers DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 18110037SARM gem5 Developers "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 18210037SARM gem5 Developers "el: %d\n", 18310037SARM gem5 Developers va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 18410037SARM gem5 Developers retval ? retval->pfn : 0, retval ? retval->size : 0, 18510037SARM gem5 Developers retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 18610037SARM gem5 Developers retval ? retval->ns : 0, retval ? retval->nstid : 0, 18710037SARM gem5 Developers retval ? retval->global : 0, retval ? retval->asid : 0, 18810367SAndrew.Bardsley@arm.com retval ? retval->el : 0); 18910037SARM gem5 Developers 1907404SAli.Saidi@ARM.com return retval; 1916019Shines@cs.fsu.edu} 1926019Shines@cs.fsu.edu 1936019Shines@cs.fsu.edu// insert a new TLB entry 1946019Shines@cs.fsu.eduvoid 1957404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1966019Shines@cs.fsu.edu{ 1977404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 19810037SARM gem5 Developers " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 19910037SARM gem5 Developers " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 20010037SARM gem5 Developers entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 20110037SARM gem5 Developers entry.global, entry.valid, entry.nonCacheable, entry.xn, 20210037SARM gem5 Developers entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 20310037SARM gem5 Developers entry.isHyp); 2047404SAli.Saidi@ARM.com 20510037SARM gem5 Developers if (table[size - 1].valid) 20610037SARM gem5 Developers DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 20710037SARM gem5 Developers "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 2087697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 20910037SARM gem5 Developers table[size-1].vmid, table[size-1].pfn << table[size-1].N, 21010037SARM gem5 Developers table[size-1].size, table[size-1].ap, table[size-1].ns, 21110037SARM gem5 Developers table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 21210037SARM gem5 Developers table[size-1].el); 2137404SAli.Saidi@ARM.com 2147697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 2157404SAli.Saidi@ARM.com 21610037SARM gem5 Developers for (int i = size - 1; i > 0; --i) 21710037SARM gem5 Developers table[i] = table[i-1]; 2187697SAli.Saidi@ARM.com table[0] = entry; 2197734SAli.Saidi@ARM.com 2207734SAli.Saidi@ARM.com inserts++; 22110463SAndreas.Sandberg@ARM.com ppRefills->notify(1); 2226019Shines@cs.fsu.edu} 2236019Shines@cs.fsu.edu 2246019Shines@cs.fsu.eduvoid 22510037SARM gem5 DevelopersTLB::printTlb() const 2267404SAli.Saidi@ARM.com{ 2277404SAli.Saidi@ARM.com int x = 0; 2287404SAli.Saidi@ARM.com TlbEntry *te; 2297404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 2307404SAli.Saidi@ARM.com while (x < size) { 23110037SARM gem5 Developers te = &table[x]; 23210037SARM gem5 Developers if (te->valid) 23310037SARM gem5 Developers DPRINTF(TLB, " * %s\n", te->print()); 23410037SARM gem5 Developers ++x; 2357404SAli.Saidi@ARM.com } 2367404SAli.Saidi@ARM.com} 2377404SAli.Saidi@ARM.com 2387404SAli.Saidi@ARM.comvoid 23914088Sgiacomo.travaglini@arm.comTLB::flushAllSecurity(bool secure_lookup, ExceptionLevel target_el, 24014088Sgiacomo.travaglini@arm.com bool ignore_el) 2416019Shines@cs.fsu.edu{ 24210037SARM gem5 Developers DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 24310037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2447404SAli.Saidi@ARM.com int x = 0; 2457404SAli.Saidi@ARM.com TlbEntry *te; 2467404SAli.Saidi@ARM.com while (x < size) { 24710037SARM gem5 Developers te = &table[x]; 24814088Sgiacomo.travaglini@arm.com const bool el_match = ignore_el ? 24914088Sgiacomo.travaglini@arm.com true : te->checkELMatch(target_el); 25014088Sgiacomo.travaglini@arm.com 25110037SARM gem5 Developers if (te->valid && secure_lookup == !te->nstid && 25214088Sgiacomo.travaglini@arm.com (te->vmid == vmid || secure_lookup) && el_match) { 25310037SARM gem5 Developers 25410037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 25510037SARM gem5 Developers te->valid = false; 25610037SARM gem5 Developers flushedEntries++; 25710037SARM gem5 Developers } 25810037SARM gem5 Developers ++x; 2597404SAli.Saidi@ARM.com } 2607404SAli.Saidi@ARM.com 26110037SARM gem5 Developers flushTlb++; 26210037SARM gem5 Developers 26310037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 26410037SARM gem5 Developers // if we're currently in hyp mode 26510037SARM gem5 Developers if (!isStage2 && isHyp) { 26614088Sgiacomo.travaglini@arm.com stage2Tlb->flushAllSecurity(secure_lookup, EL1, true); 26710037SARM gem5 Developers } 26810037SARM gem5 Developers} 26910037SARM gem5 Developers 27010037SARM gem5 Developersvoid 27114088Sgiacomo.travaglini@arm.comTLB::flushAllNs(ExceptionLevel target_el, bool ignore_el) 27210037SARM gem5 Developers{ 27313882Sgiacomo.travaglini@arm.com bool hyp = target_el == EL2; 27413882Sgiacomo.travaglini@arm.com 27510037SARM gem5 Developers DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 27610037SARM gem5 Developers (hyp ? "hyp" : "non-hyp")); 27710037SARM gem5 Developers int x = 0; 27810037SARM gem5 Developers TlbEntry *te; 27910037SARM gem5 Developers while (x < size) { 28010037SARM gem5 Developers te = &table[x]; 28114088Sgiacomo.travaglini@arm.com const bool el_match = ignore_el ? 28214088Sgiacomo.travaglini@arm.com true : te->checkELMatch(target_el); 28314088Sgiacomo.travaglini@arm.com 28414088Sgiacomo.travaglini@arm.com if (te->valid && te->nstid && te->isHyp == hyp && el_match) { 28510037SARM gem5 Developers 28610037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 28710037SARM gem5 Developers flushedEntries++; 28810037SARM gem5 Developers te->valid = false; 28910037SARM gem5 Developers } 29010037SARM gem5 Developers ++x; 29110037SARM gem5 Developers } 2927734SAli.Saidi@ARM.com 2937734SAli.Saidi@ARM.com flushTlb++; 29410037SARM gem5 Developers 29510037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 29610037SARM gem5 Developers if (!isStage2 && !hyp) { 29714088Sgiacomo.travaglini@arm.com stage2Tlb->flushAllNs(EL1, true); 29810037SARM gem5 Developers } 2996019Shines@cs.fsu.edu} 3006019Shines@cs.fsu.edu 3017404SAli.Saidi@ARM.comvoid 30214088Sgiacomo.travaglini@arm.comTLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 30314088Sgiacomo.travaglini@arm.com ExceptionLevel target_el) 3047404SAli.Saidi@ARM.com{ 30510037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 30610037SARM gem5 Developers "(%s lookup)\n", mva, asn, (secure_lookup ? 30710037SARM gem5 Developers "secure" : "non-secure")); 30813882Sgiacomo.travaglini@arm.com _flushMva(mva, asn, secure_lookup, false, target_el); 3097734SAli.Saidi@ARM.com flushTlbMvaAsid++; 3107404SAli.Saidi@ARM.com} 3117404SAli.Saidi@ARM.com 3127404SAli.Saidi@ARM.comvoid 31314088Sgiacomo.travaglini@arm.comTLB::flushAsid(uint64_t asn, bool secure_lookup, ExceptionLevel target_el) 3147404SAli.Saidi@ARM.com{ 31510037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 31610037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 3177404SAli.Saidi@ARM.com 31810037SARM gem5 Developers int x = 0 ; 3197404SAli.Saidi@ARM.com TlbEntry *te; 3207404SAli.Saidi@ARM.com 3217404SAli.Saidi@ARM.com while (x < size) { 3227404SAli.Saidi@ARM.com te = &table[x]; 32310037SARM gem5 Developers if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 32410037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 32514088Sgiacomo.travaglini@arm.com te->checkELMatch(target_el)) { 32610037SARM gem5 Developers 3277404SAli.Saidi@ARM.com te->valid = false; 32810037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3297734SAli.Saidi@ARM.com flushedEntries++; 3307404SAli.Saidi@ARM.com } 33110037SARM gem5 Developers ++x; 3327404SAli.Saidi@ARM.com } 3337734SAli.Saidi@ARM.com flushTlbAsid++; 3347404SAli.Saidi@ARM.com} 3357404SAli.Saidi@ARM.com 3367404SAli.Saidi@ARM.comvoid 33714088Sgiacomo.travaglini@arm.comTLB::flushMva(Addr mva, bool secure_lookup, ExceptionLevel target_el) 3387404SAli.Saidi@ARM.com{ 33910037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 34010037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 34113882Sgiacomo.travaglini@arm.com _flushMva(mva, 0xbeef, secure_lookup, true, target_el); 34210037SARM gem5 Developers flushTlbMva++; 34310037SARM gem5 Developers} 3447404SAli.Saidi@ARM.com 34510037SARM gem5 Developersvoid 34613882Sgiacomo.travaglini@arm.comTLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, 34714088Sgiacomo.travaglini@arm.com bool ignore_asn, ExceptionLevel target_el) 34810037SARM gem5 Developers{ 3497404SAli.Saidi@ARM.com TlbEntry *te; 35010037SARM gem5 Developers // D5.7.2: Sign-extend address to 64 bits 35110037SARM gem5 Developers mva = sext<56>(mva); 35213882Sgiacomo.travaglini@arm.com 35313882Sgiacomo.travaglini@arm.com bool hyp = target_el == EL2; 35413882Sgiacomo.travaglini@arm.com 35510037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 35610037SARM gem5 Developers target_el); 35710037SARM gem5 Developers while (te != NULL) { 35810037SARM gem5 Developers if (secure_lookup == !te->nstid) { 35910037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3607404SAli.Saidi@ARM.com te->valid = false; 3617734SAli.Saidi@ARM.com flushedEntries++; 3627404SAli.Saidi@ARM.com } 36310037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 36410037SARM gem5 Developers target_el); 3657404SAli.Saidi@ARM.com } 36610037SARM gem5 Developers} 36710037SARM gem5 Developers 36811584SDylan.Johnson@ARM.comvoid 36914088Sgiacomo.travaglini@arm.comTLB::flushIpaVmid(Addr ipa, bool secure_lookup, ExceptionLevel target_el) 37011584SDylan.Johnson@ARM.com{ 37111584SDylan.Johnson@ARM.com assert(!isStage2); 37213882Sgiacomo.travaglini@arm.com stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, true, target_el); 37311584SDylan.Johnson@ARM.com} 37411584SDylan.Johnson@ARM.com 3756019Shines@cs.fsu.eduvoid 3769439SAndreas.Sandberg@ARM.comTLB::drainResume() 3779439SAndreas.Sandberg@ARM.com{ 3789439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 3799439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 3809439SAndreas.Sandberg@ARM.com miscRegValid = false; 3819439SAndreas.Sandberg@ARM.com} 3829439SAndreas.Sandberg@ARM.com 3839439SAndreas.Sandberg@ARM.comvoid 38410194SGeoffrey.Blake@arm.comTLB::takeOverFrom(BaseTLB *_otlb) 38510194SGeoffrey.Blake@arm.com{ 38610194SGeoffrey.Blake@arm.com TLB *otlb = dynamic_cast<TLB*>(_otlb); 38710194SGeoffrey.Blake@arm.com /* Make sure we actually have a valid type */ 38810194SGeoffrey.Blake@arm.com if (otlb) { 38910194SGeoffrey.Blake@arm.com _attr = otlb->_attr; 39010194SGeoffrey.Blake@arm.com haveLPAE = otlb->haveLPAE; 39110194SGeoffrey.Blake@arm.com directToStage2 = otlb->directToStage2; 39210194SGeoffrey.Blake@arm.com stage2Req = otlb->stage2Req; 39313374Sanouk.vanlaer@arm.com stage2DescReq = otlb->stage2DescReq; 39410194SGeoffrey.Blake@arm.com 39510194SGeoffrey.Blake@arm.com /* Sync the stage2 MMU if they exist in both 39610194SGeoffrey.Blake@arm.com * the old CPU and the new 39710194SGeoffrey.Blake@arm.com */ 39810194SGeoffrey.Blake@arm.com if (!isStage2 && 39910194SGeoffrey.Blake@arm.com stage2Tlb && otlb->stage2Tlb) { 40010194SGeoffrey.Blake@arm.com stage2Tlb->takeOverFrom(otlb->stage2Tlb); 40110194SGeoffrey.Blake@arm.com } 40210194SGeoffrey.Blake@arm.com } else { 40310194SGeoffrey.Blake@arm.com panic("Incompatible TLB type!"); 40410194SGeoffrey.Blake@arm.com } 40510194SGeoffrey.Blake@arm.com} 40610194SGeoffrey.Blake@arm.com 40710194SGeoffrey.Blake@arm.comvoid 40810905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 4096019Shines@cs.fsu.edu{ 4107733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 4117733SAli.Saidi@ARM.com 4127733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 41310037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 41410037SARM gem5 Developers SERIALIZE_SCALAR(directToStage2); 41510037SARM gem5 Developers SERIALIZE_SCALAR(stage2Req); 41613374Sanouk.vanlaer@arm.com SERIALIZE_SCALAR(stage2DescReq); 4178353SAli.Saidi@ARM.com 4188353SAli.Saidi@ARM.com int num_entries = size; 4198353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 42011321Ssteve.reinhardt@amd.com for (int i = 0; i < size; i++) 42110905Sandreas.sandberg@arm.com table[i].serializeSection(cp, csprintf("TlbEntry%d", i)); 4226019Shines@cs.fsu.edu} 4236019Shines@cs.fsu.edu 4246019Shines@cs.fsu.eduvoid 42510905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 4266019Shines@cs.fsu.edu{ 4277733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 4286019Shines@cs.fsu.edu 4297733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 43010037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 43110037SARM gem5 Developers UNSERIALIZE_SCALAR(directToStage2); 43210037SARM gem5 Developers UNSERIALIZE_SCALAR(stage2Req); 43313374Sanouk.vanlaer@arm.com UNSERIALIZE_SCALAR(stage2DescReq); 43410037SARM gem5 Developers 4358353SAli.Saidi@ARM.com int num_entries; 4368353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 43711321Ssteve.reinhardt@amd.com for (int i = 0; i < min(size, num_entries); i++) 43810905Sandreas.sandberg@arm.com table[i].unserializeSection(cp, csprintf("TlbEntry%d", i)); 4396019Shines@cs.fsu.edu} 4406019Shines@cs.fsu.edu 4416019Shines@cs.fsu.eduvoid 4426019Shines@cs.fsu.eduTLB::regStats() 4436019Shines@cs.fsu.edu{ 44411522Sstephan.diestelhorst@arm.com BaseTLB::regStats(); 4457734SAli.Saidi@ARM.com instHits 4467734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 4477734SAli.Saidi@ARM.com .desc("ITB inst hits") 4487734SAli.Saidi@ARM.com ; 4497734SAli.Saidi@ARM.com 4507734SAli.Saidi@ARM.com instMisses 4517734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 4527734SAli.Saidi@ARM.com .desc("ITB inst misses") 4537734SAli.Saidi@ARM.com ; 4547734SAli.Saidi@ARM.com 4557734SAli.Saidi@ARM.com instAccesses 4567734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 4577734SAli.Saidi@ARM.com .desc("ITB inst accesses") 4587734SAli.Saidi@ARM.com ; 4597734SAli.Saidi@ARM.com 4607734SAli.Saidi@ARM.com readHits 4616019Shines@cs.fsu.edu .name(name() + ".read_hits") 4626019Shines@cs.fsu.edu .desc("DTB read hits") 4636019Shines@cs.fsu.edu ; 4646019Shines@cs.fsu.edu 4657734SAli.Saidi@ARM.com readMisses 4666019Shines@cs.fsu.edu .name(name() + ".read_misses") 4676019Shines@cs.fsu.edu .desc("DTB read misses") 4686019Shines@cs.fsu.edu ; 4696019Shines@cs.fsu.edu 4707734SAli.Saidi@ARM.com readAccesses 4716019Shines@cs.fsu.edu .name(name() + ".read_accesses") 4726019Shines@cs.fsu.edu .desc("DTB read accesses") 4736019Shines@cs.fsu.edu ; 4746019Shines@cs.fsu.edu 4757734SAli.Saidi@ARM.com writeHits 4766019Shines@cs.fsu.edu .name(name() + ".write_hits") 4776019Shines@cs.fsu.edu .desc("DTB write hits") 4786019Shines@cs.fsu.edu ; 4796019Shines@cs.fsu.edu 4807734SAli.Saidi@ARM.com writeMisses 4816019Shines@cs.fsu.edu .name(name() + ".write_misses") 4826019Shines@cs.fsu.edu .desc("DTB write misses") 4836019Shines@cs.fsu.edu ; 4846019Shines@cs.fsu.edu 4857734SAli.Saidi@ARM.com writeAccesses 4866019Shines@cs.fsu.edu .name(name() + ".write_accesses") 4876019Shines@cs.fsu.edu .desc("DTB write accesses") 4886019Shines@cs.fsu.edu ; 4896019Shines@cs.fsu.edu 4906019Shines@cs.fsu.edu hits 4916019Shines@cs.fsu.edu .name(name() + ".hits") 4926019Shines@cs.fsu.edu .desc("DTB hits") 4936019Shines@cs.fsu.edu ; 4946019Shines@cs.fsu.edu 4956019Shines@cs.fsu.edu misses 4966019Shines@cs.fsu.edu .name(name() + ".misses") 4976019Shines@cs.fsu.edu .desc("DTB misses") 4986019Shines@cs.fsu.edu ; 4996019Shines@cs.fsu.edu 5006019Shines@cs.fsu.edu accesses 5016019Shines@cs.fsu.edu .name(name() + ".accesses") 5026019Shines@cs.fsu.edu .desc("DTB accesses") 5036019Shines@cs.fsu.edu ; 5046019Shines@cs.fsu.edu 5057734SAli.Saidi@ARM.com flushTlb 5067734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 5077734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 5087734SAli.Saidi@ARM.com ; 5097734SAli.Saidi@ARM.com 5107734SAli.Saidi@ARM.com flushTlbMva 5117734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 5127734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 5137734SAli.Saidi@ARM.com ; 5147734SAli.Saidi@ARM.com 5157734SAli.Saidi@ARM.com flushTlbMvaAsid 5167734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 5177734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 5187734SAli.Saidi@ARM.com ; 5197734SAli.Saidi@ARM.com 5207734SAli.Saidi@ARM.com flushTlbAsid 5217734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 5227734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 5237734SAli.Saidi@ARM.com ; 5247734SAli.Saidi@ARM.com 5257734SAli.Saidi@ARM.com flushedEntries 5267734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 5277734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 5287734SAli.Saidi@ARM.com ; 5297734SAli.Saidi@ARM.com 5307734SAli.Saidi@ARM.com alignFaults 5317734SAli.Saidi@ARM.com .name(name() + ".align_faults") 5327734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 5337734SAli.Saidi@ARM.com ; 5347734SAli.Saidi@ARM.com 5357734SAli.Saidi@ARM.com prefetchFaults 5367734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 5377734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 5387734SAli.Saidi@ARM.com ; 5397734SAli.Saidi@ARM.com 5407734SAli.Saidi@ARM.com domainFaults 5417734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 5427734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 5437734SAli.Saidi@ARM.com ; 5447734SAli.Saidi@ARM.com 5457734SAli.Saidi@ARM.com permsFaults 5467734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 5477734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 5487734SAli.Saidi@ARM.com ; 5497734SAli.Saidi@ARM.com 5507734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 5517734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 5527734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 5537734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 5547734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 5557734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 5566019Shines@cs.fsu.edu} 5576019Shines@cs.fsu.edu 55810463SAndreas.Sandberg@ARM.comvoid 55910463SAndreas.Sandberg@ARM.comTLB::regProbePoints() 56010463SAndreas.Sandberg@ARM.com{ 56110463SAndreas.Sandberg@ARM.com ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 56210463SAndreas.Sandberg@ARM.com} 56310463SAndreas.Sandberg@ARM.com 5647404SAli.Saidi@ARM.comFault 56512749Sgiacomo.travaglini@arm.comTLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, 56610037SARM gem5 Developers Translation *translation, bool &delay, bool timing) 5677404SAli.Saidi@ARM.com{ 56810037SARM gem5 Developers updateMiscReg(tc); 56910037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 57010037SARM gem5 Developers Addr vaddr = 0; 57110037SARM gem5 Developers if (aarch64) 57210854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 57310037SARM gem5 Developers else 57410037SARM gem5 Developers vaddr = vaddr_tainted; 57511608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 5767294Sgblack@eecs.umich.edu 5777404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 5787404SAli.Saidi@ARM.com bool is_write = (mode == Write); 5797404SAli.Saidi@ARM.com 5807404SAli.Saidi@ARM.com if (!is_fetch) { 58113968Sjavier.bueno@metempsy.com assert(flags & MustBeOne || req->isPrefetch()); 5827404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 58310037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 58410037SARM gem5 Developers // LPAE is always disabled in SE mode 58510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 58610474Sandreas.hansson@arm.com vaddr_tainted, 58710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 58810474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 58910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 5907294Sgblack@eecs.umich.edu } 5917294Sgblack@eecs.umich.edu } 5927294Sgblack@eecs.umich.edu } 5936019Shines@cs.fsu.edu 5947093Sgblack@eecs.umich.edu Addr paddr; 5957404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 5967404SAli.Saidi@ARM.com 5977093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 59810474Sandreas.hansson@arm.com return std::make_shared<GenericPageTableFault>(vaddr_tainted); 5997093Sgblack@eecs.umich.edu req->setPaddr(paddr); 6006019Shines@cs.fsu.edu 60112005Sandreas.sandberg@arm.com return finalizePhysical(req, tc, mode); 6027404SAli.Saidi@ARM.com} 6037404SAli.Saidi@ARM.com 6047404SAli.Saidi@ARM.comFault 60512749Sgiacomo.travaglini@arm.comTLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode) 60610037SARM gem5 Developers{ 60712506Snikos.nikoleris@arm.com // a data cache maintenance instruction that operates by MVA does 60812506Snikos.nikoleris@arm.com // not generate a Data Abort exeception due to a Permission fault 60912506Snikos.nikoleris@arm.com if (req->isCacheMaintenance()) { 61012506Snikos.nikoleris@arm.com return NoFault; 61112506Snikos.nikoleris@arm.com } 61212506Snikos.nikoleris@arm.com 61310037SARM gem5 Developers Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 61411608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 61510037SARM gem5 Developers bool is_fetch = (mode == Execute); 61610037SARM gem5 Developers bool is_write = (mode == Write); 61710037SARM gem5 Developers bool is_priv = isPriv && !(flags & UserMode); 61810037SARM gem5 Developers 61910037SARM gem5 Developers // Get the translation type from the actuall table entry 62010037SARM gem5 Developers ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 62110037SARM gem5 Developers : ArmFault::VmsaTran; 62210037SARM gem5 Developers 62310037SARM gem5 Developers // If this is the second stage of translation and the request is for a 62410037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 62510037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 62610037SARM gem5 Developers // as a device or strongly ordered. 62710037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 62810037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 62910474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 63010474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 63110474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 63210474Sandreas.hansson@arm.com isStage2, tranMethod); 63310037SARM gem5 Developers } 63410037SARM gem5 Developers 63510037SARM gem5 Developers // Generate an alignment fault for unaligned data accesses to device or 63610037SARM gem5 Developers // strongly ordered memory 63710037SARM gem5 Developers if (!is_fetch) { 63810037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 63910037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 64010037SARM gem5 Developers alignFaults++; 64110474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 64210474Sandreas.hansson@arm.com vaddr, TlbEntry::DomainType::NoAccess, is_write, 64310474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 64410474Sandreas.hansson@arm.com tranMethod); 64510037SARM gem5 Developers } 64610037SARM gem5 Developers } 64710037SARM gem5 Developers } 64810037SARM gem5 Developers 64910037SARM gem5 Developers if (te->nonCacheable) { 65010037SARM gem5 Developers // Prevent prefetching from I/O devices. 65110037SARM gem5 Developers if (req->isPrefetch()) { 65210037SARM gem5 Developers // Here we can safely use the fault status for the short 65310037SARM gem5 Developers // desc. format in all cases 65410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 65510474Sandreas.hansson@arm.com vaddr, ArmFault::PrefetchUncacheable, 65610474Sandreas.hansson@arm.com isStage2, tranMethod); 65710037SARM gem5 Developers } 65810037SARM gem5 Developers } 65910037SARM gem5 Developers 66010037SARM gem5 Developers if (!te->longDescFormat) { 66110037SARM gem5 Developers switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 66210037SARM gem5 Developers case 0: 66310037SARM gem5 Developers domainFaults++; 66410037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 66510037SARM gem5 Developers " domain: %#x write:%d\n", dacr, 66610037SARM gem5 Developers static_cast<uint8_t>(te->domain), is_write); 66711861Snikos.nikoleris@arm.com if (is_fetch) { 66811861Snikos.nikoleris@arm.com // Use PC value instead of vaddr because vaddr might 66911861Snikos.nikoleris@arm.com // be aligned to cache line and should not be the 67011861Snikos.nikoleris@arm.com // address reported in FAR 67110474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 67211861Snikos.nikoleris@arm.com req->getPC(), 67310474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 67410474Sandreas.hansson@arm.com isStage2, tranMethod); 67511861Snikos.nikoleris@arm.com } else 67610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 67710474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 67810474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 67910474Sandreas.hansson@arm.com isStage2, tranMethod); 68010037SARM gem5 Developers case 1: 68110037SARM gem5 Developers // Continue with permissions check 68210037SARM gem5 Developers break; 68310037SARM gem5 Developers case 2: 68410037SARM gem5 Developers panic("UNPRED domain\n"); 68510037SARM gem5 Developers case 3: 68610037SARM gem5 Developers return NoFault; 68710037SARM gem5 Developers } 68810037SARM gem5 Developers } 68910037SARM gem5 Developers 69010037SARM gem5 Developers // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 69110037SARM gem5 Developers uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 69210037SARM gem5 Developers uint8_t hap = te->hap; 69310037SARM gem5 Developers 69410037SARM gem5 Developers if (sctlr.afe == 1 || te->longDescFormat) 69510037SARM gem5 Developers ap |= 1; 69610037SARM gem5 Developers 69710037SARM gem5 Developers bool abt; 69810037SARM gem5 Developers bool isWritable = true; 69910037SARM gem5 Developers // If this is a stage 2 access (eg for reading stage 1 page table entries) 70010037SARM gem5 Developers // then don't perform the AP permissions check, we stil do the HAP check 70110037SARM gem5 Developers // below. 70210037SARM gem5 Developers if (isStage2) { 70310037SARM gem5 Developers abt = false; 70410037SARM gem5 Developers } else { 70510037SARM gem5 Developers switch (ap) { 70610037SARM gem5 Developers case 0: 70710037SARM gem5 Developers DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 70810037SARM gem5 Developers (int)sctlr.rs); 70910037SARM gem5 Developers if (!sctlr.xp) { 71010037SARM gem5 Developers switch ((int)sctlr.rs) { 71110037SARM gem5 Developers case 2: 71210037SARM gem5 Developers abt = is_write; 71310037SARM gem5 Developers break; 71410037SARM gem5 Developers case 1: 71510037SARM gem5 Developers abt = is_write || !is_priv; 71610037SARM gem5 Developers break; 71710037SARM gem5 Developers case 0: 71810037SARM gem5 Developers case 3: 71910037SARM gem5 Developers default: 72010037SARM gem5 Developers abt = true; 72110037SARM gem5 Developers break; 72210037SARM gem5 Developers } 72310037SARM gem5 Developers } else { 72410037SARM gem5 Developers abt = true; 72510037SARM gem5 Developers } 72610037SARM gem5 Developers break; 72710037SARM gem5 Developers case 1: 72810037SARM gem5 Developers abt = !is_priv; 72910037SARM gem5 Developers break; 73010037SARM gem5 Developers case 2: 73110037SARM gem5 Developers abt = !is_priv && is_write; 73210037SARM gem5 Developers isWritable = is_priv; 73310037SARM gem5 Developers break; 73410037SARM gem5 Developers case 3: 73510037SARM gem5 Developers abt = false; 73610037SARM gem5 Developers break; 73710037SARM gem5 Developers case 4: 73810037SARM gem5 Developers panic("UNPRED premissions\n"); 73910037SARM gem5 Developers case 5: 74010037SARM gem5 Developers abt = !is_priv || is_write; 74110037SARM gem5 Developers isWritable = false; 74210037SARM gem5 Developers break; 74310037SARM gem5 Developers case 6: 74410037SARM gem5 Developers case 7: 74510037SARM gem5 Developers abt = is_write; 74610037SARM gem5 Developers isWritable = false; 74710037SARM gem5 Developers break; 74810037SARM gem5 Developers default: 74910037SARM gem5 Developers panic("Unknown permissions %#x\n", ap); 75010037SARM gem5 Developers } 75110037SARM gem5 Developers } 75210037SARM gem5 Developers 75310037SARM gem5 Developers bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 75410037SARM gem5 Developers bool xn = te->xn || (isWritable && sctlr.wxn) || 75510037SARM gem5 Developers (ap == 3 && sctlr.uwxn && is_priv); 75610037SARM gem5 Developers if (is_fetch && (abt || xn || 75711495Sandreas.sandberg@arm.com (te->longDescFormat && te->pxn && is_priv) || 75810037SARM gem5 Developers (isSecure && te->ns && scr.sif))) { 75910037SARM gem5 Developers permsFaults++; 76010037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 76110037SARM gem5 Developers "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 76210037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 76311861Snikos.nikoleris@arm.com // Use PC value instead of vaddr because vaddr might be aligned to 76411861Snikos.nikoleris@arm.com // cache line and should not be the address reported in FAR 76510474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 76611861Snikos.nikoleris@arm.com req->getPC(), 76710474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 76810474Sandreas.hansson@arm.com isStage2, tranMethod); 76910037SARM gem5 Developers } else if (abt | hapAbt) { 77010037SARM gem5 Developers permsFaults++; 77110037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 77210037SARM gem5 Developers " write:%d\n", ap, is_priv, is_write); 77310474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 77410474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 77510474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 77610474Sandreas.hansson@arm.com isStage2 | !abt, tranMethod); 77710037SARM gem5 Developers } 77810037SARM gem5 Developers return NoFault; 77910037SARM gem5 Developers} 78010037SARM gem5 Developers 78110037SARM gem5 Developers 78210037SARM gem5 DevelopersFault 78312749Sgiacomo.travaglini@arm.comTLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, 78410037SARM gem5 Developers ThreadContext *tc) 78510037SARM gem5 Developers{ 78610037SARM gem5 Developers assert(aarch64); 78710037SARM gem5 Developers 78812506Snikos.nikoleris@arm.com // A data cache maintenance instruction that operates by VA does 78912506Snikos.nikoleris@arm.com // not generate a Permission fault unless: 79012506Snikos.nikoleris@arm.com // * It is a data cache invalidate (dc ivac) which requires write 79112506Snikos.nikoleris@arm.com // permissions to the VA, or 79212506Snikos.nikoleris@arm.com // * It is executed from EL0 79312506Snikos.nikoleris@arm.com if (req->isCacheClean() && aarch64EL != EL0 && !isStage2) { 79412506Snikos.nikoleris@arm.com return NoFault; 79512506Snikos.nikoleris@arm.com } 79612506Snikos.nikoleris@arm.com 79710037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 79810854SNathanael.Premillieu@arm.com Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 79910037SARM gem5 Developers 80011608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 80110037SARM gem5 Developers bool is_fetch = (mode == Execute); 80212506Snikos.nikoleris@arm.com // Cache clean operations require read permissions to the specified VA 80312506Snikos.nikoleris@arm.com bool is_write = !req->isCacheClean() && mode == Write; 80410037SARM gem5 Developers bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 80510037SARM gem5 Developers 80610037SARM gem5 Developers updateMiscReg(tc, curTranType); 80710037SARM gem5 Developers 80810037SARM gem5 Developers // If this is the second stage of translation and the request is for a 80910037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 81010037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 81110037SARM gem5 Developers // as a device or strongly ordered. 81210037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 81310037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 81410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 81510474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 81610474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 81710474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 81810037SARM gem5 Developers } 81910037SARM gem5 Developers 82010037SARM gem5 Developers // Generate an alignment fault for unaligned accesses to device or 82110037SARM gem5 Developers // strongly ordered memory 82210037SARM gem5 Developers if (!is_fetch) { 82310037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 82410037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 82510037SARM gem5 Developers alignFaults++; 82610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 82710474Sandreas.hansson@arm.com vaddr_tainted, 82810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 82910474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 83010474Sandreas.hansson@arm.com ArmFault::LpaeTran); 83110037SARM gem5 Developers } 83210037SARM gem5 Developers } 83310037SARM gem5 Developers } 83410037SARM gem5 Developers 83510037SARM gem5 Developers if (te->nonCacheable) { 83610037SARM gem5 Developers // Prevent prefetching from I/O devices. 83710037SARM gem5 Developers if (req->isPrefetch()) { 83810037SARM gem5 Developers // Here we can safely use the fault status for the short 83910037SARM gem5 Developers // desc. format in all cases 84010474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 84110474Sandreas.hansson@arm.com vaddr_tainted, 84210474Sandreas.hansson@arm.com ArmFault::PrefetchUncacheable, 84310474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 84410037SARM gem5 Developers } 84510037SARM gem5 Developers } 84610037SARM gem5 Developers 84710037SARM gem5 Developers uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 84810037SARM gem5 Developers bool grant = false; 84910037SARM gem5 Developers 85010037SARM gem5 Developers uint8_t xn = te->xn; 85110037SARM gem5 Developers uint8_t pxn = te->pxn; 85210037SARM gem5 Developers bool r = !is_write && !is_fetch; 85310037SARM gem5 Developers bool w = is_write; 85410037SARM gem5 Developers bool x = is_fetch; 85510037SARM gem5 Developers DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 85610037SARM gem5 Developers "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 85710037SARM gem5 Developers 85810037SARM gem5 Developers if (isStage2) { 85911575SDylan.Johnson@ARM.com assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2); 86011575SDylan.Johnson@ARM.com // In stage 2 we use the hypervisor access permission bits. 86111575SDylan.Johnson@ARM.com // The following permissions are described in ARM DDI 0487A.f 86211575SDylan.Johnson@ARM.com // D4-1802 86311575SDylan.Johnson@ARM.com uint8_t hap = 0x3 & te->hap; 86411575SDylan.Johnson@ARM.com if (is_fetch) { 86511575SDylan.Johnson@ARM.com // sctlr.wxn overrides the xn bit 86611575SDylan.Johnson@ARM.com grant = !sctlr.wxn && !xn; 86711575SDylan.Johnson@ARM.com } else if (is_write) { 86811575SDylan.Johnson@ARM.com grant = hap & 0x2; 86911575SDylan.Johnson@ARM.com } else { // is_read 87011575SDylan.Johnson@ARM.com grant = hap & 0x1; 87111575SDylan.Johnson@ARM.com } 87210037SARM gem5 Developers } else { 87310037SARM gem5 Developers switch (aarch64EL) { 87410037SARM gem5 Developers case EL0: 87510037SARM gem5 Developers { 87610037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 87710037SARM gem5 Developers switch (perm) { 87810037SARM gem5 Developers case 0: 87910037SARM gem5 Developers case 1: 88010037SARM gem5 Developers case 8: 88110037SARM gem5 Developers case 9: 88210037SARM gem5 Developers grant = x; 88310037SARM gem5 Developers break; 88410037SARM gem5 Developers case 4: 88510037SARM gem5 Developers case 5: 88610037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 88710037SARM gem5 Developers break; 88810037SARM gem5 Developers case 6: 88910037SARM gem5 Developers case 7: 89010037SARM gem5 Developers grant = r || w; 89110037SARM gem5 Developers break; 89210037SARM gem5 Developers case 12: 89310037SARM gem5 Developers case 13: 89410037SARM gem5 Developers grant = r || x; 89510037SARM gem5 Developers break; 89610037SARM gem5 Developers case 14: 89710037SARM gem5 Developers case 15: 89810037SARM gem5 Developers grant = r; 89910037SARM gem5 Developers break; 90010037SARM gem5 Developers default: 90110037SARM gem5 Developers grant = false; 90210037SARM gem5 Developers } 90310037SARM gem5 Developers } 90410037SARM gem5 Developers break; 90510037SARM gem5 Developers case EL1: 90610037SARM gem5 Developers { 90714128Sgiacomo.travaglini@arm.com if (checkPAN(tc, ap, req, mode)) { 90814128Sgiacomo.travaglini@arm.com grant = false; 90914128Sgiacomo.travaglini@arm.com break; 91014128Sgiacomo.travaglini@arm.com } 91114128Sgiacomo.travaglini@arm.com 91210037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 91310037SARM gem5 Developers switch (perm) { 91410037SARM gem5 Developers case 0: 91510037SARM gem5 Developers case 2: 91610037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 91710037SARM gem5 Developers break; 91810037SARM gem5 Developers case 1: 91910037SARM gem5 Developers case 3: 92010037SARM gem5 Developers case 4: 92110037SARM gem5 Developers case 5: 92210037SARM gem5 Developers case 6: 92310037SARM gem5 Developers case 7: 92410037SARM gem5 Developers // regions that are writeable at EL0 should not be 92510037SARM gem5 Developers // executable at EL1 92610037SARM gem5 Developers grant = r || w; 92710037SARM gem5 Developers break; 92810037SARM gem5 Developers case 8: 92910037SARM gem5 Developers case 10: 93010037SARM gem5 Developers case 12: 93110037SARM gem5 Developers case 14: 93210037SARM gem5 Developers grant = r || x; 93310037SARM gem5 Developers break; 93410037SARM gem5 Developers case 9: 93510037SARM gem5 Developers case 11: 93610037SARM gem5 Developers case 13: 93710037SARM gem5 Developers case 15: 93810037SARM gem5 Developers grant = r; 93910037SARM gem5 Developers break; 94010037SARM gem5 Developers default: 94110037SARM gem5 Developers grant = false; 94210037SARM gem5 Developers } 94310037SARM gem5 Developers } 94410037SARM gem5 Developers break; 94510037SARM gem5 Developers case EL2: 94614278Sgiacomo.travaglini@arm.com if (hcr.e2h && checkPAN(tc, ap, req, mode)) { 94714128Sgiacomo.travaglini@arm.com grant = false; 94814128Sgiacomo.travaglini@arm.com break; 94914128Sgiacomo.travaglini@arm.com } 95014128Sgiacomo.travaglini@arm.com M5_FALLTHROUGH; 95110037SARM gem5 Developers case EL3: 95210037SARM gem5 Developers { 95310037SARM gem5 Developers uint8_t perm = (ap & 0x2) | xn; 95410037SARM gem5 Developers switch (perm) { 95510037SARM gem5 Developers case 0: 95610037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn) ; 95710037SARM gem5 Developers break; 95810037SARM gem5 Developers case 1: 95910037SARM gem5 Developers grant = r || w; 96010037SARM gem5 Developers break; 96110037SARM gem5 Developers case 2: 96210037SARM gem5 Developers grant = r || x; 96310037SARM gem5 Developers break; 96410037SARM gem5 Developers case 3: 96510037SARM gem5 Developers grant = r; 96610037SARM gem5 Developers break; 96710037SARM gem5 Developers default: 96810037SARM gem5 Developers grant = false; 96910037SARM gem5 Developers } 97010037SARM gem5 Developers } 97110037SARM gem5 Developers break; 97210037SARM gem5 Developers } 97310037SARM gem5 Developers } 97410037SARM gem5 Developers 97510037SARM gem5 Developers if (!grant) { 97610037SARM gem5 Developers if (is_fetch) { 97710037SARM gem5 Developers permsFaults++; 97810037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 97910037SARM gem5 Developers "AP:%d priv:%d write:%d ns:%d sif:%d " 98010037SARM gem5 Developers "sctlr.afe: %d\n", 98110037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 98210037SARM gem5 Developers // Use PC value instead of vaddr because vaddr might be aligned to 98310037SARM gem5 Developers // cache line and should not be the address reported in FAR 98410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 98510474Sandreas.hansson@arm.com req->getPC(), 98610474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 98710474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 98810037SARM gem5 Developers } else { 98910037SARM gem5 Developers permsFaults++; 99010037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 99110037SARM gem5 Developers "priv:%d write:%d\n", ap, is_priv, is_write); 99210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 99310474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 99410474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 99510474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 99610037SARM gem5 Developers } 99710037SARM gem5 Developers } 99810037SARM gem5 Developers 99910037SARM gem5 Developers return NoFault; 100010037SARM gem5 Developers} 100110037SARM gem5 Developers 100214128Sgiacomo.travaglini@arm.combool 100314128Sgiacomo.travaglini@arm.comTLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode) 100414128Sgiacomo.travaglini@arm.com{ 100514128Sgiacomo.travaglini@arm.com // The PAN bit has no effect on: 100614128Sgiacomo.travaglini@arm.com // 1) Instruction accesses. 100714128Sgiacomo.travaglini@arm.com // 2) Data Cache instructions other than DC ZVA 100814128Sgiacomo.travaglini@arm.com // 3) Address translation instructions, other than ATS1E1RP and 100914128Sgiacomo.travaglini@arm.com // ATS1E1WP when ARMv8.2-ATS1E1 is implemented. (Unimplemented in 101014128Sgiacomo.travaglini@arm.com // gem5) 101114128Sgiacomo.travaglini@arm.com // 4) Unprivileged instructions (Unimplemented in gem5) 101214128Sgiacomo.travaglini@arm.com AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1); 101314128Sgiacomo.travaglini@arm.com if (mmfr1.pan && cpsr.pan && (ap & 0x1) && mode != Execute && 101414128Sgiacomo.travaglini@arm.com (!req->isCacheMaintenance() || 101514128Sgiacomo.travaglini@arm.com (req->getFlags() & Request::CACHE_BLOCK_ZERO))) { 101614128Sgiacomo.travaglini@arm.com return true; 101714128Sgiacomo.travaglini@arm.com } else { 101814128Sgiacomo.travaglini@arm.com return false; 101914128Sgiacomo.travaglini@arm.com } 102014128Sgiacomo.travaglini@arm.com} 102114128Sgiacomo.travaglini@arm.com 102210037SARM gem5 DevelopersFault 102312749Sgiacomo.travaglini@arm.comTLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, 102410037SARM gem5 Developers Translation *translation, bool &delay, bool timing, 102510037SARM gem5 Developers TLB::ArmTranslationType tranType, bool functional) 10267404SAli.Saidi@ARM.com{ 10278733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 10288733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 10298733Sgeoffrey.blake@arm.com 103010037SARM gem5 Developers updateMiscReg(tc, tranType); 103110037SARM gem5 Developers 103210037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 103310037SARM gem5 Developers Addr vaddr = 0; 103410037SARM gem5 Developers if (aarch64) 103510854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 103610037SARM gem5 Developers else 103710037SARM gem5 Developers vaddr = vaddr_tainted; 103811608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 103910037SARM gem5 Developers 104010037SARM gem5 Developers bool is_fetch = (mode == Execute); 104110037SARM gem5 Developers bool is_write = (mode == Write); 104211517SCurtis.Dunham@arm.com bool long_desc_format = aarch64 || longDescFormatInUse(tc); 104310037SARM gem5 Developers ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 104410037SARM gem5 Developers : ArmFault::VmsaTran; 104510037SARM gem5 Developers 104610037SARM gem5 Developers req->setAsid(asid); 104710037SARM gem5 Developers 104810037SARM gem5 Developers DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 104910037SARM gem5 Developers isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 105010037SARM gem5 Developers 105110037SARM gem5 Developers DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 105211608Snikos.nikoleris@arm.com "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2, 105310037SARM gem5 Developers scr, sctlr, flags, tranType); 105410037SARM gem5 Developers 10557608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 10567608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 105712356Snikos.nikoleris@arm.com if (!req->isCacheMaintenance()) { 105812356Snikos.nikoleris@arm.com req->setFlags(Request::UNCACHEABLE); 105912356Snikos.nikoleris@arm.com } 106012356Snikos.nikoleris@arm.com req->setFlags(Request::STRICT_ORDER); 10617608SGene.Wu@arm.com } 10627404SAli.Saidi@ARM.com if (!is_fetch) { 106313968Sjavier.bueno@metempsy.com assert(flags & MustBeOne || req->isPrefetch()); 10647404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 106510037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 10667734SAli.Saidi@ARM.com alignFaults++; 106710474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 106810474Sandreas.hansson@arm.com vaddr_tainted, 106910474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 107010474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 107110474Sandreas.hansson@arm.com tranMethod); 10727404SAli.Saidi@ARM.com } 10737404SAli.Saidi@ARM.com } 10747404SAli.Saidi@ARM.com } 10757404SAli.Saidi@ARM.com 107610037SARM gem5 Developers // If guest MMU is off or hcr.vm=0 go straight to stage2 107710037SARM gem5 Developers if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 10787404SAli.Saidi@ARM.com 10797093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 108010037SARM gem5 Developers // When the MMU is off the security attribute corresponds to the 108110037SARM gem5 Developers // security state of the processor 108210037SARM gem5 Developers if (isSecure) 108310037SARM gem5 Developers req->setFlags(Request::SECURE); 108410037SARM gem5 Developers 108510037SARM gem5 Developers // @todo: double check this (ARM ARM issue C B3.2.1) 108612356Snikos.nikoleris@arm.com if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 || 108712356Snikos.nikoleris@arm.com nmrr.or0 == 0 || prrr.tr0 != 0x2) { 108812356Snikos.nikoleris@arm.com if (!req->isCacheMaintenance()) { 108912356Snikos.nikoleris@arm.com req->setFlags(Request::UNCACHEABLE); 109012356Snikos.nikoleris@arm.com } 109112356Snikos.nikoleris@arm.com req->setFlags(Request::STRICT_ORDER); 10927404SAli.Saidi@ARM.com } 10937436Sdam.sunwoo@arm.com 10947436Sdam.sunwoo@arm.com // Set memory attributes 10957436Sdam.sunwoo@arm.com TlbEntry temp_te; 109610037SARM gem5 Developers temp_te.ns = !isSecure; 109710037SARM gem5 Developers if (isStage2 || hcr.dc == 0 || isSecure || 109810037SARM gem5 Developers (isHyp && !(tranType & S1CTran))) { 109910037SARM gem5 Developers 110010037SARM gem5 Developers temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 110110037SARM gem5 Developers : TlbEntry::MemoryType::StronglyOrdered; 110210037SARM gem5 Developers temp_te.innerAttrs = 0x0; 110310037SARM gem5 Developers temp_te.outerAttrs = 0x0; 110410037SARM gem5 Developers temp_te.shareable = true; 110510037SARM gem5 Developers temp_te.outerShareable = true; 110610037SARM gem5 Developers } else { 110710037SARM gem5 Developers temp_te.mtype = TlbEntry::MemoryType::Normal; 110810037SARM gem5 Developers temp_te.innerAttrs = 0x3; 110910037SARM gem5 Developers temp_te.outerAttrs = 0x3; 111010037SARM gem5 Developers temp_te.shareable = false; 111110037SARM gem5 Developers temp_te.outerShareable = false; 111210037SARM gem5 Developers } 111310037SARM gem5 Developers temp_te.setAttributes(long_desc_format); 111410367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 111510367SAndrew.Bardsley@arm.com "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 111610037SARM gem5 Developers temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 111710037SARM gem5 Developers isStage2); 11187436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 11197436Sdam.sunwoo@arm.com 112011395Sandreas.sandberg@arm.com return testTranslation(req, mode, TlbEntry::DomainType::NoAccess); 11217404SAli.Saidi@ARM.com } 11227404SAli.Saidi@ARM.com 112310037SARM gem5 Developers DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 112410037SARM gem5 Developers isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 11257404SAli.Saidi@ARM.com // Translation enabled 11267404SAli.Saidi@ARM.com 112710037SARM gem5 Developers TlbEntry *te = NULL; 112810037SARM gem5 Developers TlbEntry mergeTe; 112910037SARM gem5 Developers Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 113010037SARM gem5 Developers functional, &mergeTe); 113110037SARM gem5 Developers // only proceed if we have a valid table entry 113210037SARM gem5 Developers if ((te == NULL) && (fault == NoFault)) delay = true; 113310037SARM gem5 Developers 113410037SARM gem5 Developers // If we have the table entry transfer some of the attributes to the 113510037SARM gem5 Developers // request that triggered the translation 113610037SARM gem5 Developers if (te != NULL) { 113710037SARM gem5 Developers // Set memory attributes 113810037SARM gem5 Developers DPRINTF(TLBVerbose, 113910367SAndrew.Bardsley@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, " 114010367SAndrew.Bardsley@arm.com "outerAttrs: %d, mtype: %d, isStage2: %d\n", 114110037SARM gem5 Developers te->shareable, te->innerAttrs, te->outerAttrs, 114210037SARM gem5 Developers static_cast<uint8_t>(te->mtype), isStage2); 114310037SARM gem5 Developers setAttr(te->attributes); 114410824SAndreas.Sandberg@ARM.com 114512356Snikos.nikoleris@arm.com if (te->nonCacheable && !req->isCacheMaintenance()) 114610825SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE); 114710825SAndreas.Sandberg@ARM.com 114810825SAndreas.Sandberg@ARM.com // Require requests to be ordered if the request goes to 114910825SAndreas.Sandberg@ARM.com // strongly ordered or device memory (i.e., anything other 115010825SAndreas.Sandberg@ARM.com // than normal memory requires strict order). 115110825SAndreas.Sandberg@ARM.com if (te->mtype != TlbEntry::MemoryType::Normal) 115210825SAndreas.Sandberg@ARM.com req->setFlags(Request::STRICT_ORDER); 115310037SARM gem5 Developers 115410508SAli.Saidi@ARM.com Addr pa = te->pAddr(vaddr); 115510508SAli.Saidi@ARM.com req->setPaddr(pa); 115610508SAli.Saidi@ARM.com 115710037SARM gem5 Developers if (isSecure && !te->ns) { 115810037SARM gem5 Developers req->setFlags(Request::SECURE); 115910037SARM gem5 Developers } 116010037SARM gem5 Developers if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 116110037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 116210037SARM gem5 Developers // Unaligned accesses to Device memory should always cause an 116310037SARM gem5 Developers // abort regardless of sctlr.a 116410037SARM gem5 Developers alignFaults++; 116510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 116610474Sandreas.hansson@arm.com vaddr_tainted, 116710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 116810474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 116910474Sandreas.hansson@arm.com tranMethod); 117010037SARM gem5 Developers } 117110037SARM gem5 Developers 117210037SARM gem5 Developers // Check for a trickbox generated address fault 117311395Sandreas.sandberg@arm.com if (fault == NoFault) 117411395Sandreas.sandberg@arm.com fault = testTranslation(req, mode, te->domain); 117510037SARM gem5 Developers } 117610037SARM gem5 Developers 117710037SARM gem5 Developers if (fault == NoFault) { 117812005Sandreas.sandberg@arm.com // Don't try to finalize a physical address unless the 117912005Sandreas.sandberg@arm.com // translation has completed (i.e., there is a table entry). 118012005Sandreas.sandberg@arm.com return te ? finalizePhysical(req, tc, mode) : NoFault; 118112005Sandreas.sandberg@arm.com } else { 118212005Sandreas.sandberg@arm.com return fault; 118310037SARM gem5 Developers } 118410037SARM gem5 Developers} 118510037SARM gem5 Developers 118610037SARM gem5 DevelopersFault 118712749Sgiacomo.travaglini@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, 118810037SARM gem5 Developers TLB::ArmTranslationType tranType) 118910037SARM gem5 Developers{ 119010037SARM gem5 Developers updateMiscReg(tc, tranType); 119110037SARM gem5 Developers 119210037SARM gem5 Developers if (directToStage2) { 119310037SARM gem5 Developers assert(stage2Tlb); 119410037SARM gem5 Developers return stage2Tlb->translateAtomic(req, tc, mode, tranType); 119510037SARM gem5 Developers } 119610037SARM gem5 Developers 119710037SARM gem5 Developers bool delay = false; 119810037SARM gem5 Developers Fault fault; 119910037SARM gem5 Developers if (FullSystem) 120010037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 120110037SARM gem5 Developers else 120210037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 120310037SARM gem5 Developers assert(!delay); 120410037SARM gem5 Developers return fault; 120510037SARM gem5 Developers} 120610037SARM gem5 Developers 120710037SARM gem5 DevelopersFault 120812749Sgiacomo.travaglini@arm.comTLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode, 120910037SARM gem5 Developers TLB::ArmTranslationType tranType) 121010037SARM gem5 Developers{ 121110037SARM gem5 Developers updateMiscReg(tc, tranType); 121210037SARM gem5 Developers 121310037SARM gem5 Developers if (directToStage2) { 121410037SARM gem5 Developers assert(stage2Tlb); 121510037SARM gem5 Developers return stage2Tlb->translateFunctional(req, tc, mode, tranType); 121610037SARM gem5 Developers } 121710037SARM gem5 Developers 121810037SARM gem5 Developers bool delay = false; 121910037SARM gem5 Developers Fault fault; 122010037SARM gem5 Developers if (FullSystem) 122110037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 122210037SARM gem5 Developers else 122310037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 122410037SARM gem5 Developers assert(!delay); 122510037SARM gem5 Developers return fault; 122610037SARM gem5 Developers} 122710037SARM gem5 Developers 122812406Sgabeblack@google.comvoid 122912749Sgiacomo.travaglini@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 123010037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 123110037SARM gem5 Developers{ 123210037SARM gem5 Developers updateMiscReg(tc, tranType); 123310037SARM gem5 Developers 123410037SARM gem5 Developers if (directToStage2) { 123510037SARM gem5 Developers assert(stage2Tlb); 123612406Sgabeblack@google.com stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 123712406Sgabeblack@google.com return; 123810037SARM gem5 Developers } 123910037SARM gem5 Developers 124010037SARM gem5 Developers assert(translation); 124110037SARM gem5 Developers 124212406Sgabeblack@google.com translateComplete(req, tc, translation, mode, tranType, isStage2); 124310037SARM gem5 Developers} 124410037SARM gem5 Developers 124510037SARM gem5 DevelopersFault 124612749Sgiacomo.travaglini@arm.comTLB::translateComplete(const RequestPtr &req, ThreadContext *tc, 124710037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 124810037SARM gem5 Developers bool callFromS2) 124910037SARM gem5 Developers{ 125010037SARM gem5 Developers bool delay = false; 125110037SARM gem5 Developers Fault fault; 125210037SARM gem5 Developers if (FullSystem) 125310037SARM gem5 Developers fault = translateFs(req, tc, mode, translation, delay, true, tranType); 125410037SARM gem5 Developers else 125510037SARM gem5 Developers fault = translateSe(req, tc, mode, translation, delay, true); 125610037SARM gem5 Developers DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 125710037SARM gem5 Developers NoFault); 125810037SARM gem5 Developers // If we have a translation, and we're not in the middle of doing a stage 125910037SARM gem5 Developers // 2 translation tell the translation that we've either finished or its 126010037SARM gem5 Developers // going to take a while. By not doing this when we're in the middle of a 126110037SARM gem5 Developers // stage 2 translation we prevent marking the translation as delayed twice, 126210037SARM gem5 Developers // one when the translation starts and again when the stage 1 translation 126310037SARM gem5 Developers // completes. 126410037SARM gem5 Developers if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 126510037SARM gem5 Developers if (!delay) 126610037SARM gem5 Developers translation->finish(fault, req, tc, mode); 126710037SARM gem5 Developers else 126810037SARM gem5 Developers translation->markDelayed(); 126910037SARM gem5 Developers } 127010037SARM gem5 Developers return fault; 127110037SARM gem5 Developers} 127210037SARM gem5 Developers 127313784Sgabeblack@google.comPort * 127413784Sgabeblack@google.comTLB::getTableWalkerPort() 127510037SARM gem5 Developers{ 127613795SAndrea.Mondelli@ucf.edu return &stage2Mmu->getDMAPort(); 127710037SARM gem5 Developers} 127810037SARM gem5 Developers 127910037SARM gem5 Developersvoid 128010037SARM gem5 DevelopersTLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 128110037SARM gem5 Developers{ 128210037SARM gem5 Developers // check if the regs have changed, or the translation mode is different. 128310037SARM gem5 Developers // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 128410037SARM gem5 Developers // one type of translation anyway 128511152Smitch.hayenga@arm.com if (miscRegValid && miscRegContext == tc->contextId() && 128611152Smitch.hayenga@arm.com ((tranType == curTranType) || isStage2)) { 128710037SARM gem5 Developers return; 128810037SARM gem5 Developers } 128910037SARM gem5 Developers 129010037SARM gem5 Developers DPRINTF(TLBVerbose, "TLB variables changed!\n"); 129110854SNathanael.Premillieu@arm.com cpsr = tc->readMiscReg(MISCREG_CPSR); 129211505Sandreas.sandberg@arm.com 129310037SARM gem5 Developers // Dependencies: SCR/SCR_EL3, CPSR 129411505Sandreas.sandberg@arm.com isSecure = inSecureState(tc) && 129511505Sandreas.sandberg@arm.com !(tranType & HypMode) && !(tranType & S1S2NsTran); 129611505Sandreas.sandberg@arm.com 129712735Sandreas.sandberg@arm.com aarch64EL = tranTypeEL(cpsr, tranType); 129812735Sandreas.sandberg@arm.com aarch64 = isStage2 ? 129912735Sandreas.sandberg@arm.com ELIs64(tc, EL2) : 130012735Sandreas.sandberg@arm.com ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL); 130111505Sandreas.sandberg@arm.com 130210037SARM gem5 Developers if (aarch64) { // AArch64 130311577SDylan.Johnson@ARM.com // determine EL we need to translate in 130410037SARM gem5 Developers switch (aarch64EL) { 130510037SARM gem5 Developers case EL0: 130610037SARM gem5 Developers case EL1: 130710037SARM gem5 Developers { 130810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 130910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 131010037SARM gem5 Developers uint64_t ttbr_asid = ttbcr.a1 ? 131110037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR1_EL1) : 131210037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR0_EL1); 131310037SARM gem5 Developers asid = bits(ttbr_asid, 131410037SARM gem5 Developers (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 131510037SARM gem5 Developers } 131610037SARM gem5 Developers break; 131710037SARM gem5 Developers case EL2: 131810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 131910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 132010037SARM gem5 Developers asid = -1; 132110037SARM gem5 Developers break; 132210037SARM gem5 Developers case EL3: 132310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 132410037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 132510037SARM gem5 Developers asid = -1; 132610037SARM gem5 Developers break; 132710037SARM gem5 Developers } 132811575SDylan.Johnson@ARM.com hcr = tc->readMiscReg(MISCREG_HCR_EL2); 132910037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR_EL3); 133010037SARM gem5 Developers isPriv = aarch64EL != EL0; 133111575SDylan.Johnson@ARM.com if (haveVirtualization) { 133211575SDylan.Johnson@ARM.com vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48); 133313889Sgiacomo.travaglini@arm.com isHyp = aarch64EL == EL2; 133413889Sgiacomo.travaglini@arm.com isHyp |= tranType & HypMode; 133511575SDylan.Johnson@ARM.com isHyp &= (tranType & S1S2NsTran) == 0; 133611575SDylan.Johnson@ARM.com isHyp &= (tranType & S1CTran) == 0; 133711575SDylan.Johnson@ARM.com // Work out if we should skip the first stage of translation and go 133811575SDylan.Johnson@ARM.com // directly to stage 2. This value is cached so we don't have to 133911575SDylan.Johnson@ARM.com // compute it for every translation. 134011575SDylan.Johnson@ARM.com stage2Req = isStage2 || 134111575SDylan.Johnson@ARM.com (hcr.vm && !isHyp && !isSecure && 134211577SDylan.Johnson@ARM.com !(tranType & S1CTran) && (aarch64EL < EL2) && 134311577SDylan.Johnson@ARM.com !(tranType & S1E1Tran)); // <--- FIX THIS HACK 134413374Sanouk.vanlaer@arm.com stage2DescReq = isStage2 || (hcr.vm && !isHyp && !isSecure && 134513374Sanouk.vanlaer@arm.com (aarch64EL < EL2)); 134611575SDylan.Johnson@ARM.com directToStage2 = !isStage2 && stage2Req && !sctlr.m; 134711575SDylan.Johnson@ARM.com } else { 134811575SDylan.Johnson@ARM.com vmid = 0; 134911575SDylan.Johnson@ARM.com isHyp = false; 135011575SDylan.Johnson@ARM.com directToStage2 = false; 135111575SDylan.Johnson@ARM.com stage2Req = false; 135213374Sanouk.vanlaer@arm.com stage2DescReq = false; 135311575SDylan.Johnson@ARM.com } 135410037SARM gem5 Developers } else { // AArch32 135512499Sgiacomo.travaglini@arm.com sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc, 135610037SARM gem5 Developers !isSecure)); 135712499Sgiacomo.travaglini@arm.com ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc, 135810037SARM gem5 Developers !isSecure)); 135910037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR); 136010037SARM gem5 Developers isPriv = cpsr.mode != MODE_USER; 136111517SCurtis.Dunham@arm.com if (longDescFormatInUse(tc)) { 136210037SARM gem5 Developers uint64_t ttbr_asid = tc->readMiscReg( 136312499Sgiacomo.travaglini@arm.com snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 : 136412499Sgiacomo.travaglini@arm.com MISCREG_TTBR0, 136510037SARM gem5 Developers tc, !isSecure)); 136610037SARM gem5 Developers asid = bits(ttbr_asid, 55, 48); 136711517SCurtis.Dunham@arm.com } else { // Short-descriptor translation table format in use 136812499Sgiacomo.travaglini@arm.com CONTEXTIDR context_id = tc->readMiscReg(snsBankedIndex( 136910037SARM gem5 Developers MISCREG_CONTEXTIDR, tc,!isSecure)); 137010037SARM gem5 Developers asid = context_id.asid; 137110037SARM gem5 Developers } 137212499Sgiacomo.travaglini@arm.com prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, tc, 137310037SARM gem5 Developers !isSecure)); 137412499Sgiacomo.travaglini@arm.com nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, tc, 137510037SARM gem5 Developers !isSecure)); 137612499Sgiacomo.travaglini@arm.com dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc, 137710037SARM gem5 Developers !isSecure)); 137810037SARM gem5 Developers hcr = tc->readMiscReg(MISCREG_HCR); 137910037SARM gem5 Developers 138010037SARM gem5 Developers if (haveVirtualization) { 138110037SARM gem5 Developers vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 138210037SARM gem5 Developers isHyp = cpsr.mode == MODE_HYP; 138310037SARM gem5 Developers isHyp |= tranType & HypMode; 138410037SARM gem5 Developers isHyp &= (tranType & S1S2NsTran) == 0; 138510037SARM gem5 Developers isHyp &= (tranType & S1CTran) == 0; 138610037SARM gem5 Developers if (isHyp) { 138710037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_HSCTLR); 138810037SARM gem5 Developers } 138910037SARM gem5 Developers // Work out if we should skip the first stage of translation and go 139010037SARM gem5 Developers // directly to stage 2. This value is cached so we don't have to 139110037SARM gem5 Developers // compute it for every translation. 139210037SARM gem5 Developers stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 139310037SARM gem5 Developers !(tranType & S1CTran); 139413374Sanouk.vanlaer@arm.com stage2DescReq = hcr.vm && !isStage2 && !isHyp && !isSecure; 139510037SARM gem5 Developers directToStage2 = stage2Req && !sctlr.m; 139610037SARM gem5 Developers } else { 139710037SARM gem5 Developers vmid = 0; 139810037SARM gem5 Developers stage2Req = false; 139910037SARM gem5 Developers isHyp = false; 140010037SARM gem5 Developers directToStage2 = false; 140113374Sanouk.vanlaer@arm.com stage2DescReq = false; 140210037SARM gem5 Developers } 140310037SARM gem5 Developers } 140410037SARM gem5 Developers miscRegValid = true; 140511152Smitch.hayenga@arm.com miscRegContext = tc->contextId(); 140610037SARM gem5 Developers curTranType = tranType; 140710037SARM gem5 Developers} 140810037SARM gem5 Developers 140912735Sandreas.sandberg@arm.comExceptionLevel 141012735Sandreas.sandberg@arm.comTLB::tranTypeEL(CPSR cpsr, ArmTranslationType type) 141112735Sandreas.sandberg@arm.com{ 141212735Sandreas.sandberg@arm.com switch (type) { 141312735Sandreas.sandberg@arm.com case S1E0Tran: 141412735Sandreas.sandberg@arm.com case S12E0Tran: 141512735Sandreas.sandberg@arm.com return EL0; 141612735Sandreas.sandberg@arm.com 141712735Sandreas.sandberg@arm.com case S1E1Tran: 141812735Sandreas.sandberg@arm.com case S12E1Tran: 141912735Sandreas.sandberg@arm.com return EL1; 142012735Sandreas.sandberg@arm.com 142112735Sandreas.sandberg@arm.com case S1E2Tran: 142212735Sandreas.sandberg@arm.com return EL2; 142312735Sandreas.sandberg@arm.com 142412735Sandreas.sandberg@arm.com case S1E3Tran: 142512735Sandreas.sandberg@arm.com return EL3; 142612735Sandreas.sandberg@arm.com 142712735Sandreas.sandberg@arm.com case NormalTran: 142812735Sandreas.sandberg@arm.com case S1CTran: 142912735Sandreas.sandberg@arm.com case S1S2NsTran: 143012735Sandreas.sandberg@arm.com case HypMode: 143114172Sgiacomo.travaglini@arm.com return currEL(cpsr); 143212735Sandreas.sandberg@arm.com 143312735Sandreas.sandberg@arm.com default: 143412735Sandreas.sandberg@arm.com panic("Unknown translation mode!\n"); 143512735Sandreas.sandberg@arm.com } 143612735Sandreas.sandberg@arm.com} 143712735Sandreas.sandberg@arm.com 143810037SARM gem5 DevelopersFault 143912749Sgiacomo.travaglini@arm.comTLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, 144010037SARM gem5 Developers Translation *translation, bool timing, bool functional, 144110037SARM gem5 Developers bool is_secure, TLB::ArmTranslationType tranType) 144210037SARM gem5 Developers{ 144314066Sanouk.vanlaer@arm.com // In a 2-stage system, the IPA->PA translation can be started via this 144414066Sanouk.vanlaer@arm.com // call so make sure the miscRegs are correct. 144514066Sanouk.vanlaer@arm.com if (isStage2) { 144614066Sanouk.vanlaer@arm.com updateMiscReg(tc, tranType); 144714066Sanouk.vanlaer@arm.com } 144810037SARM gem5 Developers bool is_fetch = (mode == Execute); 144910037SARM gem5 Developers bool is_write = (mode == Write); 145010037SARM gem5 Developers 145110037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 145210037SARM gem5 Developers Addr vaddr = 0; 145310037SARM gem5 Developers ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 145410037SARM gem5 Developers if (aarch64) { 145510854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr); 145610037SARM gem5 Developers } else { 145710037SARM gem5 Developers vaddr = vaddr_tainted; 145810037SARM gem5 Developers } 145910037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 146010037SARM gem5 Developers if (*te == NULL) { 146110037SARM gem5 Developers if (req->isPrefetch()) { 146210037SARM gem5 Developers // if the request is a prefetch don't attempt to fill the TLB or go 146310037SARM gem5 Developers // any further with the memory access (here we can safely use the 146410037SARM gem5 Developers // fault status for the short desc. format in all cases) 14657734SAli.Saidi@ARM.com prefetchFaults++; 146610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 146710474Sandreas.hansson@arm.com vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 14687611SGene.Wu@arm.com } 14697734SAli.Saidi@ARM.com 14707734SAli.Saidi@ARM.com if (is_fetch) 14717734SAli.Saidi@ARM.com instMisses++; 14727734SAli.Saidi@ARM.com else if (is_write) 14737734SAli.Saidi@ARM.com writeMisses++; 14747734SAli.Saidi@ARM.com else 14757734SAli.Saidi@ARM.com readMisses++; 14767734SAli.Saidi@ARM.com 14777404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 14787404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 147910037SARM gem5 Developers DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 148010037SARM gem5 Developers vaddr_tainted, asid, vmid); 148110037SARM gem5 Developers Fault fault; 148210037SARM gem5 Developers fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 148310037SARM gem5 Developers translation, timing, functional, is_secure, 148413374Sanouk.vanlaer@arm.com tranType, stage2DescReq); 148510037SARM gem5 Developers // for timing mode, return and wait for table walk, 148610037SARM gem5 Developers if (timing || fault != NoFault) { 14877437Sdam.sunwoo@arm.com return fault; 14887437Sdam.sunwoo@arm.com } 14897404SAli.Saidi@ARM.com 149010037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 149110037SARM gem5 Developers if (!*te) 14927404SAli.Saidi@ARM.com printTlb(); 149310037SARM gem5 Developers assert(*te); 14947734SAli.Saidi@ARM.com } else { 14957734SAli.Saidi@ARM.com if (is_fetch) 14967734SAli.Saidi@ARM.com instHits++; 14977734SAli.Saidi@ARM.com else if (is_write) 14987734SAli.Saidi@ARM.com writeHits++; 14997734SAli.Saidi@ARM.com else 15007734SAli.Saidi@ARM.com readHits++; 15017404SAli.Saidi@ARM.com } 15026757SAli.Saidi@ARM.com return NoFault; 15037404SAli.Saidi@ARM.com} 15046757SAli.Saidi@ARM.com 15057404SAli.Saidi@ARM.comFault 150612749Sgiacomo.travaglini@arm.comTLB::getResultTe(TlbEntry **te, const RequestPtr &req, 150712749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode, 150810037SARM gem5 Developers Translation *translation, bool timing, bool functional, 150910037SARM gem5 Developers TlbEntry *mergeTe) 15107404SAli.Saidi@ARM.com{ 15117404SAli.Saidi@ARM.com Fault fault; 151211575SDylan.Johnson@ARM.com 151311575SDylan.Johnson@ARM.com if (isStage2) { 151411575SDylan.Johnson@ARM.com // We are already in the stage 2 TLB. Grab the table entry for stage 151511575SDylan.Johnson@ARM.com // 2 only. We are here because stage 1 translation is disabled. 151611575SDylan.Johnson@ARM.com TlbEntry *s2Te = NULL; 151711575SDylan.Johnson@ARM.com // Get the stage 2 table entry 151811575SDylan.Johnson@ARM.com fault = getTE(&s2Te, req, tc, mode, translation, timing, functional, 151911575SDylan.Johnson@ARM.com isSecure, curTranType); 152011575SDylan.Johnson@ARM.com // Check permissions of stage 2 152112528Schuan.zhu@arm.com if ((s2Te != NULL) && (fault == NoFault)) { 152212528Schuan.zhu@arm.com if (aarch64) 152311575SDylan.Johnson@ARM.com fault = checkPermissions64(s2Te, req, mode, tc); 152411575SDylan.Johnson@ARM.com else 152511575SDylan.Johnson@ARM.com fault = checkPermissions(s2Te, req, mode); 152611575SDylan.Johnson@ARM.com } 152711575SDylan.Johnson@ARM.com *te = s2Te; 152811575SDylan.Johnson@ARM.com return fault; 152911575SDylan.Johnson@ARM.com } 153011575SDylan.Johnson@ARM.com 153110037SARM gem5 Developers TlbEntry *s1Te = NULL; 153210037SARM gem5 Developers 153310037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 153410037SARM gem5 Developers 153510037SARM gem5 Developers // Get the stage 1 table entry 153610037SARM gem5 Developers fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 153710037SARM gem5 Developers isSecure, curTranType); 153810037SARM gem5 Developers // only proceed if we have a valid table entry 153910037SARM gem5 Developers if ((s1Te != NULL) && (fault == NoFault)) { 154010037SARM gem5 Developers // Check stage 1 permissions before checking stage 2 154110037SARM gem5 Developers if (aarch64) 154210037SARM gem5 Developers fault = checkPermissions64(s1Te, req, mode, tc); 154310037SARM gem5 Developers else 154410037SARM gem5 Developers fault = checkPermissions(s1Te, req, mode); 154510037SARM gem5 Developers if (stage2Req & (fault == NoFault)) { 154610037SARM gem5 Developers Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 154710037SARM gem5 Developers req, translation, mode, timing, functional, curTranType); 154810037SARM gem5 Developers fault = s2Lookup->getTe(tc, mergeTe); 154910037SARM gem5 Developers if (s2Lookup->isComplete()) { 155010037SARM gem5 Developers *te = mergeTe; 155110037SARM gem5 Developers // We've finished with the lookup so delete it 155210037SARM gem5 Developers delete s2Lookup; 155310037SARM gem5 Developers } else { 155410037SARM gem5 Developers // The lookup hasn't completed, so we can't delete it now. We 155510037SARM gem5 Developers // get round this by asking the object to self delete when the 155610037SARM gem5 Developers // translation is complete. 155710037SARM gem5 Developers s2Lookup->setSelfDelete(); 155810037SARM gem5 Developers } 155910037SARM gem5 Developers } else { 156010037SARM gem5 Developers // This case deals with an S1 hit (or bypass), followed by 156110037SARM gem5 Developers // an S2 hit-but-perms issue 156210037SARM gem5 Developers if (isStage2) { 156310037SARM gem5 Developers DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 156410037SARM gem5 Developers vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 156510037SARM gem5 Developers if (fault != NoFault) { 156610037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 156710037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, false); 156810037SARM gem5 Developers armFault->annotate(ArmFault::OVA, vaddr_tainted); 156910037SARM gem5 Developers } 157010037SARM gem5 Developers } 157110037SARM gem5 Developers *te = s1Te; 157210037SARM gem5 Developers } 157310037SARM gem5 Developers } 15747404SAli.Saidi@ARM.com return fault; 15756019Shines@cs.fsu.edu} 15766019Shines@cs.fsu.edu 157711395Sandreas.sandberg@arm.comvoid 157811395Sandreas.sandberg@arm.comTLB::setTestInterface(SimObject *_ti) 157911395Sandreas.sandberg@arm.com{ 158011395Sandreas.sandberg@arm.com if (!_ti) { 158111395Sandreas.sandberg@arm.com test = nullptr; 158211395Sandreas.sandberg@arm.com } else { 158311395Sandreas.sandberg@arm.com TlbTestInterface *ti(dynamic_cast<TlbTestInterface *>(_ti)); 158411395Sandreas.sandberg@arm.com fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 158511395Sandreas.sandberg@arm.com test = ti; 158611395Sandreas.sandberg@arm.com } 158711395Sandreas.sandberg@arm.com} 158811395Sandreas.sandberg@arm.com 158911395Sandreas.sandberg@arm.comFault 159012749Sgiacomo.travaglini@arm.comTLB::testTranslation(const RequestPtr &req, Mode mode, 159112749Sgiacomo.travaglini@arm.com TlbEntry::DomainType domain) 159211395Sandreas.sandberg@arm.com{ 159312506Snikos.nikoleris@arm.com if (!test || !req->hasSize() || req->getSize() == 0 || 159412506Snikos.nikoleris@arm.com req->isCacheMaintenance()) { 159511395Sandreas.sandberg@arm.com return NoFault; 159611395Sandreas.sandberg@arm.com } else { 159711395Sandreas.sandberg@arm.com return test->translationCheck(req, isPriv, mode, domain); 159811395Sandreas.sandberg@arm.com } 159911395Sandreas.sandberg@arm.com} 160011395Sandreas.sandberg@arm.com 160111395Sandreas.sandberg@arm.comFault 160211395Sandreas.sandberg@arm.comTLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 160311395Sandreas.sandberg@arm.com TlbEntry::DomainType domain, LookupLevel lookup_level) 160411395Sandreas.sandberg@arm.com{ 160511395Sandreas.sandberg@arm.com if (!test) { 160611395Sandreas.sandberg@arm.com return NoFault; 160711395Sandreas.sandberg@arm.com } else { 160811395Sandreas.sandberg@arm.com return test->walkCheck(pa, size, va, is_secure, isPriv, mode, 160911395Sandreas.sandberg@arm.com domain, lookup_level); 161011395Sandreas.sandberg@arm.com } 161111395Sandreas.sandberg@arm.com} 161211395Sandreas.sandberg@arm.com 161311395Sandreas.sandberg@arm.com 16146116Snate@binkert.orgArmISA::TLB * 16156116Snate@binkert.orgArmTLBParams::create() 16166019Shines@cs.fsu.edu{ 16176116Snate@binkert.org return new ArmISA::TLB(this); 16186019Shines@cs.fsu.edu} 1619