tlb.cc revision 12499
16019Shines@cs.fsu.edu/* 211861Snikos.nikoleris@arm.com * Copyright (c) 2010-2013, 2016-2017 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 4510873Sandreas.sandberg@arm.com#include "arch/arm/tlb.hh" 4610873Sandreas.sandberg@arm.com 4710474Sandreas.hansson@arm.com#include <memory> 486019Shines@cs.fsu.edu#include <string> 496019Shines@cs.fsu.edu#include <vector> 506019Shines@cs.fsu.edu 516116Snate@binkert.org#include "arch/arm/faults.hh" 526019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 5311793Sbrandon.potter@amd.com#include "arch/arm/stage2_lookup.hh" 5411793Sbrandon.potter@amd.com#include "arch/arm/stage2_mmu.hh" 558782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 568756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 576019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 5812005Sandreas.sandberg@arm.com#include "arch/generic/mmapped_ipr.hh" 596019Shines@cs.fsu.edu#include "base/inifile.hh" 606019Shines@cs.fsu.edu#include "base/str.hh" 616019Shines@cs.fsu.edu#include "base/trace.hh" 6210024Sdam.sunwoo@arm.com#include "cpu/base.hh" 636019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 648232Snate@binkert.org#include "debug/Checkpoint.hh" 658232Snate@binkert.org#include "debug/TLB.hh" 668232Snate@binkert.org#include "debug/TLBVerbose.hh" 676116Snate@binkert.org#include "mem/page_table.hh" 6811608Snikos.nikoleris@arm.com#include "mem/request.hh" 696116Snate@binkert.org#include "params/ArmTLB.hh" 708756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 716019Shines@cs.fsu.edu#include "sim/process.hh" 726019Shines@cs.fsu.edu 736019Shines@cs.fsu.eduusing namespace std; 746019Shines@cs.fsu.eduusing namespace ArmISA; 756019Shines@cs.fsu.edu 7610037SARM gem5 DevelopersTLB::TLB(const ArmTLBParams *p) 7710037SARM gem5 Developers : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 7810418Sandreas.hansson@arm.com isStage2(p->is_stage2), stage2Req(false), _attr(0), 7910418Sandreas.hansson@arm.com directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 8011395Sandreas.sandberg@arm.com stage2Mmu(NULL), test(nullptr), rangeMRU(1), 8110537Sandreas.hansson@arm.com aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), 8210537Sandreas.hansson@arm.com isHyp(false), asid(0), vmid(0), dacr(0), 8311152Smitch.hayenga@arm.com miscRegValid(false), miscRegContext(0), curTranType(NormalTran) 846019Shines@cs.fsu.edu{ 8512005Sandreas.sandberg@arm.com const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys); 8612005Sandreas.sandberg@arm.com 8710037SARM gem5 Developers tableWalker->setTlb(this); 887399SAli.Saidi@ARM.com 8910037SARM gem5 Developers // Cache system-level properties 9010037SARM gem5 Developers haveLPAE = tableWalker->haveLPAE(); 9110037SARM gem5 Developers haveVirtualization = tableWalker->haveVirtualization(); 9210037SARM gem5 Developers haveLargeAsid64 = tableWalker->haveLargeAsid64(); 9312005Sandreas.sandberg@arm.com 9412005Sandreas.sandberg@arm.com if (sys) 9512005Sandreas.sandberg@arm.com m5opRange = sys->m5opRange(); 966019Shines@cs.fsu.edu} 976019Shines@cs.fsu.edu 986019Shines@cs.fsu.eduTLB::~TLB() 996019Shines@cs.fsu.edu{ 10010037SARM gem5 Developers delete[] table; 10110037SARM gem5 Developers} 10210037SARM gem5 Developers 10310037SARM gem5 Developersvoid 10410037SARM gem5 DevelopersTLB::init() 10510037SARM gem5 Developers{ 10610037SARM gem5 Developers if (stage2Mmu && !isStage2) 10710037SARM gem5 Developers stage2Tlb = stage2Mmu->stage2Tlb(); 10810037SARM gem5 Developers} 10910037SARM gem5 Developers 11010037SARM gem5 Developersvoid 11110717Sandreas.hansson@arm.comTLB::setMMU(Stage2MMU *m, MasterID master_id) 11210037SARM gem5 Developers{ 11310037SARM gem5 Developers stage2Mmu = m; 11410717Sandreas.hansson@arm.com tableWalker->setMMU(m, master_id); 1156019Shines@cs.fsu.edu} 1166019Shines@cs.fsu.edu 1177694SAli.Saidi@ARM.combool 1187694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 1197694SAli.Saidi@ARM.com{ 12010037SARM gem5 Developers updateMiscReg(tc); 12110037SARM gem5 Developers 12210037SARM gem5 Developers if (directToStage2) { 12310037SARM gem5 Developers assert(stage2Tlb); 12410037SARM gem5 Developers return stage2Tlb->translateFunctional(tc, va, pa); 12510037SARM gem5 Developers } 12610037SARM gem5 Developers 12710037SARM gem5 Developers TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 12810037SARM gem5 Developers aarch64 ? aarch64EL : EL1); 1297694SAli.Saidi@ARM.com if (!e) 1307694SAli.Saidi@ARM.com return false; 1317694SAli.Saidi@ARM.com pa = e->pAddr(va); 1327694SAli.Saidi@ARM.com return true; 1337694SAli.Saidi@ARM.com} 1347694SAli.Saidi@ARM.com 1359738Sandreas@sandberg.pp.seFault 1369738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 1379738Sandreas@sandberg.pp.se{ 13812005Sandreas.sandberg@arm.com const Addr paddr = req->getPaddr(); 13912005Sandreas.sandberg@arm.com 14012005Sandreas.sandberg@arm.com if (m5opRange.contains(paddr)) { 14112005Sandreas.sandberg@arm.com req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); 14212005Sandreas.sandberg@arm.com req->setPaddr(GenericISA::iprAddressPseudoInst( 14312005Sandreas.sandberg@arm.com (paddr >> 8) & 0xFF, 14412005Sandreas.sandberg@arm.com paddr & 0xFF)); 14512005Sandreas.sandberg@arm.com } 14612005Sandreas.sandberg@arm.com 1479738Sandreas@sandberg.pp.se return NoFault; 1489738Sandreas@sandberg.pp.se} 1499738Sandreas@sandberg.pp.se 1507404SAli.Saidi@ARM.comTlbEntry* 15110037SARM gem5 DevelopersTLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 15210037SARM gem5 Developers bool functional, bool ignore_asn, uint8_t target_el) 1536019Shines@cs.fsu.edu{ 1547404SAli.Saidi@ARM.com 1557404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1567404SAli.Saidi@ARM.com 15710037SARM gem5 Developers // Maintaining LRU array 1587404SAli.Saidi@ARM.com int x = 0; 1597404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 16010037SARM gem5 Developers if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 16110037SARM gem5 Developers target_el)) || 16210037SARM gem5 Developers (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 16310037SARM gem5 Developers // We only move the hit entry ahead when the position is higher 16410037SARM gem5 Developers // than rangeMRU 1659535Smrinmoy.ghosh@arm.com if (x > rangeMRU && !functional) { 1667697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 16711321Ssteve.reinhardt@amd.com for (int i = x; i > 0; i--) 16810037SARM gem5 Developers table[i] = table[i - 1]; 1697697SAli.Saidi@ARM.com table[0] = tmp_entry; 1707697SAli.Saidi@ARM.com retval = &table[0]; 1717697SAli.Saidi@ARM.com } else { 1727697SAli.Saidi@ARM.com retval = &table[x]; 1737697SAli.Saidi@ARM.com } 1747404SAli.Saidi@ARM.com break; 1757404SAli.Saidi@ARM.com } 17610037SARM gem5 Developers ++x; 1777404SAli.Saidi@ARM.com } 1787404SAli.Saidi@ARM.com 17910037SARM gem5 Developers DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 18010037SARM gem5 Developers "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 18110037SARM gem5 Developers "el: %d\n", 18210037SARM gem5 Developers va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 18310037SARM gem5 Developers retval ? retval->pfn : 0, retval ? retval->size : 0, 18410037SARM gem5 Developers retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 18510037SARM gem5 Developers retval ? retval->ns : 0, retval ? retval->nstid : 0, 18610037SARM gem5 Developers retval ? retval->global : 0, retval ? retval->asid : 0, 18710367SAndrew.Bardsley@arm.com retval ? retval->el : 0); 18810037SARM gem5 Developers 1897404SAli.Saidi@ARM.com return retval; 1906019Shines@cs.fsu.edu} 1916019Shines@cs.fsu.edu 1926019Shines@cs.fsu.edu// insert a new TLB entry 1936019Shines@cs.fsu.eduvoid 1947404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1956019Shines@cs.fsu.edu{ 1967404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 19710037SARM gem5 Developers " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 19810037SARM gem5 Developers " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 19910037SARM gem5 Developers entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 20010037SARM gem5 Developers entry.global, entry.valid, entry.nonCacheable, entry.xn, 20110037SARM gem5 Developers entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 20210037SARM gem5 Developers entry.isHyp); 2037404SAli.Saidi@ARM.com 20410037SARM gem5 Developers if (table[size - 1].valid) 20510037SARM gem5 Developers DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 20610037SARM gem5 Developers "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 2077697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 20810037SARM gem5 Developers table[size-1].vmid, table[size-1].pfn << table[size-1].N, 20910037SARM gem5 Developers table[size-1].size, table[size-1].ap, table[size-1].ns, 21010037SARM gem5 Developers table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 21110037SARM gem5 Developers table[size-1].el); 2127404SAli.Saidi@ARM.com 2137697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 2147404SAli.Saidi@ARM.com 21510037SARM gem5 Developers for (int i = size - 1; i > 0; --i) 21610037SARM gem5 Developers table[i] = table[i-1]; 2177697SAli.Saidi@ARM.com table[0] = entry; 2187734SAli.Saidi@ARM.com 2197734SAli.Saidi@ARM.com inserts++; 22010463SAndreas.Sandberg@ARM.com ppRefills->notify(1); 2216019Shines@cs.fsu.edu} 2226019Shines@cs.fsu.edu 2236019Shines@cs.fsu.eduvoid 22410037SARM gem5 DevelopersTLB::printTlb() const 2257404SAli.Saidi@ARM.com{ 2267404SAli.Saidi@ARM.com int x = 0; 2277404SAli.Saidi@ARM.com TlbEntry *te; 2287404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 2297404SAli.Saidi@ARM.com while (x < size) { 23010037SARM gem5 Developers te = &table[x]; 23110037SARM gem5 Developers if (te->valid) 23210037SARM gem5 Developers DPRINTF(TLB, " * %s\n", te->print()); 23310037SARM gem5 Developers ++x; 2347404SAli.Saidi@ARM.com } 2357404SAli.Saidi@ARM.com} 2367404SAli.Saidi@ARM.com 2377404SAli.Saidi@ARM.comvoid 23810037SARM gem5 DevelopersTLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el) 2396019Shines@cs.fsu.edu{ 24010037SARM gem5 Developers DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 24110037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2427404SAli.Saidi@ARM.com int x = 0; 2437404SAli.Saidi@ARM.com TlbEntry *te; 2447404SAli.Saidi@ARM.com while (x < size) { 24510037SARM gem5 Developers te = &table[x]; 24610037SARM gem5 Developers if (te->valid && secure_lookup == !te->nstid && 24710037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 24810037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 24910037SARM gem5 Developers 25010037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 25110037SARM gem5 Developers te->valid = false; 25210037SARM gem5 Developers flushedEntries++; 25310037SARM gem5 Developers } 25410037SARM gem5 Developers ++x; 2557404SAli.Saidi@ARM.com } 2567404SAli.Saidi@ARM.com 25710037SARM gem5 Developers flushTlb++; 25810037SARM gem5 Developers 25910037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 26010037SARM gem5 Developers // if we're currently in hyp mode 26110037SARM gem5 Developers if (!isStage2 && isHyp) { 26210037SARM gem5 Developers stage2Tlb->flushAllSecurity(secure_lookup, true); 26310037SARM gem5 Developers } 26410037SARM gem5 Developers} 26510037SARM gem5 Developers 26610037SARM gem5 Developersvoid 26710037SARM gem5 DevelopersTLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el) 26810037SARM gem5 Developers{ 26910037SARM gem5 Developers DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 27010037SARM gem5 Developers (hyp ? "hyp" : "non-hyp")); 27110037SARM gem5 Developers int x = 0; 27210037SARM gem5 Developers TlbEntry *te; 27310037SARM gem5 Developers while (x < size) { 27410037SARM gem5 Developers te = &table[x]; 27510037SARM gem5 Developers if (te->valid && te->nstid && te->isHyp == hyp && 27610037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 27710037SARM gem5 Developers 27810037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 27910037SARM gem5 Developers flushedEntries++; 28010037SARM gem5 Developers te->valid = false; 28110037SARM gem5 Developers } 28210037SARM gem5 Developers ++x; 28310037SARM gem5 Developers } 2847734SAli.Saidi@ARM.com 2857734SAli.Saidi@ARM.com flushTlb++; 28610037SARM gem5 Developers 28710037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 28810037SARM gem5 Developers if (!isStage2 && !hyp) { 28910037SARM gem5 Developers stage2Tlb->flushAllNs(false, true); 29010037SARM gem5 Developers } 2916019Shines@cs.fsu.edu} 2926019Shines@cs.fsu.edu 2937404SAli.Saidi@ARM.comvoid 29410037SARM gem5 DevelopersTLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) 2957404SAli.Saidi@ARM.com{ 29610037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 29710037SARM gem5 Developers "(%s lookup)\n", mva, asn, (secure_lookup ? 29810037SARM gem5 Developers "secure" : "non-secure")); 29910037SARM gem5 Developers _flushMva(mva, asn, secure_lookup, false, false, target_el); 3007734SAli.Saidi@ARM.com flushTlbMvaAsid++; 3017404SAli.Saidi@ARM.com} 3027404SAli.Saidi@ARM.com 3037404SAli.Saidi@ARM.comvoid 30410037SARM gem5 DevelopersTLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) 3057404SAli.Saidi@ARM.com{ 30610037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 30710037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 3087404SAli.Saidi@ARM.com 30910037SARM gem5 Developers int x = 0 ; 3107404SAli.Saidi@ARM.com TlbEntry *te; 3117404SAli.Saidi@ARM.com 3127404SAli.Saidi@ARM.com while (x < size) { 3137404SAli.Saidi@ARM.com te = &table[x]; 31410037SARM gem5 Developers if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 31510037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 31610037SARM gem5 Developers checkELMatch(target_el, te->el, false)) { 31710037SARM gem5 Developers 3187404SAli.Saidi@ARM.com te->valid = false; 31910037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3207734SAli.Saidi@ARM.com flushedEntries++; 3217404SAli.Saidi@ARM.com } 32210037SARM gem5 Developers ++x; 3237404SAli.Saidi@ARM.com } 3247734SAli.Saidi@ARM.com flushTlbAsid++; 3257404SAli.Saidi@ARM.com} 3267404SAli.Saidi@ARM.com 3277404SAli.Saidi@ARM.comvoid 32810037SARM gem5 DevelopersTLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) 3297404SAli.Saidi@ARM.com{ 33010037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 33110037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 33210037SARM gem5 Developers _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el); 33310037SARM gem5 Developers flushTlbMva++; 33410037SARM gem5 Developers} 3357404SAli.Saidi@ARM.com 33610037SARM gem5 Developersvoid 33710037SARM gem5 DevelopersTLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, 33810037SARM gem5 Developers bool ignore_asn, uint8_t target_el) 33910037SARM gem5 Developers{ 3407404SAli.Saidi@ARM.com TlbEntry *te; 34110037SARM gem5 Developers // D5.7.2: Sign-extend address to 64 bits 34210037SARM gem5 Developers mva = sext<56>(mva); 34310037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 34410037SARM gem5 Developers target_el); 34510037SARM gem5 Developers while (te != NULL) { 34610037SARM gem5 Developers if (secure_lookup == !te->nstid) { 34710037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3487404SAli.Saidi@ARM.com te->valid = false; 3497734SAli.Saidi@ARM.com flushedEntries++; 3507404SAli.Saidi@ARM.com } 35110037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 35210037SARM gem5 Developers target_el); 3537404SAli.Saidi@ARM.com } 35410037SARM gem5 Developers} 35510037SARM gem5 Developers 35611584SDylan.Johnson@ARM.comvoid 35711584SDylan.Johnson@ARM.comTLB::flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el) 35811584SDylan.Johnson@ARM.com{ 35911584SDylan.Johnson@ARM.com assert(!isStage2); 36011584SDylan.Johnson@ARM.com stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, hyp, true, target_el); 36111584SDylan.Johnson@ARM.com} 36211584SDylan.Johnson@ARM.com 36310037SARM gem5 Developersbool 36410037SARM gem5 DevelopersTLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) 36510037SARM gem5 Developers{ 36610037SARM gem5 Developers bool elMatch = true; 36710037SARM gem5 Developers if (!ignore_el) { 36810037SARM gem5 Developers if (target_el == 2 || target_el == 3) { 36910037SARM gem5 Developers elMatch = (tentry_el == target_el); 37010037SARM gem5 Developers } else { 37110037SARM gem5 Developers elMatch = (tentry_el == 0) || (tentry_el == 1); 37210037SARM gem5 Developers } 37310037SARM gem5 Developers } 37410037SARM gem5 Developers return elMatch; 3757404SAli.Saidi@ARM.com} 3767404SAli.Saidi@ARM.com 3776019Shines@cs.fsu.eduvoid 3789439SAndreas.Sandberg@ARM.comTLB::drainResume() 3799439SAndreas.Sandberg@ARM.com{ 3809439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 3819439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 3829439SAndreas.Sandberg@ARM.com miscRegValid = false; 3839439SAndreas.Sandberg@ARM.com} 3849439SAndreas.Sandberg@ARM.com 3859439SAndreas.Sandberg@ARM.comvoid 38610194SGeoffrey.Blake@arm.comTLB::takeOverFrom(BaseTLB *_otlb) 38710194SGeoffrey.Blake@arm.com{ 38810194SGeoffrey.Blake@arm.com TLB *otlb = dynamic_cast<TLB*>(_otlb); 38910194SGeoffrey.Blake@arm.com /* Make sure we actually have a valid type */ 39010194SGeoffrey.Blake@arm.com if (otlb) { 39110194SGeoffrey.Blake@arm.com _attr = otlb->_attr; 39210194SGeoffrey.Blake@arm.com haveLPAE = otlb->haveLPAE; 39310194SGeoffrey.Blake@arm.com directToStage2 = otlb->directToStage2; 39410194SGeoffrey.Blake@arm.com stage2Req = otlb->stage2Req; 39510194SGeoffrey.Blake@arm.com 39610194SGeoffrey.Blake@arm.com /* Sync the stage2 MMU if they exist in both 39710194SGeoffrey.Blake@arm.com * the old CPU and the new 39810194SGeoffrey.Blake@arm.com */ 39910194SGeoffrey.Blake@arm.com if (!isStage2 && 40010194SGeoffrey.Blake@arm.com stage2Tlb && otlb->stage2Tlb) { 40110194SGeoffrey.Blake@arm.com stage2Tlb->takeOverFrom(otlb->stage2Tlb); 40210194SGeoffrey.Blake@arm.com } 40310194SGeoffrey.Blake@arm.com } else { 40410194SGeoffrey.Blake@arm.com panic("Incompatible TLB type!"); 40510194SGeoffrey.Blake@arm.com } 40610194SGeoffrey.Blake@arm.com} 40710194SGeoffrey.Blake@arm.com 40810194SGeoffrey.Blake@arm.comvoid 40910905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 4106019Shines@cs.fsu.edu{ 4117733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 4127733SAli.Saidi@ARM.com 4137733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 41410037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 41510037SARM gem5 Developers SERIALIZE_SCALAR(directToStage2); 41610037SARM gem5 Developers SERIALIZE_SCALAR(stage2Req); 4178353SAli.Saidi@ARM.com 4188353SAli.Saidi@ARM.com int num_entries = size; 4198353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 42011321Ssteve.reinhardt@amd.com for (int i = 0; i < size; i++) 42110905Sandreas.sandberg@arm.com table[i].serializeSection(cp, csprintf("TlbEntry%d", i)); 4226019Shines@cs.fsu.edu} 4236019Shines@cs.fsu.edu 4246019Shines@cs.fsu.eduvoid 42510905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 4266019Shines@cs.fsu.edu{ 4277733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 4286019Shines@cs.fsu.edu 4297733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 43010037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 43110037SARM gem5 Developers UNSERIALIZE_SCALAR(directToStage2); 43210037SARM gem5 Developers UNSERIALIZE_SCALAR(stage2Req); 43310037SARM gem5 Developers 4348353SAli.Saidi@ARM.com int num_entries; 4358353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 43611321Ssteve.reinhardt@amd.com for (int i = 0; i < min(size, num_entries); i++) 43710905Sandreas.sandberg@arm.com table[i].unserializeSection(cp, csprintf("TlbEntry%d", i)); 4386019Shines@cs.fsu.edu} 4396019Shines@cs.fsu.edu 4406019Shines@cs.fsu.eduvoid 4416019Shines@cs.fsu.eduTLB::regStats() 4426019Shines@cs.fsu.edu{ 44311522Sstephan.diestelhorst@arm.com BaseTLB::regStats(); 4447734SAli.Saidi@ARM.com instHits 4457734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 4467734SAli.Saidi@ARM.com .desc("ITB inst hits") 4477734SAli.Saidi@ARM.com ; 4487734SAli.Saidi@ARM.com 4497734SAli.Saidi@ARM.com instMisses 4507734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 4517734SAli.Saidi@ARM.com .desc("ITB inst misses") 4527734SAli.Saidi@ARM.com ; 4537734SAli.Saidi@ARM.com 4547734SAli.Saidi@ARM.com instAccesses 4557734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 4567734SAli.Saidi@ARM.com .desc("ITB inst accesses") 4577734SAli.Saidi@ARM.com ; 4587734SAli.Saidi@ARM.com 4597734SAli.Saidi@ARM.com readHits 4606019Shines@cs.fsu.edu .name(name() + ".read_hits") 4616019Shines@cs.fsu.edu .desc("DTB read hits") 4626019Shines@cs.fsu.edu ; 4636019Shines@cs.fsu.edu 4647734SAli.Saidi@ARM.com readMisses 4656019Shines@cs.fsu.edu .name(name() + ".read_misses") 4666019Shines@cs.fsu.edu .desc("DTB read misses") 4676019Shines@cs.fsu.edu ; 4686019Shines@cs.fsu.edu 4697734SAli.Saidi@ARM.com readAccesses 4706019Shines@cs.fsu.edu .name(name() + ".read_accesses") 4716019Shines@cs.fsu.edu .desc("DTB read accesses") 4726019Shines@cs.fsu.edu ; 4736019Shines@cs.fsu.edu 4747734SAli.Saidi@ARM.com writeHits 4756019Shines@cs.fsu.edu .name(name() + ".write_hits") 4766019Shines@cs.fsu.edu .desc("DTB write hits") 4776019Shines@cs.fsu.edu ; 4786019Shines@cs.fsu.edu 4797734SAli.Saidi@ARM.com writeMisses 4806019Shines@cs.fsu.edu .name(name() + ".write_misses") 4816019Shines@cs.fsu.edu .desc("DTB write misses") 4826019Shines@cs.fsu.edu ; 4836019Shines@cs.fsu.edu 4847734SAli.Saidi@ARM.com writeAccesses 4856019Shines@cs.fsu.edu .name(name() + ".write_accesses") 4866019Shines@cs.fsu.edu .desc("DTB write accesses") 4876019Shines@cs.fsu.edu ; 4886019Shines@cs.fsu.edu 4896019Shines@cs.fsu.edu hits 4906019Shines@cs.fsu.edu .name(name() + ".hits") 4916019Shines@cs.fsu.edu .desc("DTB hits") 4926019Shines@cs.fsu.edu ; 4936019Shines@cs.fsu.edu 4946019Shines@cs.fsu.edu misses 4956019Shines@cs.fsu.edu .name(name() + ".misses") 4966019Shines@cs.fsu.edu .desc("DTB misses") 4976019Shines@cs.fsu.edu ; 4986019Shines@cs.fsu.edu 4996019Shines@cs.fsu.edu accesses 5006019Shines@cs.fsu.edu .name(name() + ".accesses") 5016019Shines@cs.fsu.edu .desc("DTB accesses") 5026019Shines@cs.fsu.edu ; 5036019Shines@cs.fsu.edu 5047734SAli.Saidi@ARM.com flushTlb 5057734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 5067734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 5077734SAli.Saidi@ARM.com ; 5087734SAli.Saidi@ARM.com 5097734SAli.Saidi@ARM.com flushTlbMva 5107734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 5117734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 5127734SAli.Saidi@ARM.com ; 5137734SAli.Saidi@ARM.com 5147734SAli.Saidi@ARM.com flushTlbMvaAsid 5157734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 5167734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 5177734SAli.Saidi@ARM.com ; 5187734SAli.Saidi@ARM.com 5197734SAli.Saidi@ARM.com flushTlbAsid 5207734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 5217734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 5227734SAli.Saidi@ARM.com ; 5237734SAli.Saidi@ARM.com 5247734SAli.Saidi@ARM.com flushedEntries 5257734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 5267734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 5277734SAli.Saidi@ARM.com ; 5287734SAli.Saidi@ARM.com 5297734SAli.Saidi@ARM.com alignFaults 5307734SAli.Saidi@ARM.com .name(name() + ".align_faults") 5317734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 5327734SAli.Saidi@ARM.com ; 5337734SAli.Saidi@ARM.com 5347734SAli.Saidi@ARM.com prefetchFaults 5357734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 5367734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 5377734SAli.Saidi@ARM.com ; 5387734SAli.Saidi@ARM.com 5397734SAli.Saidi@ARM.com domainFaults 5407734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 5417734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 5427734SAli.Saidi@ARM.com ; 5437734SAli.Saidi@ARM.com 5447734SAli.Saidi@ARM.com permsFaults 5457734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 5467734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 5477734SAli.Saidi@ARM.com ; 5487734SAli.Saidi@ARM.com 5497734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 5507734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 5517734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 5527734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 5537734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 5547734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 5556019Shines@cs.fsu.edu} 5566019Shines@cs.fsu.edu 55710463SAndreas.Sandberg@ARM.comvoid 55810463SAndreas.Sandberg@ARM.comTLB::regProbePoints() 55910463SAndreas.Sandberg@ARM.com{ 56010463SAndreas.Sandberg@ARM.com ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 56110463SAndreas.Sandberg@ARM.com} 56210463SAndreas.Sandberg@ARM.com 5637404SAli.Saidi@ARM.comFault 5647404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 56510037SARM gem5 Developers Translation *translation, bool &delay, bool timing) 5667404SAli.Saidi@ARM.com{ 56710037SARM gem5 Developers updateMiscReg(tc); 56810037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 56910037SARM gem5 Developers Addr vaddr = 0; 57010037SARM gem5 Developers if (aarch64) 57110854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 57210037SARM gem5 Developers else 57310037SARM gem5 Developers vaddr = vaddr_tainted; 57411608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 5757294Sgblack@eecs.umich.edu 5767404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 5777404SAli.Saidi@ARM.com bool is_write = (mode == Write); 5787404SAli.Saidi@ARM.com 5797404SAli.Saidi@ARM.com if (!is_fetch) { 5807294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 5817404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 58210037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 58310037SARM gem5 Developers // LPAE is always disabled in SE mode 58410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 58510474Sandreas.hansson@arm.com vaddr_tainted, 58610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 58710474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 58810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 5897294Sgblack@eecs.umich.edu } 5907294Sgblack@eecs.umich.edu } 5917294Sgblack@eecs.umich.edu } 5926019Shines@cs.fsu.edu 5937093Sgblack@eecs.umich.edu Addr paddr; 5947404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 5957404SAli.Saidi@ARM.com 5967093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 59710474Sandreas.hansson@arm.com return std::make_shared<GenericPageTableFault>(vaddr_tainted); 5987093Sgblack@eecs.umich.edu req->setPaddr(paddr); 5996019Shines@cs.fsu.edu 60012005Sandreas.sandberg@arm.com return finalizePhysical(req, tc, mode); 6017404SAli.Saidi@ARM.com} 6027404SAli.Saidi@ARM.com 6037404SAli.Saidi@ARM.comFault 60410037SARM gem5 DevelopersTLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 60510037SARM gem5 Developers{ 60610037SARM gem5 Developers Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 60711608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 60810037SARM gem5 Developers bool is_fetch = (mode == Execute); 60910037SARM gem5 Developers bool is_write = (mode == Write); 61010037SARM gem5 Developers bool is_priv = isPriv && !(flags & UserMode); 61110037SARM gem5 Developers 61210037SARM gem5 Developers // Get the translation type from the actuall table entry 61310037SARM gem5 Developers ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 61410037SARM gem5 Developers : ArmFault::VmsaTran; 61510037SARM gem5 Developers 61610037SARM gem5 Developers // If this is the second stage of translation and the request is for a 61710037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 61810037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 61910037SARM gem5 Developers // as a device or strongly ordered. 62010037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 62110037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 62210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 62310474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 62410474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 62510474Sandreas.hansson@arm.com isStage2, tranMethod); 62610037SARM gem5 Developers } 62710037SARM gem5 Developers 62810037SARM gem5 Developers // Generate an alignment fault for unaligned data accesses to device or 62910037SARM gem5 Developers // strongly ordered memory 63010037SARM gem5 Developers if (!is_fetch) { 63110037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 63210037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 63310037SARM gem5 Developers alignFaults++; 63410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 63510474Sandreas.hansson@arm.com vaddr, TlbEntry::DomainType::NoAccess, is_write, 63610474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 63710474Sandreas.hansson@arm.com tranMethod); 63810037SARM gem5 Developers } 63910037SARM gem5 Developers } 64010037SARM gem5 Developers } 64110037SARM gem5 Developers 64210037SARM gem5 Developers if (te->nonCacheable) { 64310037SARM gem5 Developers // Prevent prefetching from I/O devices. 64410037SARM gem5 Developers if (req->isPrefetch()) { 64510037SARM gem5 Developers // Here we can safely use the fault status for the short 64610037SARM gem5 Developers // desc. format in all cases 64710474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64810474Sandreas.hansson@arm.com vaddr, ArmFault::PrefetchUncacheable, 64910474Sandreas.hansson@arm.com isStage2, tranMethod); 65010037SARM gem5 Developers } 65110037SARM gem5 Developers } 65210037SARM gem5 Developers 65310037SARM gem5 Developers if (!te->longDescFormat) { 65410037SARM gem5 Developers switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 65510037SARM gem5 Developers case 0: 65610037SARM gem5 Developers domainFaults++; 65710037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 65810037SARM gem5 Developers " domain: %#x write:%d\n", dacr, 65910037SARM gem5 Developers static_cast<uint8_t>(te->domain), is_write); 66011861Snikos.nikoleris@arm.com if (is_fetch) { 66111861Snikos.nikoleris@arm.com // Use PC value instead of vaddr because vaddr might 66211861Snikos.nikoleris@arm.com // be aligned to cache line and should not be the 66311861Snikos.nikoleris@arm.com // address reported in FAR 66410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 66511861Snikos.nikoleris@arm.com req->getPC(), 66610474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 66710474Sandreas.hansson@arm.com isStage2, tranMethod); 66811861Snikos.nikoleris@arm.com } else 66910474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 67010474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 67110474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 67210474Sandreas.hansson@arm.com isStage2, tranMethod); 67310037SARM gem5 Developers case 1: 67410037SARM gem5 Developers // Continue with permissions check 67510037SARM gem5 Developers break; 67610037SARM gem5 Developers case 2: 67710037SARM gem5 Developers panic("UNPRED domain\n"); 67810037SARM gem5 Developers case 3: 67910037SARM gem5 Developers return NoFault; 68010037SARM gem5 Developers } 68110037SARM gem5 Developers } 68210037SARM gem5 Developers 68310037SARM gem5 Developers // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 68410037SARM gem5 Developers uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 68510037SARM gem5 Developers uint8_t hap = te->hap; 68610037SARM gem5 Developers 68710037SARM gem5 Developers if (sctlr.afe == 1 || te->longDescFormat) 68810037SARM gem5 Developers ap |= 1; 68910037SARM gem5 Developers 69010037SARM gem5 Developers bool abt; 69110037SARM gem5 Developers bool isWritable = true; 69210037SARM gem5 Developers // If this is a stage 2 access (eg for reading stage 1 page table entries) 69310037SARM gem5 Developers // then don't perform the AP permissions check, we stil do the HAP check 69410037SARM gem5 Developers // below. 69510037SARM gem5 Developers if (isStage2) { 69610037SARM gem5 Developers abt = false; 69710037SARM gem5 Developers } else { 69810037SARM gem5 Developers switch (ap) { 69910037SARM gem5 Developers case 0: 70010037SARM gem5 Developers DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 70110037SARM gem5 Developers (int)sctlr.rs); 70210037SARM gem5 Developers if (!sctlr.xp) { 70310037SARM gem5 Developers switch ((int)sctlr.rs) { 70410037SARM gem5 Developers case 2: 70510037SARM gem5 Developers abt = is_write; 70610037SARM gem5 Developers break; 70710037SARM gem5 Developers case 1: 70810037SARM gem5 Developers abt = is_write || !is_priv; 70910037SARM gem5 Developers break; 71010037SARM gem5 Developers case 0: 71110037SARM gem5 Developers case 3: 71210037SARM gem5 Developers default: 71310037SARM gem5 Developers abt = true; 71410037SARM gem5 Developers break; 71510037SARM gem5 Developers } 71610037SARM gem5 Developers } else { 71710037SARM gem5 Developers abt = true; 71810037SARM gem5 Developers } 71910037SARM gem5 Developers break; 72010037SARM gem5 Developers case 1: 72110037SARM gem5 Developers abt = !is_priv; 72210037SARM gem5 Developers break; 72310037SARM gem5 Developers case 2: 72410037SARM gem5 Developers abt = !is_priv && is_write; 72510037SARM gem5 Developers isWritable = is_priv; 72610037SARM gem5 Developers break; 72710037SARM gem5 Developers case 3: 72810037SARM gem5 Developers abt = false; 72910037SARM gem5 Developers break; 73010037SARM gem5 Developers case 4: 73110037SARM gem5 Developers panic("UNPRED premissions\n"); 73210037SARM gem5 Developers case 5: 73310037SARM gem5 Developers abt = !is_priv || is_write; 73410037SARM gem5 Developers isWritable = false; 73510037SARM gem5 Developers break; 73610037SARM gem5 Developers case 6: 73710037SARM gem5 Developers case 7: 73810037SARM gem5 Developers abt = is_write; 73910037SARM gem5 Developers isWritable = false; 74010037SARM gem5 Developers break; 74110037SARM gem5 Developers default: 74210037SARM gem5 Developers panic("Unknown permissions %#x\n", ap); 74310037SARM gem5 Developers } 74410037SARM gem5 Developers } 74510037SARM gem5 Developers 74610037SARM gem5 Developers bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 74710037SARM gem5 Developers bool xn = te->xn || (isWritable && sctlr.wxn) || 74810037SARM gem5 Developers (ap == 3 && sctlr.uwxn && is_priv); 74910037SARM gem5 Developers if (is_fetch && (abt || xn || 75011495Sandreas.sandberg@arm.com (te->longDescFormat && te->pxn && is_priv) || 75110037SARM gem5 Developers (isSecure && te->ns && scr.sif))) { 75210037SARM gem5 Developers permsFaults++; 75310037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 75410037SARM gem5 Developers "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 75510037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 75611861Snikos.nikoleris@arm.com // Use PC value instead of vaddr because vaddr might be aligned to 75711861Snikos.nikoleris@arm.com // cache line and should not be the address reported in FAR 75810474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 75911861Snikos.nikoleris@arm.com req->getPC(), 76010474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 76110474Sandreas.hansson@arm.com isStage2, tranMethod); 76210037SARM gem5 Developers } else if (abt | hapAbt) { 76310037SARM gem5 Developers permsFaults++; 76410037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 76510037SARM gem5 Developers " write:%d\n", ap, is_priv, is_write); 76610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 76710474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 76810474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 76910474Sandreas.hansson@arm.com isStage2 | !abt, tranMethod); 77010037SARM gem5 Developers } 77110037SARM gem5 Developers return NoFault; 77210037SARM gem5 Developers} 77310037SARM gem5 Developers 77410037SARM gem5 Developers 77510037SARM gem5 DevelopersFault 77610037SARM gem5 DevelopersTLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 77710037SARM gem5 Developers ThreadContext *tc) 77810037SARM gem5 Developers{ 77910037SARM gem5 Developers assert(aarch64); 78010037SARM gem5 Developers 78110037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 78210854SNathanael.Premillieu@arm.com Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 78310037SARM gem5 Developers 78411608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 78510037SARM gem5 Developers bool is_fetch = (mode == Execute); 78610037SARM gem5 Developers bool is_write = (mode == Write); 78710037SARM gem5 Developers bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 78810037SARM gem5 Developers 78910037SARM gem5 Developers updateMiscReg(tc, curTranType); 79010037SARM gem5 Developers 79110037SARM gem5 Developers // If this is the second stage of translation and the request is for a 79210037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 79310037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 79410037SARM gem5 Developers // as a device or strongly ordered. 79510037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 79610037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 79710474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 79810474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 79910474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 80010474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 80110037SARM gem5 Developers } 80210037SARM gem5 Developers 80310037SARM gem5 Developers // Generate an alignment fault for unaligned accesses to device or 80410037SARM gem5 Developers // strongly ordered memory 80510037SARM gem5 Developers if (!is_fetch) { 80610037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 80710037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 80810037SARM gem5 Developers alignFaults++; 80910474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 81010474Sandreas.hansson@arm.com vaddr_tainted, 81110474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 81210474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 81310474Sandreas.hansson@arm.com ArmFault::LpaeTran); 81410037SARM gem5 Developers } 81510037SARM gem5 Developers } 81610037SARM gem5 Developers } 81710037SARM gem5 Developers 81810037SARM gem5 Developers if (te->nonCacheable) { 81910037SARM gem5 Developers // Prevent prefetching from I/O devices. 82010037SARM gem5 Developers if (req->isPrefetch()) { 82110037SARM gem5 Developers // Here we can safely use the fault status for the short 82210037SARM gem5 Developers // desc. format in all cases 82310474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 82410474Sandreas.hansson@arm.com vaddr_tainted, 82510474Sandreas.hansson@arm.com ArmFault::PrefetchUncacheable, 82610474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 82710037SARM gem5 Developers } 82810037SARM gem5 Developers } 82910037SARM gem5 Developers 83010037SARM gem5 Developers uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 83110037SARM gem5 Developers bool grant = false; 83210037SARM gem5 Developers 83310037SARM gem5 Developers uint8_t xn = te->xn; 83410037SARM gem5 Developers uint8_t pxn = te->pxn; 83510037SARM gem5 Developers bool r = !is_write && !is_fetch; 83610037SARM gem5 Developers bool w = is_write; 83710037SARM gem5 Developers bool x = is_fetch; 83810037SARM gem5 Developers DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 83910037SARM gem5 Developers "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 84010037SARM gem5 Developers 84110037SARM gem5 Developers if (isStage2) { 84211575SDylan.Johnson@ARM.com assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2); 84311575SDylan.Johnson@ARM.com // In stage 2 we use the hypervisor access permission bits. 84411575SDylan.Johnson@ARM.com // The following permissions are described in ARM DDI 0487A.f 84511575SDylan.Johnson@ARM.com // D4-1802 84611575SDylan.Johnson@ARM.com uint8_t hap = 0x3 & te->hap; 84711575SDylan.Johnson@ARM.com if (is_fetch) { 84811575SDylan.Johnson@ARM.com // sctlr.wxn overrides the xn bit 84911575SDylan.Johnson@ARM.com grant = !sctlr.wxn && !xn; 85011575SDylan.Johnson@ARM.com } else if (is_write) { 85111575SDylan.Johnson@ARM.com grant = hap & 0x2; 85211575SDylan.Johnson@ARM.com } else { // is_read 85311575SDylan.Johnson@ARM.com grant = hap & 0x1; 85411575SDylan.Johnson@ARM.com } 85510037SARM gem5 Developers } else { 85610037SARM gem5 Developers switch (aarch64EL) { 85710037SARM gem5 Developers case EL0: 85810037SARM gem5 Developers { 85910037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 86010037SARM gem5 Developers switch (perm) { 86110037SARM gem5 Developers case 0: 86210037SARM gem5 Developers case 1: 86310037SARM gem5 Developers case 8: 86410037SARM gem5 Developers case 9: 86510037SARM gem5 Developers grant = x; 86610037SARM gem5 Developers break; 86710037SARM gem5 Developers case 4: 86810037SARM gem5 Developers case 5: 86910037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 87010037SARM gem5 Developers break; 87110037SARM gem5 Developers case 6: 87210037SARM gem5 Developers case 7: 87310037SARM gem5 Developers grant = r || w; 87410037SARM gem5 Developers break; 87510037SARM gem5 Developers case 12: 87610037SARM gem5 Developers case 13: 87710037SARM gem5 Developers grant = r || x; 87810037SARM gem5 Developers break; 87910037SARM gem5 Developers case 14: 88010037SARM gem5 Developers case 15: 88110037SARM gem5 Developers grant = r; 88210037SARM gem5 Developers break; 88310037SARM gem5 Developers default: 88410037SARM gem5 Developers grant = false; 88510037SARM gem5 Developers } 88610037SARM gem5 Developers } 88710037SARM gem5 Developers break; 88810037SARM gem5 Developers case EL1: 88910037SARM gem5 Developers { 89010037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 89110037SARM gem5 Developers switch (perm) { 89210037SARM gem5 Developers case 0: 89310037SARM gem5 Developers case 2: 89410037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 89510037SARM gem5 Developers break; 89610037SARM gem5 Developers case 1: 89710037SARM gem5 Developers case 3: 89810037SARM gem5 Developers case 4: 89910037SARM gem5 Developers case 5: 90010037SARM gem5 Developers case 6: 90110037SARM gem5 Developers case 7: 90210037SARM gem5 Developers // regions that are writeable at EL0 should not be 90310037SARM gem5 Developers // executable at EL1 90410037SARM gem5 Developers grant = r || w; 90510037SARM gem5 Developers break; 90610037SARM gem5 Developers case 8: 90710037SARM gem5 Developers case 10: 90810037SARM gem5 Developers case 12: 90910037SARM gem5 Developers case 14: 91010037SARM gem5 Developers grant = r || x; 91110037SARM gem5 Developers break; 91210037SARM gem5 Developers case 9: 91310037SARM gem5 Developers case 11: 91410037SARM gem5 Developers case 13: 91510037SARM gem5 Developers case 15: 91610037SARM gem5 Developers grant = r; 91710037SARM gem5 Developers break; 91810037SARM gem5 Developers default: 91910037SARM gem5 Developers grant = false; 92010037SARM gem5 Developers } 92110037SARM gem5 Developers } 92210037SARM gem5 Developers break; 92310037SARM gem5 Developers case EL2: 92410037SARM gem5 Developers case EL3: 92510037SARM gem5 Developers { 92610037SARM gem5 Developers uint8_t perm = (ap & 0x2) | xn; 92710037SARM gem5 Developers switch (perm) { 92810037SARM gem5 Developers case 0: 92910037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn) ; 93010037SARM gem5 Developers break; 93110037SARM gem5 Developers case 1: 93210037SARM gem5 Developers grant = r || w; 93310037SARM gem5 Developers break; 93410037SARM gem5 Developers case 2: 93510037SARM gem5 Developers grant = r || x; 93610037SARM gem5 Developers break; 93710037SARM gem5 Developers case 3: 93810037SARM gem5 Developers grant = r; 93910037SARM gem5 Developers break; 94010037SARM gem5 Developers default: 94110037SARM gem5 Developers grant = false; 94210037SARM gem5 Developers } 94310037SARM gem5 Developers } 94410037SARM gem5 Developers break; 94510037SARM gem5 Developers } 94610037SARM gem5 Developers } 94710037SARM gem5 Developers 94810037SARM gem5 Developers if (!grant) { 94910037SARM gem5 Developers if (is_fetch) { 95010037SARM gem5 Developers permsFaults++; 95110037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 95210037SARM gem5 Developers "AP:%d priv:%d write:%d ns:%d sif:%d " 95310037SARM gem5 Developers "sctlr.afe: %d\n", 95410037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 95510037SARM gem5 Developers // Use PC value instead of vaddr because vaddr might be aligned to 95610037SARM gem5 Developers // cache line and should not be the address reported in FAR 95710474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 95810474Sandreas.hansson@arm.com req->getPC(), 95910474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 96010474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 96110037SARM gem5 Developers } else { 96210037SARM gem5 Developers permsFaults++; 96310037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 96410037SARM gem5 Developers "priv:%d write:%d\n", ap, is_priv, is_write); 96510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 96610474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 96710474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 96810474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 96910037SARM gem5 Developers } 97010037SARM gem5 Developers } 97110037SARM gem5 Developers 97210037SARM gem5 Developers return NoFault; 97310037SARM gem5 Developers} 97410037SARM gem5 Developers 97510037SARM gem5 DevelopersFault 9767404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 97710037SARM gem5 Developers Translation *translation, bool &delay, bool timing, 97810037SARM gem5 Developers TLB::ArmTranslationType tranType, bool functional) 9797404SAli.Saidi@ARM.com{ 9808733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 9818733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 9828733Sgeoffrey.blake@arm.com 98310037SARM gem5 Developers updateMiscReg(tc, tranType); 98410037SARM gem5 Developers 98510037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 98610037SARM gem5 Developers Addr vaddr = 0; 98710037SARM gem5 Developers if (aarch64) 98810854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 98910037SARM gem5 Developers else 99010037SARM gem5 Developers vaddr = vaddr_tainted; 99111608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 99210037SARM gem5 Developers 99310037SARM gem5 Developers bool is_fetch = (mode == Execute); 99410037SARM gem5 Developers bool is_write = (mode == Write); 99511517SCurtis.Dunham@arm.com bool long_desc_format = aarch64 || longDescFormatInUse(tc); 99610037SARM gem5 Developers ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 99710037SARM gem5 Developers : ArmFault::VmsaTran; 99810037SARM gem5 Developers 99910037SARM gem5 Developers req->setAsid(asid); 100010037SARM gem5 Developers 100110037SARM gem5 Developers DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 100210037SARM gem5 Developers isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 100310037SARM gem5 Developers 100410037SARM gem5 Developers DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 100511608Snikos.nikoleris@arm.com "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2, 100610037SARM gem5 Developers scr, sctlr, flags, tranType); 100710037SARM gem5 Developers 10087608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 10097608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 101012356Snikos.nikoleris@arm.com if (!req->isCacheMaintenance()) { 101112356Snikos.nikoleris@arm.com req->setFlags(Request::UNCACHEABLE); 101212356Snikos.nikoleris@arm.com } 101312356Snikos.nikoleris@arm.com req->setFlags(Request::STRICT_ORDER); 10147608SGene.Wu@arm.com } 10157404SAli.Saidi@ARM.com if (!is_fetch) { 10167404SAli.Saidi@ARM.com assert(flags & MustBeOne); 10177404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 101810037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 10197734SAli.Saidi@ARM.com alignFaults++; 102010474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 102110474Sandreas.hansson@arm.com vaddr_tainted, 102210474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 102310474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 102410474Sandreas.hansson@arm.com tranMethod); 10257404SAli.Saidi@ARM.com } 10267404SAli.Saidi@ARM.com } 10277404SAli.Saidi@ARM.com } 10287404SAli.Saidi@ARM.com 102910037SARM gem5 Developers // If guest MMU is off or hcr.vm=0 go straight to stage2 103010037SARM gem5 Developers if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 10317404SAli.Saidi@ARM.com 10327093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 103310037SARM gem5 Developers // When the MMU is off the security attribute corresponds to the 103410037SARM gem5 Developers // security state of the processor 103510037SARM gem5 Developers if (isSecure) 103610037SARM gem5 Developers req->setFlags(Request::SECURE); 103710037SARM gem5 Developers 103810037SARM gem5 Developers // @todo: double check this (ARM ARM issue C B3.2.1) 103912356Snikos.nikoleris@arm.com if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 || 104012356Snikos.nikoleris@arm.com nmrr.or0 == 0 || prrr.tr0 != 0x2) { 104112356Snikos.nikoleris@arm.com if (!req->isCacheMaintenance()) { 104212356Snikos.nikoleris@arm.com req->setFlags(Request::UNCACHEABLE); 104312356Snikos.nikoleris@arm.com } 104412356Snikos.nikoleris@arm.com req->setFlags(Request::STRICT_ORDER); 10457404SAli.Saidi@ARM.com } 10467436Sdam.sunwoo@arm.com 10477436Sdam.sunwoo@arm.com // Set memory attributes 10487436Sdam.sunwoo@arm.com TlbEntry temp_te; 104910037SARM gem5 Developers temp_te.ns = !isSecure; 105010037SARM gem5 Developers if (isStage2 || hcr.dc == 0 || isSecure || 105110037SARM gem5 Developers (isHyp && !(tranType & S1CTran))) { 105210037SARM gem5 Developers 105310037SARM gem5 Developers temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 105410037SARM gem5 Developers : TlbEntry::MemoryType::StronglyOrdered; 105510037SARM gem5 Developers temp_te.innerAttrs = 0x0; 105610037SARM gem5 Developers temp_te.outerAttrs = 0x0; 105710037SARM gem5 Developers temp_te.shareable = true; 105810037SARM gem5 Developers temp_te.outerShareable = true; 105910037SARM gem5 Developers } else { 106010037SARM gem5 Developers temp_te.mtype = TlbEntry::MemoryType::Normal; 106110037SARM gem5 Developers temp_te.innerAttrs = 0x3; 106210037SARM gem5 Developers temp_te.outerAttrs = 0x3; 106310037SARM gem5 Developers temp_te.shareable = false; 106410037SARM gem5 Developers temp_te.outerShareable = false; 106510037SARM gem5 Developers } 106610037SARM gem5 Developers temp_te.setAttributes(long_desc_format); 106710367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 106810367SAndrew.Bardsley@arm.com "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 106910037SARM gem5 Developers temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 107010037SARM gem5 Developers isStage2); 10717436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 10727436Sdam.sunwoo@arm.com 107311395Sandreas.sandberg@arm.com return testTranslation(req, mode, TlbEntry::DomainType::NoAccess); 10747404SAli.Saidi@ARM.com } 10757404SAli.Saidi@ARM.com 107610037SARM gem5 Developers DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 107710037SARM gem5 Developers isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 10787404SAli.Saidi@ARM.com // Translation enabled 10797404SAli.Saidi@ARM.com 108010037SARM gem5 Developers TlbEntry *te = NULL; 108110037SARM gem5 Developers TlbEntry mergeTe; 108210037SARM gem5 Developers Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 108310037SARM gem5 Developers functional, &mergeTe); 108410037SARM gem5 Developers // only proceed if we have a valid table entry 108510037SARM gem5 Developers if ((te == NULL) && (fault == NoFault)) delay = true; 108610037SARM gem5 Developers 108710037SARM gem5 Developers // If we have the table entry transfer some of the attributes to the 108810037SARM gem5 Developers // request that triggered the translation 108910037SARM gem5 Developers if (te != NULL) { 109010037SARM gem5 Developers // Set memory attributes 109110037SARM gem5 Developers DPRINTF(TLBVerbose, 109210367SAndrew.Bardsley@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, " 109310367SAndrew.Bardsley@arm.com "outerAttrs: %d, mtype: %d, isStage2: %d\n", 109410037SARM gem5 Developers te->shareable, te->innerAttrs, te->outerAttrs, 109510037SARM gem5 Developers static_cast<uint8_t>(te->mtype), isStage2); 109610037SARM gem5 Developers setAttr(te->attributes); 109710824SAndreas.Sandberg@ARM.com 109812356Snikos.nikoleris@arm.com if (te->nonCacheable && !req->isCacheMaintenance()) 109910825SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE); 110010825SAndreas.Sandberg@ARM.com 110110825SAndreas.Sandberg@ARM.com // Require requests to be ordered if the request goes to 110210825SAndreas.Sandberg@ARM.com // strongly ordered or device memory (i.e., anything other 110310825SAndreas.Sandberg@ARM.com // than normal memory requires strict order). 110410825SAndreas.Sandberg@ARM.com if (te->mtype != TlbEntry::MemoryType::Normal) 110510825SAndreas.Sandberg@ARM.com req->setFlags(Request::STRICT_ORDER); 110610037SARM gem5 Developers 110710508SAli.Saidi@ARM.com Addr pa = te->pAddr(vaddr); 110810508SAli.Saidi@ARM.com req->setPaddr(pa); 110910508SAli.Saidi@ARM.com 111010037SARM gem5 Developers if (isSecure && !te->ns) { 111110037SARM gem5 Developers req->setFlags(Request::SECURE); 111210037SARM gem5 Developers } 111310037SARM gem5 Developers if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 111410037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 111510037SARM gem5 Developers // Unaligned accesses to Device memory should always cause an 111610037SARM gem5 Developers // abort regardless of sctlr.a 111710037SARM gem5 Developers alignFaults++; 111810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 111910474Sandreas.hansson@arm.com vaddr_tainted, 112010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 112110474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 112210474Sandreas.hansson@arm.com tranMethod); 112310037SARM gem5 Developers } 112410037SARM gem5 Developers 112510037SARM gem5 Developers // Check for a trickbox generated address fault 112611395Sandreas.sandberg@arm.com if (fault == NoFault) 112711395Sandreas.sandberg@arm.com fault = testTranslation(req, mode, te->domain); 112810037SARM gem5 Developers } 112910037SARM gem5 Developers 113010037SARM gem5 Developers if (fault == NoFault) { 113112005Sandreas.sandberg@arm.com // Generate Illegal Inst Set State fault if IL bit is set in CPSR 113210037SARM gem5 Developers if (aarch64 && is_fetch && cpsr.il == 1) { 113310474Sandreas.hansson@arm.com return std::make_shared<IllegalInstSetStateFault>(); 113410037SARM gem5 Developers } 113512005Sandreas.sandberg@arm.com 113612005Sandreas.sandberg@arm.com // Don't try to finalize a physical address unless the 113712005Sandreas.sandberg@arm.com // translation has completed (i.e., there is a table entry). 113812005Sandreas.sandberg@arm.com return te ? finalizePhysical(req, tc, mode) : NoFault; 113912005Sandreas.sandberg@arm.com } else { 114012005Sandreas.sandberg@arm.com return fault; 114110037SARM gem5 Developers } 114210037SARM gem5 Developers} 114310037SARM gem5 Developers 114410037SARM gem5 DevelopersFault 114510037SARM gem5 DevelopersTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 114610037SARM gem5 Developers TLB::ArmTranslationType tranType) 114710037SARM gem5 Developers{ 114810037SARM gem5 Developers updateMiscReg(tc, tranType); 114910037SARM gem5 Developers 115010037SARM gem5 Developers if (directToStage2) { 115110037SARM gem5 Developers assert(stage2Tlb); 115210037SARM gem5 Developers return stage2Tlb->translateAtomic(req, tc, mode, tranType); 115310037SARM gem5 Developers } 115410037SARM gem5 Developers 115510037SARM gem5 Developers bool delay = false; 115610037SARM gem5 Developers Fault fault; 115710037SARM gem5 Developers if (FullSystem) 115810037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 115910037SARM gem5 Developers else 116010037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 116110037SARM gem5 Developers assert(!delay); 116210037SARM gem5 Developers return fault; 116310037SARM gem5 Developers} 116410037SARM gem5 Developers 116510037SARM gem5 DevelopersFault 116610037SARM gem5 DevelopersTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 116710037SARM gem5 Developers TLB::ArmTranslationType tranType) 116810037SARM gem5 Developers{ 116910037SARM gem5 Developers updateMiscReg(tc, tranType); 117010037SARM gem5 Developers 117110037SARM gem5 Developers if (directToStage2) { 117210037SARM gem5 Developers assert(stage2Tlb); 117310037SARM gem5 Developers return stage2Tlb->translateFunctional(req, tc, mode, tranType); 117410037SARM gem5 Developers } 117510037SARM gem5 Developers 117610037SARM gem5 Developers bool delay = false; 117710037SARM gem5 Developers Fault fault; 117810037SARM gem5 Developers if (FullSystem) 117910037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 118010037SARM gem5 Developers else 118110037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 118210037SARM gem5 Developers assert(!delay); 118310037SARM gem5 Developers return fault; 118410037SARM gem5 Developers} 118510037SARM gem5 Developers 118612406Sgabeblack@google.comvoid 118710037SARM gem5 DevelopersTLB::translateTiming(RequestPtr req, ThreadContext *tc, 118810037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 118910037SARM gem5 Developers{ 119010037SARM gem5 Developers updateMiscReg(tc, tranType); 119110037SARM gem5 Developers 119210037SARM gem5 Developers if (directToStage2) { 119310037SARM gem5 Developers assert(stage2Tlb); 119412406Sgabeblack@google.com stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 119512406Sgabeblack@google.com return; 119610037SARM gem5 Developers } 119710037SARM gem5 Developers 119810037SARM gem5 Developers assert(translation); 119910037SARM gem5 Developers 120012406Sgabeblack@google.com translateComplete(req, tc, translation, mode, tranType, isStage2); 120110037SARM gem5 Developers} 120210037SARM gem5 Developers 120310037SARM gem5 DevelopersFault 120410037SARM gem5 DevelopersTLB::translateComplete(RequestPtr req, ThreadContext *tc, 120510037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 120610037SARM gem5 Developers bool callFromS2) 120710037SARM gem5 Developers{ 120810037SARM gem5 Developers bool delay = false; 120910037SARM gem5 Developers Fault fault; 121010037SARM gem5 Developers if (FullSystem) 121110037SARM gem5 Developers fault = translateFs(req, tc, mode, translation, delay, true, tranType); 121210037SARM gem5 Developers else 121310037SARM gem5 Developers fault = translateSe(req, tc, mode, translation, delay, true); 121410037SARM gem5 Developers DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 121510037SARM gem5 Developers NoFault); 121610037SARM gem5 Developers // If we have a translation, and we're not in the middle of doing a stage 121710037SARM gem5 Developers // 2 translation tell the translation that we've either finished or its 121810037SARM gem5 Developers // going to take a while. By not doing this when we're in the middle of a 121910037SARM gem5 Developers // stage 2 translation we prevent marking the translation as delayed twice, 122010037SARM gem5 Developers // one when the translation starts and again when the stage 1 translation 122110037SARM gem5 Developers // completes. 122210037SARM gem5 Developers if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 122310037SARM gem5 Developers if (!delay) 122410037SARM gem5 Developers translation->finish(fault, req, tc, mode); 122510037SARM gem5 Developers else 122610037SARM gem5 Developers translation->markDelayed(); 122710037SARM gem5 Developers } 122810037SARM gem5 Developers return fault; 122910037SARM gem5 Developers} 123010037SARM gem5 Developers 123110037SARM gem5 DevelopersBaseMasterPort* 123210037SARM gem5 DevelopersTLB::getMasterPort() 123310037SARM gem5 Developers{ 123410717Sandreas.hansson@arm.com return &stage2Mmu->getPort(); 123510037SARM gem5 Developers} 123610037SARM gem5 Developers 123710037SARM gem5 Developersvoid 123810037SARM gem5 DevelopersTLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 123910037SARM gem5 Developers{ 124010037SARM gem5 Developers // check if the regs have changed, or the translation mode is different. 124110037SARM gem5 Developers // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 124210037SARM gem5 Developers // one type of translation anyway 124311152Smitch.hayenga@arm.com if (miscRegValid && miscRegContext == tc->contextId() && 124411152Smitch.hayenga@arm.com ((tranType == curTranType) || isStage2)) { 124510037SARM gem5 Developers return; 124610037SARM gem5 Developers } 124710037SARM gem5 Developers 124810037SARM gem5 Developers DPRINTF(TLBVerbose, "TLB variables changed!\n"); 124910854SNathanael.Premillieu@arm.com cpsr = tc->readMiscReg(MISCREG_CPSR); 125011505Sandreas.sandberg@arm.com 125110037SARM gem5 Developers // Dependencies: SCR/SCR_EL3, CPSR 125211505Sandreas.sandberg@arm.com isSecure = inSecureState(tc) && 125311505Sandreas.sandberg@arm.com !(tranType & HypMode) && !(tranType & S1S2NsTran); 125411505Sandreas.sandberg@arm.com 125511505Sandreas.sandberg@arm.com const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode; 125611505Sandreas.sandberg@arm.com aarch64 = opModeIs64(op_mode) || 125711505Sandreas.sandberg@arm.com (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1)); 125811505Sandreas.sandberg@arm.com 125910037SARM gem5 Developers if (aarch64) { // AArch64 126011577SDylan.Johnson@ARM.com // determine EL we need to translate in 126111577SDylan.Johnson@ARM.com switch (tranType) { 126211577SDylan.Johnson@ARM.com case S1E0Tran: 126311577SDylan.Johnson@ARM.com case S12E0Tran: 126411577SDylan.Johnson@ARM.com aarch64EL = EL0; 126511577SDylan.Johnson@ARM.com break; 126611577SDylan.Johnson@ARM.com case S1E1Tran: 126711577SDylan.Johnson@ARM.com case S12E1Tran: 126811577SDylan.Johnson@ARM.com aarch64EL = EL1; 126911577SDylan.Johnson@ARM.com break; 127011577SDylan.Johnson@ARM.com case S1E2Tran: 127111577SDylan.Johnson@ARM.com aarch64EL = EL2; 127211577SDylan.Johnson@ARM.com break; 127311577SDylan.Johnson@ARM.com case S1E3Tran: 127411577SDylan.Johnson@ARM.com aarch64EL = EL3; 127511577SDylan.Johnson@ARM.com break; 127611577SDylan.Johnson@ARM.com case NormalTran: 127711577SDylan.Johnson@ARM.com case S1CTran: 127811577SDylan.Johnson@ARM.com case S1S2NsTran: 127911577SDylan.Johnson@ARM.com case HypMode: 128011577SDylan.Johnson@ARM.com aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 128111577SDylan.Johnson@ARM.com break; 128211577SDylan.Johnson@ARM.com } 128311577SDylan.Johnson@ARM.com 128410037SARM gem5 Developers switch (aarch64EL) { 128510037SARM gem5 Developers case EL0: 128610037SARM gem5 Developers case EL1: 128710037SARM gem5 Developers { 128810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 128910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 129010037SARM gem5 Developers uint64_t ttbr_asid = ttbcr.a1 ? 129110037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR1_EL1) : 129210037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR0_EL1); 129310037SARM gem5 Developers asid = bits(ttbr_asid, 129410037SARM gem5 Developers (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 129510037SARM gem5 Developers } 129610037SARM gem5 Developers break; 129710037SARM gem5 Developers case EL2: 129810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 129910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 130010037SARM gem5 Developers asid = -1; 130110037SARM gem5 Developers break; 130210037SARM gem5 Developers case EL3: 130310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 130410037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 130510037SARM gem5 Developers asid = -1; 130610037SARM gem5 Developers break; 130710037SARM gem5 Developers } 130811575SDylan.Johnson@ARM.com hcr = tc->readMiscReg(MISCREG_HCR_EL2); 130910037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR_EL3); 131010037SARM gem5 Developers isPriv = aarch64EL != EL0; 131111575SDylan.Johnson@ARM.com if (haveVirtualization) { 131211575SDylan.Johnson@ARM.com vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48); 131311575SDylan.Johnson@ARM.com isHyp = tranType & HypMode; 131411575SDylan.Johnson@ARM.com isHyp &= (tranType & S1S2NsTran) == 0; 131511575SDylan.Johnson@ARM.com isHyp &= (tranType & S1CTran) == 0; 131611575SDylan.Johnson@ARM.com // Work out if we should skip the first stage of translation and go 131711575SDylan.Johnson@ARM.com // directly to stage 2. This value is cached so we don't have to 131811575SDylan.Johnson@ARM.com // compute it for every translation. 131911575SDylan.Johnson@ARM.com stage2Req = isStage2 || 132011575SDylan.Johnson@ARM.com (hcr.vm && !isHyp && !isSecure && 132111577SDylan.Johnson@ARM.com !(tranType & S1CTran) && (aarch64EL < EL2) && 132211577SDylan.Johnson@ARM.com !(tranType & S1E1Tran)); // <--- FIX THIS HACK 132311575SDylan.Johnson@ARM.com directToStage2 = !isStage2 && stage2Req && !sctlr.m; 132411575SDylan.Johnson@ARM.com } else { 132511575SDylan.Johnson@ARM.com vmid = 0; 132611575SDylan.Johnson@ARM.com isHyp = false; 132711575SDylan.Johnson@ARM.com directToStage2 = false; 132811575SDylan.Johnson@ARM.com stage2Req = false; 132911575SDylan.Johnson@ARM.com } 133010037SARM gem5 Developers } else { // AArch32 133112499Sgiacomo.travaglini@arm.com sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc, 133210037SARM gem5 Developers !isSecure)); 133312499Sgiacomo.travaglini@arm.com ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc, 133410037SARM gem5 Developers !isSecure)); 133510037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR); 133610037SARM gem5 Developers isPriv = cpsr.mode != MODE_USER; 133711517SCurtis.Dunham@arm.com if (longDescFormatInUse(tc)) { 133810037SARM gem5 Developers uint64_t ttbr_asid = tc->readMiscReg( 133912499Sgiacomo.travaglini@arm.com snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 : 134012499Sgiacomo.travaglini@arm.com MISCREG_TTBR0, 134110037SARM gem5 Developers tc, !isSecure)); 134210037SARM gem5 Developers asid = bits(ttbr_asid, 55, 48); 134311517SCurtis.Dunham@arm.com } else { // Short-descriptor translation table format in use 134412499Sgiacomo.travaglini@arm.com CONTEXTIDR context_id = tc->readMiscReg(snsBankedIndex( 134510037SARM gem5 Developers MISCREG_CONTEXTIDR, tc,!isSecure)); 134610037SARM gem5 Developers asid = context_id.asid; 134710037SARM gem5 Developers } 134812499Sgiacomo.travaglini@arm.com prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, tc, 134910037SARM gem5 Developers !isSecure)); 135012499Sgiacomo.travaglini@arm.com nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, tc, 135110037SARM gem5 Developers !isSecure)); 135212499Sgiacomo.travaglini@arm.com dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc, 135310037SARM gem5 Developers !isSecure)); 135410037SARM gem5 Developers hcr = tc->readMiscReg(MISCREG_HCR); 135510037SARM gem5 Developers 135610037SARM gem5 Developers if (haveVirtualization) { 135710037SARM gem5 Developers vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 135810037SARM gem5 Developers isHyp = cpsr.mode == MODE_HYP; 135910037SARM gem5 Developers isHyp |= tranType & HypMode; 136010037SARM gem5 Developers isHyp &= (tranType & S1S2NsTran) == 0; 136110037SARM gem5 Developers isHyp &= (tranType & S1CTran) == 0; 136210037SARM gem5 Developers if (isHyp) { 136310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_HSCTLR); 136410037SARM gem5 Developers } 136510037SARM gem5 Developers // Work out if we should skip the first stage of translation and go 136610037SARM gem5 Developers // directly to stage 2. This value is cached so we don't have to 136710037SARM gem5 Developers // compute it for every translation. 136810037SARM gem5 Developers stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 136910037SARM gem5 Developers !(tranType & S1CTran); 137010037SARM gem5 Developers directToStage2 = stage2Req && !sctlr.m; 137110037SARM gem5 Developers } else { 137210037SARM gem5 Developers vmid = 0; 137310037SARM gem5 Developers stage2Req = false; 137410037SARM gem5 Developers isHyp = false; 137510037SARM gem5 Developers directToStage2 = false; 137610037SARM gem5 Developers } 137710037SARM gem5 Developers } 137810037SARM gem5 Developers miscRegValid = true; 137911152Smitch.hayenga@arm.com miscRegContext = tc->contextId(); 138010037SARM gem5 Developers curTranType = tranType; 138110037SARM gem5 Developers} 138210037SARM gem5 Developers 138310037SARM gem5 DevelopersFault 138410037SARM gem5 DevelopersTLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 138510037SARM gem5 Developers Translation *translation, bool timing, bool functional, 138610037SARM gem5 Developers bool is_secure, TLB::ArmTranslationType tranType) 138710037SARM gem5 Developers{ 138810037SARM gem5 Developers bool is_fetch = (mode == Execute); 138910037SARM gem5 Developers bool is_write = (mode == Write); 139010037SARM gem5 Developers 139110037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 139210037SARM gem5 Developers Addr vaddr = 0; 139310037SARM gem5 Developers ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 139410037SARM gem5 Developers if (aarch64) { 139510854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr); 139610037SARM gem5 Developers } else { 139710037SARM gem5 Developers vaddr = vaddr_tainted; 139810037SARM gem5 Developers } 139910037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 140010037SARM gem5 Developers if (*te == NULL) { 140110037SARM gem5 Developers if (req->isPrefetch()) { 140210037SARM gem5 Developers // if the request is a prefetch don't attempt to fill the TLB or go 140310037SARM gem5 Developers // any further with the memory access (here we can safely use the 140410037SARM gem5 Developers // fault status for the short desc. format in all cases) 14057734SAli.Saidi@ARM.com prefetchFaults++; 140610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 140710474Sandreas.hansson@arm.com vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 14087611SGene.Wu@arm.com } 14097734SAli.Saidi@ARM.com 14107734SAli.Saidi@ARM.com if (is_fetch) 14117734SAli.Saidi@ARM.com instMisses++; 14127734SAli.Saidi@ARM.com else if (is_write) 14137734SAli.Saidi@ARM.com writeMisses++; 14147734SAli.Saidi@ARM.com else 14157734SAli.Saidi@ARM.com readMisses++; 14167734SAli.Saidi@ARM.com 14177404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 14187404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 141910037SARM gem5 Developers DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 142010037SARM gem5 Developers vaddr_tainted, asid, vmid); 142110037SARM gem5 Developers Fault fault; 142210037SARM gem5 Developers fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 142310037SARM gem5 Developers translation, timing, functional, is_secure, 142411580SDylan.Johnson@ARM.com tranType, stage2Req); 142510037SARM gem5 Developers // for timing mode, return and wait for table walk, 142610037SARM gem5 Developers if (timing || fault != NoFault) { 14277437Sdam.sunwoo@arm.com return fault; 14287437Sdam.sunwoo@arm.com } 14297404SAli.Saidi@ARM.com 143010037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 143110037SARM gem5 Developers if (!*te) 14327404SAli.Saidi@ARM.com printTlb(); 143310037SARM gem5 Developers assert(*te); 14347734SAli.Saidi@ARM.com } else { 14357734SAli.Saidi@ARM.com if (is_fetch) 14367734SAli.Saidi@ARM.com instHits++; 14377734SAli.Saidi@ARM.com else if (is_write) 14387734SAli.Saidi@ARM.com writeHits++; 14397734SAli.Saidi@ARM.com else 14407734SAli.Saidi@ARM.com readHits++; 14417404SAli.Saidi@ARM.com } 14426757SAli.Saidi@ARM.com return NoFault; 14437404SAli.Saidi@ARM.com} 14446757SAli.Saidi@ARM.com 14457404SAli.Saidi@ARM.comFault 144610037SARM gem5 DevelopersTLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 144710037SARM gem5 Developers Translation *translation, bool timing, bool functional, 144810037SARM gem5 Developers TlbEntry *mergeTe) 14497404SAli.Saidi@ARM.com{ 14507404SAli.Saidi@ARM.com Fault fault; 145111575SDylan.Johnson@ARM.com 145211575SDylan.Johnson@ARM.com if (isStage2) { 145311575SDylan.Johnson@ARM.com // We are already in the stage 2 TLB. Grab the table entry for stage 145411575SDylan.Johnson@ARM.com // 2 only. We are here because stage 1 translation is disabled. 145511575SDylan.Johnson@ARM.com TlbEntry *s2Te = NULL; 145611575SDylan.Johnson@ARM.com // Get the stage 2 table entry 145711575SDylan.Johnson@ARM.com fault = getTE(&s2Te, req, tc, mode, translation, timing, functional, 145811575SDylan.Johnson@ARM.com isSecure, curTranType); 145911575SDylan.Johnson@ARM.com // Check permissions of stage 2 146011575SDylan.Johnson@ARM.com if ((s2Te != NULL) && (fault = NoFault)) { 146111575SDylan.Johnson@ARM.com if(aarch64) 146211575SDylan.Johnson@ARM.com fault = checkPermissions64(s2Te, req, mode, tc); 146311575SDylan.Johnson@ARM.com else 146411575SDylan.Johnson@ARM.com fault = checkPermissions(s2Te, req, mode); 146511575SDylan.Johnson@ARM.com } 146611575SDylan.Johnson@ARM.com *te = s2Te; 146711575SDylan.Johnson@ARM.com return fault; 146811575SDylan.Johnson@ARM.com } 146911575SDylan.Johnson@ARM.com 147010037SARM gem5 Developers TlbEntry *s1Te = NULL; 147110037SARM gem5 Developers 147210037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 147310037SARM gem5 Developers 147410037SARM gem5 Developers // Get the stage 1 table entry 147510037SARM gem5 Developers fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 147610037SARM gem5 Developers isSecure, curTranType); 147710037SARM gem5 Developers // only proceed if we have a valid table entry 147810037SARM gem5 Developers if ((s1Te != NULL) && (fault == NoFault)) { 147910037SARM gem5 Developers // Check stage 1 permissions before checking stage 2 148010037SARM gem5 Developers if (aarch64) 148110037SARM gem5 Developers fault = checkPermissions64(s1Te, req, mode, tc); 148210037SARM gem5 Developers else 148310037SARM gem5 Developers fault = checkPermissions(s1Te, req, mode); 148410037SARM gem5 Developers if (stage2Req & (fault == NoFault)) { 148510037SARM gem5 Developers Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 148610037SARM gem5 Developers req, translation, mode, timing, functional, curTranType); 148710037SARM gem5 Developers fault = s2Lookup->getTe(tc, mergeTe); 148810037SARM gem5 Developers if (s2Lookup->isComplete()) { 148910037SARM gem5 Developers *te = mergeTe; 149010037SARM gem5 Developers // We've finished with the lookup so delete it 149110037SARM gem5 Developers delete s2Lookup; 149210037SARM gem5 Developers } else { 149310037SARM gem5 Developers // The lookup hasn't completed, so we can't delete it now. We 149410037SARM gem5 Developers // get round this by asking the object to self delete when the 149510037SARM gem5 Developers // translation is complete. 149610037SARM gem5 Developers s2Lookup->setSelfDelete(); 149710037SARM gem5 Developers } 149810037SARM gem5 Developers } else { 149910037SARM gem5 Developers // This case deals with an S1 hit (or bypass), followed by 150010037SARM gem5 Developers // an S2 hit-but-perms issue 150110037SARM gem5 Developers if (isStage2) { 150210037SARM gem5 Developers DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 150310037SARM gem5 Developers vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 150410037SARM gem5 Developers if (fault != NoFault) { 150510037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 150610037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, false); 150710037SARM gem5 Developers armFault->annotate(ArmFault::OVA, vaddr_tainted); 150810037SARM gem5 Developers } 150910037SARM gem5 Developers } 151010037SARM gem5 Developers *te = s1Te; 151110037SARM gem5 Developers } 151210037SARM gem5 Developers } 15137404SAli.Saidi@ARM.com return fault; 15146019Shines@cs.fsu.edu} 15156019Shines@cs.fsu.edu 151611395Sandreas.sandberg@arm.comvoid 151711395Sandreas.sandberg@arm.comTLB::setTestInterface(SimObject *_ti) 151811395Sandreas.sandberg@arm.com{ 151911395Sandreas.sandberg@arm.com if (!_ti) { 152011395Sandreas.sandberg@arm.com test = nullptr; 152111395Sandreas.sandberg@arm.com } else { 152211395Sandreas.sandberg@arm.com TlbTestInterface *ti(dynamic_cast<TlbTestInterface *>(_ti)); 152311395Sandreas.sandberg@arm.com fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 152411395Sandreas.sandberg@arm.com test = ti; 152511395Sandreas.sandberg@arm.com } 152611395Sandreas.sandberg@arm.com} 152711395Sandreas.sandberg@arm.com 152811395Sandreas.sandberg@arm.comFault 152911395Sandreas.sandberg@arm.comTLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 153011395Sandreas.sandberg@arm.com{ 153111560Sandreas.sandberg@arm.com if (!test || !req->hasSize() || req->getSize() == 0) { 153211395Sandreas.sandberg@arm.com return NoFault; 153311395Sandreas.sandberg@arm.com } else { 153411395Sandreas.sandberg@arm.com return test->translationCheck(req, isPriv, mode, domain); 153511395Sandreas.sandberg@arm.com } 153611395Sandreas.sandberg@arm.com} 153711395Sandreas.sandberg@arm.com 153811395Sandreas.sandberg@arm.comFault 153911395Sandreas.sandberg@arm.comTLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 154011395Sandreas.sandberg@arm.com TlbEntry::DomainType domain, LookupLevel lookup_level) 154111395Sandreas.sandberg@arm.com{ 154211395Sandreas.sandberg@arm.com if (!test) { 154311395Sandreas.sandberg@arm.com return NoFault; 154411395Sandreas.sandberg@arm.com } else { 154511395Sandreas.sandberg@arm.com return test->walkCheck(pa, size, va, is_secure, isPriv, mode, 154611395Sandreas.sandberg@arm.com domain, lookup_level); 154711395Sandreas.sandberg@arm.com } 154811395Sandreas.sandberg@arm.com} 154911395Sandreas.sandberg@arm.com 155011395Sandreas.sandberg@arm.com 15516116Snate@binkert.orgArmISA::TLB * 15526116Snate@binkert.orgArmTLBParams::create() 15536019Shines@cs.fsu.edu{ 15546116Snate@binkert.org return new ArmISA::TLB(this); 15556019Shines@cs.fsu.edu} 1556