tlb.cc revision 11584
16019Shines@cs.fsu.edu/* 211495Sandreas.sandberg@arm.com * Copyright (c) 2010-2013, 2016 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 4510873Sandreas.sandberg@arm.com#include "arch/arm/tlb.hh" 4610873Sandreas.sandberg@arm.com 4710474Sandreas.hansson@arm.com#include <memory> 486019Shines@cs.fsu.edu#include <string> 496019Shines@cs.fsu.edu#include <vector> 506019Shines@cs.fsu.edu 516116Snate@binkert.org#include "arch/arm/faults.hh" 526019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 538782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 548756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 5510037SARM gem5 Developers#include "arch/arm/stage2_lookup.hh" 5610037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 576019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 586019Shines@cs.fsu.edu#include "base/inifile.hh" 596019Shines@cs.fsu.edu#include "base/str.hh" 606019Shines@cs.fsu.edu#include "base/trace.hh" 6110024Sdam.sunwoo@arm.com#include "cpu/base.hh" 626019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 638232Snate@binkert.org#include "debug/Checkpoint.hh" 648232Snate@binkert.org#include "debug/TLB.hh" 658232Snate@binkert.org#include "debug/TLBVerbose.hh" 666116Snate@binkert.org#include "mem/page_table.hh" 676116Snate@binkert.org#include "params/ArmTLB.hh" 688756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 696019Shines@cs.fsu.edu#include "sim/process.hh" 706019Shines@cs.fsu.edu 716019Shines@cs.fsu.eduusing namespace std; 726019Shines@cs.fsu.eduusing namespace ArmISA; 736019Shines@cs.fsu.edu 7410037SARM gem5 DevelopersTLB::TLB(const ArmTLBParams *p) 7510037SARM gem5 Developers : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 7610418Sandreas.hansson@arm.com isStage2(p->is_stage2), stage2Req(false), _attr(0), 7710418Sandreas.hansson@arm.com directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 7811395Sandreas.sandberg@arm.com stage2Mmu(NULL), test(nullptr), rangeMRU(1), 7910537Sandreas.hansson@arm.com aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), 8010537Sandreas.hansson@arm.com isHyp(false), asid(0), vmid(0), dacr(0), 8111152Smitch.hayenga@arm.com miscRegValid(false), miscRegContext(0), curTranType(NormalTran) 826019Shines@cs.fsu.edu{ 8310037SARM gem5 Developers tableWalker->setTlb(this); 847399SAli.Saidi@ARM.com 8510037SARM gem5 Developers // Cache system-level properties 8610037SARM gem5 Developers haveLPAE = tableWalker->haveLPAE(); 8710037SARM gem5 Developers haveVirtualization = tableWalker->haveVirtualization(); 8810037SARM gem5 Developers haveLargeAsid64 = tableWalker->haveLargeAsid64(); 896019Shines@cs.fsu.edu} 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.eduTLB::~TLB() 926019Shines@cs.fsu.edu{ 9310037SARM gem5 Developers delete[] table; 9410037SARM gem5 Developers} 9510037SARM gem5 Developers 9610037SARM gem5 Developersvoid 9710037SARM gem5 DevelopersTLB::init() 9810037SARM gem5 Developers{ 9910037SARM gem5 Developers if (stage2Mmu && !isStage2) 10010037SARM gem5 Developers stage2Tlb = stage2Mmu->stage2Tlb(); 10110037SARM gem5 Developers} 10210037SARM gem5 Developers 10310037SARM gem5 Developersvoid 10410717Sandreas.hansson@arm.comTLB::setMMU(Stage2MMU *m, MasterID master_id) 10510037SARM gem5 Developers{ 10610037SARM gem5 Developers stage2Mmu = m; 10710717Sandreas.hansson@arm.com tableWalker->setMMU(m, master_id); 1086019Shines@cs.fsu.edu} 1096019Shines@cs.fsu.edu 1107694SAli.Saidi@ARM.combool 1117694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 1127694SAli.Saidi@ARM.com{ 11310037SARM gem5 Developers updateMiscReg(tc); 11410037SARM gem5 Developers 11510037SARM gem5 Developers if (directToStage2) { 11610037SARM gem5 Developers assert(stage2Tlb); 11710037SARM gem5 Developers return stage2Tlb->translateFunctional(tc, va, pa); 11810037SARM gem5 Developers } 11910037SARM gem5 Developers 12010037SARM gem5 Developers TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 12110037SARM gem5 Developers aarch64 ? aarch64EL : EL1); 1227694SAli.Saidi@ARM.com if (!e) 1237694SAli.Saidi@ARM.com return false; 1247694SAli.Saidi@ARM.com pa = e->pAddr(va); 1257694SAli.Saidi@ARM.com return true; 1267694SAli.Saidi@ARM.com} 1277694SAli.Saidi@ARM.com 1289738Sandreas@sandberg.pp.seFault 1299738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 1309738Sandreas@sandberg.pp.se{ 1319738Sandreas@sandberg.pp.se return NoFault; 1329738Sandreas@sandberg.pp.se} 1339738Sandreas@sandberg.pp.se 1347404SAli.Saidi@ARM.comTlbEntry* 13510037SARM gem5 DevelopersTLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 13610037SARM gem5 Developers bool functional, bool ignore_asn, uint8_t target_el) 1376019Shines@cs.fsu.edu{ 1387404SAli.Saidi@ARM.com 1397404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1407404SAli.Saidi@ARM.com 14110037SARM gem5 Developers // Maintaining LRU array 1427404SAli.Saidi@ARM.com int x = 0; 1437404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 14410037SARM gem5 Developers if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 14510037SARM gem5 Developers target_el)) || 14610037SARM gem5 Developers (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 14710037SARM gem5 Developers // We only move the hit entry ahead when the position is higher 14810037SARM gem5 Developers // than rangeMRU 1499535Smrinmoy.ghosh@arm.com if (x > rangeMRU && !functional) { 1507697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 15111321Ssteve.reinhardt@amd.com for (int i = x; i > 0; i--) 15210037SARM gem5 Developers table[i] = table[i - 1]; 1537697SAli.Saidi@ARM.com table[0] = tmp_entry; 1547697SAli.Saidi@ARM.com retval = &table[0]; 1557697SAli.Saidi@ARM.com } else { 1567697SAli.Saidi@ARM.com retval = &table[x]; 1577697SAli.Saidi@ARM.com } 1587404SAli.Saidi@ARM.com break; 1597404SAli.Saidi@ARM.com } 16010037SARM gem5 Developers ++x; 1617404SAli.Saidi@ARM.com } 1627404SAli.Saidi@ARM.com 16310037SARM gem5 Developers DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 16410037SARM gem5 Developers "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 16510037SARM gem5 Developers "el: %d\n", 16610037SARM gem5 Developers va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 16710037SARM gem5 Developers retval ? retval->pfn : 0, retval ? retval->size : 0, 16810037SARM gem5 Developers retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 16910037SARM gem5 Developers retval ? retval->ns : 0, retval ? retval->nstid : 0, 17010037SARM gem5 Developers retval ? retval->global : 0, retval ? retval->asid : 0, 17110367SAndrew.Bardsley@arm.com retval ? retval->el : 0); 17210037SARM gem5 Developers 1737404SAli.Saidi@ARM.com return retval; 1746019Shines@cs.fsu.edu} 1756019Shines@cs.fsu.edu 1766019Shines@cs.fsu.edu// insert a new TLB entry 1776019Shines@cs.fsu.eduvoid 1787404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1796019Shines@cs.fsu.edu{ 1807404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 18110037SARM gem5 Developers " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 18210037SARM gem5 Developers " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 18310037SARM gem5 Developers entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 18410037SARM gem5 Developers entry.global, entry.valid, entry.nonCacheable, entry.xn, 18510037SARM gem5 Developers entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 18610037SARM gem5 Developers entry.isHyp); 1877404SAli.Saidi@ARM.com 18810037SARM gem5 Developers if (table[size - 1].valid) 18910037SARM gem5 Developers DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 19010037SARM gem5 Developers "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 1917697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 19210037SARM gem5 Developers table[size-1].vmid, table[size-1].pfn << table[size-1].N, 19310037SARM gem5 Developers table[size-1].size, table[size-1].ap, table[size-1].ns, 19410037SARM gem5 Developers table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 19510037SARM gem5 Developers table[size-1].el); 1967404SAli.Saidi@ARM.com 1977697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1987404SAli.Saidi@ARM.com 19910037SARM gem5 Developers for (int i = size - 1; i > 0; --i) 20010037SARM gem5 Developers table[i] = table[i-1]; 2017697SAli.Saidi@ARM.com table[0] = entry; 2027734SAli.Saidi@ARM.com 2037734SAli.Saidi@ARM.com inserts++; 20410463SAndreas.Sandberg@ARM.com ppRefills->notify(1); 2056019Shines@cs.fsu.edu} 2066019Shines@cs.fsu.edu 2076019Shines@cs.fsu.eduvoid 20810037SARM gem5 DevelopersTLB::printTlb() const 2097404SAli.Saidi@ARM.com{ 2107404SAli.Saidi@ARM.com int x = 0; 2117404SAli.Saidi@ARM.com TlbEntry *te; 2127404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 2137404SAli.Saidi@ARM.com while (x < size) { 21410037SARM gem5 Developers te = &table[x]; 21510037SARM gem5 Developers if (te->valid) 21610037SARM gem5 Developers DPRINTF(TLB, " * %s\n", te->print()); 21710037SARM gem5 Developers ++x; 2187404SAli.Saidi@ARM.com } 2197404SAli.Saidi@ARM.com} 2207404SAli.Saidi@ARM.com 2217404SAli.Saidi@ARM.comvoid 22210037SARM gem5 DevelopersTLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el) 2236019Shines@cs.fsu.edu{ 22410037SARM gem5 Developers DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 22510037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2267404SAli.Saidi@ARM.com int x = 0; 2277404SAli.Saidi@ARM.com TlbEntry *te; 2287404SAli.Saidi@ARM.com while (x < size) { 22910037SARM gem5 Developers te = &table[x]; 23010037SARM gem5 Developers if (te->valid && secure_lookup == !te->nstid && 23110037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 23210037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 23310037SARM gem5 Developers 23410037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 23510037SARM gem5 Developers te->valid = false; 23610037SARM gem5 Developers flushedEntries++; 23710037SARM gem5 Developers } 23810037SARM gem5 Developers ++x; 2397404SAli.Saidi@ARM.com } 2407404SAli.Saidi@ARM.com 24110037SARM gem5 Developers flushTlb++; 24210037SARM gem5 Developers 24310037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 24410037SARM gem5 Developers // if we're currently in hyp mode 24510037SARM gem5 Developers if (!isStage2 && isHyp) { 24610037SARM gem5 Developers stage2Tlb->flushAllSecurity(secure_lookup, true); 24710037SARM gem5 Developers } 24810037SARM gem5 Developers} 24910037SARM gem5 Developers 25010037SARM gem5 Developersvoid 25110037SARM gem5 DevelopersTLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el) 25210037SARM gem5 Developers{ 25310037SARM gem5 Developers DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 25410037SARM gem5 Developers (hyp ? "hyp" : "non-hyp")); 25510037SARM gem5 Developers int x = 0; 25610037SARM gem5 Developers TlbEntry *te; 25710037SARM gem5 Developers while (x < size) { 25810037SARM gem5 Developers te = &table[x]; 25910037SARM gem5 Developers if (te->valid && te->nstid && te->isHyp == hyp && 26010037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 26110037SARM gem5 Developers 26210037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 26310037SARM gem5 Developers flushedEntries++; 26410037SARM gem5 Developers te->valid = false; 26510037SARM gem5 Developers } 26610037SARM gem5 Developers ++x; 26710037SARM gem5 Developers } 2687734SAli.Saidi@ARM.com 2697734SAli.Saidi@ARM.com flushTlb++; 27010037SARM gem5 Developers 27110037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 27210037SARM gem5 Developers if (!isStage2 && !hyp) { 27310037SARM gem5 Developers stage2Tlb->flushAllNs(false, true); 27410037SARM gem5 Developers } 2756019Shines@cs.fsu.edu} 2766019Shines@cs.fsu.edu 2777404SAli.Saidi@ARM.comvoid 27810037SARM gem5 DevelopersTLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) 2797404SAli.Saidi@ARM.com{ 28010037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 28110037SARM gem5 Developers "(%s lookup)\n", mva, asn, (secure_lookup ? 28210037SARM gem5 Developers "secure" : "non-secure")); 28310037SARM gem5 Developers _flushMva(mva, asn, secure_lookup, false, false, target_el); 2847734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2857404SAli.Saidi@ARM.com} 2867404SAli.Saidi@ARM.com 2877404SAli.Saidi@ARM.comvoid 28810037SARM gem5 DevelopersTLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) 2897404SAli.Saidi@ARM.com{ 29010037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 29110037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2927404SAli.Saidi@ARM.com 29310037SARM gem5 Developers int x = 0 ; 2947404SAli.Saidi@ARM.com TlbEntry *te; 2957404SAli.Saidi@ARM.com 2967404SAli.Saidi@ARM.com while (x < size) { 2977404SAli.Saidi@ARM.com te = &table[x]; 29810037SARM gem5 Developers if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 29910037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 30010037SARM gem5 Developers checkELMatch(target_el, te->el, false)) { 30110037SARM gem5 Developers 3027404SAli.Saidi@ARM.com te->valid = false; 30310037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3047734SAli.Saidi@ARM.com flushedEntries++; 3057404SAli.Saidi@ARM.com } 30610037SARM gem5 Developers ++x; 3077404SAli.Saidi@ARM.com } 3087734SAli.Saidi@ARM.com flushTlbAsid++; 3097404SAli.Saidi@ARM.com} 3107404SAli.Saidi@ARM.com 3117404SAli.Saidi@ARM.comvoid 31210037SARM gem5 DevelopersTLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) 3137404SAli.Saidi@ARM.com{ 31410037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 31510037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 31610037SARM gem5 Developers _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el); 31710037SARM gem5 Developers flushTlbMva++; 31810037SARM gem5 Developers} 3197404SAli.Saidi@ARM.com 32010037SARM gem5 Developersvoid 32110037SARM gem5 DevelopersTLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, 32210037SARM gem5 Developers bool ignore_asn, uint8_t target_el) 32310037SARM gem5 Developers{ 3247404SAli.Saidi@ARM.com TlbEntry *te; 32510037SARM gem5 Developers // D5.7.2: Sign-extend address to 64 bits 32610037SARM gem5 Developers mva = sext<56>(mva); 32710037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 32810037SARM gem5 Developers target_el); 32910037SARM gem5 Developers while (te != NULL) { 33010037SARM gem5 Developers if (secure_lookup == !te->nstid) { 33110037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3327404SAli.Saidi@ARM.com te->valid = false; 3337734SAli.Saidi@ARM.com flushedEntries++; 3347404SAli.Saidi@ARM.com } 33510037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 33610037SARM gem5 Developers target_el); 3377404SAli.Saidi@ARM.com } 33810037SARM gem5 Developers} 33910037SARM gem5 Developers 34011584SDylan.Johnson@ARM.comvoid 34111584SDylan.Johnson@ARM.comTLB::flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el) 34211584SDylan.Johnson@ARM.com{ 34311584SDylan.Johnson@ARM.com assert(!isStage2); 34411584SDylan.Johnson@ARM.com stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, hyp, true, target_el); 34511584SDylan.Johnson@ARM.com} 34611584SDylan.Johnson@ARM.com 34710037SARM gem5 Developersbool 34810037SARM gem5 DevelopersTLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) 34910037SARM gem5 Developers{ 35010037SARM gem5 Developers bool elMatch = true; 35110037SARM gem5 Developers if (!ignore_el) { 35210037SARM gem5 Developers if (target_el == 2 || target_el == 3) { 35310037SARM gem5 Developers elMatch = (tentry_el == target_el); 35410037SARM gem5 Developers } else { 35510037SARM gem5 Developers elMatch = (tentry_el == 0) || (tentry_el == 1); 35610037SARM gem5 Developers } 35710037SARM gem5 Developers } 35810037SARM gem5 Developers return elMatch; 3597404SAli.Saidi@ARM.com} 3607404SAli.Saidi@ARM.com 3616019Shines@cs.fsu.eduvoid 3629439SAndreas.Sandberg@ARM.comTLB::drainResume() 3639439SAndreas.Sandberg@ARM.com{ 3649439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 3659439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 3669439SAndreas.Sandberg@ARM.com miscRegValid = false; 3679439SAndreas.Sandberg@ARM.com} 3689439SAndreas.Sandberg@ARM.com 3699439SAndreas.Sandberg@ARM.comvoid 37010194SGeoffrey.Blake@arm.comTLB::takeOverFrom(BaseTLB *_otlb) 37110194SGeoffrey.Blake@arm.com{ 37210194SGeoffrey.Blake@arm.com TLB *otlb = dynamic_cast<TLB*>(_otlb); 37310194SGeoffrey.Blake@arm.com /* Make sure we actually have a valid type */ 37410194SGeoffrey.Blake@arm.com if (otlb) { 37510194SGeoffrey.Blake@arm.com _attr = otlb->_attr; 37610194SGeoffrey.Blake@arm.com haveLPAE = otlb->haveLPAE; 37710194SGeoffrey.Blake@arm.com directToStage2 = otlb->directToStage2; 37810194SGeoffrey.Blake@arm.com stage2Req = otlb->stage2Req; 37910194SGeoffrey.Blake@arm.com 38010194SGeoffrey.Blake@arm.com /* Sync the stage2 MMU if they exist in both 38110194SGeoffrey.Blake@arm.com * the old CPU and the new 38210194SGeoffrey.Blake@arm.com */ 38310194SGeoffrey.Blake@arm.com if (!isStage2 && 38410194SGeoffrey.Blake@arm.com stage2Tlb && otlb->stage2Tlb) { 38510194SGeoffrey.Blake@arm.com stage2Tlb->takeOverFrom(otlb->stage2Tlb); 38610194SGeoffrey.Blake@arm.com } 38710194SGeoffrey.Blake@arm.com } else { 38810194SGeoffrey.Blake@arm.com panic("Incompatible TLB type!"); 38910194SGeoffrey.Blake@arm.com } 39010194SGeoffrey.Blake@arm.com} 39110194SGeoffrey.Blake@arm.com 39210194SGeoffrey.Blake@arm.comvoid 39310905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 3946019Shines@cs.fsu.edu{ 3957733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 3967733SAli.Saidi@ARM.com 3977733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 39810037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 39910037SARM gem5 Developers SERIALIZE_SCALAR(directToStage2); 40010037SARM gem5 Developers SERIALIZE_SCALAR(stage2Req); 4018353SAli.Saidi@ARM.com 4028353SAli.Saidi@ARM.com int num_entries = size; 4038353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 40411321Ssteve.reinhardt@amd.com for (int i = 0; i < size; i++) 40510905Sandreas.sandberg@arm.com table[i].serializeSection(cp, csprintf("TlbEntry%d", i)); 4066019Shines@cs.fsu.edu} 4076019Shines@cs.fsu.edu 4086019Shines@cs.fsu.eduvoid 40910905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 4106019Shines@cs.fsu.edu{ 4117733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 4126019Shines@cs.fsu.edu 4137733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 41410037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 41510037SARM gem5 Developers UNSERIALIZE_SCALAR(directToStage2); 41610037SARM gem5 Developers UNSERIALIZE_SCALAR(stage2Req); 41710037SARM gem5 Developers 4188353SAli.Saidi@ARM.com int num_entries; 4198353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 42011321Ssteve.reinhardt@amd.com for (int i = 0; i < min(size, num_entries); i++) 42110905Sandreas.sandberg@arm.com table[i].unserializeSection(cp, csprintf("TlbEntry%d", i)); 4226019Shines@cs.fsu.edu} 4236019Shines@cs.fsu.edu 4246019Shines@cs.fsu.eduvoid 4256019Shines@cs.fsu.eduTLB::regStats() 4266019Shines@cs.fsu.edu{ 42711522Sstephan.diestelhorst@arm.com BaseTLB::regStats(); 4287734SAli.Saidi@ARM.com instHits 4297734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 4307734SAli.Saidi@ARM.com .desc("ITB inst hits") 4317734SAli.Saidi@ARM.com ; 4327734SAli.Saidi@ARM.com 4337734SAli.Saidi@ARM.com instMisses 4347734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 4357734SAli.Saidi@ARM.com .desc("ITB inst misses") 4367734SAli.Saidi@ARM.com ; 4377734SAli.Saidi@ARM.com 4387734SAli.Saidi@ARM.com instAccesses 4397734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 4407734SAli.Saidi@ARM.com .desc("ITB inst accesses") 4417734SAli.Saidi@ARM.com ; 4427734SAli.Saidi@ARM.com 4437734SAli.Saidi@ARM.com readHits 4446019Shines@cs.fsu.edu .name(name() + ".read_hits") 4456019Shines@cs.fsu.edu .desc("DTB read hits") 4466019Shines@cs.fsu.edu ; 4476019Shines@cs.fsu.edu 4487734SAli.Saidi@ARM.com readMisses 4496019Shines@cs.fsu.edu .name(name() + ".read_misses") 4506019Shines@cs.fsu.edu .desc("DTB read misses") 4516019Shines@cs.fsu.edu ; 4526019Shines@cs.fsu.edu 4537734SAli.Saidi@ARM.com readAccesses 4546019Shines@cs.fsu.edu .name(name() + ".read_accesses") 4556019Shines@cs.fsu.edu .desc("DTB read accesses") 4566019Shines@cs.fsu.edu ; 4576019Shines@cs.fsu.edu 4587734SAli.Saidi@ARM.com writeHits 4596019Shines@cs.fsu.edu .name(name() + ".write_hits") 4606019Shines@cs.fsu.edu .desc("DTB write hits") 4616019Shines@cs.fsu.edu ; 4626019Shines@cs.fsu.edu 4637734SAli.Saidi@ARM.com writeMisses 4646019Shines@cs.fsu.edu .name(name() + ".write_misses") 4656019Shines@cs.fsu.edu .desc("DTB write misses") 4666019Shines@cs.fsu.edu ; 4676019Shines@cs.fsu.edu 4687734SAli.Saidi@ARM.com writeAccesses 4696019Shines@cs.fsu.edu .name(name() + ".write_accesses") 4706019Shines@cs.fsu.edu .desc("DTB write accesses") 4716019Shines@cs.fsu.edu ; 4726019Shines@cs.fsu.edu 4736019Shines@cs.fsu.edu hits 4746019Shines@cs.fsu.edu .name(name() + ".hits") 4756019Shines@cs.fsu.edu .desc("DTB hits") 4766019Shines@cs.fsu.edu ; 4776019Shines@cs.fsu.edu 4786019Shines@cs.fsu.edu misses 4796019Shines@cs.fsu.edu .name(name() + ".misses") 4806019Shines@cs.fsu.edu .desc("DTB misses") 4816019Shines@cs.fsu.edu ; 4826019Shines@cs.fsu.edu 4836019Shines@cs.fsu.edu accesses 4846019Shines@cs.fsu.edu .name(name() + ".accesses") 4856019Shines@cs.fsu.edu .desc("DTB accesses") 4866019Shines@cs.fsu.edu ; 4876019Shines@cs.fsu.edu 4887734SAli.Saidi@ARM.com flushTlb 4897734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 4907734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 4917734SAli.Saidi@ARM.com ; 4927734SAli.Saidi@ARM.com 4937734SAli.Saidi@ARM.com flushTlbMva 4947734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 4957734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 4967734SAli.Saidi@ARM.com ; 4977734SAli.Saidi@ARM.com 4987734SAli.Saidi@ARM.com flushTlbMvaAsid 4997734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 5007734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 5017734SAli.Saidi@ARM.com ; 5027734SAli.Saidi@ARM.com 5037734SAli.Saidi@ARM.com flushTlbAsid 5047734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 5057734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 5067734SAli.Saidi@ARM.com ; 5077734SAli.Saidi@ARM.com 5087734SAli.Saidi@ARM.com flushedEntries 5097734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 5107734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 5117734SAli.Saidi@ARM.com ; 5127734SAli.Saidi@ARM.com 5137734SAli.Saidi@ARM.com alignFaults 5147734SAli.Saidi@ARM.com .name(name() + ".align_faults") 5157734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 5167734SAli.Saidi@ARM.com ; 5177734SAli.Saidi@ARM.com 5187734SAli.Saidi@ARM.com prefetchFaults 5197734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 5207734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 5217734SAli.Saidi@ARM.com ; 5227734SAli.Saidi@ARM.com 5237734SAli.Saidi@ARM.com domainFaults 5247734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 5257734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 5267734SAli.Saidi@ARM.com ; 5277734SAli.Saidi@ARM.com 5287734SAli.Saidi@ARM.com permsFaults 5297734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 5307734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 5317734SAli.Saidi@ARM.com ; 5327734SAli.Saidi@ARM.com 5337734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 5347734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 5357734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 5367734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 5377734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 5387734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 5396019Shines@cs.fsu.edu} 5406019Shines@cs.fsu.edu 54110463SAndreas.Sandberg@ARM.comvoid 54210463SAndreas.Sandberg@ARM.comTLB::regProbePoints() 54310463SAndreas.Sandberg@ARM.com{ 54410463SAndreas.Sandberg@ARM.com ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 54510463SAndreas.Sandberg@ARM.com} 54610463SAndreas.Sandberg@ARM.com 5477404SAli.Saidi@ARM.comFault 5487404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 54910037SARM gem5 Developers Translation *translation, bool &delay, bool timing) 5507404SAli.Saidi@ARM.com{ 55110037SARM gem5 Developers updateMiscReg(tc); 55210037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 55310037SARM gem5 Developers Addr vaddr = 0; 55410037SARM gem5 Developers if (aarch64) 55510854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 55610037SARM gem5 Developers else 55710037SARM gem5 Developers vaddr = vaddr_tainted; 5587294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 5597294Sgblack@eecs.umich.edu 5607404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 5617404SAli.Saidi@ARM.com bool is_write = (mode == Write); 5627404SAli.Saidi@ARM.com 5637404SAli.Saidi@ARM.com if (!is_fetch) { 5647294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 5657404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 56610037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 56710037SARM gem5 Developers // LPAE is always disabled in SE mode 56810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 56910474Sandreas.hansson@arm.com vaddr_tainted, 57010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 57110474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 57210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 5737294Sgblack@eecs.umich.edu } 5747294Sgblack@eecs.umich.edu } 5757294Sgblack@eecs.umich.edu } 5766019Shines@cs.fsu.edu 5777093Sgblack@eecs.umich.edu Addr paddr; 5787404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 5797404SAli.Saidi@ARM.com 5807093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 58110474Sandreas.hansson@arm.com return std::make_shared<GenericPageTableFault>(vaddr_tainted); 5827093Sgblack@eecs.umich.edu req->setPaddr(paddr); 5836019Shines@cs.fsu.edu 5846019Shines@cs.fsu.edu return NoFault; 5857404SAli.Saidi@ARM.com} 5867404SAli.Saidi@ARM.com 5877404SAli.Saidi@ARM.comFault 58810037SARM gem5 DevelopersTLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 58910037SARM gem5 Developers{ 59010037SARM gem5 Developers Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 59110037SARM gem5 Developers uint32_t flags = req->getFlags(); 59210037SARM gem5 Developers bool is_fetch = (mode == Execute); 59310037SARM gem5 Developers bool is_write = (mode == Write); 59410037SARM gem5 Developers bool is_priv = isPriv && !(flags & UserMode); 59510037SARM gem5 Developers 59610037SARM gem5 Developers // Get the translation type from the actuall table entry 59710037SARM gem5 Developers ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 59810037SARM gem5 Developers : ArmFault::VmsaTran; 59910037SARM gem5 Developers 60010037SARM gem5 Developers // If this is the second stage of translation and the request is for a 60110037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 60210037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 60310037SARM gem5 Developers // as a device or strongly ordered. 60410037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 60510037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 60610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 60710474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 60810474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 60910474Sandreas.hansson@arm.com isStage2, tranMethod); 61010037SARM gem5 Developers } 61110037SARM gem5 Developers 61210037SARM gem5 Developers // Generate an alignment fault for unaligned data accesses to device or 61310037SARM gem5 Developers // strongly ordered memory 61410037SARM gem5 Developers if (!is_fetch) { 61510037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 61610037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 61710037SARM gem5 Developers alignFaults++; 61810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 61910474Sandreas.hansson@arm.com vaddr, TlbEntry::DomainType::NoAccess, is_write, 62010474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 62110474Sandreas.hansson@arm.com tranMethod); 62210037SARM gem5 Developers } 62310037SARM gem5 Developers } 62410037SARM gem5 Developers } 62510037SARM gem5 Developers 62610037SARM gem5 Developers if (te->nonCacheable) { 62710037SARM gem5 Developers // Prevent prefetching from I/O devices. 62810037SARM gem5 Developers if (req->isPrefetch()) { 62910037SARM gem5 Developers // Here we can safely use the fault status for the short 63010037SARM gem5 Developers // desc. format in all cases 63110474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 63210474Sandreas.hansson@arm.com vaddr, ArmFault::PrefetchUncacheable, 63310474Sandreas.hansson@arm.com isStage2, tranMethod); 63410037SARM gem5 Developers } 63510037SARM gem5 Developers } 63610037SARM gem5 Developers 63710037SARM gem5 Developers if (!te->longDescFormat) { 63810037SARM gem5 Developers switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 63910037SARM gem5 Developers case 0: 64010037SARM gem5 Developers domainFaults++; 64110037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 64210037SARM gem5 Developers " domain: %#x write:%d\n", dacr, 64310037SARM gem5 Developers static_cast<uint8_t>(te->domain), is_write); 64410037SARM gem5 Developers if (is_fetch) 64510474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64610474Sandreas.hansson@arm.com vaddr, 64710474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 64810474Sandreas.hansson@arm.com isStage2, tranMethod); 64910037SARM gem5 Developers else 65010474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65110474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 65210474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 65310474Sandreas.hansson@arm.com isStage2, tranMethod); 65410037SARM gem5 Developers case 1: 65510037SARM gem5 Developers // Continue with permissions check 65610037SARM gem5 Developers break; 65710037SARM gem5 Developers case 2: 65810037SARM gem5 Developers panic("UNPRED domain\n"); 65910037SARM gem5 Developers case 3: 66010037SARM gem5 Developers return NoFault; 66110037SARM gem5 Developers } 66210037SARM gem5 Developers } 66310037SARM gem5 Developers 66410037SARM gem5 Developers // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 66510037SARM gem5 Developers uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 66610037SARM gem5 Developers uint8_t hap = te->hap; 66710037SARM gem5 Developers 66810037SARM gem5 Developers if (sctlr.afe == 1 || te->longDescFormat) 66910037SARM gem5 Developers ap |= 1; 67010037SARM gem5 Developers 67110037SARM gem5 Developers bool abt; 67210037SARM gem5 Developers bool isWritable = true; 67310037SARM gem5 Developers // If this is a stage 2 access (eg for reading stage 1 page table entries) 67410037SARM gem5 Developers // then don't perform the AP permissions check, we stil do the HAP check 67510037SARM gem5 Developers // below. 67610037SARM gem5 Developers if (isStage2) { 67710037SARM gem5 Developers abt = false; 67810037SARM gem5 Developers } else { 67910037SARM gem5 Developers switch (ap) { 68010037SARM gem5 Developers case 0: 68110037SARM gem5 Developers DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 68210037SARM gem5 Developers (int)sctlr.rs); 68310037SARM gem5 Developers if (!sctlr.xp) { 68410037SARM gem5 Developers switch ((int)sctlr.rs) { 68510037SARM gem5 Developers case 2: 68610037SARM gem5 Developers abt = is_write; 68710037SARM gem5 Developers break; 68810037SARM gem5 Developers case 1: 68910037SARM gem5 Developers abt = is_write || !is_priv; 69010037SARM gem5 Developers break; 69110037SARM gem5 Developers case 0: 69210037SARM gem5 Developers case 3: 69310037SARM gem5 Developers default: 69410037SARM gem5 Developers abt = true; 69510037SARM gem5 Developers break; 69610037SARM gem5 Developers } 69710037SARM gem5 Developers } else { 69810037SARM gem5 Developers abt = true; 69910037SARM gem5 Developers } 70010037SARM gem5 Developers break; 70110037SARM gem5 Developers case 1: 70210037SARM gem5 Developers abt = !is_priv; 70310037SARM gem5 Developers break; 70410037SARM gem5 Developers case 2: 70510037SARM gem5 Developers abt = !is_priv && is_write; 70610037SARM gem5 Developers isWritable = is_priv; 70710037SARM gem5 Developers break; 70810037SARM gem5 Developers case 3: 70910037SARM gem5 Developers abt = false; 71010037SARM gem5 Developers break; 71110037SARM gem5 Developers case 4: 71210037SARM gem5 Developers panic("UNPRED premissions\n"); 71310037SARM gem5 Developers case 5: 71410037SARM gem5 Developers abt = !is_priv || is_write; 71510037SARM gem5 Developers isWritable = false; 71610037SARM gem5 Developers break; 71710037SARM gem5 Developers case 6: 71810037SARM gem5 Developers case 7: 71910037SARM gem5 Developers abt = is_write; 72010037SARM gem5 Developers isWritable = false; 72110037SARM gem5 Developers break; 72210037SARM gem5 Developers default: 72310037SARM gem5 Developers panic("Unknown permissions %#x\n", ap); 72410037SARM gem5 Developers } 72510037SARM gem5 Developers } 72610037SARM gem5 Developers 72710037SARM gem5 Developers bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 72810037SARM gem5 Developers bool xn = te->xn || (isWritable && sctlr.wxn) || 72910037SARM gem5 Developers (ap == 3 && sctlr.uwxn && is_priv); 73010037SARM gem5 Developers if (is_fetch && (abt || xn || 73111495Sandreas.sandberg@arm.com (te->longDescFormat && te->pxn && is_priv) || 73210037SARM gem5 Developers (isSecure && te->ns && scr.sif))) { 73310037SARM gem5 Developers permsFaults++; 73410037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 73510037SARM gem5 Developers "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 73610037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 73710474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 73810474Sandreas.hansson@arm.com vaddr, 73910474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 74010474Sandreas.hansson@arm.com isStage2, tranMethod); 74110037SARM gem5 Developers } else if (abt | hapAbt) { 74210037SARM gem5 Developers permsFaults++; 74310037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 74410037SARM gem5 Developers " write:%d\n", ap, is_priv, is_write); 74510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 74610474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 74710474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 74810474Sandreas.hansson@arm.com isStage2 | !abt, tranMethod); 74910037SARM gem5 Developers } 75010037SARM gem5 Developers return NoFault; 75110037SARM gem5 Developers} 75210037SARM gem5 Developers 75310037SARM gem5 Developers 75410037SARM gem5 DevelopersFault 75510037SARM gem5 DevelopersTLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 75610037SARM gem5 Developers ThreadContext *tc) 75710037SARM gem5 Developers{ 75810037SARM gem5 Developers assert(aarch64); 75910037SARM gem5 Developers 76010037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 76110854SNathanael.Premillieu@arm.com Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 76210037SARM gem5 Developers 76310037SARM gem5 Developers uint32_t flags = req->getFlags(); 76410037SARM gem5 Developers bool is_fetch = (mode == Execute); 76510037SARM gem5 Developers bool is_write = (mode == Write); 76610037SARM gem5 Developers bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 76710037SARM gem5 Developers 76810037SARM gem5 Developers updateMiscReg(tc, curTranType); 76910037SARM gem5 Developers 77010037SARM gem5 Developers // If this is the second stage of translation and the request is for a 77110037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 77210037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 77310037SARM gem5 Developers // as a device or strongly ordered. 77410037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 77510037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 77610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 77710474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 77810474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 77910474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 78010037SARM gem5 Developers } 78110037SARM gem5 Developers 78210037SARM gem5 Developers // Generate an alignment fault for unaligned accesses to device or 78310037SARM gem5 Developers // strongly ordered memory 78410037SARM gem5 Developers if (!is_fetch) { 78510037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 78610037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 78710037SARM gem5 Developers alignFaults++; 78810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 78910474Sandreas.hansson@arm.com vaddr_tainted, 79010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 79110474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 79210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 79310037SARM gem5 Developers } 79410037SARM gem5 Developers } 79510037SARM gem5 Developers } 79610037SARM gem5 Developers 79710037SARM gem5 Developers if (te->nonCacheable) { 79810037SARM gem5 Developers // Prevent prefetching from I/O devices. 79910037SARM gem5 Developers if (req->isPrefetch()) { 80010037SARM gem5 Developers // Here we can safely use the fault status for the short 80110037SARM gem5 Developers // desc. format in all cases 80210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 80310474Sandreas.hansson@arm.com vaddr_tainted, 80410474Sandreas.hansson@arm.com ArmFault::PrefetchUncacheable, 80510474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 80610037SARM gem5 Developers } 80710037SARM gem5 Developers } 80810037SARM gem5 Developers 80910037SARM gem5 Developers uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 81010037SARM gem5 Developers bool grant = false; 81110037SARM gem5 Developers 81210037SARM gem5 Developers uint8_t xn = te->xn; 81310037SARM gem5 Developers uint8_t pxn = te->pxn; 81410037SARM gem5 Developers bool r = !is_write && !is_fetch; 81510037SARM gem5 Developers bool w = is_write; 81610037SARM gem5 Developers bool x = is_fetch; 81710037SARM gem5 Developers DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 81810037SARM gem5 Developers "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 81910037SARM gem5 Developers 82010037SARM gem5 Developers if (isStage2) { 82111575SDylan.Johnson@ARM.com assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2); 82211575SDylan.Johnson@ARM.com // In stage 2 we use the hypervisor access permission bits. 82311575SDylan.Johnson@ARM.com // The following permissions are described in ARM DDI 0487A.f 82411575SDylan.Johnson@ARM.com // D4-1802 82511575SDylan.Johnson@ARM.com uint8_t hap = 0x3 & te->hap; 82611575SDylan.Johnson@ARM.com if (is_fetch) { 82711575SDylan.Johnson@ARM.com // sctlr.wxn overrides the xn bit 82811575SDylan.Johnson@ARM.com grant = !sctlr.wxn && !xn; 82911575SDylan.Johnson@ARM.com } else if (is_write) { 83011575SDylan.Johnson@ARM.com grant = hap & 0x2; 83111575SDylan.Johnson@ARM.com } else { // is_read 83211575SDylan.Johnson@ARM.com grant = hap & 0x1; 83311575SDylan.Johnson@ARM.com } 83410037SARM gem5 Developers } else { 83510037SARM gem5 Developers switch (aarch64EL) { 83610037SARM gem5 Developers case EL0: 83710037SARM gem5 Developers { 83810037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 83910037SARM gem5 Developers switch (perm) { 84010037SARM gem5 Developers case 0: 84110037SARM gem5 Developers case 1: 84210037SARM gem5 Developers case 8: 84310037SARM gem5 Developers case 9: 84410037SARM gem5 Developers grant = x; 84510037SARM gem5 Developers break; 84610037SARM gem5 Developers case 4: 84710037SARM gem5 Developers case 5: 84810037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 84910037SARM gem5 Developers break; 85010037SARM gem5 Developers case 6: 85110037SARM gem5 Developers case 7: 85210037SARM gem5 Developers grant = r || w; 85310037SARM gem5 Developers break; 85410037SARM gem5 Developers case 12: 85510037SARM gem5 Developers case 13: 85610037SARM gem5 Developers grant = r || x; 85710037SARM gem5 Developers break; 85810037SARM gem5 Developers case 14: 85910037SARM gem5 Developers case 15: 86010037SARM gem5 Developers grant = r; 86110037SARM gem5 Developers break; 86210037SARM gem5 Developers default: 86310037SARM gem5 Developers grant = false; 86410037SARM gem5 Developers } 86510037SARM gem5 Developers } 86610037SARM gem5 Developers break; 86710037SARM gem5 Developers case EL1: 86810037SARM gem5 Developers { 86910037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 87010037SARM gem5 Developers switch (perm) { 87110037SARM gem5 Developers case 0: 87210037SARM gem5 Developers case 2: 87310037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 87410037SARM gem5 Developers break; 87510037SARM gem5 Developers case 1: 87610037SARM gem5 Developers case 3: 87710037SARM gem5 Developers case 4: 87810037SARM gem5 Developers case 5: 87910037SARM gem5 Developers case 6: 88010037SARM gem5 Developers case 7: 88110037SARM gem5 Developers // regions that are writeable at EL0 should not be 88210037SARM gem5 Developers // executable at EL1 88310037SARM gem5 Developers grant = r || w; 88410037SARM gem5 Developers break; 88510037SARM gem5 Developers case 8: 88610037SARM gem5 Developers case 10: 88710037SARM gem5 Developers case 12: 88810037SARM gem5 Developers case 14: 88910037SARM gem5 Developers grant = r || x; 89010037SARM gem5 Developers break; 89110037SARM gem5 Developers case 9: 89210037SARM gem5 Developers case 11: 89310037SARM gem5 Developers case 13: 89410037SARM gem5 Developers case 15: 89510037SARM gem5 Developers grant = r; 89610037SARM gem5 Developers break; 89710037SARM gem5 Developers default: 89810037SARM gem5 Developers grant = false; 89910037SARM gem5 Developers } 90010037SARM gem5 Developers } 90110037SARM gem5 Developers break; 90210037SARM gem5 Developers case EL2: 90310037SARM gem5 Developers case EL3: 90410037SARM gem5 Developers { 90510037SARM gem5 Developers uint8_t perm = (ap & 0x2) | xn; 90610037SARM gem5 Developers switch (perm) { 90710037SARM gem5 Developers case 0: 90810037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn) ; 90910037SARM gem5 Developers break; 91010037SARM gem5 Developers case 1: 91110037SARM gem5 Developers grant = r || w; 91210037SARM gem5 Developers break; 91310037SARM gem5 Developers case 2: 91410037SARM gem5 Developers grant = r || x; 91510037SARM gem5 Developers break; 91610037SARM gem5 Developers case 3: 91710037SARM gem5 Developers grant = r; 91810037SARM gem5 Developers break; 91910037SARM gem5 Developers default: 92010037SARM gem5 Developers grant = false; 92110037SARM gem5 Developers } 92210037SARM gem5 Developers } 92310037SARM gem5 Developers break; 92410037SARM gem5 Developers } 92510037SARM gem5 Developers } 92610037SARM gem5 Developers 92710037SARM gem5 Developers if (!grant) { 92810037SARM gem5 Developers if (is_fetch) { 92910037SARM gem5 Developers permsFaults++; 93010037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 93110037SARM gem5 Developers "AP:%d priv:%d write:%d ns:%d sif:%d " 93210037SARM gem5 Developers "sctlr.afe: %d\n", 93310037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 93410037SARM gem5 Developers // Use PC value instead of vaddr because vaddr might be aligned to 93510037SARM gem5 Developers // cache line and should not be the address reported in FAR 93610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 93710474Sandreas.hansson@arm.com req->getPC(), 93810474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 93910474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 94010037SARM gem5 Developers } else { 94110037SARM gem5 Developers permsFaults++; 94210037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 94310037SARM gem5 Developers "priv:%d write:%d\n", ap, is_priv, is_write); 94410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 94510474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 94610474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 94710474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 94810037SARM gem5 Developers } 94910037SARM gem5 Developers } 95010037SARM gem5 Developers 95110037SARM gem5 Developers return NoFault; 95210037SARM gem5 Developers} 95310037SARM gem5 Developers 95410037SARM gem5 DevelopersFault 9557404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 95610037SARM gem5 Developers Translation *translation, bool &delay, bool timing, 95710037SARM gem5 Developers TLB::ArmTranslationType tranType, bool functional) 9587404SAli.Saidi@ARM.com{ 9598733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 9608733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 9618733Sgeoffrey.blake@arm.com 96210037SARM gem5 Developers updateMiscReg(tc, tranType); 96310037SARM gem5 Developers 96410037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 96510037SARM gem5 Developers Addr vaddr = 0; 96610037SARM gem5 Developers if (aarch64) 96710854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 96810037SARM gem5 Developers else 96910037SARM gem5 Developers vaddr = vaddr_tainted; 97010037SARM gem5 Developers uint32_t flags = req->getFlags(); 97110037SARM gem5 Developers 97210037SARM gem5 Developers bool is_fetch = (mode == Execute); 97310037SARM gem5 Developers bool is_write = (mode == Write); 97411517SCurtis.Dunham@arm.com bool long_desc_format = aarch64 || longDescFormatInUse(tc); 97510037SARM gem5 Developers ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 97610037SARM gem5 Developers : ArmFault::VmsaTran; 97710037SARM gem5 Developers 97810037SARM gem5 Developers req->setAsid(asid); 97910037SARM gem5 Developers 98010037SARM gem5 Developers DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 98110037SARM gem5 Developers isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 98210037SARM gem5 Developers 98310037SARM gem5 Developers DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 98410037SARM gem5 Developers "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, 98510037SARM gem5 Developers scr, sctlr, flags, tranType); 98610037SARM gem5 Developers 9877608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 9887608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 98910824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 9907608SGene.Wu@arm.com } 9917404SAli.Saidi@ARM.com if (!is_fetch) { 9927404SAli.Saidi@ARM.com assert(flags & MustBeOne); 9937404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 99410037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 9957734SAli.Saidi@ARM.com alignFaults++; 99610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 99710474Sandreas.hansson@arm.com vaddr_tainted, 99810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 99910474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 100010474Sandreas.hansson@arm.com tranMethod); 10017404SAli.Saidi@ARM.com } 10027404SAli.Saidi@ARM.com } 10037404SAli.Saidi@ARM.com } 10047404SAli.Saidi@ARM.com 100510037SARM gem5 Developers // If guest MMU is off or hcr.vm=0 go straight to stage2 100610037SARM gem5 Developers if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 10077404SAli.Saidi@ARM.com 10087093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 100910037SARM gem5 Developers // When the MMU is off the security attribute corresponds to the 101010037SARM gem5 Developers // security state of the processor 101110037SARM gem5 Developers if (isSecure) 101210037SARM gem5 Developers req->setFlags(Request::SECURE); 101310037SARM gem5 Developers 101410037SARM gem5 Developers // @todo: double check this (ARM ARM issue C B3.2.1) 101510037SARM gem5 Developers if (long_desc_format || sctlr.tre == 0) { 101610824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 10177404SAli.Saidi@ARM.com } else { 10187404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 101910824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 10207404SAli.Saidi@ARM.com } 10217436Sdam.sunwoo@arm.com 10227436Sdam.sunwoo@arm.com // Set memory attributes 10237436Sdam.sunwoo@arm.com TlbEntry temp_te; 102410037SARM gem5 Developers temp_te.ns = !isSecure; 102510037SARM gem5 Developers if (isStage2 || hcr.dc == 0 || isSecure || 102610037SARM gem5 Developers (isHyp && !(tranType & S1CTran))) { 102710037SARM gem5 Developers 102810037SARM gem5 Developers temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 102910037SARM gem5 Developers : TlbEntry::MemoryType::StronglyOrdered; 103010037SARM gem5 Developers temp_te.innerAttrs = 0x0; 103110037SARM gem5 Developers temp_te.outerAttrs = 0x0; 103210037SARM gem5 Developers temp_te.shareable = true; 103310037SARM gem5 Developers temp_te.outerShareable = true; 103410037SARM gem5 Developers } else { 103510037SARM gem5 Developers temp_te.mtype = TlbEntry::MemoryType::Normal; 103610037SARM gem5 Developers temp_te.innerAttrs = 0x3; 103710037SARM gem5 Developers temp_te.outerAttrs = 0x3; 103810037SARM gem5 Developers temp_te.shareable = false; 103910037SARM gem5 Developers temp_te.outerShareable = false; 104010037SARM gem5 Developers } 104110037SARM gem5 Developers temp_te.setAttributes(long_desc_format); 104210367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 104310367SAndrew.Bardsley@arm.com "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 104410037SARM gem5 Developers temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 104510037SARM gem5 Developers isStage2); 10467436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 10477436Sdam.sunwoo@arm.com 104811395Sandreas.sandberg@arm.com return testTranslation(req, mode, TlbEntry::DomainType::NoAccess); 10497404SAli.Saidi@ARM.com } 10507404SAli.Saidi@ARM.com 105110037SARM gem5 Developers DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 105210037SARM gem5 Developers isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 10537404SAli.Saidi@ARM.com // Translation enabled 10547404SAli.Saidi@ARM.com 105510037SARM gem5 Developers TlbEntry *te = NULL; 105610037SARM gem5 Developers TlbEntry mergeTe; 105710037SARM gem5 Developers Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 105810037SARM gem5 Developers functional, &mergeTe); 105910037SARM gem5 Developers // only proceed if we have a valid table entry 106010037SARM gem5 Developers if ((te == NULL) && (fault == NoFault)) delay = true; 106110037SARM gem5 Developers 106210037SARM gem5 Developers // If we have the table entry transfer some of the attributes to the 106310037SARM gem5 Developers // request that triggered the translation 106410037SARM gem5 Developers if (te != NULL) { 106510037SARM gem5 Developers // Set memory attributes 106610037SARM gem5 Developers DPRINTF(TLBVerbose, 106710367SAndrew.Bardsley@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, " 106810367SAndrew.Bardsley@arm.com "outerAttrs: %d, mtype: %d, isStage2: %d\n", 106910037SARM gem5 Developers te->shareable, te->innerAttrs, te->outerAttrs, 107010037SARM gem5 Developers static_cast<uint8_t>(te->mtype), isStage2); 107110037SARM gem5 Developers setAttr(te->attributes); 107210824SAndreas.Sandberg@ARM.com 107310824SAndreas.Sandberg@ARM.com if (te->nonCacheable) 107410825SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE); 107510825SAndreas.Sandberg@ARM.com 107610825SAndreas.Sandberg@ARM.com // Require requests to be ordered if the request goes to 107710825SAndreas.Sandberg@ARM.com // strongly ordered or device memory (i.e., anything other 107810825SAndreas.Sandberg@ARM.com // than normal memory requires strict order). 107910825SAndreas.Sandberg@ARM.com if (te->mtype != TlbEntry::MemoryType::Normal) 108010825SAndreas.Sandberg@ARM.com req->setFlags(Request::STRICT_ORDER); 108110037SARM gem5 Developers 108210508SAli.Saidi@ARM.com Addr pa = te->pAddr(vaddr); 108310508SAli.Saidi@ARM.com req->setPaddr(pa); 108410508SAli.Saidi@ARM.com 108510037SARM gem5 Developers if (isSecure && !te->ns) { 108610037SARM gem5 Developers req->setFlags(Request::SECURE); 108710037SARM gem5 Developers } 108810037SARM gem5 Developers if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 108910037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 109010037SARM gem5 Developers // Unaligned accesses to Device memory should always cause an 109110037SARM gem5 Developers // abort regardless of sctlr.a 109210037SARM gem5 Developers alignFaults++; 109310474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 109410474Sandreas.hansson@arm.com vaddr_tainted, 109510474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 109610474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 109710474Sandreas.hansson@arm.com tranMethod); 109810037SARM gem5 Developers } 109910037SARM gem5 Developers 110010037SARM gem5 Developers // Check for a trickbox generated address fault 110111395Sandreas.sandberg@arm.com if (fault == NoFault) 110211395Sandreas.sandberg@arm.com fault = testTranslation(req, mode, te->domain); 110310037SARM gem5 Developers } 110410037SARM gem5 Developers 110510037SARM gem5 Developers // Generate Illegal Inst Set State fault if IL bit is set in CPSR 110610037SARM gem5 Developers if (fault == NoFault) { 110710037SARM gem5 Developers if (aarch64 && is_fetch && cpsr.il == 1) { 110810474Sandreas.hansson@arm.com return std::make_shared<IllegalInstSetStateFault>(); 110910037SARM gem5 Developers } 111010037SARM gem5 Developers } 111110037SARM gem5 Developers 111210037SARM gem5 Developers return fault; 111310037SARM gem5 Developers} 111410037SARM gem5 Developers 111510037SARM gem5 DevelopersFault 111610037SARM gem5 DevelopersTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 111710037SARM gem5 Developers TLB::ArmTranslationType tranType) 111810037SARM gem5 Developers{ 111910037SARM gem5 Developers updateMiscReg(tc, tranType); 112010037SARM gem5 Developers 112110037SARM gem5 Developers if (directToStage2) { 112210037SARM gem5 Developers assert(stage2Tlb); 112310037SARM gem5 Developers return stage2Tlb->translateAtomic(req, tc, mode, tranType); 112410037SARM gem5 Developers } 112510037SARM gem5 Developers 112610037SARM gem5 Developers bool delay = false; 112710037SARM gem5 Developers Fault fault; 112810037SARM gem5 Developers if (FullSystem) 112910037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 113010037SARM gem5 Developers else 113110037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 113210037SARM gem5 Developers assert(!delay); 113310037SARM gem5 Developers return fault; 113410037SARM gem5 Developers} 113510037SARM gem5 Developers 113610037SARM gem5 DevelopersFault 113710037SARM gem5 DevelopersTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 113810037SARM gem5 Developers TLB::ArmTranslationType tranType) 113910037SARM gem5 Developers{ 114010037SARM gem5 Developers updateMiscReg(tc, tranType); 114110037SARM gem5 Developers 114210037SARM gem5 Developers if (directToStage2) { 114310037SARM gem5 Developers assert(stage2Tlb); 114410037SARM gem5 Developers return stage2Tlb->translateFunctional(req, tc, mode, tranType); 114510037SARM gem5 Developers } 114610037SARM gem5 Developers 114710037SARM gem5 Developers bool delay = false; 114810037SARM gem5 Developers Fault fault; 114910037SARM gem5 Developers if (FullSystem) 115010037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 115110037SARM gem5 Developers else 115210037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 115310037SARM gem5 Developers assert(!delay); 115410037SARM gem5 Developers return fault; 115510037SARM gem5 Developers} 115610037SARM gem5 Developers 115710037SARM gem5 DevelopersFault 115810037SARM gem5 DevelopersTLB::translateTiming(RequestPtr req, ThreadContext *tc, 115910037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 116010037SARM gem5 Developers{ 116110037SARM gem5 Developers updateMiscReg(tc, tranType); 116210037SARM gem5 Developers 116310037SARM gem5 Developers if (directToStage2) { 116410037SARM gem5 Developers assert(stage2Tlb); 116510037SARM gem5 Developers return stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 116610037SARM gem5 Developers } 116710037SARM gem5 Developers 116810037SARM gem5 Developers assert(translation); 116910037SARM gem5 Developers 117010037SARM gem5 Developers return translateComplete(req, tc, translation, mode, tranType, isStage2); 117110037SARM gem5 Developers} 117210037SARM gem5 Developers 117310037SARM gem5 DevelopersFault 117410037SARM gem5 DevelopersTLB::translateComplete(RequestPtr req, ThreadContext *tc, 117510037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 117610037SARM gem5 Developers bool callFromS2) 117710037SARM gem5 Developers{ 117810037SARM gem5 Developers bool delay = false; 117910037SARM gem5 Developers Fault fault; 118010037SARM gem5 Developers if (FullSystem) 118110037SARM gem5 Developers fault = translateFs(req, tc, mode, translation, delay, true, tranType); 118210037SARM gem5 Developers else 118310037SARM gem5 Developers fault = translateSe(req, tc, mode, translation, delay, true); 118410037SARM gem5 Developers DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 118510037SARM gem5 Developers NoFault); 118610037SARM gem5 Developers // If we have a translation, and we're not in the middle of doing a stage 118710037SARM gem5 Developers // 2 translation tell the translation that we've either finished or its 118810037SARM gem5 Developers // going to take a while. By not doing this when we're in the middle of a 118910037SARM gem5 Developers // stage 2 translation we prevent marking the translation as delayed twice, 119010037SARM gem5 Developers // one when the translation starts and again when the stage 1 translation 119110037SARM gem5 Developers // completes. 119210037SARM gem5 Developers if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 119310037SARM gem5 Developers if (!delay) 119410037SARM gem5 Developers translation->finish(fault, req, tc, mode); 119510037SARM gem5 Developers else 119610037SARM gem5 Developers translation->markDelayed(); 119710037SARM gem5 Developers } 119810037SARM gem5 Developers return fault; 119910037SARM gem5 Developers} 120010037SARM gem5 Developers 120110037SARM gem5 DevelopersBaseMasterPort* 120210037SARM gem5 DevelopersTLB::getMasterPort() 120310037SARM gem5 Developers{ 120410717Sandreas.hansson@arm.com return &stage2Mmu->getPort(); 120510037SARM gem5 Developers} 120610037SARM gem5 Developers 120710037SARM gem5 Developersvoid 120810037SARM gem5 DevelopersTLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 120910037SARM gem5 Developers{ 121010037SARM gem5 Developers // check if the regs have changed, or the translation mode is different. 121110037SARM gem5 Developers // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 121210037SARM gem5 Developers // one type of translation anyway 121311152Smitch.hayenga@arm.com if (miscRegValid && miscRegContext == tc->contextId() && 121411152Smitch.hayenga@arm.com ((tranType == curTranType) || isStage2)) { 121510037SARM gem5 Developers return; 121610037SARM gem5 Developers } 121710037SARM gem5 Developers 121810037SARM gem5 Developers DPRINTF(TLBVerbose, "TLB variables changed!\n"); 121910854SNathanael.Premillieu@arm.com cpsr = tc->readMiscReg(MISCREG_CPSR); 122011505Sandreas.sandberg@arm.com 122110037SARM gem5 Developers // Dependencies: SCR/SCR_EL3, CPSR 122211505Sandreas.sandberg@arm.com isSecure = inSecureState(tc) && 122311505Sandreas.sandberg@arm.com !(tranType & HypMode) && !(tranType & S1S2NsTran); 122411505Sandreas.sandberg@arm.com 122511505Sandreas.sandberg@arm.com const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode; 122611505Sandreas.sandberg@arm.com aarch64 = opModeIs64(op_mode) || 122711505Sandreas.sandberg@arm.com (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1)); 122811505Sandreas.sandberg@arm.com 122910037SARM gem5 Developers if (aarch64) { // AArch64 123011577SDylan.Johnson@ARM.com // determine EL we need to translate in 123111577SDylan.Johnson@ARM.com switch (tranType) { 123211577SDylan.Johnson@ARM.com case S1E0Tran: 123311577SDylan.Johnson@ARM.com case S12E0Tran: 123411577SDylan.Johnson@ARM.com aarch64EL = EL0; 123511577SDylan.Johnson@ARM.com break; 123611577SDylan.Johnson@ARM.com case S1E1Tran: 123711577SDylan.Johnson@ARM.com case S12E1Tran: 123811577SDylan.Johnson@ARM.com aarch64EL = EL1; 123911577SDylan.Johnson@ARM.com break; 124011577SDylan.Johnson@ARM.com case S1E2Tran: 124111577SDylan.Johnson@ARM.com aarch64EL = EL2; 124211577SDylan.Johnson@ARM.com break; 124311577SDylan.Johnson@ARM.com case S1E3Tran: 124411577SDylan.Johnson@ARM.com aarch64EL = EL3; 124511577SDylan.Johnson@ARM.com break; 124611577SDylan.Johnson@ARM.com case NormalTran: 124711577SDylan.Johnson@ARM.com case S1CTran: 124811577SDylan.Johnson@ARM.com case S1S2NsTran: 124911577SDylan.Johnson@ARM.com case HypMode: 125011577SDylan.Johnson@ARM.com aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 125111577SDylan.Johnson@ARM.com break; 125211577SDylan.Johnson@ARM.com } 125311577SDylan.Johnson@ARM.com 125410037SARM gem5 Developers switch (aarch64EL) { 125510037SARM gem5 Developers case EL0: 125610037SARM gem5 Developers case EL1: 125710037SARM gem5 Developers { 125810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 125910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 126010037SARM gem5 Developers uint64_t ttbr_asid = ttbcr.a1 ? 126110037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR1_EL1) : 126210037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR0_EL1); 126310037SARM gem5 Developers asid = bits(ttbr_asid, 126410037SARM gem5 Developers (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 126510037SARM gem5 Developers } 126610037SARM gem5 Developers break; 126710037SARM gem5 Developers case EL2: 126810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 126910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 127010037SARM gem5 Developers asid = -1; 127110037SARM gem5 Developers break; 127210037SARM gem5 Developers case EL3: 127310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 127410037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 127510037SARM gem5 Developers asid = -1; 127610037SARM gem5 Developers break; 127710037SARM gem5 Developers } 127811575SDylan.Johnson@ARM.com hcr = tc->readMiscReg(MISCREG_HCR_EL2); 127910037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR_EL3); 128010037SARM gem5 Developers isPriv = aarch64EL != EL0; 128111575SDylan.Johnson@ARM.com if (haveVirtualization) { 128211575SDylan.Johnson@ARM.com vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48); 128311575SDylan.Johnson@ARM.com isHyp = tranType & HypMode; 128411575SDylan.Johnson@ARM.com isHyp &= (tranType & S1S2NsTran) == 0; 128511575SDylan.Johnson@ARM.com isHyp &= (tranType & S1CTran) == 0; 128611575SDylan.Johnson@ARM.com // Work out if we should skip the first stage of translation and go 128711575SDylan.Johnson@ARM.com // directly to stage 2. This value is cached so we don't have to 128811575SDylan.Johnson@ARM.com // compute it for every translation. 128911575SDylan.Johnson@ARM.com stage2Req = isStage2 || 129011575SDylan.Johnson@ARM.com (hcr.vm && !isHyp && !isSecure && 129111577SDylan.Johnson@ARM.com !(tranType & S1CTran) && (aarch64EL < EL2) && 129211577SDylan.Johnson@ARM.com !(tranType & S1E1Tran)); // <--- FIX THIS HACK 129311575SDylan.Johnson@ARM.com directToStage2 = !isStage2 && stage2Req && !sctlr.m; 129411575SDylan.Johnson@ARM.com } else { 129511575SDylan.Johnson@ARM.com vmid = 0; 129611575SDylan.Johnson@ARM.com isHyp = false; 129711575SDylan.Johnson@ARM.com directToStage2 = false; 129811575SDylan.Johnson@ARM.com stage2Req = false; 129911575SDylan.Johnson@ARM.com } 130010037SARM gem5 Developers } else { // AArch32 130110037SARM gem5 Developers sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 130210037SARM gem5 Developers !isSecure)); 130310037SARM gem5 Developers ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 130410037SARM gem5 Developers !isSecure)); 130510037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR); 130610037SARM gem5 Developers isPriv = cpsr.mode != MODE_USER; 130711517SCurtis.Dunham@arm.com if (longDescFormatInUse(tc)) { 130810037SARM gem5 Developers uint64_t ttbr_asid = tc->readMiscReg( 130910037SARM gem5 Developers flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1 131010037SARM gem5 Developers : MISCREG_TTBR0, 131110037SARM gem5 Developers tc, !isSecure)); 131210037SARM gem5 Developers asid = bits(ttbr_asid, 55, 48); 131311517SCurtis.Dunham@arm.com } else { // Short-descriptor translation table format in use 131410037SARM gem5 Developers CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked( 131510037SARM gem5 Developers MISCREG_CONTEXTIDR, tc,!isSecure)); 131610037SARM gem5 Developers asid = context_id.asid; 131710037SARM gem5 Developers } 131810037SARM gem5 Developers prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc, 131910037SARM gem5 Developers !isSecure)); 132010037SARM gem5 Developers nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc, 132110037SARM gem5 Developers !isSecure)); 132210037SARM gem5 Developers dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc, 132310037SARM gem5 Developers !isSecure)); 132410037SARM gem5 Developers hcr = tc->readMiscReg(MISCREG_HCR); 132510037SARM gem5 Developers 132610037SARM gem5 Developers if (haveVirtualization) { 132710037SARM gem5 Developers vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 132810037SARM gem5 Developers isHyp = cpsr.mode == MODE_HYP; 132910037SARM gem5 Developers isHyp |= tranType & HypMode; 133010037SARM gem5 Developers isHyp &= (tranType & S1S2NsTran) == 0; 133110037SARM gem5 Developers isHyp &= (tranType & S1CTran) == 0; 133210037SARM gem5 Developers if (isHyp) { 133310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_HSCTLR); 133410037SARM gem5 Developers } 133510037SARM gem5 Developers // Work out if we should skip the first stage of translation and go 133610037SARM gem5 Developers // directly to stage 2. This value is cached so we don't have to 133710037SARM gem5 Developers // compute it for every translation. 133810037SARM gem5 Developers stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 133910037SARM gem5 Developers !(tranType & S1CTran); 134010037SARM gem5 Developers directToStage2 = stage2Req && !sctlr.m; 134110037SARM gem5 Developers } else { 134210037SARM gem5 Developers vmid = 0; 134310037SARM gem5 Developers stage2Req = false; 134410037SARM gem5 Developers isHyp = false; 134510037SARM gem5 Developers directToStage2 = false; 134610037SARM gem5 Developers } 134710037SARM gem5 Developers } 134810037SARM gem5 Developers miscRegValid = true; 134911152Smitch.hayenga@arm.com miscRegContext = tc->contextId(); 135010037SARM gem5 Developers curTranType = tranType; 135110037SARM gem5 Developers} 135210037SARM gem5 Developers 135310037SARM gem5 DevelopersFault 135410037SARM gem5 DevelopersTLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 135510037SARM gem5 Developers Translation *translation, bool timing, bool functional, 135610037SARM gem5 Developers bool is_secure, TLB::ArmTranslationType tranType) 135710037SARM gem5 Developers{ 135810037SARM gem5 Developers bool is_fetch = (mode == Execute); 135910037SARM gem5 Developers bool is_write = (mode == Write); 136010037SARM gem5 Developers 136110037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 136210037SARM gem5 Developers Addr vaddr = 0; 136310037SARM gem5 Developers ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 136410037SARM gem5 Developers if (aarch64) { 136510854SNathanael.Premillieu@arm.com vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr); 136610037SARM gem5 Developers } else { 136710037SARM gem5 Developers vaddr = vaddr_tainted; 136810037SARM gem5 Developers } 136910037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 137010037SARM gem5 Developers if (*te == NULL) { 137110037SARM gem5 Developers if (req->isPrefetch()) { 137210037SARM gem5 Developers // if the request is a prefetch don't attempt to fill the TLB or go 137310037SARM gem5 Developers // any further with the memory access (here we can safely use the 137410037SARM gem5 Developers // fault status for the short desc. format in all cases) 13757734SAli.Saidi@ARM.com prefetchFaults++; 137610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 137710474Sandreas.hansson@arm.com vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 13787611SGene.Wu@arm.com } 13797734SAli.Saidi@ARM.com 13807734SAli.Saidi@ARM.com if (is_fetch) 13817734SAli.Saidi@ARM.com instMisses++; 13827734SAli.Saidi@ARM.com else if (is_write) 13837734SAli.Saidi@ARM.com writeMisses++; 13847734SAli.Saidi@ARM.com else 13857734SAli.Saidi@ARM.com readMisses++; 13867734SAli.Saidi@ARM.com 13877404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 13887404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 138910037SARM gem5 Developers DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 139010037SARM gem5 Developers vaddr_tainted, asid, vmid); 139110037SARM gem5 Developers Fault fault; 139210037SARM gem5 Developers fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 139310037SARM gem5 Developers translation, timing, functional, is_secure, 139411580SDylan.Johnson@ARM.com tranType, stage2Req); 139510037SARM gem5 Developers // for timing mode, return and wait for table walk, 139610037SARM gem5 Developers if (timing || fault != NoFault) { 13977437Sdam.sunwoo@arm.com return fault; 13987437Sdam.sunwoo@arm.com } 13997404SAli.Saidi@ARM.com 140010037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 140110037SARM gem5 Developers if (!*te) 14027404SAli.Saidi@ARM.com printTlb(); 140310037SARM gem5 Developers assert(*te); 14047734SAli.Saidi@ARM.com } else { 14057734SAli.Saidi@ARM.com if (is_fetch) 14067734SAli.Saidi@ARM.com instHits++; 14077734SAli.Saidi@ARM.com else if (is_write) 14087734SAli.Saidi@ARM.com writeHits++; 14097734SAli.Saidi@ARM.com else 14107734SAli.Saidi@ARM.com readHits++; 14117404SAli.Saidi@ARM.com } 14126757SAli.Saidi@ARM.com return NoFault; 14137404SAli.Saidi@ARM.com} 14146757SAli.Saidi@ARM.com 14157404SAli.Saidi@ARM.comFault 141610037SARM gem5 DevelopersTLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 141710037SARM gem5 Developers Translation *translation, bool timing, bool functional, 141810037SARM gem5 Developers TlbEntry *mergeTe) 14197404SAli.Saidi@ARM.com{ 14207404SAli.Saidi@ARM.com Fault fault; 142111575SDylan.Johnson@ARM.com 142211575SDylan.Johnson@ARM.com if (isStage2) { 142311575SDylan.Johnson@ARM.com // We are already in the stage 2 TLB. Grab the table entry for stage 142411575SDylan.Johnson@ARM.com // 2 only. We are here because stage 1 translation is disabled. 142511575SDylan.Johnson@ARM.com TlbEntry *s2Te = NULL; 142611575SDylan.Johnson@ARM.com // Get the stage 2 table entry 142711575SDylan.Johnson@ARM.com fault = getTE(&s2Te, req, tc, mode, translation, timing, functional, 142811575SDylan.Johnson@ARM.com isSecure, curTranType); 142911575SDylan.Johnson@ARM.com // Check permissions of stage 2 143011575SDylan.Johnson@ARM.com if ((s2Te != NULL) && (fault = NoFault)) { 143111575SDylan.Johnson@ARM.com if(aarch64) 143211575SDylan.Johnson@ARM.com fault = checkPermissions64(s2Te, req, mode, tc); 143311575SDylan.Johnson@ARM.com else 143411575SDylan.Johnson@ARM.com fault = checkPermissions(s2Te, req, mode); 143511575SDylan.Johnson@ARM.com } 143611575SDylan.Johnson@ARM.com *te = s2Te; 143711575SDylan.Johnson@ARM.com return fault; 143811575SDylan.Johnson@ARM.com } 143911575SDylan.Johnson@ARM.com 144010037SARM gem5 Developers TlbEntry *s1Te = NULL; 144110037SARM gem5 Developers 144210037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 144310037SARM gem5 Developers 144410037SARM gem5 Developers // Get the stage 1 table entry 144510037SARM gem5 Developers fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 144610037SARM gem5 Developers isSecure, curTranType); 144710037SARM gem5 Developers // only proceed if we have a valid table entry 144810037SARM gem5 Developers if ((s1Te != NULL) && (fault == NoFault)) { 144910037SARM gem5 Developers // Check stage 1 permissions before checking stage 2 145010037SARM gem5 Developers if (aarch64) 145110037SARM gem5 Developers fault = checkPermissions64(s1Te, req, mode, tc); 145210037SARM gem5 Developers else 145310037SARM gem5 Developers fault = checkPermissions(s1Te, req, mode); 145410037SARM gem5 Developers if (stage2Req & (fault == NoFault)) { 145510037SARM gem5 Developers Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 145610037SARM gem5 Developers req, translation, mode, timing, functional, curTranType); 145710037SARM gem5 Developers fault = s2Lookup->getTe(tc, mergeTe); 145810037SARM gem5 Developers if (s2Lookup->isComplete()) { 145910037SARM gem5 Developers *te = mergeTe; 146010037SARM gem5 Developers // We've finished with the lookup so delete it 146110037SARM gem5 Developers delete s2Lookup; 146210037SARM gem5 Developers } else { 146310037SARM gem5 Developers // The lookup hasn't completed, so we can't delete it now. We 146410037SARM gem5 Developers // get round this by asking the object to self delete when the 146510037SARM gem5 Developers // translation is complete. 146610037SARM gem5 Developers s2Lookup->setSelfDelete(); 146710037SARM gem5 Developers } 146810037SARM gem5 Developers } else { 146910037SARM gem5 Developers // This case deals with an S1 hit (or bypass), followed by 147010037SARM gem5 Developers // an S2 hit-but-perms issue 147110037SARM gem5 Developers if (isStage2) { 147210037SARM gem5 Developers DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 147310037SARM gem5 Developers vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 147410037SARM gem5 Developers if (fault != NoFault) { 147510037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 147610037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, false); 147710037SARM gem5 Developers armFault->annotate(ArmFault::OVA, vaddr_tainted); 147810037SARM gem5 Developers } 147910037SARM gem5 Developers } 148010037SARM gem5 Developers *te = s1Te; 148110037SARM gem5 Developers } 148210037SARM gem5 Developers } 14837404SAli.Saidi@ARM.com return fault; 14846019Shines@cs.fsu.edu} 14856019Shines@cs.fsu.edu 148611395Sandreas.sandberg@arm.comvoid 148711395Sandreas.sandberg@arm.comTLB::setTestInterface(SimObject *_ti) 148811395Sandreas.sandberg@arm.com{ 148911395Sandreas.sandberg@arm.com if (!_ti) { 149011395Sandreas.sandberg@arm.com test = nullptr; 149111395Sandreas.sandberg@arm.com } else { 149211395Sandreas.sandberg@arm.com TlbTestInterface *ti(dynamic_cast<TlbTestInterface *>(_ti)); 149311395Sandreas.sandberg@arm.com fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 149411395Sandreas.sandberg@arm.com test = ti; 149511395Sandreas.sandberg@arm.com } 149611395Sandreas.sandberg@arm.com} 149711395Sandreas.sandberg@arm.com 149811395Sandreas.sandberg@arm.comFault 149911395Sandreas.sandberg@arm.comTLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 150011395Sandreas.sandberg@arm.com{ 150111560Sandreas.sandberg@arm.com if (!test || !req->hasSize() || req->getSize() == 0) { 150211395Sandreas.sandberg@arm.com return NoFault; 150311395Sandreas.sandberg@arm.com } else { 150411395Sandreas.sandberg@arm.com return test->translationCheck(req, isPriv, mode, domain); 150511395Sandreas.sandberg@arm.com } 150611395Sandreas.sandberg@arm.com} 150711395Sandreas.sandberg@arm.com 150811395Sandreas.sandberg@arm.comFault 150911395Sandreas.sandberg@arm.comTLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 151011395Sandreas.sandberg@arm.com TlbEntry::DomainType domain, LookupLevel lookup_level) 151111395Sandreas.sandberg@arm.com{ 151211395Sandreas.sandberg@arm.com if (!test) { 151311395Sandreas.sandberg@arm.com return NoFault; 151411395Sandreas.sandberg@arm.com } else { 151511395Sandreas.sandberg@arm.com return test->walkCheck(pa, size, va, is_secure, isPriv, mode, 151611395Sandreas.sandberg@arm.com domain, lookup_level); 151711395Sandreas.sandberg@arm.com } 151811395Sandreas.sandberg@arm.com} 151911395Sandreas.sandberg@arm.com 152011395Sandreas.sandberg@arm.com 15216116Snate@binkert.orgArmISA::TLB * 15226116Snate@binkert.orgArmTLBParams::create() 15236019Shines@cs.fsu.edu{ 15246116Snate@binkert.org return new ArmISA::TLB(this); 15256019Shines@cs.fsu.edu} 1526