tlb.cc revision 10825
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2010-2013 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 4510474Sandreas.hansson@arm.com#include <memory> 466019Shines@cs.fsu.edu#include <string> 476019Shines@cs.fsu.edu#include <vector> 486019Shines@cs.fsu.edu 496116Snate@binkert.org#include "arch/arm/faults.hh" 506019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 518782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 528756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 5310037SARM gem5 Developers#include "arch/arm/stage2_lookup.hh" 5410037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 556019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 566019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 576019Shines@cs.fsu.edu#include "base/inifile.hh" 586019Shines@cs.fsu.edu#include "base/str.hh" 596019Shines@cs.fsu.edu#include "base/trace.hh" 6010024Sdam.sunwoo@arm.com#include "cpu/base.hh" 616019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 628232Snate@binkert.org#include "debug/Checkpoint.hh" 638232Snate@binkert.org#include "debug/TLB.hh" 648232Snate@binkert.org#include "debug/TLBVerbose.hh" 656116Snate@binkert.org#include "mem/page_table.hh" 666116Snate@binkert.org#include "params/ArmTLB.hh" 678756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 686019Shines@cs.fsu.edu#include "sim/process.hh" 696019Shines@cs.fsu.edu 706019Shines@cs.fsu.eduusing namespace std; 716019Shines@cs.fsu.eduusing namespace ArmISA; 726019Shines@cs.fsu.edu 7310037SARM gem5 DevelopersTLB::TLB(const ArmTLBParams *p) 7410037SARM gem5 Developers : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 7510418Sandreas.hansson@arm.com isStage2(p->is_stage2), stage2Req(false), _attr(0), 7610418Sandreas.hansson@arm.com directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 7710822Sandreas.hansson@arm.com stage2Mmu(NULL), rangeMRU(1), 7810537Sandreas.hansson@arm.com aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), 7910537Sandreas.hansson@arm.com isHyp(false), asid(0), vmid(0), dacr(0), 8010418Sandreas.hansson@arm.com miscRegValid(false), curTranType(NormalTran) 816019Shines@cs.fsu.edu{ 8210037SARM gem5 Developers tableWalker->setTlb(this); 837399SAli.Saidi@ARM.com 8410037SARM gem5 Developers // Cache system-level properties 8510037SARM gem5 Developers haveLPAE = tableWalker->haveLPAE(); 8610037SARM gem5 Developers haveVirtualization = tableWalker->haveVirtualization(); 8710037SARM gem5 Developers haveLargeAsid64 = tableWalker->haveLargeAsid64(); 886019Shines@cs.fsu.edu} 896019Shines@cs.fsu.edu 906019Shines@cs.fsu.eduTLB::~TLB() 916019Shines@cs.fsu.edu{ 9210037SARM gem5 Developers delete[] table; 9310037SARM gem5 Developers} 9410037SARM gem5 Developers 9510037SARM gem5 Developersvoid 9610037SARM gem5 DevelopersTLB::init() 9710037SARM gem5 Developers{ 9810037SARM gem5 Developers if (stage2Mmu && !isStage2) 9910037SARM gem5 Developers stage2Tlb = stage2Mmu->stage2Tlb(); 10010037SARM gem5 Developers} 10110037SARM gem5 Developers 10210037SARM gem5 Developersvoid 10310717Sandreas.hansson@arm.comTLB::setMMU(Stage2MMU *m, MasterID master_id) 10410037SARM gem5 Developers{ 10510037SARM gem5 Developers stage2Mmu = m; 10610717Sandreas.hansson@arm.com tableWalker->setMMU(m, master_id); 1076019Shines@cs.fsu.edu} 1086019Shines@cs.fsu.edu 1097694SAli.Saidi@ARM.combool 1107694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 1117694SAli.Saidi@ARM.com{ 11210037SARM gem5 Developers updateMiscReg(tc); 11310037SARM gem5 Developers 11410037SARM gem5 Developers if (directToStage2) { 11510037SARM gem5 Developers assert(stage2Tlb); 11610037SARM gem5 Developers return stage2Tlb->translateFunctional(tc, va, pa); 11710037SARM gem5 Developers } 11810037SARM gem5 Developers 11910037SARM gem5 Developers TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 12010037SARM gem5 Developers aarch64 ? aarch64EL : EL1); 1217694SAli.Saidi@ARM.com if (!e) 1227694SAli.Saidi@ARM.com return false; 1237694SAli.Saidi@ARM.com pa = e->pAddr(va); 1247694SAli.Saidi@ARM.com return true; 1257694SAli.Saidi@ARM.com} 1267694SAli.Saidi@ARM.com 1279738Sandreas@sandberg.pp.seFault 1289738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 1299738Sandreas@sandberg.pp.se{ 1309738Sandreas@sandberg.pp.se return NoFault; 1319738Sandreas@sandberg.pp.se} 1329738Sandreas@sandberg.pp.se 1337404SAli.Saidi@ARM.comTlbEntry* 13410037SARM gem5 DevelopersTLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 13510037SARM gem5 Developers bool functional, bool ignore_asn, uint8_t target_el) 1366019Shines@cs.fsu.edu{ 1377404SAli.Saidi@ARM.com 1387404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1397404SAli.Saidi@ARM.com 14010037SARM gem5 Developers // Maintaining LRU array 1417404SAli.Saidi@ARM.com int x = 0; 1427404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 14310037SARM gem5 Developers if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 14410037SARM gem5 Developers target_el)) || 14510037SARM gem5 Developers (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 14610037SARM gem5 Developers // We only move the hit entry ahead when the position is higher 14710037SARM gem5 Developers // than rangeMRU 1489535Smrinmoy.ghosh@arm.com if (x > rangeMRU && !functional) { 1497697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1507697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 15110037SARM gem5 Developers table[i] = table[i - 1]; 1527697SAli.Saidi@ARM.com table[0] = tmp_entry; 1537697SAli.Saidi@ARM.com retval = &table[0]; 1547697SAli.Saidi@ARM.com } else { 1557697SAli.Saidi@ARM.com retval = &table[x]; 1567697SAli.Saidi@ARM.com } 1577404SAli.Saidi@ARM.com break; 1587404SAli.Saidi@ARM.com } 15910037SARM gem5 Developers ++x; 1607404SAli.Saidi@ARM.com } 1617404SAli.Saidi@ARM.com 16210037SARM gem5 Developers DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 16310037SARM gem5 Developers "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 16410037SARM gem5 Developers "el: %d\n", 16510037SARM gem5 Developers va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 16610037SARM gem5 Developers retval ? retval->pfn : 0, retval ? retval->size : 0, 16710037SARM gem5 Developers retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 16810037SARM gem5 Developers retval ? retval->ns : 0, retval ? retval->nstid : 0, 16910037SARM gem5 Developers retval ? retval->global : 0, retval ? retval->asid : 0, 17010367SAndrew.Bardsley@arm.com retval ? retval->el : 0); 17110037SARM gem5 Developers 1727404SAli.Saidi@ARM.com return retval; 1736019Shines@cs.fsu.edu} 1746019Shines@cs.fsu.edu 1756019Shines@cs.fsu.edu// insert a new TLB entry 1766019Shines@cs.fsu.eduvoid 1777404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1786019Shines@cs.fsu.edu{ 1797404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 18010037SARM gem5 Developers " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 18110037SARM gem5 Developers " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 18210037SARM gem5 Developers entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 18310037SARM gem5 Developers entry.global, entry.valid, entry.nonCacheable, entry.xn, 18410037SARM gem5 Developers entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 18510037SARM gem5 Developers entry.isHyp); 1867404SAli.Saidi@ARM.com 18710037SARM gem5 Developers if (table[size - 1].valid) 18810037SARM gem5 Developers DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 18910037SARM gem5 Developers "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 1907697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 19110037SARM gem5 Developers table[size-1].vmid, table[size-1].pfn << table[size-1].N, 19210037SARM gem5 Developers table[size-1].size, table[size-1].ap, table[size-1].ns, 19310037SARM gem5 Developers table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 19410037SARM gem5 Developers table[size-1].el); 1957404SAli.Saidi@ARM.com 1967697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1977404SAli.Saidi@ARM.com 19810037SARM gem5 Developers for (int i = size - 1; i > 0; --i) 19910037SARM gem5 Developers table[i] = table[i-1]; 2007697SAli.Saidi@ARM.com table[0] = entry; 2017734SAli.Saidi@ARM.com 2027734SAli.Saidi@ARM.com inserts++; 20310463SAndreas.Sandberg@ARM.com ppRefills->notify(1); 2046019Shines@cs.fsu.edu} 2056019Shines@cs.fsu.edu 2066019Shines@cs.fsu.eduvoid 20710037SARM gem5 DevelopersTLB::printTlb() const 2087404SAli.Saidi@ARM.com{ 2097404SAli.Saidi@ARM.com int x = 0; 2107404SAli.Saidi@ARM.com TlbEntry *te; 2117404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 2127404SAli.Saidi@ARM.com while (x < size) { 21310037SARM gem5 Developers te = &table[x]; 21410037SARM gem5 Developers if (te->valid) 21510037SARM gem5 Developers DPRINTF(TLB, " * %s\n", te->print()); 21610037SARM gem5 Developers ++x; 2177404SAli.Saidi@ARM.com } 2187404SAli.Saidi@ARM.com} 2197404SAli.Saidi@ARM.com 2207404SAli.Saidi@ARM.comvoid 22110037SARM gem5 DevelopersTLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el) 2226019Shines@cs.fsu.edu{ 22310037SARM gem5 Developers DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 22410037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2257404SAli.Saidi@ARM.com int x = 0; 2267404SAli.Saidi@ARM.com TlbEntry *te; 2277404SAli.Saidi@ARM.com while (x < size) { 22810037SARM gem5 Developers te = &table[x]; 22910037SARM gem5 Developers if (te->valid && secure_lookup == !te->nstid && 23010037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 23110037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 23210037SARM gem5 Developers 23310037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 23410037SARM gem5 Developers te->valid = false; 23510037SARM gem5 Developers flushedEntries++; 23610037SARM gem5 Developers } 23710037SARM gem5 Developers ++x; 2387404SAli.Saidi@ARM.com } 2397404SAli.Saidi@ARM.com 24010037SARM gem5 Developers flushTlb++; 24110037SARM gem5 Developers 24210037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 24310037SARM gem5 Developers // if we're currently in hyp mode 24410037SARM gem5 Developers if (!isStage2 && isHyp) { 24510037SARM gem5 Developers stage2Tlb->flushAllSecurity(secure_lookup, true); 24610037SARM gem5 Developers } 24710037SARM gem5 Developers} 24810037SARM gem5 Developers 24910037SARM gem5 Developersvoid 25010037SARM gem5 DevelopersTLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el) 25110037SARM gem5 Developers{ 25210037SARM gem5 Developers DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 25310037SARM gem5 Developers (hyp ? "hyp" : "non-hyp")); 25410037SARM gem5 Developers int x = 0; 25510037SARM gem5 Developers TlbEntry *te; 25610037SARM gem5 Developers while (x < size) { 25710037SARM gem5 Developers te = &table[x]; 25810037SARM gem5 Developers if (te->valid && te->nstid && te->isHyp == hyp && 25910037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 26010037SARM gem5 Developers 26110037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 26210037SARM gem5 Developers flushedEntries++; 26310037SARM gem5 Developers te->valid = false; 26410037SARM gem5 Developers } 26510037SARM gem5 Developers ++x; 26610037SARM gem5 Developers } 2677734SAli.Saidi@ARM.com 2687734SAli.Saidi@ARM.com flushTlb++; 26910037SARM gem5 Developers 27010037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 27110037SARM gem5 Developers if (!isStage2 && !hyp) { 27210037SARM gem5 Developers stage2Tlb->flushAllNs(false, true); 27310037SARM gem5 Developers } 2746019Shines@cs.fsu.edu} 2756019Shines@cs.fsu.edu 2767404SAli.Saidi@ARM.comvoid 27710037SARM gem5 DevelopersTLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) 2787404SAli.Saidi@ARM.com{ 27910037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 28010037SARM gem5 Developers "(%s lookup)\n", mva, asn, (secure_lookup ? 28110037SARM gem5 Developers "secure" : "non-secure")); 28210037SARM gem5 Developers _flushMva(mva, asn, secure_lookup, false, false, target_el); 2837734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2847404SAli.Saidi@ARM.com} 2857404SAli.Saidi@ARM.com 2867404SAli.Saidi@ARM.comvoid 28710037SARM gem5 DevelopersTLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) 2887404SAli.Saidi@ARM.com{ 28910037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 29010037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2917404SAli.Saidi@ARM.com 29210037SARM gem5 Developers int x = 0 ; 2937404SAli.Saidi@ARM.com TlbEntry *te; 2947404SAli.Saidi@ARM.com 2957404SAli.Saidi@ARM.com while (x < size) { 2967404SAli.Saidi@ARM.com te = &table[x]; 29710037SARM gem5 Developers if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 29810037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 29910037SARM gem5 Developers checkELMatch(target_el, te->el, false)) { 30010037SARM gem5 Developers 3017404SAli.Saidi@ARM.com te->valid = false; 30210037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3037734SAli.Saidi@ARM.com flushedEntries++; 3047404SAli.Saidi@ARM.com } 30510037SARM gem5 Developers ++x; 3067404SAli.Saidi@ARM.com } 3077734SAli.Saidi@ARM.com flushTlbAsid++; 3087404SAli.Saidi@ARM.com} 3097404SAli.Saidi@ARM.com 3107404SAli.Saidi@ARM.comvoid 31110037SARM gem5 DevelopersTLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) 3127404SAli.Saidi@ARM.com{ 31310037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 31410037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 31510037SARM gem5 Developers _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el); 31610037SARM gem5 Developers flushTlbMva++; 31710037SARM gem5 Developers} 3187404SAli.Saidi@ARM.com 31910037SARM gem5 Developersvoid 32010037SARM gem5 DevelopersTLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, 32110037SARM gem5 Developers bool ignore_asn, uint8_t target_el) 32210037SARM gem5 Developers{ 3237404SAli.Saidi@ARM.com TlbEntry *te; 32410037SARM gem5 Developers // D5.7.2: Sign-extend address to 64 bits 32510037SARM gem5 Developers mva = sext<56>(mva); 32610037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 32710037SARM gem5 Developers target_el); 32810037SARM gem5 Developers while (te != NULL) { 32910037SARM gem5 Developers if (secure_lookup == !te->nstid) { 33010037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3317404SAli.Saidi@ARM.com te->valid = false; 3327734SAli.Saidi@ARM.com flushedEntries++; 3337404SAli.Saidi@ARM.com } 33410037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 33510037SARM gem5 Developers target_el); 3367404SAli.Saidi@ARM.com } 33710037SARM gem5 Developers} 33810037SARM gem5 Developers 33910037SARM gem5 Developersbool 34010037SARM gem5 DevelopersTLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) 34110037SARM gem5 Developers{ 34210037SARM gem5 Developers bool elMatch = true; 34310037SARM gem5 Developers if (!ignore_el) { 34410037SARM gem5 Developers if (target_el == 2 || target_el == 3) { 34510037SARM gem5 Developers elMatch = (tentry_el == target_el); 34610037SARM gem5 Developers } else { 34710037SARM gem5 Developers elMatch = (tentry_el == 0) || (tentry_el == 1); 34810037SARM gem5 Developers } 34910037SARM gem5 Developers } 35010037SARM gem5 Developers return elMatch; 3517404SAli.Saidi@ARM.com} 3527404SAli.Saidi@ARM.com 3536019Shines@cs.fsu.eduvoid 3549439SAndreas.Sandberg@ARM.comTLB::drainResume() 3559439SAndreas.Sandberg@ARM.com{ 3569439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 3579439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 3589439SAndreas.Sandberg@ARM.com miscRegValid = false; 3599439SAndreas.Sandberg@ARM.com} 3609439SAndreas.Sandberg@ARM.com 3619439SAndreas.Sandberg@ARM.comvoid 36210194SGeoffrey.Blake@arm.comTLB::takeOverFrom(BaseTLB *_otlb) 36310194SGeoffrey.Blake@arm.com{ 36410194SGeoffrey.Blake@arm.com TLB *otlb = dynamic_cast<TLB*>(_otlb); 36510194SGeoffrey.Blake@arm.com /* Make sure we actually have a valid type */ 36610194SGeoffrey.Blake@arm.com if (otlb) { 36710194SGeoffrey.Blake@arm.com _attr = otlb->_attr; 36810194SGeoffrey.Blake@arm.com haveLPAE = otlb->haveLPAE; 36910194SGeoffrey.Blake@arm.com directToStage2 = otlb->directToStage2; 37010194SGeoffrey.Blake@arm.com stage2Req = otlb->stage2Req; 37110194SGeoffrey.Blake@arm.com 37210194SGeoffrey.Blake@arm.com /* Sync the stage2 MMU if they exist in both 37310194SGeoffrey.Blake@arm.com * the old CPU and the new 37410194SGeoffrey.Blake@arm.com */ 37510194SGeoffrey.Blake@arm.com if (!isStage2 && 37610194SGeoffrey.Blake@arm.com stage2Tlb && otlb->stage2Tlb) { 37710194SGeoffrey.Blake@arm.com stage2Tlb->takeOverFrom(otlb->stage2Tlb); 37810194SGeoffrey.Blake@arm.com } 37910194SGeoffrey.Blake@arm.com } else { 38010194SGeoffrey.Blake@arm.com panic("Incompatible TLB type!"); 38110194SGeoffrey.Blake@arm.com } 38210194SGeoffrey.Blake@arm.com} 38310194SGeoffrey.Blake@arm.com 38410194SGeoffrey.Blake@arm.comvoid 3856019Shines@cs.fsu.eduTLB::serialize(ostream &os) 3866019Shines@cs.fsu.edu{ 3877733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 3887733SAli.Saidi@ARM.com 3897733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 39010037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 39110037SARM gem5 Developers SERIALIZE_SCALAR(directToStage2); 39210037SARM gem5 Developers SERIALIZE_SCALAR(stage2Req); 3938353SAli.Saidi@ARM.com 3948353SAli.Saidi@ARM.com int num_entries = size; 3958353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 3967733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 3977733SAli.Saidi@ARM.com nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 3987733SAli.Saidi@ARM.com table[i].serialize(os); 3997733SAli.Saidi@ARM.com } 4006019Shines@cs.fsu.edu} 4016019Shines@cs.fsu.edu 4026019Shines@cs.fsu.eduvoid 4036019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 4046019Shines@cs.fsu.edu{ 4057733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 4066019Shines@cs.fsu.edu 4077733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 40810037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 40910037SARM gem5 Developers UNSERIALIZE_SCALAR(directToStage2); 41010037SARM gem5 Developers UNSERIALIZE_SCALAR(stage2Req); 41110037SARM gem5 Developers 4128353SAli.Saidi@ARM.com int num_entries; 4138353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 4148353SAli.Saidi@ARM.com for(int i = 0; i < min(size, num_entries); i++){ 4157733SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 4167733SAli.Saidi@ARM.com } 4176019Shines@cs.fsu.edu} 4186019Shines@cs.fsu.edu 4196019Shines@cs.fsu.eduvoid 4206019Shines@cs.fsu.eduTLB::regStats() 4216019Shines@cs.fsu.edu{ 4227734SAli.Saidi@ARM.com instHits 4237734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 4247734SAli.Saidi@ARM.com .desc("ITB inst hits") 4257734SAli.Saidi@ARM.com ; 4267734SAli.Saidi@ARM.com 4277734SAli.Saidi@ARM.com instMisses 4287734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 4297734SAli.Saidi@ARM.com .desc("ITB inst misses") 4307734SAli.Saidi@ARM.com ; 4317734SAli.Saidi@ARM.com 4327734SAli.Saidi@ARM.com instAccesses 4337734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 4347734SAli.Saidi@ARM.com .desc("ITB inst accesses") 4357734SAli.Saidi@ARM.com ; 4367734SAli.Saidi@ARM.com 4377734SAli.Saidi@ARM.com readHits 4386019Shines@cs.fsu.edu .name(name() + ".read_hits") 4396019Shines@cs.fsu.edu .desc("DTB read hits") 4406019Shines@cs.fsu.edu ; 4416019Shines@cs.fsu.edu 4427734SAli.Saidi@ARM.com readMisses 4436019Shines@cs.fsu.edu .name(name() + ".read_misses") 4446019Shines@cs.fsu.edu .desc("DTB read misses") 4456019Shines@cs.fsu.edu ; 4466019Shines@cs.fsu.edu 4477734SAli.Saidi@ARM.com readAccesses 4486019Shines@cs.fsu.edu .name(name() + ".read_accesses") 4496019Shines@cs.fsu.edu .desc("DTB read accesses") 4506019Shines@cs.fsu.edu ; 4516019Shines@cs.fsu.edu 4527734SAli.Saidi@ARM.com writeHits 4536019Shines@cs.fsu.edu .name(name() + ".write_hits") 4546019Shines@cs.fsu.edu .desc("DTB write hits") 4556019Shines@cs.fsu.edu ; 4566019Shines@cs.fsu.edu 4577734SAli.Saidi@ARM.com writeMisses 4586019Shines@cs.fsu.edu .name(name() + ".write_misses") 4596019Shines@cs.fsu.edu .desc("DTB write misses") 4606019Shines@cs.fsu.edu ; 4616019Shines@cs.fsu.edu 4627734SAli.Saidi@ARM.com writeAccesses 4636019Shines@cs.fsu.edu .name(name() + ".write_accesses") 4646019Shines@cs.fsu.edu .desc("DTB write accesses") 4656019Shines@cs.fsu.edu ; 4666019Shines@cs.fsu.edu 4676019Shines@cs.fsu.edu hits 4686019Shines@cs.fsu.edu .name(name() + ".hits") 4696019Shines@cs.fsu.edu .desc("DTB hits") 4706019Shines@cs.fsu.edu ; 4716019Shines@cs.fsu.edu 4726019Shines@cs.fsu.edu misses 4736019Shines@cs.fsu.edu .name(name() + ".misses") 4746019Shines@cs.fsu.edu .desc("DTB misses") 4756019Shines@cs.fsu.edu ; 4766019Shines@cs.fsu.edu 4776019Shines@cs.fsu.edu accesses 4786019Shines@cs.fsu.edu .name(name() + ".accesses") 4796019Shines@cs.fsu.edu .desc("DTB accesses") 4806019Shines@cs.fsu.edu ; 4816019Shines@cs.fsu.edu 4827734SAli.Saidi@ARM.com flushTlb 4837734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 4847734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 4857734SAli.Saidi@ARM.com ; 4867734SAli.Saidi@ARM.com 4877734SAli.Saidi@ARM.com flushTlbMva 4887734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 4897734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 4907734SAli.Saidi@ARM.com ; 4917734SAli.Saidi@ARM.com 4927734SAli.Saidi@ARM.com flushTlbMvaAsid 4937734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 4947734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 4957734SAli.Saidi@ARM.com ; 4967734SAli.Saidi@ARM.com 4977734SAli.Saidi@ARM.com flushTlbAsid 4987734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 4997734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 5007734SAli.Saidi@ARM.com ; 5017734SAli.Saidi@ARM.com 5027734SAli.Saidi@ARM.com flushedEntries 5037734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 5047734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 5057734SAli.Saidi@ARM.com ; 5067734SAli.Saidi@ARM.com 5077734SAli.Saidi@ARM.com alignFaults 5087734SAli.Saidi@ARM.com .name(name() + ".align_faults") 5097734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 5107734SAli.Saidi@ARM.com ; 5117734SAli.Saidi@ARM.com 5127734SAli.Saidi@ARM.com prefetchFaults 5137734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 5147734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 5157734SAli.Saidi@ARM.com ; 5167734SAli.Saidi@ARM.com 5177734SAli.Saidi@ARM.com domainFaults 5187734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 5197734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 5207734SAli.Saidi@ARM.com ; 5217734SAli.Saidi@ARM.com 5227734SAli.Saidi@ARM.com permsFaults 5237734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 5247734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 5257734SAli.Saidi@ARM.com ; 5267734SAli.Saidi@ARM.com 5277734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 5287734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 5297734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 5307734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 5317734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 5327734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 5336019Shines@cs.fsu.edu} 5346019Shines@cs.fsu.edu 53510463SAndreas.Sandberg@ARM.comvoid 53610463SAndreas.Sandberg@ARM.comTLB::regProbePoints() 53710463SAndreas.Sandberg@ARM.com{ 53810463SAndreas.Sandberg@ARM.com ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 53910463SAndreas.Sandberg@ARM.com} 54010463SAndreas.Sandberg@ARM.com 5417404SAli.Saidi@ARM.comFault 5427404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 54310037SARM gem5 Developers Translation *translation, bool &delay, bool timing) 5447404SAli.Saidi@ARM.com{ 54510037SARM gem5 Developers updateMiscReg(tc); 54610037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 54710037SARM gem5 Developers Addr vaddr = 0; 54810037SARM gem5 Developers if (aarch64) 54910037SARM gem5 Developers vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 55010037SARM gem5 Developers else 55110037SARM gem5 Developers vaddr = vaddr_tainted; 5527294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 5537294Sgblack@eecs.umich.edu 5547404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 5557404SAli.Saidi@ARM.com bool is_write = (mode == Write); 5567404SAli.Saidi@ARM.com 5577404SAli.Saidi@ARM.com if (!is_fetch) { 5587294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 5597404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 56010037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 56110037SARM gem5 Developers // LPAE is always disabled in SE mode 56210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 56310474Sandreas.hansson@arm.com vaddr_tainted, 56410474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 56510474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 56610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 5677294Sgblack@eecs.umich.edu } 5687294Sgblack@eecs.umich.edu } 5697294Sgblack@eecs.umich.edu } 5706019Shines@cs.fsu.edu 5717093Sgblack@eecs.umich.edu Addr paddr; 5727404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 5737404SAli.Saidi@ARM.com 5747093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 57510474Sandreas.hansson@arm.com return std::make_shared<GenericPageTableFault>(vaddr_tainted); 5767093Sgblack@eecs.umich.edu req->setPaddr(paddr); 5776019Shines@cs.fsu.edu 5786019Shines@cs.fsu.edu return NoFault; 5797404SAli.Saidi@ARM.com} 5807404SAli.Saidi@ARM.com 5817404SAli.Saidi@ARM.comFault 58210037SARM gem5 DevelopersTLB::trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 5837406SAli.Saidi@ARM.com{ 5847406SAli.Saidi@ARM.com return NoFault; 5857406SAli.Saidi@ARM.com} 5867406SAli.Saidi@ARM.com 5877406SAli.Saidi@ARM.comFault 58810037SARM gem5 DevelopersTLB::walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 58910037SARM gem5 Developers bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level) 5907406SAli.Saidi@ARM.com{ 5917406SAli.Saidi@ARM.com return NoFault; 5927406SAli.Saidi@ARM.com} 5937406SAli.Saidi@ARM.com 5947406SAli.Saidi@ARM.comFault 59510037SARM gem5 DevelopersTLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 59610037SARM gem5 Developers{ 59710037SARM gem5 Developers Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 59810037SARM gem5 Developers uint32_t flags = req->getFlags(); 59910037SARM gem5 Developers bool is_fetch = (mode == Execute); 60010037SARM gem5 Developers bool is_write = (mode == Write); 60110037SARM gem5 Developers bool is_priv = isPriv && !(flags & UserMode); 60210037SARM gem5 Developers 60310037SARM gem5 Developers // Get the translation type from the actuall table entry 60410037SARM gem5 Developers ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 60510037SARM gem5 Developers : ArmFault::VmsaTran; 60610037SARM gem5 Developers 60710037SARM gem5 Developers // If this is the second stage of translation and the request is for a 60810037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 60910037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 61010037SARM gem5 Developers // as a device or strongly ordered. 61110037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 61210037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 61310474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 61410474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 61510474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 61610474Sandreas.hansson@arm.com isStage2, tranMethod); 61710037SARM gem5 Developers } 61810037SARM gem5 Developers 61910037SARM gem5 Developers // Generate an alignment fault for unaligned data accesses to device or 62010037SARM gem5 Developers // strongly ordered memory 62110037SARM gem5 Developers if (!is_fetch) { 62210037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 62310037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 62410037SARM gem5 Developers alignFaults++; 62510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 62610474Sandreas.hansson@arm.com vaddr, TlbEntry::DomainType::NoAccess, is_write, 62710474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 62810474Sandreas.hansson@arm.com tranMethod); 62910037SARM gem5 Developers } 63010037SARM gem5 Developers } 63110037SARM gem5 Developers } 63210037SARM gem5 Developers 63310037SARM gem5 Developers if (te->nonCacheable) { 63410037SARM gem5 Developers // Prevent prefetching from I/O devices. 63510037SARM gem5 Developers if (req->isPrefetch()) { 63610037SARM gem5 Developers // Here we can safely use the fault status for the short 63710037SARM gem5 Developers // desc. format in all cases 63810474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 63910474Sandreas.hansson@arm.com vaddr, ArmFault::PrefetchUncacheable, 64010474Sandreas.hansson@arm.com isStage2, tranMethod); 64110037SARM gem5 Developers } 64210037SARM gem5 Developers } 64310037SARM gem5 Developers 64410037SARM gem5 Developers if (!te->longDescFormat) { 64510037SARM gem5 Developers switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 64610037SARM gem5 Developers case 0: 64710037SARM gem5 Developers domainFaults++; 64810037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 64910037SARM gem5 Developers " domain: %#x write:%d\n", dacr, 65010037SARM gem5 Developers static_cast<uint8_t>(te->domain), is_write); 65110037SARM gem5 Developers if (is_fetch) 65210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 65310474Sandreas.hansson@arm.com vaddr, 65410474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 65510474Sandreas.hansson@arm.com isStage2, tranMethod); 65610037SARM gem5 Developers else 65710474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65810474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 65910474Sandreas.hansson@arm.com ArmFault::DomainLL + te->lookupLevel, 66010474Sandreas.hansson@arm.com isStage2, tranMethod); 66110037SARM gem5 Developers case 1: 66210037SARM gem5 Developers // Continue with permissions check 66310037SARM gem5 Developers break; 66410037SARM gem5 Developers case 2: 66510037SARM gem5 Developers panic("UNPRED domain\n"); 66610037SARM gem5 Developers case 3: 66710037SARM gem5 Developers return NoFault; 66810037SARM gem5 Developers } 66910037SARM gem5 Developers } 67010037SARM gem5 Developers 67110037SARM gem5 Developers // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 67210037SARM gem5 Developers uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 67310037SARM gem5 Developers uint8_t hap = te->hap; 67410037SARM gem5 Developers 67510037SARM gem5 Developers if (sctlr.afe == 1 || te->longDescFormat) 67610037SARM gem5 Developers ap |= 1; 67710037SARM gem5 Developers 67810037SARM gem5 Developers bool abt; 67910037SARM gem5 Developers bool isWritable = true; 68010037SARM gem5 Developers // If this is a stage 2 access (eg for reading stage 1 page table entries) 68110037SARM gem5 Developers // then don't perform the AP permissions check, we stil do the HAP check 68210037SARM gem5 Developers // below. 68310037SARM gem5 Developers if (isStage2) { 68410037SARM gem5 Developers abt = false; 68510037SARM gem5 Developers } else { 68610037SARM gem5 Developers switch (ap) { 68710037SARM gem5 Developers case 0: 68810037SARM gem5 Developers DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 68910037SARM gem5 Developers (int)sctlr.rs); 69010037SARM gem5 Developers if (!sctlr.xp) { 69110037SARM gem5 Developers switch ((int)sctlr.rs) { 69210037SARM gem5 Developers case 2: 69310037SARM gem5 Developers abt = is_write; 69410037SARM gem5 Developers break; 69510037SARM gem5 Developers case 1: 69610037SARM gem5 Developers abt = is_write || !is_priv; 69710037SARM gem5 Developers break; 69810037SARM gem5 Developers case 0: 69910037SARM gem5 Developers case 3: 70010037SARM gem5 Developers default: 70110037SARM gem5 Developers abt = true; 70210037SARM gem5 Developers break; 70310037SARM gem5 Developers } 70410037SARM gem5 Developers } else { 70510037SARM gem5 Developers abt = true; 70610037SARM gem5 Developers } 70710037SARM gem5 Developers break; 70810037SARM gem5 Developers case 1: 70910037SARM gem5 Developers abt = !is_priv; 71010037SARM gem5 Developers break; 71110037SARM gem5 Developers case 2: 71210037SARM gem5 Developers abt = !is_priv && is_write; 71310037SARM gem5 Developers isWritable = is_priv; 71410037SARM gem5 Developers break; 71510037SARM gem5 Developers case 3: 71610037SARM gem5 Developers abt = false; 71710037SARM gem5 Developers break; 71810037SARM gem5 Developers case 4: 71910037SARM gem5 Developers panic("UNPRED premissions\n"); 72010037SARM gem5 Developers case 5: 72110037SARM gem5 Developers abt = !is_priv || is_write; 72210037SARM gem5 Developers isWritable = false; 72310037SARM gem5 Developers break; 72410037SARM gem5 Developers case 6: 72510037SARM gem5 Developers case 7: 72610037SARM gem5 Developers abt = is_write; 72710037SARM gem5 Developers isWritable = false; 72810037SARM gem5 Developers break; 72910037SARM gem5 Developers default: 73010037SARM gem5 Developers panic("Unknown permissions %#x\n", ap); 73110037SARM gem5 Developers } 73210037SARM gem5 Developers } 73310037SARM gem5 Developers 73410037SARM gem5 Developers bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 73510037SARM gem5 Developers bool xn = te->xn || (isWritable && sctlr.wxn) || 73610037SARM gem5 Developers (ap == 3 && sctlr.uwxn && is_priv); 73710037SARM gem5 Developers if (is_fetch && (abt || xn || 73810037SARM gem5 Developers (te->longDescFormat && te->pxn && !is_priv) || 73910037SARM gem5 Developers (isSecure && te->ns && scr.sif))) { 74010037SARM gem5 Developers permsFaults++; 74110037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 74210037SARM gem5 Developers "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 74310037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 74410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 74510474Sandreas.hansson@arm.com vaddr, 74610474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 74710474Sandreas.hansson@arm.com isStage2, tranMethod); 74810037SARM gem5 Developers } else if (abt | hapAbt) { 74910037SARM gem5 Developers permsFaults++; 75010037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 75110037SARM gem5 Developers " write:%d\n", ap, is_priv, is_write); 75210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 75310474Sandreas.hansson@arm.com vaddr, te->domain, is_write, 75410474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 75510474Sandreas.hansson@arm.com isStage2 | !abt, tranMethod); 75610037SARM gem5 Developers } 75710037SARM gem5 Developers return NoFault; 75810037SARM gem5 Developers} 75910037SARM gem5 Developers 76010037SARM gem5 Developers 76110037SARM gem5 DevelopersFault 76210037SARM gem5 DevelopersTLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 76310037SARM gem5 Developers ThreadContext *tc) 76410037SARM gem5 Developers{ 76510037SARM gem5 Developers assert(aarch64); 76610037SARM gem5 Developers 76710037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 76810037SARM gem5 Developers Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 76910037SARM gem5 Developers 77010037SARM gem5 Developers uint32_t flags = req->getFlags(); 77110037SARM gem5 Developers bool is_fetch = (mode == Execute); 77210037SARM gem5 Developers bool is_write = (mode == Write); 77310037SARM gem5 Developers bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 77410037SARM gem5 Developers 77510037SARM gem5 Developers updateMiscReg(tc, curTranType); 77610037SARM gem5 Developers 77710037SARM gem5 Developers // If this is the second stage of translation and the request is for a 77810037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 77910037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 78010037SARM gem5 Developers // as a device or strongly ordered. 78110037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 78210037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 78310474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 78410474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 78510474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 78610474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 78710037SARM gem5 Developers } 78810037SARM gem5 Developers 78910037SARM gem5 Developers // Generate an alignment fault for unaligned accesses to device or 79010037SARM gem5 Developers // strongly ordered memory 79110037SARM gem5 Developers if (!is_fetch) { 79210037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 79310037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 79410037SARM gem5 Developers alignFaults++; 79510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 79610474Sandreas.hansson@arm.com vaddr_tainted, 79710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 79810474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 79910474Sandreas.hansson@arm.com ArmFault::LpaeTran); 80010037SARM gem5 Developers } 80110037SARM gem5 Developers } 80210037SARM gem5 Developers } 80310037SARM gem5 Developers 80410037SARM gem5 Developers if (te->nonCacheable) { 80510037SARM gem5 Developers // Prevent prefetching from I/O devices. 80610037SARM gem5 Developers if (req->isPrefetch()) { 80710037SARM gem5 Developers // Here we can safely use the fault status for the short 80810037SARM gem5 Developers // desc. format in all cases 80910474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 81010474Sandreas.hansson@arm.com vaddr_tainted, 81110474Sandreas.hansson@arm.com ArmFault::PrefetchUncacheable, 81210474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 81310037SARM gem5 Developers } 81410037SARM gem5 Developers } 81510037SARM gem5 Developers 81610037SARM gem5 Developers uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 81710037SARM gem5 Developers bool grant = false; 81810037SARM gem5 Developers 81910037SARM gem5 Developers uint8_t xn = te->xn; 82010037SARM gem5 Developers uint8_t pxn = te->pxn; 82110037SARM gem5 Developers bool r = !is_write && !is_fetch; 82210037SARM gem5 Developers bool w = is_write; 82310037SARM gem5 Developers bool x = is_fetch; 82410037SARM gem5 Developers DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 82510037SARM gem5 Developers "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 82610037SARM gem5 Developers 82710037SARM gem5 Developers if (isStage2) { 82810037SARM gem5 Developers panic("Virtualization in AArch64 state is not supported yet"); 82910037SARM gem5 Developers } else { 83010037SARM gem5 Developers switch (aarch64EL) { 83110037SARM gem5 Developers case EL0: 83210037SARM gem5 Developers { 83310037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 83410037SARM gem5 Developers switch (perm) { 83510037SARM gem5 Developers case 0: 83610037SARM gem5 Developers case 1: 83710037SARM gem5 Developers case 8: 83810037SARM gem5 Developers case 9: 83910037SARM gem5 Developers grant = x; 84010037SARM gem5 Developers break; 84110037SARM gem5 Developers case 4: 84210037SARM gem5 Developers case 5: 84310037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 84410037SARM gem5 Developers break; 84510037SARM gem5 Developers case 6: 84610037SARM gem5 Developers case 7: 84710037SARM gem5 Developers grant = r || w; 84810037SARM gem5 Developers break; 84910037SARM gem5 Developers case 12: 85010037SARM gem5 Developers case 13: 85110037SARM gem5 Developers grant = r || x; 85210037SARM gem5 Developers break; 85310037SARM gem5 Developers case 14: 85410037SARM gem5 Developers case 15: 85510037SARM gem5 Developers grant = r; 85610037SARM gem5 Developers break; 85710037SARM gem5 Developers default: 85810037SARM gem5 Developers grant = false; 85910037SARM gem5 Developers } 86010037SARM gem5 Developers } 86110037SARM gem5 Developers break; 86210037SARM gem5 Developers case EL1: 86310037SARM gem5 Developers { 86410037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 86510037SARM gem5 Developers switch (perm) { 86610037SARM gem5 Developers case 0: 86710037SARM gem5 Developers case 2: 86810037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 86910037SARM gem5 Developers break; 87010037SARM gem5 Developers case 1: 87110037SARM gem5 Developers case 3: 87210037SARM gem5 Developers case 4: 87310037SARM gem5 Developers case 5: 87410037SARM gem5 Developers case 6: 87510037SARM gem5 Developers case 7: 87610037SARM gem5 Developers // regions that are writeable at EL0 should not be 87710037SARM gem5 Developers // executable at EL1 87810037SARM gem5 Developers grant = r || w; 87910037SARM gem5 Developers break; 88010037SARM gem5 Developers case 8: 88110037SARM gem5 Developers case 10: 88210037SARM gem5 Developers case 12: 88310037SARM gem5 Developers case 14: 88410037SARM gem5 Developers grant = r || x; 88510037SARM gem5 Developers break; 88610037SARM gem5 Developers case 9: 88710037SARM gem5 Developers case 11: 88810037SARM gem5 Developers case 13: 88910037SARM gem5 Developers case 15: 89010037SARM gem5 Developers grant = r; 89110037SARM gem5 Developers break; 89210037SARM gem5 Developers default: 89310037SARM gem5 Developers grant = false; 89410037SARM gem5 Developers } 89510037SARM gem5 Developers } 89610037SARM gem5 Developers break; 89710037SARM gem5 Developers case EL2: 89810037SARM gem5 Developers case EL3: 89910037SARM gem5 Developers { 90010037SARM gem5 Developers uint8_t perm = (ap & 0x2) | xn; 90110037SARM gem5 Developers switch (perm) { 90210037SARM gem5 Developers case 0: 90310037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn) ; 90410037SARM gem5 Developers break; 90510037SARM gem5 Developers case 1: 90610037SARM gem5 Developers grant = r || w; 90710037SARM gem5 Developers break; 90810037SARM gem5 Developers case 2: 90910037SARM gem5 Developers grant = r || x; 91010037SARM gem5 Developers break; 91110037SARM gem5 Developers case 3: 91210037SARM gem5 Developers grant = r; 91310037SARM gem5 Developers break; 91410037SARM gem5 Developers default: 91510037SARM gem5 Developers grant = false; 91610037SARM gem5 Developers } 91710037SARM gem5 Developers } 91810037SARM gem5 Developers break; 91910037SARM gem5 Developers } 92010037SARM gem5 Developers } 92110037SARM gem5 Developers 92210037SARM gem5 Developers if (!grant) { 92310037SARM gem5 Developers if (is_fetch) { 92410037SARM gem5 Developers permsFaults++; 92510037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 92610037SARM gem5 Developers "AP:%d priv:%d write:%d ns:%d sif:%d " 92710037SARM gem5 Developers "sctlr.afe: %d\n", 92810037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 92910037SARM gem5 Developers // Use PC value instead of vaddr because vaddr might be aligned to 93010037SARM gem5 Developers // cache line and should not be the address reported in FAR 93110474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 93210474Sandreas.hansson@arm.com req->getPC(), 93310474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 93410474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 93510037SARM gem5 Developers } else { 93610037SARM gem5 Developers permsFaults++; 93710037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 93810037SARM gem5 Developers "priv:%d write:%d\n", ap, is_priv, is_write); 93910474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 94010474Sandreas.hansson@arm.com vaddr_tainted, te->domain, is_write, 94110474Sandreas.hansson@arm.com ArmFault::PermissionLL + te->lookupLevel, 94210474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 94310037SARM gem5 Developers } 94410037SARM gem5 Developers } 94510037SARM gem5 Developers 94610037SARM gem5 Developers return NoFault; 94710037SARM gem5 Developers} 94810037SARM gem5 Developers 94910037SARM gem5 DevelopersFault 9507404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 95110037SARM gem5 Developers Translation *translation, bool &delay, bool timing, 95210037SARM gem5 Developers TLB::ArmTranslationType tranType, bool functional) 9537404SAli.Saidi@ARM.com{ 9548733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 9558733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 9568733Sgeoffrey.blake@arm.com 95710037SARM gem5 Developers updateMiscReg(tc, tranType); 95810037SARM gem5 Developers 95910037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 96010037SARM gem5 Developers Addr vaddr = 0; 96110037SARM gem5 Developers if (aarch64) 96210037SARM gem5 Developers vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 96310037SARM gem5 Developers else 96410037SARM gem5 Developers vaddr = vaddr_tainted; 96510037SARM gem5 Developers uint32_t flags = req->getFlags(); 96610037SARM gem5 Developers 96710037SARM gem5 Developers bool is_fetch = (mode == Execute); 96810037SARM gem5 Developers bool is_write = (mode == Write); 96910037SARM gem5 Developers bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae); 97010037SARM gem5 Developers ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 97110037SARM gem5 Developers : ArmFault::VmsaTran; 97210037SARM gem5 Developers 97310037SARM gem5 Developers req->setAsid(asid); 97410037SARM gem5 Developers 97510037SARM gem5 Developers DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 97610037SARM gem5 Developers isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 97710037SARM gem5 Developers 97810037SARM gem5 Developers DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 97910037SARM gem5 Developers "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, 98010037SARM gem5 Developers scr, sctlr, flags, tranType); 98110037SARM gem5 Developers 9827603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 9837603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 9847603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 9857705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 98610037SARM gem5 Developers // @todo: check implications of security extensions 9877603SGene.Wu@arm.com req->setPaddr(0); 98810824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 9897705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 9907603SGene.Wu@arm.com return NoFault; 9917603SGene.Wu@arm.com } 9927608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 9937608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 99410824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 9957608SGene.Wu@arm.com } 9967404SAli.Saidi@ARM.com if (!is_fetch) { 9977404SAli.Saidi@ARM.com assert(flags & MustBeOne); 9987404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 99910037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 10007734SAli.Saidi@ARM.com alignFaults++; 100110474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 100210474Sandreas.hansson@arm.com vaddr_tainted, 100310474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 100410474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 100510474Sandreas.hansson@arm.com tranMethod); 10067404SAli.Saidi@ARM.com } 10077404SAli.Saidi@ARM.com } 10087404SAli.Saidi@ARM.com } 10097404SAli.Saidi@ARM.com 101010037SARM gem5 Developers // If guest MMU is off or hcr.vm=0 go straight to stage2 101110037SARM gem5 Developers if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 10127404SAli.Saidi@ARM.com 10137093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 101410037SARM gem5 Developers // When the MMU is off the security attribute corresponds to the 101510037SARM gem5 Developers // security state of the processor 101610037SARM gem5 Developers if (isSecure) 101710037SARM gem5 Developers req->setFlags(Request::SECURE); 101810037SARM gem5 Developers 101910037SARM gem5 Developers // @todo: double check this (ARM ARM issue C B3.2.1) 102010037SARM gem5 Developers if (long_desc_format || sctlr.tre == 0) { 102110824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 10227404SAli.Saidi@ARM.com } else { 10237404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 102410824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 10257404SAli.Saidi@ARM.com } 10267436Sdam.sunwoo@arm.com 10277436Sdam.sunwoo@arm.com // Set memory attributes 10287436Sdam.sunwoo@arm.com TlbEntry temp_te; 102910037SARM gem5 Developers temp_te.ns = !isSecure; 103010037SARM gem5 Developers if (isStage2 || hcr.dc == 0 || isSecure || 103110037SARM gem5 Developers (isHyp && !(tranType & S1CTran))) { 103210037SARM gem5 Developers 103310037SARM gem5 Developers temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 103410037SARM gem5 Developers : TlbEntry::MemoryType::StronglyOrdered; 103510037SARM gem5 Developers temp_te.innerAttrs = 0x0; 103610037SARM gem5 Developers temp_te.outerAttrs = 0x0; 103710037SARM gem5 Developers temp_te.shareable = true; 103810037SARM gem5 Developers temp_te.outerShareable = true; 103910037SARM gem5 Developers } else { 104010037SARM gem5 Developers temp_te.mtype = TlbEntry::MemoryType::Normal; 104110037SARM gem5 Developers temp_te.innerAttrs = 0x3; 104210037SARM gem5 Developers temp_te.outerAttrs = 0x3; 104310037SARM gem5 Developers temp_te.shareable = false; 104410037SARM gem5 Developers temp_te.outerShareable = false; 104510037SARM gem5 Developers } 104610037SARM gem5 Developers temp_te.setAttributes(long_desc_format); 104710367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 104810367SAndrew.Bardsley@arm.com "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 104910037SARM gem5 Developers temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 105010037SARM gem5 Developers isStage2); 10517436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 10527436Sdam.sunwoo@arm.com 105310037SARM gem5 Developers return trickBoxCheck(req, mode, TlbEntry::DomainType::NoAccess); 10547404SAli.Saidi@ARM.com } 10557404SAli.Saidi@ARM.com 105610037SARM gem5 Developers DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 105710037SARM gem5 Developers isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 10587404SAli.Saidi@ARM.com // Translation enabled 10597404SAli.Saidi@ARM.com 106010037SARM gem5 Developers TlbEntry *te = NULL; 106110037SARM gem5 Developers TlbEntry mergeTe; 106210037SARM gem5 Developers Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 106310037SARM gem5 Developers functional, &mergeTe); 106410037SARM gem5 Developers // only proceed if we have a valid table entry 106510037SARM gem5 Developers if ((te == NULL) && (fault == NoFault)) delay = true; 106610037SARM gem5 Developers 106710037SARM gem5 Developers // If we have the table entry transfer some of the attributes to the 106810037SARM gem5 Developers // request that triggered the translation 106910037SARM gem5 Developers if (te != NULL) { 107010037SARM gem5 Developers // Set memory attributes 107110037SARM gem5 Developers DPRINTF(TLBVerbose, 107210367SAndrew.Bardsley@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, " 107310367SAndrew.Bardsley@arm.com "outerAttrs: %d, mtype: %d, isStage2: %d\n", 107410037SARM gem5 Developers te->shareable, te->innerAttrs, te->outerAttrs, 107510037SARM gem5 Developers static_cast<uint8_t>(te->mtype), isStage2); 107610037SARM gem5 Developers setAttr(te->attributes); 107710824SAndreas.Sandberg@ARM.com 107810824SAndreas.Sandberg@ARM.com if (te->nonCacheable) 107910825SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE); 108010825SAndreas.Sandberg@ARM.com 108110825SAndreas.Sandberg@ARM.com // Require requests to be ordered if the request goes to 108210825SAndreas.Sandberg@ARM.com // strongly ordered or device memory (i.e., anything other 108310825SAndreas.Sandberg@ARM.com // than normal memory requires strict order). 108410825SAndreas.Sandberg@ARM.com if (te->mtype != TlbEntry::MemoryType::Normal) 108510825SAndreas.Sandberg@ARM.com req->setFlags(Request::STRICT_ORDER); 108610037SARM gem5 Developers 108710508SAli.Saidi@ARM.com Addr pa = te->pAddr(vaddr); 108810508SAli.Saidi@ARM.com req->setPaddr(pa); 108910508SAli.Saidi@ARM.com 109010037SARM gem5 Developers if (isSecure && !te->ns) { 109110037SARM gem5 Developers req->setFlags(Request::SECURE); 109210037SARM gem5 Developers } 109310037SARM gem5 Developers if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 109410037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 109510037SARM gem5 Developers // Unaligned accesses to Device memory should always cause an 109610037SARM gem5 Developers // abort regardless of sctlr.a 109710037SARM gem5 Developers alignFaults++; 109810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 109910474Sandreas.hansson@arm.com vaddr_tainted, 110010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, is_write, 110110474Sandreas.hansson@arm.com ArmFault::AlignmentFault, isStage2, 110210474Sandreas.hansson@arm.com tranMethod); 110310037SARM gem5 Developers } 110410037SARM gem5 Developers 110510037SARM gem5 Developers // Check for a trickbox generated address fault 110610037SARM gem5 Developers if (fault == NoFault) { 110710037SARM gem5 Developers fault = trickBoxCheck(req, mode, te->domain); 110810037SARM gem5 Developers } 110910037SARM gem5 Developers } 111010037SARM gem5 Developers 111110037SARM gem5 Developers // Generate Illegal Inst Set State fault if IL bit is set in CPSR 111210037SARM gem5 Developers if (fault == NoFault) { 111310037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 111410037SARM gem5 Developers if (aarch64 && is_fetch && cpsr.il == 1) { 111510474Sandreas.hansson@arm.com return std::make_shared<IllegalInstSetStateFault>(); 111610037SARM gem5 Developers } 111710037SARM gem5 Developers } 111810037SARM gem5 Developers 111910037SARM gem5 Developers return fault; 112010037SARM gem5 Developers} 112110037SARM gem5 Developers 112210037SARM gem5 DevelopersFault 112310037SARM gem5 DevelopersTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 112410037SARM gem5 Developers TLB::ArmTranslationType tranType) 112510037SARM gem5 Developers{ 112610037SARM gem5 Developers updateMiscReg(tc, tranType); 112710037SARM gem5 Developers 112810037SARM gem5 Developers if (directToStage2) { 112910037SARM gem5 Developers assert(stage2Tlb); 113010037SARM gem5 Developers return stage2Tlb->translateAtomic(req, tc, mode, tranType); 113110037SARM gem5 Developers } 113210037SARM gem5 Developers 113310037SARM gem5 Developers bool delay = false; 113410037SARM gem5 Developers Fault fault; 113510037SARM gem5 Developers if (FullSystem) 113610037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 113710037SARM gem5 Developers else 113810037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 113910037SARM gem5 Developers assert(!delay); 114010037SARM gem5 Developers return fault; 114110037SARM gem5 Developers} 114210037SARM gem5 Developers 114310037SARM gem5 DevelopersFault 114410037SARM gem5 DevelopersTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 114510037SARM gem5 Developers TLB::ArmTranslationType tranType) 114610037SARM gem5 Developers{ 114710037SARM gem5 Developers updateMiscReg(tc, tranType); 114810037SARM gem5 Developers 114910037SARM gem5 Developers if (directToStage2) { 115010037SARM gem5 Developers assert(stage2Tlb); 115110037SARM gem5 Developers return stage2Tlb->translateFunctional(req, tc, mode, tranType); 115210037SARM gem5 Developers } 115310037SARM gem5 Developers 115410037SARM gem5 Developers bool delay = false; 115510037SARM gem5 Developers Fault fault; 115610037SARM gem5 Developers if (FullSystem) 115710037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 115810037SARM gem5 Developers else 115910037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 116010037SARM gem5 Developers assert(!delay); 116110037SARM gem5 Developers return fault; 116210037SARM gem5 Developers} 116310037SARM gem5 Developers 116410037SARM gem5 DevelopersFault 116510037SARM gem5 DevelopersTLB::translateTiming(RequestPtr req, ThreadContext *tc, 116610037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 116710037SARM gem5 Developers{ 116810037SARM gem5 Developers updateMiscReg(tc, tranType); 116910037SARM gem5 Developers 117010037SARM gem5 Developers if (directToStage2) { 117110037SARM gem5 Developers assert(stage2Tlb); 117210037SARM gem5 Developers return stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 117310037SARM gem5 Developers } 117410037SARM gem5 Developers 117510037SARM gem5 Developers assert(translation); 117610037SARM gem5 Developers 117710037SARM gem5 Developers return translateComplete(req, tc, translation, mode, tranType, isStage2); 117810037SARM gem5 Developers} 117910037SARM gem5 Developers 118010037SARM gem5 DevelopersFault 118110037SARM gem5 DevelopersTLB::translateComplete(RequestPtr req, ThreadContext *tc, 118210037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 118310037SARM gem5 Developers bool callFromS2) 118410037SARM gem5 Developers{ 118510037SARM gem5 Developers bool delay = false; 118610037SARM gem5 Developers Fault fault; 118710037SARM gem5 Developers if (FullSystem) 118810037SARM gem5 Developers fault = translateFs(req, tc, mode, translation, delay, true, tranType); 118910037SARM gem5 Developers else 119010037SARM gem5 Developers fault = translateSe(req, tc, mode, translation, delay, true); 119110037SARM gem5 Developers DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 119210037SARM gem5 Developers NoFault); 119310037SARM gem5 Developers // If we have a translation, and we're not in the middle of doing a stage 119410037SARM gem5 Developers // 2 translation tell the translation that we've either finished or its 119510037SARM gem5 Developers // going to take a while. By not doing this when we're in the middle of a 119610037SARM gem5 Developers // stage 2 translation we prevent marking the translation as delayed twice, 119710037SARM gem5 Developers // one when the translation starts and again when the stage 1 translation 119810037SARM gem5 Developers // completes. 119910037SARM gem5 Developers if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 120010037SARM gem5 Developers if (!delay) 120110037SARM gem5 Developers translation->finish(fault, req, tc, mode); 120210037SARM gem5 Developers else 120310037SARM gem5 Developers translation->markDelayed(); 120410037SARM gem5 Developers } 120510037SARM gem5 Developers return fault; 120610037SARM gem5 Developers} 120710037SARM gem5 Developers 120810037SARM gem5 DevelopersBaseMasterPort* 120910037SARM gem5 DevelopersTLB::getMasterPort() 121010037SARM gem5 Developers{ 121110717Sandreas.hansson@arm.com return &stage2Mmu->getPort(); 121210037SARM gem5 Developers} 121310037SARM gem5 Developers 121410037SARM gem5 Developersvoid 121510037SARM gem5 DevelopersTLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 121610037SARM gem5 Developers{ 121710037SARM gem5 Developers // check if the regs have changed, or the translation mode is different. 121810037SARM gem5 Developers // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 121910037SARM gem5 Developers // one type of translation anyway 122010037SARM gem5 Developers if (miscRegValid && ((tranType == curTranType) || isStage2)) { 122110037SARM gem5 Developers return; 122210037SARM gem5 Developers } 122310037SARM gem5 Developers 122410037SARM gem5 Developers DPRINTF(TLBVerbose, "TLB variables changed!\n"); 122510037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 122610037SARM gem5 Developers // Dependencies: SCR/SCR_EL3, CPSR 122710037SARM gem5 Developers isSecure = inSecureState(tc); 122810037SARM gem5 Developers isSecure &= (tranType & HypMode) == 0; 122910037SARM gem5 Developers isSecure &= (tranType & S1S2NsTran) == 0; 123010037SARM gem5 Developers aarch64 = !cpsr.width; 123110037SARM gem5 Developers if (aarch64) { // AArch64 123210037SARM gem5 Developers aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 123310037SARM gem5 Developers switch (aarch64EL) { 123410037SARM gem5 Developers case EL0: 123510037SARM gem5 Developers case EL1: 123610037SARM gem5 Developers { 123710037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 123810037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 123910037SARM gem5 Developers uint64_t ttbr_asid = ttbcr.a1 ? 124010037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR1_EL1) : 124110037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR0_EL1); 124210037SARM gem5 Developers asid = bits(ttbr_asid, 124310037SARM gem5 Developers (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 124410037SARM gem5 Developers } 124510037SARM gem5 Developers break; 124610037SARM gem5 Developers case EL2: 124710037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 124810037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 124910037SARM gem5 Developers asid = -1; 125010037SARM gem5 Developers break; 125110037SARM gem5 Developers case EL3: 125210037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 125310037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 125410037SARM gem5 Developers asid = -1; 125510037SARM gem5 Developers break; 125610037SARM gem5 Developers } 125710037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR_EL3); 125810037SARM gem5 Developers isPriv = aarch64EL != EL0; 125910037SARM gem5 Developers // @todo: modify this behaviour to support Virtualization in 126010037SARM gem5 Developers // AArch64 126110037SARM gem5 Developers vmid = 0; 126210037SARM gem5 Developers isHyp = false; 126310037SARM gem5 Developers directToStage2 = false; 126410037SARM gem5 Developers stage2Req = false; 126510037SARM gem5 Developers } else { // AArch32 126610037SARM gem5 Developers sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 126710037SARM gem5 Developers !isSecure)); 126810037SARM gem5 Developers ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 126910037SARM gem5 Developers !isSecure)); 127010037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR); 127110037SARM gem5 Developers isPriv = cpsr.mode != MODE_USER; 127210037SARM gem5 Developers if (haveLPAE && ttbcr.eae) { 127310037SARM gem5 Developers // Long-descriptor translation table format in use 127410037SARM gem5 Developers uint64_t ttbr_asid = tc->readMiscReg( 127510037SARM gem5 Developers flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1 127610037SARM gem5 Developers : MISCREG_TTBR0, 127710037SARM gem5 Developers tc, !isSecure)); 127810037SARM gem5 Developers asid = bits(ttbr_asid, 55, 48); 127910037SARM gem5 Developers } else { 128010037SARM gem5 Developers // Short-descriptor translation table format in use 128110037SARM gem5 Developers CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked( 128210037SARM gem5 Developers MISCREG_CONTEXTIDR, tc,!isSecure)); 128310037SARM gem5 Developers asid = context_id.asid; 128410037SARM gem5 Developers } 128510037SARM gem5 Developers prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc, 128610037SARM gem5 Developers !isSecure)); 128710037SARM gem5 Developers nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc, 128810037SARM gem5 Developers !isSecure)); 128910037SARM gem5 Developers dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc, 129010037SARM gem5 Developers !isSecure)); 129110037SARM gem5 Developers hcr = tc->readMiscReg(MISCREG_HCR); 129210037SARM gem5 Developers 129310037SARM gem5 Developers if (haveVirtualization) { 129410037SARM gem5 Developers vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 129510037SARM gem5 Developers isHyp = cpsr.mode == MODE_HYP; 129610037SARM gem5 Developers isHyp |= tranType & HypMode; 129710037SARM gem5 Developers isHyp &= (tranType & S1S2NsTran) == 0; 129810037SARM gem5 Developers isHyp &= (tranType & S1CTran) == 0; 129910037SARM gem5 Developers if (isHyp) { 130010037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_HSCTLR); 130110037SARM gem5 Developers } 130210037SARM gem5 Developers // Work out if we should skip the first stage of translation and go 130310037SARM gem5 Developers // directly to stage 2. This value is cached so we don't have to 130410037SARM gem5 Developers // compute it for every translation. 130510037SARM gem5 Developers stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 130610037SARM gem5 Developers !(tranType & S1CTran); 130710037SARM gem5 Developers directToStage2 = stage2Req && !sctlr.m; 130810037SARM gem5 Developers } else { 130910037SARM gem5 Developers vmid = 0; 131010037SARM gem5 Developers stage2Req = false; 131110037SARM gem5 Developers isHyp = false; 131210037SARM gem5 Developers directToStage2 = false; 131310037SARM gem5 Developers } 131410037SARM gem5 Developers } 131510037SARM gem5 Developers miscRegValid = true; 131610037SARM gem5 Developers curTranType = tranType; 131710037SARM gem5 Developers} 131810037SARM gem5 Developers 131910037SARM gem5 DevelopersFault 132010037SARM gem5 DevelopersTLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 132110037SARM gem5 Developers Translation *translation, bool timing, bool functional, 132210037SARM gem5 Developers bool is_secure, TLB::ArmTranslationType tranType) 132310037SARM gem5 Developers{ 132410037SARM gem5 Developers bool is_fetch = (mode == Execute); 132510037SARM gem5 Developers bool is_write = (mode == Write); 132610037SARM gem5 Developers 132710037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 132810037SARM gem5 Developers Addr vaddr = 0; 132910037SARM gem5 Developers ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 133010037SARM gem5 Developers if (aarch64) { 133110037SARM gem5 Developers vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el); 133210037SARM gem5 Developers } else { 133310037SARM gem5 Developers vaddr = vaddr_tainted; 133410037SARM gem5 Developers } 133510037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 133610037SARM gem5 Developers if (*te == NULL) { 133710037SARM gem5 Developers if (req->isPrefetch()) { 133810037SARM gem5 Developers // if the request is a prefetch don't attempt to fill the TLB or go 133910037SARM gem5 Developers // any further with the memory access (here we can safely use the 134010037SARM gem5 Developers // fault status for the short desc. format in all cases) 13417734SAli.Saidi@ARM.com prefetchFaults++; 134210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 134310474Sandreas.hansson@arm.com vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 13447611SGene.Wu@arm.com } 13457734SAli.Saidi@ARM.com 13467734SAli.Saidi@ARM.com if (is_fetch) 13477734SAli.Saidi@ARM.com instMisses++; 13487734SAli.Saidi@ARM.com else if (is_write) 13497734SAli.Saidi@ARM.com writeMisses++; 13507734SAli.Saidi@ARM.com else 13517734SAli.Saidi@ARM.com readMisses++; 13527734SAli.Saidi@ARM.com 13537404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 13547404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 135510037SARM gem5 Developers DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 135610037SARM gem5 Developers vaddr_tainted, asid, vmid); 135710037SARM gem5 Developers Fault fault; 135810037SARM gem5 Developers fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 135910037SARM gem5 Developers translation, timing, functional, is_secure, 136010037SARM gem5 Developers tranType); 136110037SARM gem5 Developers // for timing mode, return and wait for table walk, 136210037SARM gem5 Developers if (timing || fault != NoFault) { 13637437Sdam.sunwoo@arm.com return fault; 13647437Sdam.sunwoo@arm.com } 13657404SAli.Saidi@ARM.com 136610037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 136710037SARM gem5 Developers if (!*te) 13687404SAli.Saidi@ARM.com printTlb(); 136910037SARM gem5 Developers assert(*te); 13707734SAli.Saidi@ARM.com } else { 13717734SAli.Saidi@ARM.com if (is_fetch) 13727734SAli.Saidi@ARM.com instHits++; 13737734SAli.Saidi@ARM.com else if (is_write) 13747734SAli.Saidi@ARM.com writeHits++; 13757734SAli.Saidi@ARM.com else 13767734SAli.Saidi@ARM.com readHits++; 13777404SAli.Saidi@ARM.com } 13786757SAli.Saidi@ARM.com return NoFault; 13797404SAli.Saidi@ARM.com} 13806757SAli.Saidi@ARM.com 13817404SAli.Saidi@ARM.comFault 138210037SARM gem5 DevelopersTLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 138310037SARM gem5 Developers Translation *translation, bool timing, bool functional, 138410037SARM gem5 Developers TlbEntry *mergeTe) 13857404SAli.Saidi@ARM.com{ 13867404SAli.Saidi@ARM.com Fault fault; 138710037SARM gem5 Developers TlbEntry *s1Te = NULL; 138810037SARM gem5 Developers 138910037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 139010037SARM gem5 Developers 139110037SARM gem5 Developers // Get the stage 1 table entry 139210037SARM gem5 Developers fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 139310037SARM gem5 Developers isSecure, curTranType); 139410037SARM gem5 Developers // only proceed if we have a valid table entry 139510037SARM gem5 Developers if ((s1Te != NULL) && (fault == NoFault)) { 139610037SARM gem5 Developers // Check stage 1 permissions before checking stage 2 139710037SARM gem5 Developers if (aarch64) 139810037SARM gem5 Developers fault = checkPermissions64(s1Te, req, mode, tc); 139910037SARM gem5 Developers else 140010037SARM gem5 Developers fault = checkPermissions(s1Te, req, mode); 140110037SARM gem5 Developers if (stage2Req & (fault == NoFault)) { 140210037SARM gem5 Developers Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 140310037SARM gem5 Developers req, translation, mode, timing, functional, curTranType); 140410037SARM gem5 Developers fault = s2Lookup->getTe(tc, mergeTe); 140510037SARM gem5 Developers if (s2Lookup->isComplete()) { 140610037SARM gem5 Developers *te = mergeTe; 140710037SARM gem5 Developers // We've finished with the lookup so delete it 140810037SARM gem5 Developers delete s2Lookup; 140910037SARM gem5 Developers } else { 141010037SARM gem5 Developers // The lookup hasn't completed, so we can't delete it now. We 141110037SARM gem5 Developers // get round this by asking the object to self delete when the 141210037SARM gem5 Developers // translation is complete. 141310037SARM gem5 Developers s2Lookup->setSelfDelete(); 141410037SARM gem5 Developers } 141510037SARM gem5 Developers } else { 141610037SARM gem5 Developers // This case deals with an S1 hit (or bypass), followed by 141710037SARM gem5 Developers // an S2 hit-but-perms issue 141810037SARM gem5 Developers if (isStage2) { 141910037SARM gem5 Developers DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 142010037SARM gem5 Developers vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 142110037SARM gem5 Developers if (fault != NoFault) { 142210037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 142310037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, false); 142410037SARM gem5 Developers armFault->annotate(ArmFault::OVA, vaddr_tainted); 142510037SARM gem5 Developers } 142610037SARM gem5 Developers } 142710037SARM gem5 Developers *te = s1Te; 142810037SARM gem5 Developers } 142910037SARM gem5 Developers } 14307404SAli.Saidi@ARM.com return fault; 14316019Shines@cs.fsu.edu} 14326019Shines@cs.fsu.edu 14336116Snate@binkert.orgArmISA::TLB * 14346116Snate@binkert.orgArmTLBParams::create() 14356019Shines@cs.fsu.edu{ 14366116Snate@binkert.org return new ArmISA::TLB(this); 14376019Shines@cs.fsu.edu} 1438