table_walker.hh revision 9165
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 41#define __ARCH_ARM_TABLE_WALKER_HH__ 42 43#include <list> 44 45#include "arch/arm/miscregs.hh" 46#include "arch/arm/tlb.hh" 47#include "dev/dma_device.hh" 48#include "mem/mem_object.hh" 49#include "mem/request.hh" 50#include "params/ArmTableWalker.hh" 51#include "sim/eventq.hh" 52#include "sim/fault_fwd.hh" 53 54class ThreadContext; 55 56namespace ArmISA { 57class Translation; 58class TLB; 59 60class TableWalker : public MemObject 61{ 62 public: 63 struct L1Descriptor { 64 /** Type of page table entry ARM DDI 0406B: B3-8*/ 65 enum EntryType { 66 Ignore, 67 PageTable, 68 Section, 69 Reserved 70 }; 71 72 /** The raw bits of the entry */ 73 uint32_t data; 74 75 /** This entry has been modified (access flag set) and needs to be 76 * written back to memory */ 77 bool _dirty; 78 79 EntryType type() const 80 { 81 return (EntryType)(data & 0x3); 82 } 83 84 /** Is the page a Supersection (16MB)?*/ 85 bool supersection() const 86 { 87 return bits(data, 18); 88 } 89 90 /** Return the physcal address of the entry, bits in position*/ 91 Addr paddr() const 92 { 93 if (supersection()) 94 panic("Super sections not implemented\n"); 95 return mbits(data, 31, 20); 96 } 97 /** Return the physcal address of the entry, bits in position*/ 98 Addr paddr(Addr va) const 99 { 100 if (supersection()) 101 panic("Super sections not implemented\n"); 102 return mbits(data, 31, 20) | mbits(va, 19, 0); 103 } 104 105 106 /** Return the physical frame, bits shifted right */ 107 Addr pfn() const 108 { 109 if (supersection()) 110 panic("Super sections not implemented\n"); 111 return bits(data, 31, 20); 112 } 113 114 /** Is the translation global (no asid used)? */ 115 bool global() const 116 { 117 return bits(data, 17); 118 } 119 120 /** Is the translation not allow execution? */ 121 bool xn() const 122 { 123 return bits(data, 4); 124 } 125 126 /** Three bit access protection flags */ 127 uint8_t ap() const 128 { 129 return (bits(data, 15) << 2) | bits(data, 11, 10); 130 } 131 132 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 133 uint8_t domain() const 134 { 135 return bits(data, 8, 5); 136 } 137 138 /** Address of L2 descriptor if it exists */ 139 Addr l2Addr() const 140 { 141 return mbits(data, 31, 10); 142 } 143 144 /** Memory region attributes: ARM DDI 0406B: B3-32. 145 * These bits are largly ignored by M5 and only used to 146 * provide the illusion that the memory system cares about 147 * anything but cachable vs. uncachable. 148 */ 149 uint8_t texcb() const 150 { 151 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 152 } 153 154 /** If the section is shareable. See texcb() comment. */ 155 bool shareable() const 156 { 157 return bits(data, 16); 158 } 159 160 /** Set access flag that this entry has been touched. Mark 161 * the entry as requiring a writeback, in the future. 162 */ 163 void setAp0() 164 { 165 data |= 1 << 10; 166 _dirty = true; 167 } 168 169 /** This entry needs to be written back to memory */ 170 bool dirty() const 171 { 172 return _dirty; 173 } 174 }; 175 176 /** Level 2 page table descriptor */ 177 struct L2Descriptor { 178 179 /** The raw bits of the entry. */ 180 uint32_t data; 181 182 /** This entry has been modified (access flag set) and needs to be 183 * written back to memory */ 184 bool _dirty; 185 186 /** Is the entry invalid */ 187 bool invalid() const 188 { 189 return bits(data, 1, 0) == 0; 190 } 191 192 /** What is the size of the mapping? */ 193 bool large() const 194 { 195 return bits(data, 1) == 0; 196 } 197 198 /** Is execution allowed on this mapping? */ 199 bool xn() const 200 { 201 return large() ? bits(data, 15) : bits(data, 0); 202 } 203 204 /** Is the translation global (no asid used)? */ 205 bool global() const 206 { 207 return !bits(data, 11); 208 } 209 210 /** Three bit access protection flags */ 211 uint8_t ap() const 212 { 213 return bits(data, 5, 4) | (bits(data, 9) << 2); 214 } 215 216 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 217 uint8_t texcb() const 218 { 219 return large() ? 220 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 222 } 223 224 /** Return the physical frame, bits shifted right */ 225 Addr pfn() const 226 { 227 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 228 } 229 230 /** Return complete physical address given a VA */ 231 Addr paddr(Addr va) const 232 { 233 if (large()) 234 return mbits(data, 31, 16) | mbits(va, 15, 0); 235 else 236 return mbits(data, 31, 12) | mbits(va, 11, 0); 237 } 238 239 /** If the section is shareable. See texcb() comment. */ 240 bool shareable() const 241 { 242 return bits(data, 10); 243 } 244 245 /** Set access flag that this entry has been touched. Mark 246 * the entry as requiring a writeback, in the future. 247 */ 248 void setAp0() 249 { 250 data |= 1 << 4; 251 _dirty = true; 252 } 253 254 /** This entry needs to be written back to memory */ 255 bool dirty() const 256 { 257 return _dirty; 258 } 259 260 }; 261 262 protected: 263 264 /** 265 * A snooping DMA port that currently does nothing besides 266 * extending the DMA port to accept snoops without complaining. 267 */ 268 class SnoopingDmaPort : public DmaPort 269 { 270 271 protected: 272 273 virtual void recvTimingSnoopReq(PacketPtr pkt) 274 { } 275 276 virtual Tick recvAtomicSnoop(PacketPtr pkt) 277 { return 0; } 278 279 virtual void recvFunctionalSnoop(PacketPtr pkt) 280 { } 281 282 virtual bool isSnooping() const { return true; } 283 284 public: 285 286 /** 287 * A snooping DMA port merely calls the construtor of the DMA 288 * port. 289 */ 290 SnoopingDmaPort(MemObject *dev, System *s) : 291 DmaPort(dev, s) 292 { } 293 }; 294 295 struct WalkerState //: public SimObject 296 { 297 /** Thread context that we're doing the walk for */ 298 ThreadContext *tc; 299 300 /** Request that is currently being serviced */ 301 RequestPtr req; 302 303 /** Context ID that we're servicing the request under */ 304 uint8_t contextId; 305 306 /** Translation state for delayed requests */ 307 TLB::Translation *transState; 308 309 /** The fault that we are going to return */ 310 Fault fault; 311 312 /** The virtual address that is being translated */ 313 Addr vaddr; 314 315 /** Cached copy of the sctlr as it existed when translation began */ 316 SCTLR sctlr; 317 318 /** Width of the base address held in TTRB0 */ 319 uint32_t N; 320 321 /** If the access is a write */ 322 bool isWrite; 323 324 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 325 bool isFetch; 326 327 /** If the mode is timing or atomic */ 328 bool timing; 329 330 /** If the atomic mode should be functional */ 331 bool functional; 332 333 /** Save mode for use in delayed response */ 334 BaseTLB::Mode mode; 335 336 L1Descriptor l1Desc; 337 L2Descriptor l2Desc; 338 339 /** Whether L1/L2 descriptor response is delayed in timing mode */ 340 bool delayed; 341 342 TableWalker *tableWalker; 343 344 void doL1Descriptor(); 345 void doL2Descriptor(); 346 347 std::string name() const {return tableWalker->name();} 348 }; 349 350 351 /** Queue of requests that need processing first level translation */ 352 std::list<WalkerState *> stateQueueL1; 353 354 /** Queue of requests that have passed first level translation and 355 * require an additional level. */ 356 std::list<WalkerState *> stateQueueL2; 357 358 /** Queue of requests that have passed are waiting because the walker is 359 * currently busy. */ 360 std::list<WalkerState *> pendingQueue; 361 362 363 /** Port to issue translation requests from */ 364 SnoopingDmaPort port; 365 366 /** If we're draining keep the drain event around until we're drained */ 367 Event *drainEvent; 368 369 /** TLB that is initiating these table walks */ 370 TLB *tlb; 371 372 /** Cached copy of the sctlr as it existed when translation began */ 373 SCTLR sctlr; 374 375 WalkerState *currState; 376 377 /** If a timing translation is currently in progress */ 378 bool pending; 379 380 /** Request id for requests generated by this walker */ 381 MasterID masterId; 382 383 public: 384 typedef ArmTableWalkerParams Params; 385 TableWalker(const Params *p); 386 virtual ~TableWalker(); 387 388 const Params * 389 params() const 390 { 391 return dynamic_cast<const Params *>(_params); 392 } 393 394 /** Checks if all state is cleared and if so, completes drain */ 395 void completeDrain(); 396 virtual unsigned int drain(Event *de); 397 virtual void resume(); 398 virtual MasterPort& getMasterPort(const std::string &if_name, 399 int idx = -1); 400 401 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 402 TLB::Translation *_trans, bool timing, bool functional = false); 403 404 void setTlb(TLB *_tlb) { tlb = _tlb; } 405 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 406 uint8_t texcb, bool s); 407 408 private: 409 410 void doL1Descriptor(); 411 void doL1DescriptorWrapper(); 412 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 413 414 void doL2Descriptor(); 415 void doL2DescriptorWrapper(); 416 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 417 418 Fault processWalk(); 419 void processWalkWrapper(); 420 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 421 422 void nextWalk(ThreadContext *tc); 423}; 424 425 426} // namespace ArmISA 427 428#endif //__ARCH_ARM_TABLE_WALKER_HH__ 429 430