table_walker.hh revision 8733:64a7bf8fa56c
12SN/A/* 21762SN/A * Copyright (c) 2010 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365882Snate@binkert.org * 371492SN/A * Authors: Ali Saidi 381717SN/A */ 398229Snate@binkert.org 402680Sktlim@umich.edu#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 418232Snate@binkert.org#define __ARCH_ARM_TABLE_WALKER_HH__ 424167Sbinkertn@umich.edu 432190SN/A#include <list> 442SN/A 452SN/A#include "arch/arm/miscregs.hh" 462SN/A#include "arch/arm/tlb.hh" 472SN/A#include "mem/mem_object.hh" 482SN/A#include "mem/request.hh" 492SN/A#include "params/ArmTableWalker.hh" 502SN/A#include "sim/eventq.hh" 512SN/A#include "sim/fault_fwd.hh" 522SN/A 532SN/Aclass DmaPort; 542SN/Aclass ThreadContext; 552SN/A 562SN/Anamespace ArmISA { 572SN/Aclass Translation; 588991SAli.Saidi@ARM.comclass TLB; 598991SAli.Saidi@ARM.com 608991SAli.Saidi@ARM.comclass TableWalker : public MemObject 612SN/A{ 622SN/A public: 632SN/A struct L1Descriptor { 648991SAli.Saidi@ARM.com /** Type of page table entry ARM DDI 0406B: B3-8*/ 652SN/A enum EntryType { 668991SAli.Saidi@ARM.com Ignore, 678991SAli.Saidi@ARM.com PageTable, 682SN/A Section, 698991SAli.Saidi@ARM.com Reserved 702SN/A }; 712SN/A 722SN/A /** The raw bits of the entry */ 732SN/A uint32_t data; 742SN/A 752SN/A /** This entry has been modified (access flag set) and needs to be 762SN/A * written back to memory */ 772SN/A bool _dirty; 782SN/A 792SN/A EntryType type() const 802SN/A { 812SN/A return (EntryType)(data & 0x3); 822SN/A } 832SN/A 842SN/A /** Is the page a Supersection (16MB)?*/ 852SN/A bool supersection() const 862SN/A { 872SN/A return bits(data, 18); 882680Sktlim@umich.edu } 892SN/A 908670Ss052838@student.dtu.dk /** Return the physcal address of the entry, bits in position*/ 918670Ss052838@student.dtu.dk Addr paddr() const 928670Ss052838@student.dtu.dk { 932SN/A if (supersection()) 942SN/A panic("Super sections not implemented\n"); 952SN/A return mbits(data, 31, 20); 962SN/A } 972SN/A /** Return the physcal address of the entry, bits in position*/ 982SN/A Addr paddr(Addr va) const 992SN/A { 1008670Ss052838@student.dtu.dk if (supersection()) 1012SN/A panic("Super sections not implemented\n"); 1022SN/A return mbits(data, 31, 20) | mbits(va, 19, 0); 1032SN/A } 1042SN/A 1052SN/A 1062680Sktlim@umich.edu /** Return the physical frame, bits shifted right */ 1072SN/A Addr pfn() const 1082SN/A { 1092SN/A if (supersection()) 1102SN/A panic("Super sections not implemented\n"); 1112SN/A return bits(data, 31, 20); 1122SN/A } 1132SN/A 1142SN/A /** Is the translation global (no asid used)? */ 1152SN/A bool global() const 1162SN/A { 1172SN/A return bits(data, 17); 1182SN/A } 1192SN/A 1207823Ssteve.reinhardt@amd.com /** Is the translation not allow execution? */ 1212SN/A bool xn() const 1222SN/A { 1232SN/A return bits(data, 4); 1242SN/A } 1252SN/A 1262SN/A /** Three bit access protection flags */ 1272SN/A uint8_t ap() const 1282SN/A { 1292SN/A return (bits(data, 15) << 2) | bits(data, 11, 10); 1301885SN/A } 1311885SN/A 1321885SN/A /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 1332SN/A uint8_t domain() const 1342SN/A { 1352SN/A return bits(data, 8, 5); 1362SN/A } 1372680Sktlim@umich.edu 1382SN/A /** Address of L2 descriptor if it exists */ 1392680Sktlim@umich.edu Addr l2Addr() const 1401646SN/A { 1418231Snate@binkert.org return mbits(data, 31, 10); 1422SN/A } 1432SN/A 1442SN/A /** Memory region attributes: ARM DDI 0406B: B3-32. 1452SN/A * These bits are largly ignored by M5 and only used to 1462SN/A * provide the illusion that the memory system cares about 1472130SN/A * anything but cachable vs. uncachable. 1482SN/A */ 1491885SN/A uint8_t texcb() const 1502SN/A { 1512SN/A return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 1522SN/A } 1532130SN/A 1542SN/A /** If the section is shareable. See texcb() comment. */ 1552SN/A bool shareable() const 1562SN/A { 1572SN/A return bits(data, 16); 1582SN/A } 1592SN/A 1602SN/A /** Set access flag that this entry has been touched. Mark 1619649SAndreas.Sandberg@ARM.com * the entry as requiring a writeback, in the future. 1629649SAndreas.Sandberg@ARM.com */ 1639649SAndreas.Sandberg@ARM.com void setAp0() 1649649SAndreas.Sandberg@ARM.com { 1659649SAndreas.Sandberg@ARM.com data |= 1 << 10; 1669649SAndreas.Sandberg@ARM.com _dirty = true; 1679649SAndreas.Sandberg@ARM.com } 1689649SAndreas.Sandberg@ARM.com 1699649SAndreas.Sandberg@ARM.com /** This entry needs to be written back to memory */ 1709649SAndreas.Sandberg@ARM.com bool dirty() const 1719649SAndreas.Sandberg@ARM.com { 1729649SAndreas.Sandberg@ARM.com return _dirty; 173 } 174 }; 175 176 /** Level 2 page table descriptor */ 177 struct L2Descriptor { 178 179 /** The raw bits of the entry. */ 180 uint32_t data; 181 182 /** This entry has been modified (access flag set) and needs to be 183 * written back to memory */ 184 bool _dirty; 185 186 /** Is the entry invalid */ 187 bool invalid() const 188 { 189 return bits(data, 1, 0) == 0; 190 } 191 192 /** What is the size of the mapping? */ 193 bool large() const 194 { 195 return bits(data, 1) == 0; 196 } 197 198 /** Is execution allowed on this mapping? */ 199 bool xn() const 200 { 201 return large() ? bits(data, 15) : bits(data, 0); 202 } 203 204 /** Is the translation global (no asid used)? */ 205 bool global() const 206 { 207 return !bits(data, 11); 208 } 209 210 /** Three bit access protection flags */ 211 uint8_t ap() const 212 { 213 return bits(data, 5, 4) | (bits(data, 9) << 2); 214 } 215 216 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 217 uint8_t texcb() const 218 { 219 return large() ? 220 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 222 } 223 224 /** Return the physical frame, bits shifted right */ 225 Addr pfn() const 226 { 227 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 228 } 229 230 /** Return complete physical address given a VA */ 231 Addr paddr(Addr va) const 232 { 233 if (large()) 234 return mbits(data, 31, 16) | mbits(va, 15, 0); 235 else 236 return mbits(data, 31, 12) | mbits(va, 11, 0); 237 } 238 239 /** If the section is shareable. See texcb() comment. */ 240 bool shareable() const 241 { 242 return bits(data, 10); 243 } 244 245 /** Set access flag that this entry has been touched. Mark 246 * the entry as requiring a writeback, in the future. 247 */ 248 void setAp0() 249 { 250 data |= 1 << 4; 251 _dirty = true; 252 } 253 254 /** This entry needs to be written back to memory */ 255 bool dirty() const 256 { 257 return _dirty; 258 } 259 260 }; 261 262 struct WalkerState //: public SimObject 263 { 264 /** Thread context that we're doing the walk for */ 265 ThreadContext *tc; 266 267 /** Request that is currently being serviced */ 268 RequestPtr req; 269 270 /** Context ID that we're servicing the request under */ 271 uint8_t contextId; 272 273 /** Translation state for delayed requests */ 274 TLB::Translation *transState; 275 276 /** The fault that we are going to return */ 277 Fault fault; 278 279 /** The virtual address that is being translated */ 280 Addr vaddr; 281 282 /** Cached copy of the sctlr as it existed when translation began */ 283 SCTLR sctlr; 284 285 /** Width of the base address held in TTRB0 */ 286 uint32_t N; 287 288 /** If the access is a write */ 289 bool isWrite; 290 291 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 292 bool isFetch; 293 294 /** If the mode is timing or atomic */ 295 bool timing; 296 297 /** If the atomic mode should be functional */ 298 bool functional; 299 300 /** Save mode for use in delayed response */ 301 BaseTLB::Mode mode; 302 303 L1Descriptor l1Desc; 304 L2Descriptor l2Desc; 305 306 /** Whether L1/L2 descriptor response is delayed in timing mode */ 307 bool delayed; 308 309 TableWalker *tableWalker; 310 311 void doL1Descriptor(); 312 void doL2Descriptor(); 313 314 std::string name() const {return tableWalker->name();} 315 }; 316 317 318 /** Queue of requests that need processing first level translation */ 319 std::list<WalkerState *> stateQueueL1; 320 321 /** Queue of requests that have passed first level translation and 322 * require an additional level. */ 323 std::list<WalkerState *> stateQueueL2; 324 325 /** Queue of requests that have passed are waiting because the walker is 326 * currently busy. */ 327 std::list<WalkerState *> pendingQueue;; 328 329 330 /** Port to issue translation requests from */ 331 DmaPort *port; 332 333 /** TLB that is initiating these table walks */ 334 TLB *tlb; 335 336 /** Cached copy of the sctlr as it existed when translation began */ 337 SCTLR sctlr; 338 339 WalkerState *currState; 340 341 /** If a timing translation is currently in progress */ 342 bool pending; 343 344 public: 345 typedef ArmTableWalkerParams Params; 346 TableWalker(const Params *p); 347 virtual ~TableWalker(); 348 349 const Params * 350 params() const 351 { 352 return dynamic_cast<const Params *>(_params); 353 } 354 355 virtual unsigned int drain(Event *de); 356 virtual void resume(); 357 virtual Port *getPort(const std::string &if_name, int idx = -1); 358 359 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 360 TLB::Translation *_trans, bool timing, bool functional = false); 361 362 void setTlb(TLB *_tlb) { tlb = _tlb; } 363 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 364 uint8_t texcb, bool s); 365 366 private: 367 368 void doL1Descriptor(); 369 void doL1DescriptorWrapper(); 370 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 371 372 void doL2Descriptor(); 373 void doL2DescriptorWrapper(); 374 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 375 376 Fault processWalk(); 377 void processWalkWrapper(); 378 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 379 380 void nextWalk(ThreadContext *tc); 381}; 382 383 384} // namespace ArmISA 385 386#endif //__ARCH_ARM_TABLE_WALKER_HH__ 387 388