table_walker.hh revision 7728:cf9db1c47a77
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2010 ARM Limited 36019Shines@cs.fsu.edu * All rights reserved 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * The license below extends only to copyright in the software and shall 66019Shines@cs.fsu.edu * not be construed as granting a license to any other intellectual 76019Shines@cs.fsu.edu * property including but not limited to intellectual property relating 86019Shines@cs.fsu.edu * to a hardware implementation of the functionality of the software 96019Shines@cs.fsu.edu * licensed hereunder. You may use the software subject to the license 106019Shines@cs.fsu.edu * terms below provided that you ensure that this notice is replicated 116019Shines@cs.fsu.edu * unmodified and in its entirety in all distributions of the software, 126019Shines@cs.fsu.edu * modified or unmodified, in source code or in binary form. 136019Shines@cs.fsu.edu * 146019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 156019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 166019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 176019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 186019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 196019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 206019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 216019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 226019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 236019Shines@cs.fsu.edu * this software without specific prior written permission. 246019Shines@cs.fsu.edu * 256019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366019Shines@cs.fsu.edu * 376214Snate@binkert.org * Authors: Ali Saidi 386019Shines@cs.fsu.edu */ 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 416019Shines@cs.fsu.edu#define __ARCH_ARM_TABLE_WALKER_HH__ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#include <list> 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include "arch/arm/miscregs.hh" 466019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 476019Shines@cs.fsu.edu#include "mem/mem_object.hh" 486019Shines@cs.fsu.edu#include "mem/request.hh" 496019Shines@cs.fsu.edu#include "mem/request.hh" 506019Shines@cs.fsu.edu#include "params/ArmTableWalker.hh" 516019Shines@cs.fsu.edu#include "sim/eventq.hh" 526019Shines@cs.fsu.edu#include "sim/fault.hh" 536019Shines@cs.fsu.edu 546019Shines@cs.fsu.educlass DmaPort; 556019Shines@cs.fsu.educlass ThreadContext; 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edunamespace ArmISA { 586019Shines@cs.fsu.educlass Translation; 596019Shines@cs.fsu.educlass TLB; 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.educlass TableWalker : public MemObject 626019Shines@cs.fsu.edu{ 636019Shines@cs.fsu.edu public: 646019Shines@cs.fsu.edu struct L1Descriptor { 656019Shines@cs.fsu.edu /** Type of page table entry ARM DDI 0406B: B3-8*/ 666019Shines@cs.fsu.edu enum EntryType { 676019Shines@cs.fsu.edu Ignore, 686019Shines@cs.fsu.edu PageTable, 696019Shines@cs.fsu.edu Section, 706019Shines@cs.fsu.edu Reserved 716019Shines@cs.fsu.edu }; 726019Shines@cs.fsu.edu 736019Shines@cs.fsu.edu /** The raw bits of the entry */ 746019Shines@cs.fsu.edu uint32_t data; 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.edu /** This entry has been modified (access flag set) and needs to be 776019Shines@cs.fsu.edu * written back to memory */ 786019Shines@cs.fsu.edu bool _dirty; 796019Shines@cs.fsu.edu 806019Shines@cs.fsu.edu EntryType type() const 816019Shines@cs.fsu.edu { 826019Shines@cs.fsu.edu return (EntryType)(data & 0x3); 836019Shines@cs.fsu.edu } 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.edu /** Is the page a Supersection (16MB)?*/ 866019Shines@cs.fsu.edu bool supersection() const 876019Shines@cs.fsu.edu { 886019Shines@cs.fsu.edu return bits(data, 18); 896019Shines@cs.fsu.edu } 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.edu /** Return the physcal address of the entry, bits in position*/ 926019Shines@cs.fsu.edu Addr paddr() const 936019Shines@cs.fsu.edu { 946019Shines@cs.fsu.edu if (supersection()) 956019Shines@cs.fsu.edu panic("Super sections not implemented\n"); 966019Shines@cs.fsu.edu return mbits(data, 31,20); 976019Shines@cs.fsu.edu } 986019Shines@cs.fsu.edu /** Return the physcal address of the entry, bits in position*/ 996019Shines@cs.fsu.edu Addr paddr(Addr va) const 1006019Shines@cs.fsu.edu { 1016019Shines@cs.fsu.edu if (supersection()) 1026019Shines@cs.fsu.edu panic("Super sections not implemented\n"); 1036019Shines@cs.fsu.edu return mbits(data, 31,20) | mbits(va, 20, 0); 1046019Shines@cs.fsu.edu } 1056019Shines@cs.fsu.edu 1066019Shines@cs.fsu.edu 1076735Sgblack@eecs.umich.edu /** Return the physical frame, bits shifted right */ 1086735Sgblack@eecs.umich.edu Addr pfn() const 1096974Stjones1@inf.ed.ac.uk { 1106974Stjones1@inf.ed.ac.uk if (supersection()) 1116974Stjones1@inf.ed.ac.uk panic("Super sections not implemented\n"); 1126019Shines@cs.fsu.edu return bits(data, 31,20); 1136019Shines@cs.fsu.edu } 1146019Shines@cs.fsu.edu 1156019Shines@cs.fsu.edu /** Is the translation global (no asid used)? */ 1166019Shines@cs.fsu.edu bool global() const 117 { 118 return bits(data, 17); 119 } 120 121 /** Is the translation not allow execution? */ 122 bool xn() const 123 { 124 return bits(data, 4); 125 } 126 127 /** Three bit access protection flags */ 128 uint8_t ap() const 129 { 130 return (bits(data, 15) << 2) | bits(data,11,10); 131 } 132 133 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 134 uint8_t domain() const 135 { 136 return bits(data,8,5); 137 } 138 139 /** Address of L2 descriptor if it exists */ 140 Addr l2Addr() const 141 { 142 return mbits(data, 31,10); 143 } 144 145 /** Memory region attributes: ARM DDI 0406B: B3-32. 146 * These bits are largly ignored by M5 and only used to 147 * provide the illusion that the memory system cares about 148 * anything but cachable vs. uncachable. 149 */ 150 uint8_t texcb() const 151 { 152 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2; 153 } 154 155 /** If the section is shareable. See texcb() comment. */ 156 bool shareable() const 157 { 158 return bits(data, 16); 159 } 160 161 /** Set access flag that this entry has been touched. Mark 162 * the entry as requiring a writeback, in the future. 163 */ 164 void setAp0() 165 { 166 data |= 1 << 10; 167 _dirty = true; 168 } 169 170 /** This entry needs to be written back to memory */ 171 bool dirty() const 172 { 173 return _dirty; 174 } 175 }; 176 177 /** Level 2 page table descriptor */ 178 struct L2Descriptor { 179 180 /** The raw bits of the entry. */ 181 uint32_t data; 182 183 /** This entry has been modified (access flag set) and needs to be 184 * written back to memory */ 185 bool _dirty; 186 187 /** Is the entry invalid */ 188 bool invalid() const 189 { 190 return bits(data, 1,0) == 0;; 191 } 192 193 /** What is the size of the mapping? */ 194 bool large() const 195 { 196 return bits(data, 1) == 0; 197 } 198 199 /** Is execution allowed on this mapping? */ 200 bool xn() const 201 { 202 return large() ? bits(data, 15) : bits(data, 0); 203 } 204 205 /** Is the translation global (no asid used)? */ 206 bool global() const 207 { 208 return !bits(data, 11); 209 } 210 211 /** Three bit access protection flags */ 212 uint8_t ap() const 213 { 214 return bits(data, 5, 4) | (bits(data, 9) << 2); 215 } 216 217 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 218 uint8_t texcb() const 219 { 220 return large() ? 221 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) : 222 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2)); 223 } 224 225 /** Return the physical frame, bits shifted right */ 226 Addr pfn() const 227 { 228 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 229 } 230 231 /** Return complete physical address given a VA */ 232 Addr paddr(Addr va) const 233 { 234 if (large()) 235 return mbits(data, 31, 16) | mbits(va, 15, 0); 236 else 237 return mbits(data, 31, 12) | mbits(va, 11, 0); 238 } 239 240 /** If the section is shareable. See texcb() comment. */ 241 bool shareable() const 242 { 243 return bits(data, 10); 244 } 245 246 /** Set access flag that this entry has been touched. Mark 247 * the entry as requiring a writeback, in the future. 248 */ 249 void setAp0() 250 { 251 data |= 1 << 4; 252 _dirty = true; 253 } 254 255 /** This entry needs to be written back to memory */ 256 bool dirty() const 257 { 258 return _dirty; 259 } 260 261 }; 262 263 struct WalkerState //: public SimObject 264 { 265 /** Thread context that we're doing the walk for */ 266 ThreadContext *tc; 267 268 /** Request that is currently being serviced */ 269 RequestPtr req; 270 271 /** Context ID that we're servicing the request under */ 272 uint8_t contextId; 273 274 /** Translation state for delayed requests */ 275 TLB::Translation *transState; 276 277 /** The fault that we are going to return */ 278 Fault fault; 279 280 /** The virtual address that is being translated */ 281 Addr vaddr; 282 283 /** Cached copy of the sctlr as it existed when translation began */ 284 SCTLR sctlr; 285 286 /** Width of the base address held in TTRB0 */ 287 uint32_t N; 288 289 /** If the access is a write */ 290 bool isWrite; 291 292 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 293 bool isFetch; 294 295 /** If the mode is timing or atomic */ 296 bool timing; 297 298 /** Save mode for use in delayed response */ 299 BaseTLB::Mode mode; 300 301 L1Descriptor l1Desc; 302 L2Descriptor l2Desc; 303 304 /** Whether L1/L2 descriptor response is delayed in timing mode */ 305 bool delayed; 306 307 TableWalker *tableWalker; 308 309 void doL1Descriptor(); 310 void doL2Descriptor(); 311 312 std::string name() const {return tableWalker->name();} 313 }; 314 315 316 /** Queue of requests that need processing first level translation */ 317 std::list<WalkerState *> stateQueueL1; 318 319 /** Queue of requests that have passed first level translation and 320 * require an additional level. */ 321 std::list<WalkerState *> stateQueueL2; 322 323 /** Queue of requests that have passed are waiting because the walker is 324 * currently busy. */ 325 std::list<WalkerState *> pendingQueue;; 326 327 328 /** Port to issue translation requests from */ 329 DmaPort *port; 330 331 /** TLB that is initiating these table walks */ 332 TLB *tlb; 333 334 /** Cached copy of the sctlr as it existed when translation began */ 335 SCTLR sctlr; 336 337 WalkerState *currState; 338 339 /** If a timing translation is currently in progress */ 340 bool pending; 341 342 public: 343 typedef ArmTableWalkerParams Params; 344 TableWalker(const Params *p); 345 virtual ~TableWalker(); 346 347 const Params * 348 params() const 349 { 350 return dynamic_cast<const Params *>(_params); 351 } 352 353 virtual unsigned int drain(Event *de) { panic("write me\n"); } 354 virtual Port *getPort(const std::string &if_name, int idx = -1); 355 356 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 357 TLB::Translation *_trans, bool timing); 358 359 void setTlb(TLB *_tlb) { tlb = _tlb; } 360 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 361 uint8_t texcb, bool s); 362 363 private: 364 365 void doL1Descriptor(); 366 void doL1DescriptorWrapper(); 367 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 368 369 void doL2Descriptor(); 370 void doL2DescriptorWrapper(); 371 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 372 373 Fault processWalk(); 374 void processWalkWrapper(); 375 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 376 377 void nextWalk(ThreadContext *tc); 378}; 379 380 381} // namespace ArmISA 382 383#endif //__ARCH_ARM_TABLE_WALKER_HH__ 384 385