table_walker.hh revision 7404:bfc74724914e 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __ARCH_ARM_TABLE_WALKER_HH__
41#define __ARCH_ARM_TABLE_WALKER_HH__
42
43#include "arch/arm/miscregs.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/mem_object.hh"
46#include "mem/request.hh"
47#include "mem/request.hh"
48#include "params/ArmTableWalker.hh"
49#include "sim/faults.hh"
50#include "sim/eventq.hh"
51
52class DmaPort;
53class ThreadContext;
54
55namespace ArmISA {
56class Translation;
57class TLB;
58
59class TableWalker : public MemObject
60{
61  protected:
62    struct L1Descriptor {
63        /** Type of page table entry ARM DDI 0406B: B3-8*/
64        enum EntryType {
65            Ignore,
66            PageTable,
67            Section,
68            Reserved
69        };
70
71        uint32_t data;
72
73        EntryType type() const
74        {
75            return (EntryType)(data & 0x3);
76        }
77
78        /** Is the page a Supersection (16MB)?*/
79        bool supersection() const
80        {
81            return bits(data, 18);
82        }
83
84        /** Return the physcal address of the entry, bits in position*/
85        Addr paddr() const
86        {
87            if (supersection())
88                panic("Super sections not implemented\n");
89            return mbits(data, 31,20);
90        }
91
92        /** Return the physical frame, bits shifted right */
93        Addr pfn() const
94        {
95            if (supersection())
96                panic("Super sections not implemented\n");
97            return bits(data, 31,20);
98        }
99
100        /** Is the translation global (no asid used)? */
101        bool global() const
102        {
103            return bits(data, 17);
104        }
105
106        /** Is the translation not allow execution? */
107        bool xn() const
108        {
109            return bits(data, 17);
110        }
111
112        /** Three bit access protection flags */
113        uint8_t ap() const
114        {
115            return (bits(data, 15) << 2) | bits(data,11,10);
116        }
117
118        /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
119        uint8_t domain() const
120        {
121            return bits(data,8,5);
122        }
123
124        /** Address of L2 descriptor if it exists */
125        Addr l2Addr() const
126        {
127            return mbits(data, 31,10);
128        }
129
130        /** Memory region attributes: ARM DDI 0406B: B3-32 */
131        uint8_t texcb() const
132        {
133            return bits(data, 2) | bits(data,3) << 1 | bits(data, 12, 14) << 2;
134        }
135
136    };
137
138    /** Level 2 page table descriptor */
139    struct L2Descriptor {
140
141        uint32_t data;
142
143        /** Is the entry invalid */
144        bool invalid() const
145        {
146            return bits(data, 1,0) == 0;;
147        }
148
149        /** What is the size of the mapping? */
150        bool large() const
151        {
152            return bits(data, 1) == 0;
153        }
154
155        /** Is execution allowed on this mapping? */
156        bool xn() const
157        {
158            return large() ? bits(data, 15) : bits(data, 0);
159        }
160
161        /** Is the translation global (no asid used)? */
162        bool global() const
163        {
164            return !bits(data, 11);
165        }
166
167        /** Three bit access protection flags */
168        uint8_t ap() const
169        {
170           return bits(data, 5, 4) | (bits(data, 9) << 2);
171        }
172
173        /** Memory region attributes: ARM DDI 0406B: B3-32 */
174        uint8_t texcb() const
175        {
176            return large() ?
177                (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 12, 14) << 2)) :
178                (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 6, 8) << 2));
179        }
180
181        /** Return the physical frame, bits shifted right */
182        Addr pfn() const
183        {
184            return large() ? bits(data, 31, 16) : bits(data, 31, 12);
185        }
186
187    };
188
189    /** Port to issue translation requests from */
190    DmaPort *port;
191
192    /** TLB that is initiating these table walks */
193    TLB *tlb;
194
195    /** Thread context that we're doing the walk for */
196    ThreadContext *tc;
197
198    /** Request that is currently being serviced */
199    RequestPtr req;
200
201    /** Context ID that we're servicing the request under */
202    uint8_t contextId;
203
204    /** Translation state for delayed requests */
205    TLB::Translation *transState;
206
207    /** The fault that we are going to return */
208    Fault fault;
209
210    /** The virtual address that is being translated */
211    Addr vaddr;
212
213    /** Cached copy of the sctlr as it existed when translation began */
214    SCTLR sctlr;
215
216    /** Cached copy of the cpsr as it existed when the translation began */
217    CPSR cpsr;
218
219    /** Width of the base address held in TTRB0 */
220    uint32_t N;
221
222    /** If the access is a write */
223    bool isWrite;
224
225    /** If the access is not from user mode */
226    bool isPriv;
227
228    /** If the access is a fetch (for execution, and no-exec) must be checked?*/
229    bool isFetch;
230
231    /** If the mode is timing or atomic */
232    bool timing;
233
234    L1Descriptor l1Desc;
235    L2Descriptor l2Desc;
236
237  public:
238    typedef ArmTableWalkerParams Params;
239    TableWalker(const Params *p);
240    virtual ~TableWalker();
241
242    const Params *
243    params() const
244    {
245        return dynamic_cast<const Params *>(_params);
246    }
247
248    virtual unsigned int drain(Event *de) { panic("write me\n"); }
249    virtual Port *getPort(const std::string &if_name, int idx = -1);
250
251    Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
252            TLB::Translation *_trans, bool timing);
253
254    void setTlb(TLB *_tlb) { tlb = _tlb; }
255
256  private:
257    void memAttrs(TlbEntry &te, uint8_t texcb);
258
259    void doL1Descriptor();
260    EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent;
261
262    void doL2Descriptor();
263    EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent;
264
265
266};
267
268
269} // namespace ArmISA
270
271#endif //__ARCH_ARM_TABLE_WALKER_HH__
272
273