table_walker.hh revision 7578 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __ARCH_ARM_TABLE_WALKER_HH__
41#define __ARCH_ARM_TABLE_WALKER_HH__
42
43#include <list>
44
45#include "arch/arm/miscregs.hh"
46#include "arch/arm/tlb.hh"
47#include "mem/mem_object.hh"
48#include "mem/request.hh"
49#include "mem/request.hh"
50#include "params/ArmTableWalker.hh"
51#include "sim/faults.hh"
52#include "sim/eventq.hh"
53
54class DmaPort;
55class ThreadContext;
56
57namespace ArmISA {
58class Translation;
59class TLB;
60
61class TableWalker : public MemObject
62{
63  protected:
64    struct L1Descriptor {
65        /** Type of page table entry ARM DDI 0406B: B3-8*/
66        enum EntryType {
67            Ignore,
68            PageTable,
69            Section,
70            Reserved
71        };
72
73        /** The raw bits of the entry */
74        uint32_t data;
75
76        /** This entry has been modified (access flag set) and needs to be
77         * written back to memory */
78        bool _dirty;
79
80        EntryType type() const
81        {
82            return (EntryType)(data & 0x3);
83        }
84
85        /** Is the page a Supersection (16MB)?*/
86        bool supersection() const
87        {
88            return bits(data, 18);
89        }
90
91        /** Return the physcal address of the entry, bits in position*/
92        Addr paddr() const
93        {
94            if (supersection())
95                panic("Super sections not implemented\n");
96            return mbits(data, 31,20);
97        }
98
99        /** Return the physical frame, bits shifted right */
100        Addr pfn() const
101        {
102            if (supersection())
103                panic("Super sections not implemented\n");
104            return bits(data, 31,20);
105        }
106
107        /** Is the translation global (no asid used)? */
108        bool global() const
109        {
110            return bits(data, 4);
111        }
112
113        /** Is the translation not allow execution? */
114        bool xn() const
115        {
116            return bits(data, 17);
117        }
118
119        /** Three bit access protection flags */
120        uint8_t ap() const
121        {
122            return (bits(data, 15) << 2) | bits(data,11,10);
123        }
124
125        /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
126        uint8_t domain() const
127        {
128            return bits(data,8,5);
129        }
130
131        /** Address of L2 descriptor if it exists */
132        Addr l2Addr() const
133        {
134            return mbits(data, 31,10);
135        }
136
137        /** Memory region attributes: ARM DDI 0406B: B3-32.
138         * These bits are largly ignored by M5 and only used to
139         * provide the illusion that the memory system cares about
140         * anything but cachable vs. uncachable.
141         */
142        uint8_t texcb() const
143        {
144            return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
145        }
146
147        /** If the section is shareable. See texcb() comment. */
148        bool shareable() const
149        {
150            return bits(data, 16);
151        }
152
153        /** Set access flag that this entry has been touched. Mark
154         * the entry as requiring a writeback, in the future.
155         */
156        void setAp0()
157        {
158            data |= 1 << 10;
159            _dirty = true;
160        }
161
162        /** This entry needs to be written back to memory */
163        bool dirty() const
164        {
165            return _dirty;
166        }
167    };
168
169    /** Level 2 page table descriptor */
170    struct L2Descriptor {
171
172        /** The raw bits of the entry. */
173        uint32_t data;
174
175        /** This entry has been modified (access flag set) and needs to be
176         * written back to memory */
177        bool _dirty;
178
179        /** Is the entry invalid */
180        bool invalid() const
181        {
182            return bits(data, 1,0) == 0;;
183        }
184
185        /** What is the size of the mapping? */
186        bool large() const
187        {
188            return bits(data, 1) == 0;
189        }
190
191        /** Is execution allowed on this mapping? */
192        bool xn() const
193        {
194            return large() ? bits(data, 15) : bits(data, 0);
195        }
196
197        /** Is the translation global (no asid used)? */
198        bool global() const
199        {
200            return !bits(data, 11);
201        }
202
203        /** Three bit access protection flags */
204        uint8_t ap() const
205        {
206           return bits(data, 5, 4) | (bits(data, 9) << 2);
207        }
208
209        /** Memory region attributes: ARM DDI 0406B: B3-32 */
210        uint8_t texcb() const
211        {
212            return large() ?
213                (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
214                (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
215        }
216
217        /** Return the physical frame, bits shifted right */
218        Addr pfn() const
219        {
220            return large() ? bits(data, 31, 16) : bits(data, 31, 12);
221        }
222
223        /** If the section is shareable. See texcb() comment. */
224        bool shareable() const
225        {
226            return bits(data, 10);
227        }
228
229        /** Set access flag that this entry has been touched. Mark
230         * the entry as requiring a writeback, in the future.
231         */
232        void setAp0()
233        {
234            data |= 1 << 4;
235            _dirty = true;
236        }
237
238        /** This entry needs to be written back to memory */
239        bool dirty() const
240        {
241            return _dirty;
242        }
243
244    };
245
246    struct WalkerState //: public SimObject
247    {
248        /** Thread context that we're doing the walk for */
249        ThreadContext *tc;
250
251        /** Request that is currently being serviced */
252        RequestPtr req;
253
254        /** Context ID that we're servicing the request under */
255        uint8_t contextId;
256
257        /** Translation state for delayed requests */
258        TLB::Translation *transState;
259
260        /** The fault that we are going to return */
261        Fault fault;
262
263        /** The virtual address that is being translated */
264        Addr vaddr;
265
266        /** Cached copy of the sctlr as it existed when translation began */
267        SCTLR sctlr;
268
269        /** Cached copy of the cpsr as it existed when the translation began */
270        CPSR cpsr;
271
272        /** Width of the base address held in TTRB0 */
273        uint32_t N;
274
275        /** If the access is a write */
276        bool isWrite;
277
278        /** If the access is not from user mode */
279        bool isPriv;
280
281        /** If the access is a fetch (for execution, and no-exec) must be checked?*/
282        bool isFetch;
283
284        /** If the mode is timing or atomic */
285        bool timing;
286
287        /** Save mode for use in delayed response */
288        BaseTLB::Mode mode;
289
290        L1Descriptor l1Desc;
291        L2Descriptor l2Desc;
292
293        /** Whether L1/L2 descriptor response is delayed in timing mode */
294        bool delayed;
295
296        TableWalker *tableWalker;
297
298        void doL1Descriptor();
299        void doL2Descriptor();
300
301        std::string name() const {return tableWalker->name();}
302    };
303
304
305    std::list<WalkerState *> stateQueue;
306
307    /** Port to issue translation requests from */
308    DmaPort *port;
309
310    /** TLB that is initiating these table walks */
311    TLB *tlb;
312
313    /** Cached copy of the sctlr as it existed when translation began */
314    SCTLR sctlr;
315
316    WalkerState *currState;
317
318  public:
319    typedef ArmTableWalkerParams Params;
320    TableWalker(const Params *p);
321    virtual ~TableWalker();
322
323    const Params *
324    params() const
325    {
326        return dynamic_cast<const Params *>(_params);
327    }
328
329    virtual unsigned int drain(Event *de) { panic("write me\n"); }
330    virtual Port *getPort(const std::string &if_name, int idx = -1);
331
332    Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
333            TLB::Translation *_trans, bool timing);
334
335    void setTlb(TLB *_tlb) { tlb = _tlb; }
336    void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
337                  uint8_t texcb, bool s);
338
339  private:
340
341    void doL1Descriptor();
342    void doL1DescriptorWrapper();
343    EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
344
345    void doL2Descriptor();
346    void doL2DescriptorWrapper();
347    EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
348
349
350};
351
352
353} // namespace ArmISA
354
355#endif //__ARCH_ARM_TABLE_WALKER_HH__
356
357