table_walker.hh revision 10324
17404SAli.Saidi@ARM.com/* 210324SCurtis.Dunham@arm.com * Copyright (c) 2010-2014 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 407404SAli.Saidi@ARM.com 417404SAli.Saidi@ARM.com#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 427404SAli.Saidi@ARM.com#define __ARCH_ARM_TABLE_WALKER_HH__ 437404SAli.Saidi@ARM.com 447578Sdam.sunwoo@arm.com#include <list> 457578Sdam.sunwoo@arm.com 467404SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 4710037SARM gem5 Developers#include "arch/arm/system.hh" 487404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 499016Sandreas.hansson@arm.com#include "dev/dma_device.hh" 507404SAli.Saidi@ARM.com#include "mem/mem_object.hh" 517404SAli.Saidi@ARM.com#include "mem/request.hh" 527404SAli.Saidi@ARM.com#include "params/ArmTableWalker.hh" 537404SAli.Saidi@ARM.com#include "sim/eventq.hh" 547878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 557404SAli.Saidi@ARM.com 567404SAli.Saidi@ARM.comclass ThreadContext; 577404SAli.Saidi@ARM.com 587404SAli.Saidi@ARM.comnamespace ArmISA { 597404SAli.Saidi@ARM.comclass Translation; 607404SAli.Saidi@ARM.comclass TLB; 6110037SARM gem5 Developersclass Stage2MMU; 627404SAli.Saidi@ARM.com 637404SAli.Saidi@ARM.comclass TableWalker : public MemObject 647404SAli.Saidi@ARM.com{ 657694SAli.Saidi@ARM.com public: 6610037SARM gem5 Developers class WalkerState; 6710037SARM gem5 Developers 6810037SARM gem5 Developers class DescriptorBase { 6910037SARM gem5 Developers public: 7010037SARM gem5 Developers /** Current lookup level for this descriptor */ 7110037SARM gem5 Developers LookupLevel lookupLevel; 7210037SARM gem5 Developers 7310037SARM gem5 Developers virtual Addr pfn() const = 0; 7410037SARM gem5 Developers virtual TlbEntry::DomainType domain() const = 0; 7510037SARM gem5 Developers virtual bool xn() const = 0; 7610037SARM gem5 Developers virtual uint8_t ap() const = 0; 7710037SARM gem5 Developers virtual bool global(WalkerState *currState) const = 0; 7810037SARM gem5 Developers virtual uint8_t offsetBits() const = 0; 7910037SARM gem5 Developers virtual bool secure(bool have_security, WalkerState *currState) const = 0; 8010037SARM gem5 Developers virtual std::string dbgHeader() const = 0; 8110037SARM gem5 Developers virtual uint64_t getRawData() const = 0; 8210037SARM gem5 Developers virtual uint8_t texcb() const 8310037SARM gem5 Developers { 8410037SARM gem5 Developers panic("texcb() not implemented for this class\n"); 8510037SARM gem5 Developers } 8610037SARM gem5 Developers virtual bool shareable() const 8710037SARM gem5 Developers { 8810037SARM gem5 Developers panic("shareable() not implemented for this class\n"); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers }; 9110037SARM gem5 Developers 9210037SARM gem5 Developers class L1Descriptor : public DescriptorBase { 9310037SARM gem5 Developers public: 947404SAli.Saidi@ARM.com /** Type of page table entry ARM DDI 0406B: B3-8*/ 957404SAli.Saidi@ARM.com enum EntryType { 967404SAli.Saidi@ARM.com Ignore, 977404SAli.Saidi@ARM.com PageTable, 987404SAli.Saidi@ARM.com Section, 997404SAli.Saidi@ARM.com Reserved 1007404SAli.Saidi@ARM.com }; 1017404SAli.Saidi@ARM.com 1027436Sdam.sunwoo@arm.com /** The raw bits of the entry */ 1037404SAli.Saidi@ARM.com uint32_t data; 1047404SAli.Saidi@ARM.com 1057436Sdam.sunwoo@arm.com /** This entry has been modified (access flag set) and needs to be 1067436Sdam.sunwoo@arm.com * written back to memory */ 1077436Sdam.sunwoo@arm.com bool _dirty; 1087436Sdam.sunwoo@arm.com 10910037SARM gem5 Developers /** Default ctor */ 11010037SARM gem5 Developers L1Descriptor() 11110037SARM gem5 Developers { 11210037SARM gem5 Developers lookupLevel = L1; 11310037SARM gem5 Developers } 11410037SARM gem5 Developers 11510037SARM gem5 Developers virtual uint64_t getRawData() const 11610037SARM gem5 Developers { 11710037SARM gem5 Developers return (data); 11810037SARM gem5 Developers } 11910037SARM gem5 Developers 12010037SARM gem5 Developers virtual std::string dbgHeader() const 12110037SARM gem5 Developers { 12210037SARM gem5 Developers return "Inserting Section Descriptor into TLB\n"; 12310037SARM gem5 Developers } 12410037SARM gem5 Developers 12510037SARM gem5 Developers virtual uint8_t offsetBits() const 12610037SARM gem5 Developers { 12710037SARM gem5 Developers return 20; 12810037SARM gem5 Developers } 12910037SARM gem5 Developers 1307404SAli.Saidi@ARM.com EntryType type() const 1317404SAli.Saidi@ARM.com { 1327404SAli.Saidi@ARM.com return (EntryType)(data & 0x3); 1337404SAli.Saidi@ARM.com } 1347404SAli.Saidi@ARM.com 1357404SAli.Saidi@ARM.com /** Is the page a Supersection (16MB)?*/ 1367404SAli.Saidi@ARM.com bool supersection() const 1377404SAli.Saidi@ARM.com { 1387404SAli.Saidi@ARM.com return bits(data, 18); 1397404SAli.Saidi@ARM.com } 1407404SAli.Saidi@ARM.com 1417404SAli.Saidi@ARM.com /** Return the physcal address of the entry, bits in position*/ 1427404SAli.Saidi@ARM.com Addr paddr() const 1437404SAli.Saidi@ARM.com { 1447404SAli.Saidi@ARM.com if (supersection()) 1457404SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1467946SGiacomo.Gabrielli@arm.com return mbits(data, 31, 20); 1477404SAli.Saidi@ARM.com } 1487694SAli.Saidi@ARM.com /** Return the physcal address of the entry, bits in position*/ 1497694SAli.Saidi@ARM.com Addr paddr(Addr va) const 1507694SAli.Saidi@ARM.com { 1517694SAli.Saidi@ARM.com if (supersection()) 1527694SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1537946SGiacomo.Gabrielli@arm.com return mbits(data, 31, 20) | mbits(va, 19, 0); 1547694SAli.Saidi@ARM.com } 1557694SAli.Saidi@ARM.com 1567404SAli.Saidi@ARM.com 1577404SAli.Saidi@ARM.com /** Return the physical frame, bits shifted right */ 1587404SAli.Saidi@ARM.com Addr pfn() const 1597404SAli.Saidi@ARM.com { 1607404SAli.Saidi@ARM.com if (supersection()) 1617404SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1627946SGiacomo.Gabrielli@arm.com return bits(data, 31, 20); 1637404SAli.Saidi@ARM.com } 1647404SAli.Saidi@ARM.com 1657404SAli.Saidi@ARM.com /** Is the translation global (no asid used)? */ 16610037SARM gem5 Developers bool global(WalkerState *currState) const 1677404SAli.Saidi@ARM.com { 16810037SARM gem5 Developers return !bits(data, 17); 1697404SAli.Saidi@ARM.com } 1707404SAli.Saidi@ARM.com 1717404SAli.Saidi@ARM.com /** Is the translation not allow execution? */ 1727404SAli.Saidi@ARM.com bool xn() const 1737404SAli.Saidi@ARM.com { 1747608SGene.Wu@arm.com return bits(data, 4); 1757404SAli.Saidi@ARM.com } 1767404SAli.Saidi@ARM.com 1777404SAli.Saidi@ARM.com /** Three bit access protection flags */ 1787404SAli.Saidi@ARM.com uint8_t ap() const 1797404SAli.Saidi@ARM.com { 1807946SGiacomo.Gabrielli@arm.com return (bits(data, 15) << 2) | bits(data, 11, 10); 1817404SAli.Saidi@ARM.com } 1827404SAli.Saidi@ARM.com 1837404SAli.Saidi@ARM.com /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 18410037SARM gem5 Developers TlbEntry::DomainType domain() const 1857404SAli.Saidi@ARM.com { 18610037SARM gem5 Developers return static_cast<TlbEntry::DomainType>(bits(data, 8, 5)); 1877404SAli.Saidi@ARM.com } 1887404SAli.Saidi@ARM.com 1897404SAli.Saidi@ARM.com /** Address of L2 descriptor if it exists */ 1907404SAli.Saidi@ARM.com Addr l2Addr() const 1917404SAli.Saidi@ARM.com { 1927946SGiacomo.Gabrielli@arm.com return mbits(data, 31, 10); 1937404SAli.Saidi@ARM.com } 1947404SAli.Saidi@ARM.com 1957436Sdam.sunwoo@arm.com /** Memory region attributes: ARM DDI 0406B: B3-32. 1967436Sdam.sunwoo@arm.com * These bits are largly ignored by M5 and only used to 1977436Sdam.sunwoo@arm.com * provide the illusion that the memory system cares about 1987436Sdam.sunwoo@arm.com * anything but cachable vs. uncachable. 1997436Sdam.sunwoo@arm.com */ 2007404SAli.Saidi@ARM.com uint8_t texcb() const 2017404SAli.Saidi@ARM.com { 2027946SGiacomo.Gabrielli@arm.com return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 2037404SAli.Saidi@ARM.com } 2047404SAli.Saidi@ARM.com 2057436Sdam.sunwoo@arm.com /** If the section is shareable. See texcb() comment. */ 2067436Sdam.sunwoo@arm.com bool shareable() const 2077436Sdam.sunwoo@arm.com { 2087436Sdam.sunwoo@arm.com return bits(data, 16); 2097436Sdam.sunwoo@arm.com } 2107436Sdam.sunwoo@arm.com 2117436Sdam.sunwoo@arm.com /** Set access flag that this entry has been touched. Mark 2127436Sdam.sunwoo@arm.com * the entry as requiring a writeback, in the future. 2137436Sdam.sunwoo@arm.com */ 2147436Sdam.sunwoo@arm.com void setAp0() 2157436Sdam.sunwoo@arm.com { 2167436Sdam.sunwoo@arm.com data |= 1 << 10; 2177436Sdam.sunwoo@arm.com _dirty = true; 2187436Sdam.sunwoo@arm.com } 2197436Sdam.sunwoo@arm.com 2207436Sdam.sunwoo@arm.com /** This entry needs to be written back to memory */ 2217436Sdam.sunwoo@arm.com bool dirty() const 2227436Sdam.sunwoo@arm.com { 2237436Sdam.sunwoo@arm.com return _dirty; 2247436Sdam.sunwoo@arm.com } 22510037SARM gem5 Developers 22610037SARM gem5 Developers /** 22710037SARM gem5 Developers * Returns true if this entry targets the secure physical address 22810037SARM gem5 Developers * map. 22910037SARM gem5 Developers */ 23010037SARM gem5 Developers bool secure(bool have_security, WalkerState *currState) const 23110037SARM gem5 Developers { 23210037SARM gem5 Developers if (have_security) { 23310037SARM gem5 Developers if (type() == PageTable) 23410037SARM gem5 Developers return !bits(data, 3); 23510037SARM gem5 Developers else 23610037SARM gem5 Developers return !bits(data, 19); 23710037SARM gem5 Developers } 23810037SARM gem5 Developers return false; 23910037SARM gem5 Developers } 2407404SAli.Saidi@ARM.com }; 2417404SAli.Saidi@ARM.com 2427404SAli.Saidi@ARM.com /** Level 2 page table descriptor */ 24310037SARM gem5 Developers class L2Descriptor : public DescriptorBase { 24410037SARM gem5 Developers public: 2457436Sdam.sunwoo@arm.com /** The raw bits of the entry. */ 24610037SARM gem5 Developers uint32_t data; 24710037SARM gem5 Developers L1Descriptor *l1Parent; 2487404SAli.Saidi@ARM.com 2497436Sdam.sunwoo@arm.com /** This entry has been modified (access flag set) and needs to be 2507436Sdam.sunwoo@arm.com * written back to memory */ 2517436Sdam.sunwoo@arm.com bool _dirty; 2527436Sdam.sunwoo@arm.com 25310037SARM gem5 Developers /** Default ctor */ 25410037SARM gem5 Developers L2Descriptor() 25510037SARM gem5 Developers { 25610037SARM gem5 Developers lookupLevel = L2; 25710037SARM gem5 Developers } 25810037SARM gem5 Developers 25910037SARM gem5 Developers L2Descriptor(L1Descriptor &parent) : l1Parent(&parent) 26010037SARM gem5 Developers { 26110037SARM gem5 Developers lookupLevel = L2; 26210037SARM gem5 Developers } 26310037SARM gem5 Developers 26410037SARM gem5 Developers virtual uint64_t getRawData() const 26510037SARM gem5 Developers { 26610037SARM gem5 Developers return (data); 26710037SARM gem5 Developers } 26810037SARM gem5 Developers 26910037SARM gem5 Developers virtual std::string dbgHeader() const 27010037SARM gem5 Developers { 27110037SARM gem5 Developers return "Inserting L2 Descriptor into TLB\n"; 27210037SARM gem5 Developers } 27310037SARM gem5 Developers 27410037SARM gem5 Developers virtual TlbEntry::DomainType domain() const 27510037SARM gem5 Developers { 27610037SARM gem5 Developers return l1Parent->domain(); 27710037SARM gem5 Developers } 27810037SARM gem5 Developers 27910037SARM gem5 Developers bool secure(bool have_security, WalkerState *currState) const 28010037SARM gem5 Developers { 28110037SARM gem5 Developers return l1Parent->secure(have_security, currState); 28210037SARM gem5 Developers } 28310037SARM gem5 Developers 28410037SARM gem5 Developers virtual uint8_t offsetBits() const 28510037SARM gem5 Developers { 28610037SARM gem5 Developers return large() ? 16 : 12; 28710037SARM gem5 Developers } 28810037SARM gem5 Developers 2897404SAli.Saidi@ARM.com /** Is the entry invalid */ 2907404SAli.Saidi@ARM.com bool invalid() const 2917404SAli.Saidi@ARM.com { 2927946SGiacomo.Gabrielli@arm.com return bits(data, 1, 0) == 0; 2937404SAli.Saidi@ARM.com } 2947404SAli.Saidi@ARM.com 2957404SAli.Saidi@ARM.com /** What is the size of the mapping? */ 2967404SAli.Saidi@ARM.com bool large() const 2977404SAli.Saidi@ARM.com { 2987404SAli.Saidi@ARM.com return bits(data, 1) == 0; 2997404SAli.Saidi@ARM.com } 3007404SAli.Saidi@ARM.com 3017404SAli.Saidi@ARM.com /** Is execution allowed on this mapping? */ 3027404SAli.Saidi@ARM.com bool xn() const 3037404SAli.Saidi@ARM.com { 3047404SAli.Saidi@ARM.com return large() ? bits(data, 15) : bits(data, 0); 3057404SAli.Saidi@ARM.com } 3067404SAli.Saidi@ARM.com 3077404SAli.Saidi@ARM.com /** Is the translation global (no asid used)? */ 30810037SARM gem5 Developers bool global(WalkerState *currState) const 3097404SAli.Saidi@ARM.com { 3107404SAli.Saidi@ARM.com return !bits(data, 11); 3117404SAli.Saidi@ARM.com } 3127404SAli.Saidi@ARM.com 3137404SAli.Saidi@ARM.com /** Three bit access protection flags */ 3147404SAli.Saidi@ARM.com uint8_t ap() const 3157404SAli.Saidi@ARM.com { 3167404SAli.Saidi@ARM.com return bits(data, 5, 4) | (bits(data, 9) << 2); 3177404SAli.Saidi@ARM.com } 3187404SAli.Saidi@ARM.com 3197404SAli.Saidi@ARM.com /** Memory region attributes: ARM DDI 0406B: B3-32 */ 3207404SAli.Saidi@ARM.com uint8_t texcb() const 3217404SAli.Saidi@ARM.com { 3227404SAli.Saidi@ARM.com return large() ? 3237946SGiacomo.Gabrielli@arm.com (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 3247946SGiacomo.Gabrielli@arm.com (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 3257404SAli.Saidi@ARM.com } 3267404SAli.Saidi@ARM.com 3277404SAli.Saidi@ARM.com /** Return the physical frame, bits shifted right */ 3287404SAli.Saidi@ARM.com Addr pfn() const 3297404SAli.Saidi@ARM.com { 3307404SAli.Saidi@ARM.com return large() ? bits(data, 31, 16) : bits(data, 31, 12); 3317404SAli.Saidi@ARM.com } 3327404SAli.Saidi@ARM.com 3337694SAli.Saidi@ARM.com /** Return complete physical address given a VA */ 3347694SAli.Saidi@ARM.com Addr paddr(Addr va) const 3357694SAli.Saidi@ARM.com { 3367694SAli.Saidi@ARM.com if (large()) 3377694SAli.Saidi@ARM.com return mbits(data, 31, 16) | mbits(va, 15, 0); 3387694SAli.Saidi@ARM.com else 3397694SAli.Saidi@ARM.com return mbits(data, 31, 12) | mbits(va, 11, 0); 3407694SAli.Saidi@ARM.com } 3417694SAli.Saidi@ARM.com 3427436Sdam.sunwoo@arm.com /** If the section is shareable. See texcb() comment. */ 3437436Sdam.sunwoo@arm.com bool shareable() const 3447436Sdam.sunwoo@arm.com { 3457436Sdam.sunwoo@arm.com return bits(data, 10); 3467436Sdam.sunwoo@arm.com } 3477436Sdam.sunwoo@arm.com 3487436Sdam.sunwoo@arm.com /** Set access flag that this entry has been touched. Mark 3497436Sdam.sunwoo@arm.com * the entry as requiring a writeback, in the future. 3507436Sdam.sunwoo@arm.com */ 3517436Sdam.sunwoo@arm.com void setAp0() 3527436Sdam.sunwoo@arm.com { 3537436Sdam.sunwoo@arm.com data |= 1 << 4; 3547436Sdam.sunwoo@arm.com _dirty = true; 3557436Sdam.sunwoo@arm.com } 3567436Sdam.sunwoo@arm.com 3577436Sdam.sunwoo@arm.com /** This entry needs to be written back to memory */ 3587436Sdam.sunwoo@arm.com bool dirty() const 3597436Sdam.sunwoo@arm.com { 3607436Sdam.sunwoo@arm.com return _dirty; 3617436Sdam.sunwoo@arm.com } 3627436Sdam.sunwoo@arm.com 3637404SAli.Saidi@ARM.com }; 3647404SAli.Saidi@ARM.com 36510324SCurtis.Dunham@arm.com // Granule sizes for AArch64 long descriptors 36610324SCurtis.Dunham@arm.com enum GrainSize { 36710324SCurtis.Dunham@arm.com Grain4KB = 12, 36810324SCurtis.Dunham@arm.com Grain16KB = 14, 36910324SCurtis.Dunham@arm.com Grain64KB = 16, 37010324SCurtis.Dunham@arm.com ReservedGrain = 0 37110324SCurtis.Dunham@arm.com }; 37210324SCurtis.Dunham@arm.com 37310037SARM gem5 Developers /** Long-descriptor format (LPAE) */ 37410037SARM gem5 Developers class LongDescriptor : public DescriptorBase { 37510037SARM gem5 Developers public: 37610037SARM gem5 Developers /** Descriptor type */ 37710037SARM gem5 Developers enum EntryType { 37810037SARM gem5 Developers Invalid, 37910037SARM gem5 Developers Table, 38010037SARM gem5 Developers Block, 38110037SARM gem5 Developers Page 38210037SARM gem5 Developers }; 38310037SARM gem5 Developers 38410037SARM gem5 Developers /** The raw bits of the entry */ 38510037SARM gem5 Developers uint64_t data; 38610037SARM gem5 Developers 38710037SARM gem5 Developers /** This entry has been modified (access flag set) and needs to be 38810037SARM gem5 Developers * written back to memory */ 38910037SARM gem5 Developers bool _dirty; 39010037SARM gem5 Developers 39110037SARM gem5 Developers virtual uint64_t getRawData() const 39210037SARM gem5 Developers { 39310037SARM gem5 Developers return (data); 39410037SARM gem5 Developers } 39510037SARM gem5 Developers 39610037SARM gem5 Developers virtual std::string dbgHeader() const 39710037SARM gem5 Developers { 39810037SARM gem5 Developers if (type() == LongDescriptor::Page) { 39910037SARM gem5 Developers assert(lookupLevel == L3); 40010037SARM gem5 Developers return "Inserting Page descriptor into TLB\n"; 40110037SARM gem5 Developers } else { 40210037SARM gem5 Developers assert(lookupLevel < L3); 40310037SARM gem5 Developers return "Inserting Block descriptor into TLB\n"; 40410037SARM gem5 Developers } 40510037SARM gem5 Developers } 40610037SARM gem5 Developers 40710037SARM gem5 Developers /** 40810037SARM gem5 Developers * Returns true if this entry targets the secure physical address 40910037SARM gem5 Developers * map. 41010037SARM gem5 Developers */ 41110037SARM gem5 Developers bool secure(bool have_security, WalkerState *currState) const 41210037SARM gem5 Developers { 41310037SARM gem5 Developers assert(type() == Block || type() == Page); 41410037SARM gem5 Developers return have_security && (currState->secureLookup && !bits(data, 5)); 41510037SARM gem5 Developers } 41610037SARM gem5 Developers 41710037SARM gem5 Developers /** True if the current lookup is performed in AArch64 state */ 41810037SARM gem5 Developers bool aarch64; 41910037SARM gem5 Developers 42010037SARM gem5 Developers /** Width of the granule size in bits */ 42110324SCurtis.Dunham@arm.com GrainSize grainSize; 42210037SARM gem5 Developers 42310037SARM gem5 Developers /** Return the descriptor type */ 42410037SARM gem5 Developers EntryType type() const 42510037SARM gem5 Developers { 42610037SARM gem5 Developers switch (bits(data, 1, 0)) { 42710037SARM gem5 Developers case 0x1: 42810037SARM gem5 Developers // In AArch64 blocks are not allowed at L0 for the 4 KB granule 42910324SCurtis.Dunham@arm.com // and at L1 for 16/64 KB granules 43010324SCurtis.Dunham@arm.com if (grainSize > Grain4KB) 43110037SARM gem5 Developers return lookupLevel == L2 ? Block : Invalid; 43210037SARM gem5 Developers return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block; 43310037SARM gem5 Developers case 0x3: 43410037SARM gem5 Developers return lookupLevel == L3 ? Page : Table; 43510037SARM gem5 Developers default: 43610037SARM gem5 Developers return Invalid; 43710037SARM gem5 Developers } 43810037SARM gem5 Developers } 43910037SARM gem5 Developers 44010037SARM gem5 Developers /** Return the bit width of the page/block offset */ 44110037SARM gem5 Developers uint8_t offsetBits() const 44210037SARM gem5 Developers { 44310324SCurtis.Dunham@arm.com if (type() == Block) { 44410324SCurtis.Dunham@arm.com switch (grainSize) { 44510324SCurtis.Dunham@arm.com case Grain4KB: 44610324SCurtis.Dunham@arm.com return lookupLevel == L1 ? 30 /* 1 GB */ 44710324SCurtis.Dunham@arm.com : 21 /* 2 MB */; 44810324SCurtis.Dunham@arm.com case Grain16KB: 44910324SCurtis.Dunham@arm.com return 25 /* 32 MB */; 45010324SCurtis.Dunham@arm.com case Grain64KB: 45110324SCurtis.Dunham@arm.com return 29 /* 512 MB */; 45210324SCurtis.Dunham@arm.com default: 45310324SCurtis.Dunham@arm.com panic("Invalid AArch64 VM granule size\n"); 45410324SCurtis.Dunham@arm.com } 45510324SCurtis.Dunham@arm.com } else if (type() == Page) { 45610324SCurtis.Dunham@arm.com switch (grainSize) { 45710324SCurtis.Dunham@arm.com case Grain4KB: 45810324SCurtis.Dunham@arm.com case Grain16KB: 45910324SCurtis.Dunham@arm.com case Grain64KB: 46010324SCurtis.Dunham@arm.com return grainSize; /* enum -> uint okay */ 46110324SCurtis.Dunham@arm.com default: 46210324SCurtis.Dunham@arm.com panic("Invalid AArch64 VM granule size\n"); 46310324SCurtis.Dunham@arm.com } 46410037SARM gem5 Developers } else { 46510324SCurtis.Dunham@arm.com panic("AArch64 page table entry must be block or page\n"); 46610037SARM gem5 Developers } 46710037SARM gem5 Developers } 46810037SARM gem5 Developers 46910037SARM gem5 Developers /** Return the physical frame, bits shifted right */ 47010037SARM gem5 Developers Addr pfn() const 47110037SARM gem5 Developers { 47210037SARM gem5 Developers if (aarch64) 47310037SARM gem5 Developers return bits(data, 47, offsetBits()); 47410037SARM gem5 Developers return bits(data, 39, offsetBits()); 47510037SARM gem5 Developers } 47610037SARM gem5 Developers 47710037SARM gem5 Developers /** Return the complete physical address given a VA */ 47810037SARM gem5 Developers Addr paddr(Addr va) const 47910037SARM gem5 Developers { 48010037SARM gem5 Developers int n = offsetBits(); 48110037SARM gem5 Developers if (aarch64) 48210037SARM gem5 Developers return mbits(data, 47, n) | mbits(va, n - 1, 0); 48310037SARM gem5 Developers return mbits(data, 39, n) | mbits(va, n - 1, 0); 48410037SARM gem5 Developers } 48510037SARM gem5 Developers 48610037SARM gem5 Developers /** Return the physical address of the entry */ 48710037SARM gem5 Developers Addr paddr() const 48810037SARM gem5 Developers { 48910037SARM gem5 Developers if (aarch64) 49010037SARM gem5 Developers return mbits(data, 47, offsetBits()); 49110037SARM gem5 Developers return mbits(data, 39, offsetBits()); 49210037SARM gem5 Developers } 49310037SARM gem5 Developers 49410037SARM gem5 Developers /** Return the address of the next page table */ 49510037SARM gem5 Developers Addr nextTableAddr() const 49610037SARM gem5 Developers { 49710037SARM gem5 Developers assert(type() == Table); 49810037SARM gem5 Developers if (aarch64) 49910037SARM gem5 Developers return mbits(data, 47, grainSize); 50010037SARM gem5 Developers else 50110037SARM gem5 Developers return mbits(data, 39, 12); 50210037SARM gem5 Developers } 50310037SARM gem5 Developers 50410037SARM gem5 Developers /** Return the address of the next descriptor */ 50510037SARM gem5 Developers Addr nextDescAddr(Addr va) const 50610037SARM gem5 Developers { 50710037SARM gem5 Developers assert(type() == Table); 50810037SARM gem5 Developers Addr pa = 0; 50910037SARM gem5 Developers if (aarch64) { 51010037SARM gem5 Developers int stride = grainSize - 3; 51110037SARM gem5 Developers int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize; 51210037SARM gem5 Developers int va_hi = va_lo + stride - 1; 51310037SARM gem5 Developers pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3); 51410037SARM gem5 Developers } else { 51510037SARM gem5 Developers if (lookupLevel == L1) 51610037SARM gem5 Developers pa = nextTableAddr() | (bits(va, 29, 21) << 3); 51710037SARM gem5 Developers else // lookupLevel == L2 51810037SARM gem5 Developers pa = nextTableAddr() | (bits(va, 20, 12) << 3); 51910037SARM gem5 Developers } 52010037SARM gem5 Developers return pa; 52110037SARM gem5 Developers } 52210037SARM gem5 Developers 52310037SARM gem5 Developers /** Is execution allowed on this mapping? */ 52410037SARM gem5 Developers bool xn() const 52510037SARM gem5 Developers { 52610037SARM gem5 Developers assert(type() == Block || type() == Page); 52710037SARM gem5 Developers return bits(data, 54); 52810037SARM gem5 Developers } 52910037SARM gem5 Developers 53010037SARM gem5 Developers /** Is privileged execution allowed on this mapping? (LPAE only) */ 53110037SARM gem5 Developers bool pxn() const 53210037SARM gem5 Developers { 53310037SARM gem5 Developers assert(type() == Block || type() == Page); 53410037SARM gem5 Developers return bits(data, 53); 53510037SARM gem5 Developers } 53610037SARM gem5 Developers 53710037SARM gem5 Developers /** Contiguous hint bit. */ 53810037SARM gem5 Developers bool contiguousHint() const 53910037SARM gem5 Developers { 54010037SARM gem5 Developers assert(type() == Block || type() == Page); 54110037SARM gem5 Developers return bits(data, 52); 54210037SARM gem5 Developers } 54310037SARM gem5 Developers 54410037SARM gem5 Developers /** Is the translation global (no asid used)? */ 54510037SARM gem5 Developers bool global(WalkerState *currState) const 54610037SARM gem5 Developers { 54710037SARM gem5 Developers assert(currState && (type() == Block || type() == Page)); 54810037SARM gem5 Developers if (!currState->aarch64 && (currState->isSecure && 54910037SARM gem5 Developers !currState->secureLookup)) { 55010037SARM gem5 Developers return false; // ARM ARM issue C B3.6.3 55110037SARM gem5 Developers } else if (currState->aarch64) { 55210037SARM gem5 Developers if (currState->el == EL2 || currState->el == EL3) { 55310037SARM gem5 Developers return true; // By default translations are treated as global 55410037SARM gem5 Developers // in AArch64 EL2 and EL3 55510037SARM gem5 Developers } else if (currState->isSecure && !currState->secureLookup) { 55610037SARM gem5 Developers return false; 55710037SARM gem5 Developers } 55810037SARM gem5 Developers } 55910037SARM gem5 Developers return !bits(data, 11); 56010037SARM gem5 Developers } 56110037SARM gem5 Developers 56210037SARM gem5 Developers /** Returns true if the access flag (AF) is set. */ 56310037SARM gem5 Developers bool af() const 56410037SARM gem5 Developers { 56510037SARM gem5 Developers assert(type() == Block || type() == Page); 56610037SARM gem5 Developers return bits(data, 10); 56710037SARM gem5 Developers } 56810037SARM gem5 Developers 56910037SARM gem5 Developers /** 2-bit shareability field */ 57010037SARM gem5 Developers uint8_t sh() const 57110037SARM gem5 Developers { 57210037SARM gem5 Developers assert(type() == Block || type() == Page); 57310037SARM gem5 Developers return bits(data, 9, 8); 57410037SARM gem5 Developers } 57510037SARM gem5 Developers 57610037SARM gem5 Developers /** 2-bit access protection flags */ 57710037SARM gem5 Developers uint8_t ap() const 57810037SARM gem5 Developers { 57910037SARM gem5 Developers assert(type() == Block || type() == Page); 58010037SARM gem5 Developers // Long descriptors only support the AP[2:1] scheme 58110037SARM gem5 Developers return bits(data, 7, 6); 58210037SARM gem5 Developers } 58310037SARM gem5 Developers 58410037SARM gem5 Developers /** Read/write access protection flag */ 58510037SARM gem5 Developers bool rw() const 58610037SARM gem5 Developers { 58710037SARM gem5 Developers assert(type() == Block || type() == Page); 58810037SARM gem5 Developers return !bits(data, 7); 58910037SARM gem5 Developers } 59010037SARM gem5 Developers 59110037SARM gem5 Developers /** User/privileged level access protection flag */ 59210037SARM gem5 Developers bool user() const 59310037SARM gem5 Developers { 59410037SARM gem5 Developers assert(type() == Block || type() == Page); 59510037SARM gem5 Developers return bits(data, 6); 59610037SARM gem5 Developers } 59710037SARM gem5 Developers 59810037SARM gem5 Developers /** Return the AP bits as compatible with the AP[2:0] format. Utility 59910037SARM gem5 Developers * function used to simplify the code in the TLB for performing 60010037SARM gem5 Developers * permission checks. */ 60110037SARM gem5 Developers static uint8_t ap(bool rw, bool user) 60210037SARM gem5 Developers { 60310037SARM gem5 Developers return ((!rw) << 2) | (user << 1); 60410037SARM gem5 Developers } 60510037SARM gem5 Developers 60610037SARM gem5 Developers TlbEntry::DomainType domain() const 60710037SARM gem5 Developers { 60810037SARM gem5 Developers // Long-desc. format only supports Client domain 60910037SARM gem5 Developers assert(type() == Block || type() == Page); 61010037SARM gem5 Developers return TlbEntry::DomainType::Client; 61110037SARM gem5 Developers } 61210037SARM gem5 Developers 61310037SARM gem5 Developers /** Attribute index */ 61410037SARM gem5 Developers uint8_t attrIndx() const 61510037SARM gem5 Developers { 61610037SARM gem5 Developers assert(type() == Block || type() == Page); 61710037SARM gem5 Developers return bits(data, 4, 2); 61810037SARM gem5 Developers } 61910037SARM gem5 Developers 62010037SARM gem5 Developers /** Memory attributes, only used by stage 2 translations */ 62110037SARM gem5 Developers uint8_t memAttr() const 62210037SARM gem5 Developers { 62310037SARM gem5 Developers assert(type() == Block || type() == Page); 62410037SARM gem5 Developers return bits(data, 5, 2); 62510037SARM gem5 Developers } 62610037SARM gem5 Developers 62710037SARM gem5 Developers /** Set access flag that this entry has been touched. Mark the entry as 62810037SARM gem5 Developers * requiring a writeback, in the future. */ 62910037SARM gem5 Developers void setAf() 63010037SARM gem5 Developers { 63110037SARM gem5 Developers data |= 1 << 10; 63210037SARM gem5 Developers _dirty = true; 63310037SARM gem5 Developers } 63410037SARM gem5 Developers 63510037SARM gem5 Developers /** This entry needs to be written back to memory */ 63610037SARM gem5 Developers bool dirty() const 63710037SARM gem5 Developers { 63810037SARM gem5 Developers return _dirty; 63910037SARM gem5 Developers } 64010037SARM gem5 Developers 64110037SARM gem5 Developers /** Whether the subsequent levels of lookup are secure */ 64210037SARM gem5 Developers bool secureTable() const 64310037SARM gem5 Developers { 64410037SARM gem5 Developers assert(type() == Table); 64510037SARM gem5 Developers return !bits(data, 63); 64610037SARM gem5 Developers } 64710037SARM gem5 Developers 64810037SARM gem5 Developers /** Two bit access protection flags for subsequent levels of lookup */ 64910037SARM gem5 Developers uint8_t apTable() const 65010037SARM gem5 Developers { 65110037SARM gem5 Developers assert(type() == Table); 65210037SARM gem5 Developers return bits(data, 62, 61); 65310037SARM gem5 Developers } 65410037SARM gem5 Developers 65510037SARM gem5 Developers /** R/W protection flag for subsequent levels of lookup */ 65610037SARM gem5 Developers uint8_t rwTable() const 65710037SARM gem5 Developers { 65810037SARM gem5 Developers assert(type() == Table); 65910037SARM gem5 Developers return !bits(data, 62); 66010037SARM gem5 Developers } 66110037SARM gem5 Developers 66210037SARM gem5 Developers /** User/privileged mode protection flag for subsequent levels of 66310037SARM gem5 Developers * lookup */ 66410037SARM gem5 Developers uint8_t userTable() const 66510037SARM gem5 Developers { 66610037SARM gem5 Developers assert(type() == Table); 66710037SARM gem5 Developers return !bits(data, 61); 66810037SARM gem5 Developers } 66910037SARM gem5 Developers 67010037SARM gem5 Developers /** Is execution allowed on subsequent lookup levels? */ 67110037SARM gem5 Developers bool xnTable() const 67210037SARM gem5 Developers { 67310037SARM gem5 Developers assert(type() == Table); 67410037SARM gem5 Developers return bits(data, 60); 67510037SARM gem5 Developers } 67610037SARM gem5 Developers 67710037SARM gem5 Developers /** Is privileged execution allowed on subsequent lookup levels? */ 67810037SARM gem5 Developers bool pxnTable() const 67910037SARM gem5 Developers { 68010037SARM gem5 Developers assert(type() == Table); 68110037SARM gem5 Developers return bits(data, 59); 68210037SARM gem5 Developers } 68310037SARM gem5 Developers }; 68410037SARM gem5 Developers 68510037SARM gem5 Developers class WalkerState 68610037SARM gem5 Developers { 68710037SARM gem5 Developers public: 68810037SARM gem5 Developers /** Thread context that we're doing the walk for */ 68910037SARM gem5 Developers ThreadContext *tc; 69010037SARM gem5 Developers 69110037SARM gem5 Developers /** If the access is performed in AArch64 state */ 69210037SARM gem5 Developers bool aarch64; 69310037SARM gem5 Developers 69410037SARM gem5 Developers /** Current exception level */ 69510037SARM gem5 Developers ExceptionLevel el; 69610037SARM gem5 Developers 69710037SARM gem5 Developers /** Current physical address range in bits */ 69810037SARM gem5 Developers int physAddrRange; 69910037SARM gem5 Developers 70010037SARM gem5 Developers /** Request that is currently being serviced */ 70110037SARM gem5 Developers RequestPtr req; 70210037SARM gem5 Developers 70310037SARM gem5 Developers /** ASID that we're servicing the request under */ 70410037SARM gem5 Developers uint16_t asid; 70510037SARM gem5 Developers uint8_t vmid; 70610037SARM gem5 Developers bool isHyp; 70710037SARM gem5 Developers 70810037SARM gem5 Developers /** Translation state for delayed requests */ 70910037SARM gem5 Developers TLB::Translation *transState; 71010037SARM gem5 Developers 71110037SARM gem5 Developers /** The fault that we are going to return */ 71210037SARM gem5 Developers Fault fault; 71310037SARM gem5 Developers 71410037SARM gem5 Developers /** The virtual address that is being translated with tagging removed.*/ 71510037SARM gem5 Developers Addr vaddr; 71610037SARM gem5 Developers 71710037SARM gem5 Developers /** The virtual address that is being translated */ 71810037SARM gem5 Developers Addr vaddr_tainted; 71910037SARM gem5 Developers 72010037SARM gem5 Developers /** Cached copy of the sctlr as it existed when translation began */ 72110037SARM gem5 Developers SCTLR sctlr; 72210037SARM gem5 Developers 72310037SARM gem5 Developers /** Cached copy of the scr as it existed when translation began */ 72410037SARM gem5 Developers SCR scr; 72510037SARM gem5 Developers 72610037SARM gem5 Developers /** Cached copy of the cpsr as it existed when translation began */ 72710037SARM gem5 Developers CPSR cpsr; 72810037SARM gem5 Developers 72910324SCurtis.Dunham@arm.com /** Cached copy of ttbcr/tcr as it existed when translation began */ 73010324SCurtis.Dunham@arm.com union { 73110324SCurtis.Dunham@arm.com TTBCR ttbcr; // AArch32 translations 73210324SCurtis.Dunham@arm.com TCR tcr; // AArch64 translations 73310324SCurtis.Dunham@arm.com }; 73410037SARM gem5 Developers 73510037SARM gem5 Developers /** Cached copy of the htcr as it existed when translation began. */ 73610037SARM gem5 Developers HTCR htcr; 73710037SARM gem5 Developers 73810037SARM gem5 Developers /** Cached copy of the htcr as it existed when translation began. */ 73910037SARM gem5 Developers HCR hcr; 74010037SARM gem5 Developers 74110037SARM gem5 Developers /** Cached copy of the vtcr as it existed when translation began. */ 74210037SARM gem5 Developers VTCR_t vtcr; 74310037SARM gem5 Developers 74410037SARM gem5 Developers /** If the access is a write */ 74510037SARM gem5 Developers bool isWrite; 74610037SARM gem5 Developers 74710037SARM gem5 Developers /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 74810037SARM gem5 Developers bool isFetch; 74910037SARM gem5 Developers 75010037SARM gem5 Developers /** If the access comes from the secure state. */ 75110037SARM gem5 Developers bool isSecure; 75210037SARM gem5 Developers 75310037SARM gem5 Developers /** Helper variables used to implement hierarchical access permissions 75410037SARM gem5 Developers * when the long-desc. format is used (LPAE only) */ 75510037SARM gem5 Developers bool secureLookup; 75610037SARM gem5 Developers bool rwTable; 75710037SARM gem5 Developers bool userTable; 75810037SARM gem5 Developers bool xnTable; 75910037SARM gem5 Developers bool pxnTable; 76010037SARM gem5 Developers 76110037SARM gem5 Developers /** Flag indicating if a second stage of lookup is required */ 76210037SARM gem5 Developers bool stage2Req; 76310037SARM gem5 Developers 76410037SARM gem5 Developers /** Indicates whether the translation has been passed onto the second 76510037SARM gem5 Developers * stage mmu, and no more work is required from the first stage. 76610037SARM gem5 Developers */ 76710037SARM gem5 Developers bool doingStage2; 76810037SARM gem5 Developers 76910037SARM gem5 Developers /** A pointer to the stage 2 translation that's in progress */ 77010037SARM gem5 Developers TLB::Translation *stage2Tran; 77110037SARM gem5 Developers 77210037SARM gem5 Developers /** If the mode is timing or atomic */ 77310037SARM gem5 Developers bool timing; 77410037SARM gem5 Developers 77510037SARM gem5 Developers /** If the atomic mode should be functional */ 77610037SARM gem5 Developers bool functional; 77710037SARM gem5 Developers 77810037SARM gem5 Developers /** Save mode for use in delayed response */ 77910037SARM gem5 Developers BaseTLB::Mode mode; 78010037SARM gem5 Developers 78110037SARM gem5 Developers /** The translation type that has been requested */ 78210037SARM gem5 Developers TLB::ArmTranslationType tranType; 78310037SARM gem5 Developers 78410037SARM gem5 Developers /** Short-format descriptors */ 78510037SARM gem5 Developers L1Descriptor l1Desc; 78610037SARM gem5 Developers L2Descriptor l2Desc; 78710037SARM gem5 Developers 78810037SARM gem5 Developers /** Long-format descriptor (LPAE and AArch64) */ 78910037SARM gem5 Developers LongDescriptor longDesc; 79010037SARM gem5 Developers 79110037SARM gem5 Developers /** Whether the response is delayed in timing mode due to additional 79210037SARM gem5 Developers * lookups */ 79310037SARM gem5 Developers bool delayed; 79410037SARM gem5 Developers 79510037SARM gem5 Developers TableWalker *tableWalker; 79610037SARM gem5 Developers 79710037SARM gem5 Developers void doL1Descriptor(); 79810037SARM gem5 Developers void doL2Descriptor(); 79910037SARM gem5 Developers 80010037SARM gem5 Developers void doLongDescriptor(); 80110037SARM gem5 Developers 80210037SARM gem5 Developers WalkerState(); 80310037SARM gem5 Developers 80410037SARM gem5 Developers std::string name() const { return tableWalker->name(); } 80510037SARM gem5 Developers }; 80610037SARM gem5 Developers 8079015Sandreas.hansson@arm.com protected: 8089015Sandreas.hansson@arm.com 8099015Sandreas.hansson@arm.com /** 8109015Sandreas.hansson@arm.com * A snooping DMA port that currently does nothing besides 8119015Sandreas.hansson@arm.com * extending the DMA port to accept snoops without complaining. 8129015Sandreas.hansson@arm.com */ 8139015Sandreas.hansson@arm.com class SnoopingDmaPort : public DmaPort 8149015Sandreas.hansson@arm.com { 8159015Sandreas.hansson@arm.com 8169015Sandreas.hansson@arm.com protected: 8179015Sandreas.hansson@arm.com 8189015Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt) 8199015Sandreas.hansson@arm.com { } 8209015Sandreas.hansson@arm.com 8219015Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt) 8229015Sandreas.hansson@arm.com { return 0; } 8239015Sandreas.hansson@arm.com 8249015Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt) 8259015Sandreas.hansson@arm.com { } 8269015Sandreas.hansson@arm.com 8279015Sandreas.hansson@arm.com virtual bool isSnooping() const { return true; } 8289015Sandreas.hansson@arm.com 8299015Sandreas.hansson@arm.com public: 8309015Sandreas.hansson@arm.com 8319015Sandreas.hansson@arm.com /** 8329015Sandreas.hansson@arm.com * A snooping DMA port merely calls the construtor of the DMA 8339015Sandreas.hansson@arm.com * port. 8349015Sandreas.hansson@arm.com */ 8359165Sandreas.hansson@arm.com SnoopingDmaPort(MemObject *dev, System *s) : 8369165Sandreas.hansson@arm.com DmaPort(dev, s) 8379015Sandreas.hansson@arm.com { } 8389015Sandreas.hansson@arm.com }; 8399015Sandreas.hansson@arm.com 84010037SARM gem5 Developers /** Queues of requests for all the different lookup levels */ 84110037SARM gem5 Developers std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS]; 8427439Sdam.sunwoo@arm.com 8437728SAli.Saidi@ARM.com /** Queue of requests that have passed are waiting because the walker is 8447728SAli.Saidi@ARM.com * currently busy. */ 8458902Sandreas.hansson@arm.com std::list<WalkerState *> pendingQueue; 8467728SAli.Saidi@ARM.com 8477728SAli.Saidi@ARM.com 8487404SAli.Saidi@ARM.com /** Port to issue translation requests from */ 8499015Sandreas.hansson@arm.com SnoopingDmaPort port; 8507404SAli.Saidi@ARM.com 8519152Satgutier@umich.edu /** If we're draining keep the drain event around until we're drained */ 8529342SAndreas.Sandberg@arm.com DrainManager *drainManager; 8539152Satgutier@umich.edu 85410037SARM gem5 Developers /** The MMU to forward second stage look upts to */ 85510037SARM gem5 Developers Stage2MMU *stage2Mmu; 85610037SARM gem5 Developers 85710037SARM gem5 Developers /** Indicates whether this table walker is part of the stage 2 mmu */ 85810037SARM gem5 Developers const bool isStage2; 85910037SARM gem5 Developers 8607404SAli.Saidi@ARM.com /** TLB that is initiating these table walks */ 8617404SAli.Saidi@ARM.com TLB *tlb; 8627404SAli.Saidi@ARM.com 8637404SAli.Saidi@ARM.com /** Cached copy of the sctlr as it existed when translation began */ 8647404SAli.Saidi@ARM.com SCTLR sctlr; 8657404SAli.Saidi@ARM.com 8667439Sdam.sunwoo@arm.com WalkerState *currState; 8677437Sdam.sunwoo@arm.com 8687728SAli.Saidi@ARM.com /** If a timing translation is currently in progress */ 8697728SAli.Saidi@ARM.com bool pending; 8707728SAli.Saidi@ARM.com 8718832SAli.Saidi@ARM.com /** Request id for requests generated by this walker */ 8728832SAli.Saidi@ARM.com MasterID masterId; 8738832SAli.Saidi@ARM.com 8749258SAli.Saidi@ARM.com /** The number of walks belonging to squashed instructions that can be 8759258SAli.Saidi@ARM.com * removed from the pendingQueue per cycle. */ 8769258SAli.Saidi@ARM.com unsigned numSquashable; 8779258SAli.Saidi@ARM.com 87810037SARM gem5 Developers /** Cached copies of system-level properties */ 87910037SARM gem5 Developers bool haveSecurity; 88010037SARM gem5 Developers bool _haveLPAE; 88110037SARM gem5 Developers bool _haveVirtualization; 88210037SARM gem5 Developers uint8_t physAddrRange; 88310037SARM gem5 Developers bool _haveLargeAsid64; 88410037SARM gem5 Developers ArmSystem *armSys; 88510037SARM gem5 Developers 8867404SAli.Saidi@ARM.com public: 88710037SARM gem5 Developers typedef ArmTableWalkerParams Params; 8887404SAli.Saidi@ARM.com TableWalker(const Params *p); 8897404SAli.Saidi@ARM.com virtual ~TableWalker(); 8907404SAli.Saidi@ARM.com 8917404SAli.Saidi@ARM.com const Params * 8927404SAli.Saidi@ARM.com params() const 8937404SAli.Saidi@ARM.com { 8947404SAli.Saidi@ARM.com return dynamic_cast<const Params *>(_params); 8957404SAli.Saidi@ARM.com } 8967404SAli.Saidi@ARM.com 89710037SARM gem5 Developers bool haveLPAE() const { return _haveLPAE; } 89810037SARM gem5 Developers bool haveVirtualization() const { return _haveVirtualization; } 89910037SARM gem5 Developers bool haveLargeAsid64() const { return _haveLargeAsid64; } 9009152Satgutier@umich.edu /** Checks if all state is cleared and if so, completes drain */ 9019152Satgutier@umich.edu void completeDrain(); 9029342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 90310037SARM gem5 Developers virtual void drainResume(); 9049294Sandreas.hansson@arm.com virtual BaseMasterPort& getMasterPort(const std::string &if_name, 9059294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 9067404SAli.Saidi@ARM.com 90710037SARM gem5 Developers /** 90810037SARM gem5 Developers * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to 90910037SARM gem5 Developers * access the table walker port through the TLB so that it can 91010037SARM gem5 Developers * orchestrate staged translations. 91110037SARM gem5 Developers * 91210037SARM gem5 Developers * @return Our DMA port 91310037SARM gem5 Developers */ 91410037SARM gem5 Developers DmaPort& getWalkerPort() { return port; } 91510037SARM gem5 Developers 91610037SARM gem5 Developers Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, 91710037SARM gem5 Developers bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, 91810037SARM gem5 Developers bool timing, bool functional, bool secure, 91910037SARM gem5 Developers TLB::ArmTranslationType tranType); 9207404SAli.Saidi@ARM.com 9217404SAli.Saidi@ARM.com void setTlb(TLB *_tlb) { tlb = _tlb; } 92210037SARM gem5 Developers TLB* getTlb() { return tlb; } 92310037SARM gem5 Developers void setMMU(Stage2MMU *m) { stage2Mmu = m; } 9247439Sdam.sunwoo@arm.com void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 9257439Sdam.sunwoo@arm.com uint8_t texcb, bool s); 92610037SARM gem5 Developers void memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 92710037SARM gem5 Developers LongDescriptor &lDescriptor); 92810037SARM gem5 Developers void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 92910037SARM gem5 Developers uint8_t sh); 93010037SARM gem5 Developers 93110037SARM gem5 Developers static LookupLevel toLookupLevel(uint8_t lookup_level_as_int); 9327404SAli.Saidi@ARM.com 9337404SAli.Saidi@ARM.com private: 9347404SAli.Saidi@ARM.com 9357404SAli.Saidi@ARM.com void doL1Descriptor(); 9367437Sdam.sunwoo@arm.com void doL1DescriptorWrapper(); 93710037SARM gem5 Developers EventWrapper<TableWalker, 93810037SARM gem5 Developers &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 9397404SAli.Saidi@ARM.com 9407404SAli.Saidi@ARM.com void doL2Descriptor(); 9417437Sdam.sunwoo@arm.com void doL2DescriptorWrapper(); 94210037SARM gem5 Developers EventWrapper<TableWalker, 94310037SARM gem5 Developers &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 94410037SARM gem5 Developers 94510037SARM gem5 Developers void doLongDescriptor(); 94610037SARM gem5 Developers 94710037SARM gem5 Developers void doL0LongDescriptorWrapper(); 94810037SARM gem5 Developers EventWrapper<TableWalker, 94910037SARM gem5 Developers &TableWalker::doL0LongDescriptorWrapper> doL0LongDescEvent; 95010037SARM gem5 Developers void doL1LongDescriptorWrapper(); 95110037SARM gem5 Developers EventWrapper<TableWalker, 95210037SARM gem5 Developers &TableWalker::doL1LongDescriptorWrapper> doL1LongDescEvent; 95310037SARM gem5 Developers void doL2LongDescriptorWrapper(); 95410037SARM gem5 Developers EventWrapper<TableWalker, 95510037SARM gem5 Developers &TableWalker::doL2LongDescriptorWrapper> doL2LongDescEvent; 95610037SARM gem5 Developers void doL3LongDescriptorWrapper(); 95710037SARM gem5 Developers EventWrapper<TableWalker, 95810037SARM gem5 Developers &TableWalker::doL3LongDescriptorWrapper> doL3LongDescEvent; 95910037SARM gem5 Developers 96010037SARM gem5 Developers void doLongDescriptorWrapper(LookupLevel curr_lookup_level); 96110037SARM gem5 Developers 96210037SARM gem5 Developers bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 96310037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 96410037SARM gem5 Developers void (TableWalker::*doDescriptor)()); 96510037SARM gem5 Developers 96610037SARM gem5 Developers void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor); 9677404SAli.Saidi@ARM.com 9687728SAli.Saidi@ARM.com Fault processWalk(); 96910037SARM gem5 Developers Fault processWalkLPAE(); 97010037SARM gem5 Developers static unsigned adjustTableSizeAArch64(unsigned tsz); 97110037SARM gem5 Developers /// Returns true if the address exceeds the range permitted by the 97210037SARM gem5 Developers /// system-wide setting or by the TCR_ELx IPS/PS setting 97310037SARM gem5 Developers static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange); 97410037SARM gem5 Developers Fault processWalkAArch64(); 9757728SAli.Saidi@ARM.com void processWalkWrapper(); 9767728SAli.Saidi@ARM.com EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 9777404SAli.Saidi@ARM.com 9787728SAli.Saidi@ARM.com void nextWalk(ThreadContext *tc); 9797404SAli.Saidi@ARM.com}; 9807404SAli.Saidi@ARM.com 9817404SAli.Saidi@ARM.com} // namespace ArmISA 9827404SAli.Saidi@ARM.com 9837404SAli.Saidi@ARM.com#endif //__ARCH_ARM_TABLE_WALKER_HH__ 9847404SAli.Saidi@ARM.com 985