table_walker.cc revision 7579
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#include "arch/arm/faults.hh" 41#include "arch/arm/table_walker.hh" 42#include "arch/arm/tlb.hh" 43#include "dev/io_device.hh" 44#include "cpu/thread_context.hh" 45 46using namespace ArmISA; 47 48TableWalker::TableWalker(const Params *p) 49 : MemObject(p), port(NULL), tlb(NULL), 50 currState(NULL), doL1DescEvent(this), doL2DescEvent(this) 51{ 52 sctlr = 0; 53} 54 55TableWalker::~TableWalker() 56{ 57 ; 58} 59 60 61unsigned int 62drain(Event *de) 63{ 64 panic("Not implemented\n"); 65} 66 67Port* 68TableWalker::getPort(const std::string &if_name, int idx) 69{ 70 if (if_name == "port") { 71 if (port != NULL) 72 fatal("%s: port already connected to %s", 73 name(), port->getPeer()->name()); 74 System *sys = params()->sys; 75 Tick minb = params()->min_backoff; 76 Tick maxb = params()->max_backoff; 77 port = new DmaPort(this, sys, minb, maxb); 78 return port; 79 } 80 return NULL; 81} 82 83Fault 84TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 85 TLB::Translation *_trans, bool _timing) 86{ 87 if (!currState) { 88 // For atomic mode, a new WalkerState instance should be only created 89 // once per TLB. For timing mode, a new instance is generated for every 90 // TLB miss. 91 DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 92 93 currState = new WalkerState(); 94 currState->tableWalker = this; 95 } 96 else if (_timing) { 97 panic("currState should always be empty in timing mode!\n"); 98 } 99 100 currState->tc = _tc; 101 currState->transState = _trans; 102 currState->req = _req; 103 currState->fault = NoFault; 104 currState->contextId = _cid; 105 currState->timing = _timing; 106 currState->mode = _mode; 107 108 /** @todo These should be cached or grabbed from cached copies in 109 the TLB, all these miscreg reads are expensive */ 110 currState->vaddr = currState->req->getVaddr() & ~PcModeMask; 111 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 112 sctlr = currState->sctlr; 113 currState->cpsr = currState->tc->readMiscReg(MISCREG_CPSR); 114 currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 115 116 currState->isFetch = (currState->mode == TLB::Execute); 117 currState->isWrite = (currState->mode == TLB::Write); 118 currState->isPriv = (currState->cpsr.mode != MODE_USER); 119 120 Addr ttbr = 0; 121 122 // If translation isn't enabled, we shouldn't be here 123 assert(currState->sctlr.m); 124 125 DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 126 currState->vaddr, currState->N, mbits(currState->vaddr, 31, 127 32-currState->N)); 128 129 if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 130 DPRINTF(TLB, " - Selecting TTBR0\n"); 131 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 132 } else { 133 DPRINTF(TLB, " - Selecting TTBR1\n"); 134 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 135 currState->N = 0; 136 } 137 138 Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 139 (bits(currState->vaddr,31-currState->N,20) << 2); 140 DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 141 142 143 // Trickbox address check 144 Fault f; 145 f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 146 currState->isFetch, currState->isWrite, 0, true); 147 if (f) { 148 if (currState->timing) { 149 currState->transState->finish(f, currState->req, 150 currState->tc, currState->mode); 151 currState = NULL; 152 } else { 153 currState->tc = NULL; 154 currState->req = NULL; 155 } 156 return f; 157 } 158 159 if (currState->timing) { 160 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 161 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0); 162 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 163 stateQueue.size()); 164 stateQueue.push_back(currState); 165 assert(stateQueue.size() < 5); 166 currState = NULL; 167 } else { 168 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 169 NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0); 170 doL1Descriptor(); 171 f = currState->fault; 172 } 173 174 return f; 175} 176 177void 178TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 179 uint8_t texcb, bool s) 180{ 181 // Note: tc and sctlr local variables are hiding tc and sctrl class 182 // variables 183 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 184 te.shareable = false; // default value 185 bool outer_shareable = false; 186 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 187 switch(texcb) { 188 case 0: // Stongly-ordered 189 te.nonCacheable = true; 190 te.mtype = TlbEntry::StronglyOrdered; 191 te.shareable = true; 192 te.innerAttrs = 1; 193 te.outerAttrs = 0; 194 break; 195 case 1: // Shareable Device 196 te.nonCacheable = true; 197 te.mtype = TlbEntry::Device; 198 te.shareable = true; 199 te.innerAttrs = 3; 200 te.outerAttrs = 0; 201 break; 202 case 2: // Outer and Inner Write-Through, no Write-Allocate 203 te.mtype = TlbEntry::Normal; 204 te.shareable = s; 205 te.innerAttrs = 6; 206 te.outerAttrs = bits(texcb, 1, 0); 207 break; 208 case 3: // Outer and Inner Write-Back, no Write-Allocate 209 te.mtype = TlbEntry::Normal; 210 te.shareable = s; 211 te.innerAttrs = 7; 212 te.outerAttrs = bits(texcb, 1, 0); 213 break; 214 case 4: // Outer and Inner Non-cacheable 215 te.nonCacheable = true; 216 te.mtype = TlbEntry::Normal; 217 te.shareable = s; 218 te.innerAttrs = 0; 219 te.outerAttrs = bits(texcb, 1, 0); 220 break; 221 case 5: // Reserved 222 panic("Reserved texcb value!\n"); 223 break; 224 case 6: // Implementation Defined 225 panic("Implementation-defined texcb value!\n"); 226 break; 227 case 7: // Outer and Inner Write-Back, Write-Allocate 228 te.mtype = TlbEntry::Normal; 229 te.shareable = s; 230 te.innerAttrs = 5; 231 te.outerAttrs = 1; 232 break; 233 case 8: // Non-shareable Device 234 te.nonCacheable = true; 235 te.mtype = TlbEntry::Device; 236 te.shareable = false; 237 te.innerAttrs = 3; 238 te.outerAttrs = 0; 239 break; 240 case 9 ... 15: // Reserved 241 panic("Reserved texcb value!\n"); 242 break; 243 case 16 ... 31: // Cacheable Memory 244 te.mtype = TlbEntry::Normal; 245 te.shareable = s; 246 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 247 te.nonCacheable = true; 248 te.innerAttrs = bits(texcb, 1, 0); 249 te.outerAttrs = bits(texcb, 3, 2); 250 break; 251 default: 252 panic("More than 32 states for 5 bits?\n"); 253 } 254 } else { 255 assert(tc); 256 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 257 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 258 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 259 uint8_t curr_tr, curr_ir, curr_or; 260 switch(bits(texcb, 2,0)) { 261 case 0: 262 curr_tr = prrr.tr0; 263 curr_ir = nmrr.ir0; 264 curr_or = nmrr.or0; 265 outer_shareable = (prrr.nos0 == 0); 266 break; 267 case 1: 268 curr_tr = prrr.tr1; 269 curr_ir = nmrr.ir1; 270 curr_or = nmrr.or1; 271 outer_shareable = (prrr.nos1 == 0); 272 break; 273 case 2: 274 curr_tr = prrr.tr2; 275 curr_ir = nmrr.ir2; 276 curr_or = nmrr.or2; 277 outer_shareable = (prrr.nos2 == 0); 278 break; 279 case 3: 280 curr_tr = prrr.tr3; 281 curr_ir = nmrr.ir3; 282 curr_or = nmrr.or3; 283 outer_shareable = (prrr.nos3 == 0); 284 break; 285 case 4: 286 curr_tr = prrr.tr4; 287 curr_ir = nmrr.ir4; 288 curr_or = nmrr.or4; 289 outer_shareable = (prrr.nos4 == 0); 290 break; 291 case 5: 292 curr_tr = prrr.tr5; 293 curr_ir = nmrr.ir5; 294 curr_or = nmrr.or5; 295 outer_shareable = (prrr.nos5 == 0); 296 break; 297 case 6: 298 panic("Imp defined type\n"); 299 case 7: 300 curr_tr = prrr.tr7; 301 curr_ir = nmrr.ir7; 302 curr_or = nmrr.or7; 303 outer_shareable = (prrr.nos7 == 0); 304 break; 305 } 306 307 switch(curr_tr) { 308 case 0: 309 DPRINTF(TLBVerbose, "StronglyOrdered\n"); 310 te.mtype = TlbEntry::StronglyOrdered; 311 te.nonCacheable = true; 312 te.innerAttrs = 1; 313 te.outerAttrs = 0; 314 te.shareable = true; 315 break; 316 case 1: 317 DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 318 prrr.ds1, prrr.ds0, s); 319 te.mtype = TlbEntry::Device; 320 te.nonCacheable = true; 321 te.innerAttrs = 3; 322 te.outerAttrs = 0; 323 if (prrr.ds1 && s) 324 te.shareable = true; 325 if (prrr.ds0 && !s) 326 te.shareable = true; 327 break; 328 case 2: 329 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 330 prrr.ns1, prrr.ns0, s); 331 te.mtype = TlbEntry::Normal; 332 if (prrr.ns1 && s) 333 te.shareable = true; 334 if (prrr.ns0 && !s) 335 te.shareable = true; 336 break; 337 case 3: 338 panic("Reserved type"); 339 } 340 341 if (te.mtype == TlbEntry::Normal){ 342 switch(curr_ir) { 343 case 0: 344 te.nonCacheable = true; 345 te.innerAttrs = 0; 346 break; 347 case 1: 348 te.innerAttrs = 5; 349 break; 350 case 2: 351 te.innerAttrs = 6; 352 break; 353 case 3: 354 te.innerAttrs = 7; 355 break; 356 } 357 358 switch(curr_or) { 359 case 0: 360 te.nonCacheable = true; 361 te.outerAttrs = 0; 362 break; 363 case 1: 364 te.outerAttrs = 1; 365 break; 366 case 2: 367 te.outerAttrs = 2; 368 break; 369 case 3: 370 te.outerAttrs = 3; 371 break; 372 } 373 } 374 } 375 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 376 outerAttrs: %d\n", 377 te.shareable, te.innerAttrs, te.outerAttrs); 378 379 /** Formatting for Physical Address Register (PAR) 380 * Only including lower bits (TLB info here) 381 * PAR: 382 * PA [31:12] 383 * Reserved [11] 384 * TLB info [10:1] 385 * NOS [10] (Not Outer Sharable) 386 * NS [9] (Non-Secure) 387 * -- [8] (Implementation Defined) 388 * SH [7] (Sharable) 389 * Inner[6:4](Inner memory attributes) 390 * Outer[3:2](Outer memory attributes) 391 * SS [1] (SuperSection) 392 * F [0] (Fault, Fault Status in [6:1] if faulted) 393 */ 394 te.attributes = ( 395 ((outer_shareable ? 0:1) << 10) | 396 // TODO: NS Bit 397 ((te.shareable ? 1:0) << 7) | 398 (te.innerAttrs << 4) | 399 (te.outerAttrs << 2) 400 // TODO: Supersection bit 401 // TODO: Fault bit 402 ); 403 404 405} 406 407void 408TableWalker::doL1Descriptor() 409{ 410 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 411 currState->vaddr, currState->l1Desc.data); 412 TlbEntry te; 413 414 switch (currState->l1Desc.type()) { 415 case L1Descriptor::Ignore: 416 case L1Descriptor::Reserved: 417 if (!currState->delayed) { 418 currState->tc = NULL; 419 currState->req = NULL; 420 } 421 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 422 if (currState->isFetch) 423 currState->fault = 424 new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 425 else 426 currState->fault = 427 new DataAbort(currState->vaddr, 0, currState->isWrite, 428 ArmFault::Translation0); 429 return; 430 case L1Descriptor::Section: 431 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 432 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 433 * enabled if set, do l1.Desc.setAp0() instead of generating 434 * AccessFlag0 435 */ 436 437 currState->fault = 438 new DataAbort(currState->vaddr, NULL, currState->isWrite, 439 ArmFault::AccessFlag0); 440 } 441 442 if (currState->l1Desc.supersection()) { 443 panic("Haven't implemented supersections\n"); 444 } 445 te.N = 20; 446 te.pfn = currState->l1Desc.pfn(); 447 te.size = (1<<te.N) - 1; 448 te.global = !currState->l1Desc.global(); 449 te.valid = true; 450 te.vpn = currState->vaddr >> te.N; 451 te.sNp = true; 452 te.xn = currState->l1Desc.xn(); 453 te.ap = currState->l1Desc.ap(); 454 te.domain = currState->l1Desc.domain(); 455 te.asid = currState->contextId; 456 memAttrs(currState->tc, te, currState->sctlr, 457 currState->l1Desc.texcb(), currState->l1Desc.shareable()); 458 459 DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 460 DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n", 461 te.N, te.pfn, te.size, te.global, te.valid); 462 DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n", 463 te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid); 464 DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 465 currState->l1Desc.domain(), currState->l1Desc.data, 466 (currState->l1Desc.data >> 5) & 0xF ); 467 468 if (!currState->timing) { 469 currState->tc = NULL; 470 currState->req = NULL; 471 } 472 tlb->insert(currState->vaddr, te); 473 474 return; 475 case L1Descriptor::PageTable: 476 Addr l2desc_addr; 477 l2desc_addr = currState->l1Desc.l2Addr() | 478 (bits(currState->vaddr, 19,12) << 2); 479 DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 480 l2desc_addr); 481 482 // Trickbox address check 483 currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 484 sizeof(uint32_t), currState->isFetch, currState->isWrite, 485 currState->l1Desc.domain(), false); 486 487 if (currState->fault) { 488 if (!currState->timing) { 489 currState->tc = NULL; 490 currState->req = NULL; 491 } 492 return; 493 } 494 495 496 if (currState->timing) { 497 currState->delayed = true; 498 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 499 &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 0); 500 } else { 501 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 502 NULL, (uint8_t*)&currState->l2Desc.data, 0); 503 doL2Descriptor(); 504 } 505 return; 506 default: 507 panic("A new type in a 2 bit field?\n"); 508 } 509} 510 511void 512TableWalker::doL2Descriptor() 513{ 514 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 515 currState->vaddr, currState->l2Desc.data); 516 TlbEntry te; 517 518 if (currState->l2Desc.invalid()) { 519 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 520 if (!currState->delayed) { 521 currState->tc = NULL; 522 currState->req = NULL; 523 } 524 if (currState->isFetch) 525 currState->fault = 526 new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 527 else 528 currState->fault = 529 new DataAbort(currState->vaddr, currState->l1Desc.domain(), 530 currState->isWrite, ArmFault::Translation1); 531 return; 532 } 533 534 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 535 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 536 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 537 */ 538 539 currState->fault = 540 new DataAbort(currState->vaddr, 0, currState->isWrite, 541 ArmFault::AccessFlag1); 542 543 } 544 545 if (currState->l2Desc.large()) { 546 te.N = 16; 547 te.pfn = currState->l2Desc.pfn(); 548 } else { 549 te.N = 12; 550 te.pfn = currState->l2Desc.pfn(); 551 } 552 553 te.valid = true; 554 te.size = (1 << te.N) - 1; 555 te.asid = currState->contextId; 556 te.sNp = false; 557 te.vpn = currState->vaddr >> te.N; 558 te.global = currState->l2Desc.global(); 559 te.xn = currState->l2Desc.xn(); 560 te.ap = currState->l2Desc.ap(); 561 te.domain = currState->l1Desc.domain(); 562 memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 563 currState->l2Desc.shareable()); 564 565 if (!currState->delayed) { 566 currState->tc = NULL; 567 currState->req = NULL; 568 } 569 tlb->insert(currState->vaddr, te); 570} 571 572void 573TableWalker::doL1DescriptorWrapper() 574{ 575 currState = stateQueue.front(); 576 currState->delayed = false; 577 578 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 579 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 580 581 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 582 doL1Descriptor(); 583 584 // Check if fault was generated 585 if (currState->fault != NoFault) { 586 currState->transState->finish(currState->fault, currState->req, 587 currState->tc, currState->mode); 588 589 currState->req = NULL; 590 currState->tc = NULL; 591 currState->delayed = false; 592 593 stateQueue.pop_front(); 594 } 595 else if (!currState->delayed) { 596 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 597 currState->fault = tlb->translateTiming(currState->req, currState->tc, 598 currState->transState, currState->mode); 599 600 currState->req = NULL; 601 currState->tc = NULL; 602 currState->delayed = false; 603 604 stateQueue.pop_front(); 605 } 606 currState = NULL; 607} 608 609void 610TableWalker::doL2DescriptorWrapper() 611{ 612 currState = stateQueue.front(); 613 assert(currState->delayed); 614 615 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 616 currState->vaddr); 617 doL2Descriptor(); 618 619 // Check if fault was generated 620 if (currState->fault != NoFault) { 621 currState->transState->finish(currState->fault, currState->req, 622 currState->tc, currState->mode); 623 } 624 else { 625 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 626 currState->fault = tlb->translateTiming(currState->req, currState->tc, 627 currState->transState, currState->mode); 628 } 629 630 currState->req = NULL; 631 currState->tc = NULL; 632 currState->delayed = false; 633 634 stateQueue.pop_front(); 635 currState = NULL; 636} 637 638ArmISA::TableWalker * 639ArmTableWalkerParams::create() 640{ 641 return new ArmISA::TableWalker(this); 642} 643 644