table_walker.cc revision 12738
1/* 2 * Copyright (c) 2010, 2012-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 * Giacomo Gabrielli 39 */ 40#include "arch/arm/table_walker.hh" 41 42#include <memory> 43 44#include "arch/arm/faults.hh" 45#include "arch/arm/stage2_mmu.hh" 46#include "arch/arm/system.hh" 47#include "arch/arm/tlb.hh" 48#include "cpu/base.hh" 49#include "cpu/thread_context.hh" 50#include "debug/Checkpoint.hh" 51#include "debug/Drain.hh" 52#include "debug/TLB.hh" 53#include "debug/TLBVerbose.hh" 54#include "dev/dma_device.hh" 55#include "sim/system.hh" 56 57using namespace ArmISA; 58 59TableWalker::TableWalker(const Params *p) 60 : MemObject(p), 61 stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 62 isStage2(p->is_stage2), tlb(NULL), 63 currState(NULL), pending(false), 64 numSquashable(p->num_squash_per_cycle), 65 pendingReqs(0), 66 pendingChangeTick(curTick()), 67 doL1DescEvent([this]{ doL1DescriptorWrapper(); }, name()), 68 doL2DescEvent([this]{ doL2DescriptorWrapper(); }, name()), 69 doL0LongDescEvent([this]{ doL0LongDescriptorWrapper(); }, name()), 70 doL1LongDescEvent([this]{ doL1LongDescriptorWrapper(); }, name()), 71 doL2LongDescEvent([this]{ doL2LongDescriptorWrapper(); }, name()), 72 doL3LongDescEvent([this]{ doL3LongDescriptorWrapper(); }, name()), 73 LongDescEventByLevel { &doL0LongDescEvent, &doL1LongDescEvent, 74 &doL2LongDescEvent, &doL3LongDescEvent }, 75 doProcessEvent([this]{ processWalkWrapper(); }, name()) 76{ 77 sctlr = 0; 78 79 // Cache system-level properties 80 if (FullSystem) { 81 ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 82 assert(armSys); 83 haveSecurity = armSys->haveSecurity(); 84 _haveLPAE = armSys->haveLPAE(); 85 _haveVirtualization = armSys->haveVirtualization(); 86 physAddrRange = armSys->physAddrRange(); 87 _haveLargeAsid64 = armSys->haveLargeAsid64(); 88 } else { 89 haveSecurity = _haveLPAE = _haveVirtualization = false; 90 _haveLargeAsid64 = false; 91 physAddrRange = 32; 92 } 93 94} 95 96TableWalker::~TableWalker() 97{ 98 ; 99} 100 101void 102TableWalker::setMMU(Stage2MMU *m, MasterID master_id) 103{ 104 stage2Mmu = m; 105 port = &m->getPort(); 106 masterId = master_id; 107} 108 109void 110TableWalker::init() 111{ 112 fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 113 fatal_if(!port, "Table walker must have a valid port\n"); 114 fatal_if(!tlb, "Table walker must have a valid TLB\n"); 115} 116 117BaseMasterPort& 118TableWalker::getMasterPort(const std::string &if_name, PortID idx) 119{ 120 if (if_name == "port") { 121 if (!isStage2) { 122 return *port; 123 } else { 124 fatal("Cannot access table walker port through stage-two walker\n"); 125 } 126 } 127 return MemObject::getMasterPort(if_name, idx); 128} 129 130TableWalker::WalkerState::WalkerState() : 131 tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 132 asid(0), vmid(0), isHyp(false), transState(nullptr), 133 vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 134 secureLookup(false), rwTable(false), userTable(false), xnTable(false), 135 pxnTable(false), stage2Req(false), 136 stage2Tran(nullptr), timing(false), functional(false), 137 mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 138 delayed(false), tableWalker(nullptr) 139{ 140} 141 142void 143TableWalker::completeDrain() 144{ 145 if (drainState() == DrainState::Draining && 146 stateQueues[L0].empty() && stateQueues[L1].empty() && 147 stateQueues[L2].empty() && stateQueues[L3].empty() && 148 pendingQueue.empty()) { 149 150 DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 151 signalDrainDone(); 152 } 153} 154 155DrainState 156TableWalker::drain() 157{ 158 bool state_queues_not_empty = false; 159 160 for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 161 if (!stateQueues[i].empty()) { 162 state_queues_not_empty = true; 163 break; 164 } 165 } 166 167 if (state_queues_not_empty || pendingQueue.size()) { 168 DPRINTF(Drain, "TableWalker not drained\n"); 169 return DrainState::Draining; 170 } else { 171 DPRINTF(Drain, "TableWalker free, no need to drain\n"); 172 return DrainState::Drained; 173 } 174} 175 176void 177TableWalker::drainResume() 178{ 179 if (params()->sys->isTimingMode() && currState) { 180 delete currState; 181 currState = NULL; 182 pendingChange(); 183 } 184} 185 186Fault 187TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 188 uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 189 TLB::Translation *_trans, bool _timing, bool _functional, 190 bool secure, TLB::ArmTranslationType tranType, 191 bool _stage2Req) 192{ 193 assert(!(_functional && _timing)); 194 ++statWalks; 195 196 WalkerState *savedCurrState = NULL; 197 198 if (!currState && !_functional) { 199 // For atomic mode, a new WalkerState instance should be only created 200 // once per TLB. For timing mode, a new instance is generated for every 201 // TLB miss. 202 DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 203 204 currState = new WalkerState(); 205 currState->tableWalker = this; 206 } else if (_functional) { 207 // If we are mixing functional mode with timing (or even 208 // atomic), we need to to be careful and clean up after 209 // ourselves to not risk getting into an inconsistent state. 210 DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 211 savedCurrState = currState; 212 currState = new WalkerState(); 213 currState->tableWalker = this; 214 } else if (_timing) { 215 // This is a translation that was completed and then faulted again 216 // because some underlying parameters that affect the translation 217 // changed out from under us (e.g. asid). It will either be a 218 // misprediction, in which case nothing will happen or we'll use 219 // this fault to re-execute the faulting instruction which should clean 220 // up everything. 221 if (currState->vaddr_tainted == _req->getVaddr()) { 222 ++statSquashedBefore; 223 return std::make_shared<ReExec>(); 224 } 225 } 226 pendingChange(); 227 228 currState->startTime = curTick(); 229 currState->tc = _tc; 230 // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 231 // aarch32/translation/translation/AArch32.TranslateAddress dictates 232 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 233 if (isStage2) { 234 currState->el = EL1; 235 currState->aarch64 = ELIs64(_tc, EL2); 236 } else { 237 currState->el = 238 TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType); 239 currState->aarch64 = 240 ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el); 241 } 242 currState->transState = _trans; 243 currState->req = _req; 244 currState->fault = NoFault; 245 currState->asid = _asid; 246 currState->vmid = _vmid; 247 currState->isHyp = _isHyp; 248 currState->timing = _timing; 249 currState->functional = _functional; 250 currState->mode = _mode; 251 currState->tranType = tranType; 252 currState->isSecure = secure; 253 currState->physAddrRange = physAddrRange; 254 255 /** @todo These should be cached or grabbed from cached copies in 256 the TLB, all these miscreg reads are expensive */ 257 currState->vaddr_tainted = currState->req->getVaddr(); 258 if (currState->aarch64) 259 currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 260 currState->tc, currState->el); 261 else 262 currState->vaddr = currState->vaddr_tainted; 263 264 if (currState->aarch64) { 265 if (isStage2) { 266 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 267 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 268 } else switch (currState->el) { 269 case EL0: 270 case EL1: 271 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 272 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 273 break; 274 case EL2: 275 assert(_haveVirtualization); 276 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 277 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 278 break; 279 case EL3: 280 assert(haveSecurity); 281 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 282 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 283 break; 284 default: 285 panic("Invalid exception level"); 286 break; 287 } 288 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 289 } else { 290 currState->sctlr = currState->tc->readMiscReg(snsBankedIndex( 291 MISCREG_SCTLR, currState->tc, !currState->isSecure)); 292 currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex( 293 MISCREG_TTBCR, currState->tc, !currState->isSecure)); 294 currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 295 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 296 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 297 } 298 sctlr = currState->sctlr; 299 300 currState->isFetch = (currState->mode == TLB::Execute); 301 currState->isWrite = (currState->mode == TLB::Write); 302 303 statRequestOrigin[REQUESTED][currState->isFetch]++; 304 305 currState->stage2Req = _stage2Req && !isStage2; 306 307 bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 308 longDescFormatInUse(currState->tc); 309 310 if (long_desc_format) { 311 // Helper variables used for hierarchical permissions 312 currState->secureLookup = currState->isSecure; 313 currState->rwTable = true; 314 currState->userTable = true; 315 currState->xnTable = false; 316 currState->pxnTable = false; 317 318 ++statWalksLongDescriptor; 319 } else { 320 ++statWalksShortDescriptor; 321 } 322 323 if (!currState->timing) { 324 Fault fault = NoFault; 325 if (currState->aarch64) 326 fault = processWalkAArch64(); 327 else if (long_desc_format) 328 fault = processWalkLPAE(); 329 else 330 fault = processWalk(); 331 332 // If this was a functional non-timing access restore state to 333 // how we found it. 334 if (currState->functional) { 335 delete currState; 336 currState = savedCurrState; 337 } 338 return fault; 339 } 340 341 if (pending || pendingQueue.size()) { 342 pendingQueue.push_back(currState); 343 currState = NULL; 344 pendingChange(); 345 } else { 346 pending = true; 347 pendingChange(); 348 if (currState->aarch64) 349 return processWalkAArch64(); 350 else if (long_desc_format) 351 return processWalkLPAE(); 352 else 353 return processWalk(); 354 } 355 356 return NoFault; 357} 358 359void 360TableWalker::processWalkWrapper() 361{ 362 assert(!currState); 363 assert(pendingQueue.size()); 364 pendingChange(); 365 currState = pendingQueue.front(); 366 367 // Check if a previous walk filled this request already 368 // @TODO Should this always be the TLB or should we look in the stage2 TLB? 369 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 370 currState->vmid, currState->isHyp, currState->isSecure, true, false, 371 currState->el); 372 373 // Check if we still need to have a walk for this request. If the requesting 374 // instruction has been squashed, or a previous walk has filled the TLB with 375 // a match, we just want to get rid of the walk. The latter could happen 376 // when there are multiple outstanding misses to a single page and a 377 // previous request has been successfully translated. 378 if (!currState->transState->squashed() && !te) { 379 // We've got a valid request, lets process it 380 pending = true; 381 pendingQueue.pop_front(); 382 // Keep currState in case one of the processWalk... calls NULLs it 383 WalkerState *curr_state_copy = currState; 384 Fault f; 385 if (currState->aarch64) 386 f = processWalkAArch64(); 387 else if (longDescFormatInUse(currState->tc) || 388 currState->isHyp || isStage2) 389 f = processWalkLPAE(); 390 else 391 f = processWalk(); 392 393 if (f != NoFault) { 394 curr_state_copy->transState->finish(f, curr_state_copy->req, 395 curr_state_copy->tc, curr_state_copy->mode); 396 397 delete curr_state_copy; 398 } 399 return; 400 } 401 402 403 // If the instruction that we were translating for has been 404 // squashed we shouldn't bother. 405 unsigned num_squashed = 0; 406 ThreadContext *tc = currState->tc; 407 while ((num_squashed < numSquashable) && currState && 408 (currState->transState->squashed() || te)) { 409 pendingQueue.pop_front(); 410 num_squashed++; 411 statSquashedBefore++; 412 413 DPRINTF(TLB, "Squashing table walk for address %#x\n", 414 currState->vaddr_tainted); 415 416 if (currState->transState->squashed()) { 417 // finish the translation which will delete the translation object 418 currState->transState->finish( 419 std::make_shared<UnimpFault>("Squashed Inst"), 420 currState->req, currState->tc, currState->mode); 421 } else { 422 // translate the request now that we know it will work 423 statWalkServiceTime.sample(curTick() - currState->startTime); 424 tlb->translateTiming(currState->req, currState->tc, 425 currState->transState, currState->mode); 426 427 } 428 429 // delete the current request 430 delete currState; 431 432 // peak at the next one 433 if (pendingQueue.size()) { 434 currState = pendingQueue.front(); 435 te = tlb->lookup(currState->vaddr, currState->asid, 436 currState->vmid, currState->isHyp, currState->isSecure, true, 437 false, currState->el); 438 } else { 439 // Terminate the loop, nothing more to do 440 currState = NULL; 441 } 442 } 443 pendingChange(); 444 445 // if we still have pending translations, schedule more work 446 nextWalk(tc); 447 currState = NULL; 448} 449 450Fault 451TableWalker::processWalk() 452{ 453 Addr ttbr = 0; 454 455 // If translation isn't enabled, we shouldn't be here 456 assert(currState->sctlr.m || isStage2); 457 458 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 459 currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 460 32 - currState->ttbcr.n)); 461 462 statWalkWaitTime.sample(curTick() - currState->startTime); 463 464 if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 465 32 - currState->ttbcr.n)) { 466 DPRINTF(TLB, " - Selecting TTBR0\n"); 467 // Check if table walk is allowed when Security Extensions are enabled 468 if (haveSecurity && currState->ttbcr.pd0) { 469 if (currState->isFetch) 470 return std::make_shared<PrefetchAbort>( 471 currState->vaddr_tainted, 472 ArmFault::TranslationLL + L1, 473 isStage2, 474 ArmFault::VmsaTran); 475 else 476 return std::make_shared<DataAbort>( 477 currState->vaddr_tainted, 478 TlbEntry::DomainType::NoAccess, currState->isWrite, 479 ArmFault::TranslationLL + L1, isStage2, 480 ArmFault::VmsaTran); 481 } 482 ttbr = currState->tc->readMiscReg(snsBankedIndex( 483 MISCREG_TTBR0, currState->tc, !currState->isSecure)); 484 } else { 485 DPRINTF(TLB, " - Selecting TTBR1\n"); 486 // Check if table walk is allowed when Security Extensions are enabled 487 if (haveSecurity && currState->ttbcr.pd1) { 488 if (currState->isFetch) 489 return std::make_shared<PrefetchAbort>( 490 currState->vaddr_tainted, 491 ArmFault::TranslationLL + L1, 492 isStage2, 493 ArmFault::VmsaTran); 494 else 495 return std::make_shared<DataAbort>( 496 currState->vaddr_tainted, 497 TlbEntry::DomainType::NoAccess, currState->isWrite, 498 ArmFault::TranslationLL + L1, isStage2, 499 ArmFault::VmsaTran); 500 } 501 ttbr = currState->tc->readMiscReg(snsBankedIndex( 502 MISCREG_TTBR1, currState->tc, !currState->isSecure)); 503 currState->ttbcr.n = 0; 504 } 505 506 Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 507 (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 508 DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 509 currState->isSecure ? "s" : "ns"); 510 511 // Trickbox address check 512 Fault f; 513 f = testWalk(l1desc_addr, sizeof(uint32_t), 514 TlbEntry::DomainType::NoAccess, L1); 515 if (f) { 516 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 517 if (currState->timing) { 518 pending = false; 519 nextWalk(currState->tc); 520 currState = NULL; 521 } else { 522 currState->tc = NULL; 523 currState->req = NULL; 524 } 525 return f; 526 } 527 528 Request::Flags flag = Request::PT_WALK; 529 if (currState->sctlr.c == 0) { 530 flag.set(Request::UNCACHEABLE); 531 } 532 533 if (currState->isSecure) { 534 flag.set(Request::SECURE); 535 } 536 537 bool delayed; 538 delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 539 sizeof(uint32_t), flag, L1, &doL1DescEvent, 540 &TableWalker::doL1Descriptor); 541 if (!delayed) { 542 f = currState->fault; 543 } 544 545 return f; 546} 547 548Fault 549TableWalker::processWalkLPAE() 550{ 551 Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 552 int tsz, n; 553 LookupLevel start_lookup_level = L1; 554 555 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 556 currState->vaddr_tainted, currState->ttbcr); 557 558 statWalkWaitTime.sample(curTick() - currState->startTime); 559 560 Request::Flags flag = Request::PT_WALK; 561 if (currState->isSecure) 562 flag.set(Request::SECURE); 563 564 // work out which base address register to use, if in hyp mode we always 565 // use HTTBR 566 if (isStage2) { 567 DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 568 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 569 tsz = sext<4>(currState->vtcr.t0sz); 570 start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 571 } else if (currState->isHyp) { 572 DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 573 ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 574 tsz = currState->htcr.t0sz; 575 } else { 576 assert(longDescFormatInUse(currState->tc)); 577 578 // Determine boundaries of TTBR0/1 regions 579 if (currState->ttbcr.t0sz) 580 ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 581 else if (currState->ttbcr.t1sz) 582 ttbr0_max = (1ULL << 32) - 583 (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 584 else 585 ttbr0_max = (1ULL << 32) - 1; 586 if (currState->ttbcr.t1sz) 587 ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 588 else 589 ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 590 591 // The following code snippet selects the appropriate translation table base 592 // address (TTBR0 or TTBR1) and the appropriate starting lookup level 593 // depending on the address range supported by the translation table (ARM 594 // ARM issue C B3.6.4) 595 if (currState->vaddr <= ttbr0_max) { 596 DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 597 // Check if table walk is allowed 598 if (currState->ttbcr.epd0) { 599 if (currState->isFetch) 600 return std::make_shared<PrefetchAbort>( 601 currState->vaddr_tainted, 602 ArmFault::TranslationLL + L1, 603 isStage2, 604 ArmFault::LpaeTran); 605 else 606 return std::make_shared<DataAbort>( 607 currState->vaddr_tainted, 608 TlbEntry::DomainType::NoAccess, 609 currState->isWrite, 610 ArmFault::TranslationLL + L1, 611 isStage2, 612 ArmFault::LpaeTran); 613 } 614 ttbr = currState->tc->readMiscReg(snsBankedIndex( 615 MISCREG_TTBR0, currState->tc, !currState->isSecure)); 616 tsz = currState->ttbcr.t0sz; 617 if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 618 start_lookup_level = L2; 619 } else if (currState->vaddr >= ttbr1_min) { 620 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 621 // Check if table walk is allowed 622 if (currState->ttbcr.epd1) { 623 if (currState->isFetch) 624 return std::make_shared<PrefetchAbort>( 625 currState->vaddr_tainted, 626 ArmFault::TranslationLL + L1, 627 isStage2, 628 ArmFault::LpaeTran); 629 else 630 return std::make_shared<DataAbort>( 631 currState->vaddr_tainted, 632 TlbEntry::DomainType::NoAccess, 633 currState->isWrite, 634 ArmFault::TranslationLL + L1, 635 isStage2, 636 ArmFault::LpaeTran); 637 } 638 ttbr = currState->tc->readMiscReg(snsBankedIndex( 639 MISCREG_TTBR1, currState->tc, !currState->isSecure)); 640 tsz = currState->ttbcr.t1sz; 641 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 642 start_lookup_level = L2; 643 } else { 644 // Out of boundaries -> translation fault 645 if (currState->isFetch) 646 return std::make_shared<PrefetchAbort>( 647 currState->vaddr_tainted, 648 ArmFault::TranslationLL + L1, 649 isStage2, 650 ArmFault::LpaeTran); 651 else 652 return std::make_shared<DataAbort>( 653 currState->vaddr_tainted, 654 TlbEntry::DomainType::NoAccess, 655 currState->isWrite, ArmFault::TranslationLL + L1, 656 isStage2, ArmFault::LpaeTran); 657 } 658 659 } 660 661 // Perform lookup (ARM ARM issue C B3.6.6) 662 if (start_lookup_level == L1) { 663 n = 5 - tsz; 664 desc_addr = mbits(ttbr, 39, n) | 665 (bits(currState->vaddr, n + 26, 30) << 3); 666 DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 667 desc_addr, currState->isSecure ? "s" : "ns"); 668 } else { 669 // Skip first-level lookup 670 n = (tsz >= 2 ? 14 - tsz : 12); 671 desc_addr = mbits(ttbr, 39, n) | 672 (bits(currState->vaddr, n + 17, 21) << 3); 673 DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 674 desc_addr, currState->isSecure ? "s" : "ns"); 675 } 676 677 // Trickbox address check 678 Fault f = testWalk(desc_addr, sizeof(uint64_t), 679 TlbEntry::DomainType::NoAccess, start_lookup_level); 680 if (f) { 681 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 682 if (currState->timing) { 683 pending = false; 684 nextWalk(currState->tc); 685 currState = NULL; 686 } else { 687 currState->tc = NULL; 688 currState->req = NULL; 689 } 690 return f; 691 } 692 693 if (currState->sctlr.c == 0) { 694 flag.set(Request::UNCACHEABLE); 695 } 696 697 currState->longDesc.lookupLevel = start_lookup_level; 698 currState->longDesc.aarch64 = false; 699 currState->longDesc.grainSize = Grain4KB; 700 701 bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 702 sizeof(uint64_t), flag, start_lookup_level, 703 LongDescEventByLevel[start_lookup_level], 704 &TableWalker::doLongDescriptor); 705 if (!delayed) { 706 f = currState->fault; 707 } 708 709 return f; 710} 711 712unsigned 713TableWalker::adjustTableSizeAArch64(unsigned tsz) 714{ 715 if (tsz < 25) 716 return 25; 717 if (tsz > 48) 718 return 48; 719 return tsz; 720} 721 722bool 723TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 724{ 725 return (currPhysAddrRange != MaxPhysAddrRange && 726 bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 727} 728 729Fault 730TableWalker::processWalkAArch64() 731{ 732 assert(currState->aarch64); 733 734 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 735 currState->vaddr_tainted, currState->tcr); 736 737 static const GrainSize GrainMap_tg0[] = 738 { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 739 static const GrainSize GrainMap_tg1[] = 740 { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 741 742 statWalkWaitTime.sample(curTick() - currState->startTime); 743 744 // Determine TTBR, table size, granule size and phys. address range 745 Addr ttbr = 0; 746 int tsz = 0, ps = 0; 747 GrainSize tg = Grain4KB; // grain size computed from tg* field 748 bool fault = false; 749 750 LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 751 752 switch (currState->el) { 753 case EL0: 754 case EL1: 755 if (isStage2) { 756 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 757 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 758 tsz = 64 - currState->vtcr.t0sz64; 759 tg = GrainMap_tg0[currState->vtcr.tg0]; 760 // ARM DDI 0487A.f D7-2148 761 // The starting level of stage 2 translation depends on 762 // VTCR_EL2.SL0 and VTCR_EL2.TG0 763 LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 764 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 765 static const LookupLevel SLL[] = { 766 L2, L3, L3, __, // sl0 == 0 767 L1, L2, L2, __, // sl0 == 1, etc. 768 L0, L1, L1, __, 769 __, __, __, __ 770 }; 771 start_lookup_level = SLL[sl_tg]; 772 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 773 "Cannot discern lookup level from vtcr.{sl0,tg0}"); 774 } else switch (bits(currState->vaddr, 63,48)) { 775 case 0: 776 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 777 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 778 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 779 tg = GrainMap_tg0[currState->tcr.tg0]; 780 if (bits(currState->vaddr, 63, tsz) != 0x0 || 781 currState->tcr.epd0) 782 fault = true; 783 break; 784 case 0xffff: 785 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 786 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 787 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 788 tg = GrainMap_tg1[currState->tcr.tg1]; 789 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 790 currState->tcr.epd1) 791 fault = true; 792 break; 793 default: 794 // top two bytes must be all 0s or all 1s, else invalid addr 795 fault = true; 796 } 797 ps = currState->tcr.ips; 798 break; 799 case EL2: 800 switch(bits(currState->vaddr, 63,48)) { 801 case 0: 802 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 803 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 804 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 805 tg = GrainMap_tg0[currState->tcr.tg0]; 806 break; 807 808 case 0xffff: 809 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 810 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2); 811 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 812 tg = GrainMap_tg1[currState->tcr.tg1]; 813 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 814 currState->tcr.epd1 || !currState->hcr.e2h) 815 fault = true; 816 break; 817 818 default: 819 // invalid addr if top two bytes are not all 0s 820 fault = true; 821 } 822 ps = currState->tcr.ips; 823 break; 824 case EL3: 825 switch(bits(currState->vaddr, 63,48)) { 826 case 0: 827 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 828 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 829 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 830 tg = GrainMap_tg0[currState->tcr.tg0]; 831 break; 832 default: 833 // invalid addr if top two bytes are not all 0s 834 fault = true; 835 } 836 ps = currState->tcr.ips; 837 break; 838 } 839 840 if (fault) { 841 Fault f; 842 if (currState->isFetch) 843 f = std::make_shared<PrefetchAbort>( 844 currState->vaddr_tainted, 845 ArmFault::TranslationLL + L0, isStage2, 846 ArmFault::LpaeTran); 847 else 848 f = std::make_shared<DataAbort>( 849 currState->vaddr_tainted, 850 TlbEntry::DomainType::NoAccess, 851 currState->isWrite, 852 ArmFault::TranslationLL + L0, 853 isStage2, ArmFault::LpaeTran); 854 855 if (currState->timing) { 856 pending = false; 857 nextWalk(currState->tc); 858 currState = NULL; 859 } else { 860 currState->tc = NULL; 861 currState->req = NULL; 862 } 863 return f; 864 865 } 866 867 if (tg == ReservedGrain) { 868 warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 869 "DEFINED behavior takes this to mean 4KB granules\n"); 870 tg = Grain4KB; 871 } 872 873 // Determine starting lookup level 874 // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 875 // in ARM DDI 0487A. These table values correspond to the cascading tests 876 // to compute the lookup level and are of the form 877 // (grain_size + N*stride), for N = {1, 2, 3}. 878 // A value of 64 will never succeed and a value of 0 will always succeed. 879 if (start_lookup_level == MAX_LOOKUP_LEVELS) { 880 struct GrainMap { 881 GrainSize grain_size; 882 unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 883 }; 884 static const GrainMap GM[] = { 885 { Grain4KB, { 39, 30, 0, 0 } }, 886 { Grain16KB, { 47, 36, 25, 0 } }, 887 { Grain64KB, { 64, 42, 29, 0 } } 888 }; 889 890 const unsigned *lookup = NULL; // points to a lookup_level_cutoff 891 892 for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 893 if (tg == GM[i].grain_size) { 894 lookup = GM[i].lookup_level_cutoff; 895 break; 896 } 897 } 898 assert(lookup); 899 900 for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 901 if (tsz > lookup[L]) { 902 start_lookup_level = (LookupLevel) L; 903 break; 904 } 905 } 906 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 907 "Table walker couldn't find lookup level\n"); 908 } 909 910 int stride = tg - 3; 911 912 // Determine table base address 913 int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 914 Addr base_addr = mbits(ttbr, 47, base_addr_lo); 915 916 // Determine physical address size and raise an Address Size Fault if 917 // necessary 918 int pa_range = decodePhysAddrRange64(ps); 919 // Clamp to lower limit 920 if (pa_range > physAddrRange) 921 currState->physAddrRange = physAddrRange; 922 else 923 currState->physAddrRange = pa_range; 924 if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 925 DPRINTF(TLB, "Address size fault before any lookup\n"); 926 Fault f; 927 if (currState->isFetch) 928 f = std::make_shared<PrefetchAbort>( 929 currState->vaddr_tainted, 930 ArmFault::AddressSizeLL + start_lookup_level, 931 isStage2, 932 ArmFault::LpaeTran); 933 else 934 f = std::make_shared<DataAbort>( 935 currState->vaddr_tainted, 936 TlbEntry::DomainType::NoAccess, 937 currState->isWrite, 938 ArmFault::AddressSizeLL + start_lookup_level, 939 isStage2, 940 ArmFault::LpaeTran); 941 942 943 if (currState->timing) { 944 pending = false; 945 nextWalk(currState->tc); 946 currState = NULL; 947 } else { 948 currState->tc = NULL; 949 currState->req = NULL; 950 } 951 return f; 952 953 } 954 955 // Determine descriptor address 956 Addr desc_addr = base_addr | 957 (bits(currState->vaddr, tsz - 1, 958 stride * (3 - start_lookup_level) + tg) << 3); 959 960 // Trickbox address check 961 Fault f = testWalk(desc_addr, sizeof(uint64_t), 962 TlbEntry::DomainType::NoAccess, start_lookup_level); 963 if (f) { 964 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 965 if (currState->timing) { 966 pending = false; 967 nextWalk(currState->tc); 968 currState = NULL; 969 } else { 970 currState->tc = NULL; 971 currState->req = NULL; 972 } 973 return f; 974 } 975 976 Request::Flags flag = Request::PT_WALK; 977 if (currState->sctlr.c == 0) { 978 flag.set(Request::UNCACHEABLE); 979 } 980 981 if (currState->isSecure) { 982 flag.set(Request::SECURE); 983 } 984 985 currState->longDesc.lookupLevel = start_lookup_level; 986 currState->longDesc.aarch64 = true; 987 currState->longDesc.grainSize = tg; 988 989 if (currState->timing) { 990 fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data, 991 sizeof(uint64_t), flag, start_lookup_level, 992 LongDescEventByLevel[start_lookup_level], NULL); 993 } else { 994 fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 995 sizeof(uint64_t), flag, -1, NULL, 996 &TableWalker::doLongDescriptor); 997 f = currState->fault; 998 } 999 1000 return f; 1001} 1002 1003void 1004TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 1005 uint8_t texcb, bool s) 1006{ 1007 // Note: tc and sctlr local variables are hiding tc and sctrl class 1008 // variables 1009 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1010 te.shareable = false; // default value 1011 te.nonCacheable = false; 1012 te.outerShareable = false; 1013 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 1014 switch(texcb) { 1015 case 0: // Stongly-ordered 1016 te.nonCacheable = true; 1017 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1018 te.shareable = true; 1019 te.innerAttrs = 1; 1020 te.outerAttrs = 0; 1021 break; 1022 case 1: // Shareable Device 1023 te.nonCacheable = true; 1024 te.mtype = TlbEntry::MemoryType::Device; 1025 te.shareable = true; 1026 te.innerAttrs = 3; 1027 te.outerAttrs = 0; 1028 break; 1029 case 2: // Outer and Inner Write-Through, no Write-Allocate 1030 te.mtype = TlbEntry::MemoryType::Normal; 1031 te.shareable = s; 1032 te.innerAttrs = 6; 1033 te.outerAttrs = bits(texcb, 1, 0); 1034 break; 1035 case 3: // Outer and Inner Write-Back, no Write-Allocate 1036 te.mtype = TlbEntry::MemoryType::Normal; 1037 te.shareable = s; 1038 te.innerAttrs = 7; 1039 te.outerAttrs = bits(texcb, 1, 0); 1040 break; 1041 case 4: // Outer and Inner Non-cacheable 1042 te.nonCacheable = true; 1043 te.mtype = TlbEntry::MemoryType::Normal; 1044 te.shareable = s; 1045 te.innerAttrs = 0; 1046 te.outerAttrs = bits(texcb, 1, 0); 1047 break; 1048 case 5: // Reserved 1049 panic("Reserved texcb value!\n"); 1050 break; 1051 case 6: // Implementation Defined 1052 panic("Implementation-defined texcb value!\n"); 1053 break; 1054 case 7: // Outer and Inner Write-Back, Write-Allocate 1055 te.mtype = TlbEntry::MemoryType::Normal; 1056 te.shareable = s; 1057 te.innerAttrs = 5; 1058 te.outerAttrs = 1; 1059 break; 1060 case 8: // Non-shareable Device 1061 te.nonCacheable = true; 1062 te.mtype = TlbEntry::MemoryType::Device; 1063 te.shareable = false; 1064 te.innerAttrs = 3; 1065 te.outerAttrs = 0; 1066 break; 1067 case 9 ... 15: // Reserved 1068 panic("Reserved texcb value!\n"); 1069 break; 1070 case 16 ... 31: // Cacheable Memory 1071 te.mtype = TlbEntry::MemoryType::Normal; 1072 te.shareable = s; 1073 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 1074 te.nonCacheable = true; 1075 te.innerAttrs = bits(texcb, 1, 0); 1076 te.outerAttrs = bits(texcb, 3, 2); 1077 break; 1078 default: 1079 panic("More than 32 states for 5 bits?\n"); 1080 } 1081 } else { 1082 assert(tc); 1083 PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, 1084 currState->tc, !currState->isSecure)); 1085 NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, 1086 currState->tc, !currState->isSecure)); 1087 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 1088 uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 1089 switch(bits(texcb, 2,0)) { 1090 case 0: 1091 curr_tr = prrr.tr0; 1092 curr_ir = nmrr.ir0; 1093 curr_or = nmrr.or0; 1094 te.outerShareable = (prrr.nos0 == 0); 1095 break; 1096 case 1: 1097 curr_tr = prrr.tr1; 1098 curr_ir = nmrr.ir1; 1099 curr_or = nmrr.or1; 1100 te.outerShareable = (prrr.nos1 == 0); 1101 break; 1102 case 2: 1103 curr_tr = prrr.tr2; 1104 curr_ir = nmrr.ir2; 1105 curr_or = nmrr.or2; 1106 te.outerShareable = (prrr.nos2 == 0); 1107 break; 1108 case 3: 1109 curr_tr = prrr.tr3; 1110 curr_ir = nmrr.ir3; 1111 curr_or = nmrr.or3; 1112 te.outerShareable = (prrr.nos3 == 0); 1113 break; 1114 case 4: 1115 curr_tr = prrr.tr4; 1116 curr_ir = nmrr.ir4; 1117 curr_or = nmrr.or4; 1118 te.outerShareable = (prrr.nos4 == 0); 1119 break; 1120 case 5: 1121 curr_tr = prrr.tr5; 1122 curr_ir = nmrr.ir5; 1123 curr_or = nmrr.or5; 1124 te.outerShareable = (prrr.nos5 == 0); 1125 break; 1126 case 6: 1127 panic("Imp defined type\n"); 1128 case 7: 1129 curr_tr = prrr.tr7; 1130 curr_ir = nmrr.ir7; 1131 curr_or = nmrr.or7; 1132 te.outerShareable = (prrr.nos7 == 0); 1133 break; 1134 } 1135 1136 switch(curr_tr) { 1137 case 0: 1138 DPRINTF(TLBVerbose, "StronglyOrdered\n"); 1139 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1140 te.nonCacheable = true; 1141 te.innerAttrs = 1; 1142 te.outerAttrs = 0; 1143 te.shareable = true; 1144 break; 1145 case 1: 1146 DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 1147 prrr.ds1, prrr.ds0, s); 1148 te.mtype = TlbEntry::MemoryType::Device; 1149 te.nonCacheable = true; 1150 te.innerAttrs = 3; 1151 te.outerAttrs = 0; 1152 if (prrr.ds1 && s) 1153 te.shareable = true; 1154 if (prrr.ds0 && !s) 1155 te.shareable = true; 1156 break; 1157 case 2: 1158 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 1159 prrr.ns1, prrr.ns0, s); 1160 te.mtype = TlbEntry::MemoryType::Normal; 1161 if (prrr.ns1 && s) 1162 te.shareable = true; 1163 if (prrr.ns0 && !s) 1164 te.shareable = true; 1165 break; 1166 case 3: 1167 panic("Reserved type"); 1168 } 1169 1170 if (te.mtype == TlbEntry::MemoryType::Normal){ 1171 switch(curr_ir) { 1172 case 0: 1173 te.nonCacheable = true; 1174 te.innerAttrs = 0; 1175 break; 1176 case 1: 1177 te.innerAttrs = 5; 1178 break; 1179 case 2: 1180 te.innerAttrs = 6; 1181 break; 1182 case 3: 1183 te.innerAttrs = 7; 1184 break; 1185 } 1186 1187 switch(curr_or) { 1188 case 0: 1189 te.nonCacheable = true; 1190 te.outerAttrs = 0; 1191 break; 1192 case 1: 1193 te.outerAttrs = 1; 1194 break; 1195 case 2: 1196 te.outerAttrs = 2; 1197 break; 1198 case 3: 1199 te.outerAttrs = 3; 1200 break; 1201 } 1202 } 1203 } 1204 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 1205 "outerAttrs: %d\n", 1206 te.shareable, te.innerAttrs, te.outerAttrs); 1207 te.setAttributes(false); 1208} 1209 1210void 1211TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 1212 LongDescriptor &lDescriptor) 1213{ 1214 assert(_haveLPAE); 1215 1216 uint8_t attr; 1217 uint8_t sh = lDescriptor.sh(); 1218 // Different format and source of attributes if this is a stage 2 1219 // translation 1220 if (isStage2) { 1221 attr = lDescriptor.memAttr(); 1222 uint8_t attr_3_2 = (attr >> 2) & 0x3; 1223 uint8_t attr_1_0 = attr & 0x3; 1224 1225 DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 1226 1227 if (attr_3_2 == 0) { 1228 te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 1229 : TlbEntry::MemoryType::Device; 1230 te.outerAttrs = 0; 1231 te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 1232 te.nonCacheable = true; 1233 } else { 1234 te.mtype = TlbEntry::MemoryType::Normal; 1235 te.outerAttrs = attr_3_2 == 1 ? 0 : 1236 attr_3_2 == 2 ? 2 : 1; 1237 te.innerAttrs = attr_1_0 == 1 ? 0 : 1238 attr_1_0 == 2 ? 6 : 5; 1239 te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 1240 } 1241 } else { 1242 uint8_t attrIndx = lDescriptor.attrIndx(); 1243 1244 // LPAE always uses remapping of memory attributes, irrespective of the 1245 // value of SCTLR.TRE 1246 MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 1247 int reg_as_int = snsBankedIndex(reg, currState->tc, 1248 !currState->isSecure); 1249 uint32_t mair = currState->tc->readMiscReg(reg_as_int); 1250 attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 1251 uint8_t attr_7_4 = bits(attr, 7, 4); 1252 uint8_t attr_3_0 = bits(attr, 3, 0); 1253 DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 1254 1255 // Note: the memory subsystem only cares about the 'cacheable' memory 1256 // attribute. The other attributes are only used to fill the PAR register 1257 // accordingly to provide the illusion of full support 1258 te.nonCacheable = false; 1259 1260 switch (attr_7_4) { 1261 case 0x0: 1262 // Strongly-ordered or Device memory 1263 if (attr_3_0 == 0x0) 1264 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1265 else if (attr_3_0 == 0x4) 1266 te.mtype = TlbEntry::MemoryType::Device; 1267 else 1268 panic("Unpredictable behavior\n"); 1269 te.nonCacheable = true; 1270 te.outerAttrs = 0; 1271 break; 1272 case 0x4: 1273 // Normal memory, Outer Non-cacheable 1274 te.mtype = TlbEntry::MemoryType::Normal; 1275 te.outerAttrs = 0; 1276 if (attr_3_0 == 0x4) 1277 // Inner Non-cacheable 1278 te.nonCacheable = true; 1279 else if (attr_3_0 < 0x8) 1280 panic("Unpredictable behavior\n"); 1281 break; 1282 case 0x8: 1283 case 0x9: 1284 case 0xa: 1285 case 0xb: 1286 case 0xc: 1287 case 0xd: 1288 case 0xe: 1289 case 0xf: 1290 if (attr_7_4 & 0x4) { 1291 te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 1292 } else { 1293 te.outerAttrs = 0x2; 1294 } 1295 // Normal memory, Outer Cacheable 1296 te.mtype = TlbEntry::MemoryType::Normal; 1297 if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 1298 panic("Unpredictable behavior\n"); 1299 break; 1300 default: 1301 panic("Unpredictable behavior\n"); 1302 break; 1303 } 1304 1305 switch (attr_3_0) { 1306 case 0x0: 1307 te.innerAttrs = 0x1; 1308 break; 1309 case 0x4: 1310 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 1311 break; 1312 case 0x8: 1313 case 0x9: 1314 case 0xA: 1315 case 0xB: 1316 te.innerAttrs = 6; 1317 break; 1318 case 0xC: 1319 case 0xD: 1320 case 0xE: 1321 case 0xF: 1322 te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 1323 break; 1324 default: 1325 panic("Unpredictable behavior\n"); 1326 break; 1327 } 1328 } 1329 1330 te.outerShareable = sh == 2; 1331 te.shareable = (sh & 0x2) ? true : false; 1332 te.setAttributes(true); 1333 te.attributes |= (uint64_t) attr << 56; 1334} 1335 1336void 1337TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, 1338 LongDescriptor &lDescriptor) 1339{ 1340 uint8_t attr; 1341 uint8_t attr_hi; 1342 uint8_t attr_lo; 1343 uint8_t sh = lDescriptor.sh(); 1344 1345 if (isStage2) { 1346 attr = lDescriptor.memAttr(); 1347 uint8_t attr_hi = (attr >> 2) & 0x3; 1348 uint8_t attr_lo = attr & 0x3; 1349 1350 DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh); 1351 1352 if (attr_hi == 0) { 1353 te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered 1354 : TlbEntry::MemoryType::Device; 1355 te.outerAttrs = 0; 1356 te.innerAttrs = attr_lo == 0 ? 1 : 3; 1357 te.nonCacheable = true; 1358 } else { 1359 te.mtype = TlbEntry::MemoryType::Normal; 1360 te.outerAttrs = attr_hi == 1 ? 0 : 1361 attr_hi == 2 ? 2 : 1; 1362 te.innerAttrs = attr_lo == 1 ? 0 : 1363 attr_lo == 2 ? 6 : 5; 1364 // Treat write-through memory as uncacheable, this is safe 1365 // but for performance reasons not optimal. 1366 te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) || 1367 (attr_lo == 1) || (attr_lo == 2); 1368 } 1369 } else { 1370 uint8_t attrIndx = lDescriptor.attrIndx(); 1371 1372 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 1373 1374 // Select MAIR 1375 uint64_t mair; 1376 switch (currState->el) { 1377 case EL0: 1378 case EL1: 1379 mair = tc->readMiscReg(MISCREG_MAIR_EL1); 1380 break; 1381 case EL2: 1382 mair = tc->readMiscReg(MISCREG_MAIR_EL2); 1383 break; 1384 case EL3: 1385 mair = tc->readMiscReg(MISCREG_MAIR_EL3); 1386 break; 1387 default: 1388 panic("Invalid exception level"); 1389 break; 1390 } 1391 1392 // Select attributes 1393 attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 1394 attr_lo = bits(attr, 3, 0); 1395 attr_hi = bits(attr, 7, 4); 1396 1397 // Memory type 1398 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 1399 1400 // Cacheability 1401 te.nonCacheable = false; 1402 if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory 1403 te.nonCacheable = true; 1404 } 1405 // Treat write-through memory as uncacheable, this is safe 1406 // but for performance reasons not optimal. 1407 switch (attr_hi) { 1408 case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 1409 case 0x4: // Normal memory, Outer Non-cacheable 1410 case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 1411 te.nonCacheable = true; 1412 } 1413 switch (attr_lo) { 1414 case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 1415 case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 1416 warn_if(!attr_hi, "Unpredictable behavior"); 1417 M5_FALLTHROUGH; 1418 case 0x4: // Device-nGnRE memory or 1419 // Normal memory, Inner Non-cacheable 1420 case 0x8: // Device-nGRE memory or 1421 // Normal memory, Inner Write-through non-transient 1422 te.nonCacheable = true; 1423 } 1424 1425 te.shareable = sh == 2; 1426 te.outerShareable = (sh & 0x2) ? true : false; 1427 // Attributes formatted according to the 64-bit PAR 1428 te.attributes = ((uint64_t) attr << 56) | 1429 (1 << 11) | // LPAE bit 1430 (te.ns << 9) | // NS bit 1431 (sh << 7); 1432 } 1433} 1434 1435void 1436TableWalker::doL1Descriptor() 1437{ 1438 if (currState->fault != NoFault) { 1439 return; 1440 } 1441 1442 currState->l1Desc.data = htog(currState->l1Desc.data, 1443 byteOrder(currState->tc)); 1444 1445 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 1446 currState->vaddr_tainted, currState->l1Desc.data); 1447 TlbEntry te; 1448 1449 switch (currState->l1Desc.type()) { 1450 case L1Descriptor::Ignore: 1451 case L1Descriptor::Reserved: 1452 if (!currState->timing) { 1453 currState->tc = NULL; 1454 currState->req = NULL; 1455 } 1456 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 1457 if (currState->isFetch) 1458 currState->fault = 1459 std::make_shared<PrefetchAbort>( 1460 currState->vaddr_tainted, 1461 ArmFault::TranslationLL + L1, 1462 isStage2, 1463 ArmFault::VmsaTran); 1464 else 1465 currState->fault = 1466 std::make_shared<DataAbort>( 1467 currState->vaddr_tainted, 1468 TlbEntry::DomainType::NoAccess, 1469 currState->isWrite, 1470 ArmFault::TranslationLL + L1, isStage2, 1471 ArmFault::VmsaTran); 1472 return; 1473 case L1Descriptor::Section: 1474 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 1475 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 1476 * enabled if set, do l1.Desc.setAp0() instead of generating 1477 * AccessFlag0 1478 */ 1479 1480 currState->fault = std::make_shared<DataAbort>( 1481 currState->vaddr_tainted, 1482 currState->l1Desc.domain(), 1483 currState->isWrite, 1484 ArmFault::AccessFlagLL + L1, 1485 isStage2, 1486 ArmFault::VmsaTran); 1487 } 1488 if (currState->l1Desc.supersection()) { 1489 panic("Haven't implemented supersections\n"); 1490 } 1491 insertTableEntry(currState->l1Desc, false); 1492 return; 1493 case L1Descriptor::PageTable: 1494 { 1495 Addr l2desc_addr; 1496 l2desc_addr = currState->l1Desc.l2Addr() | 1497 (bits(currState->vaddr, 19, 12) << 2); 1498 DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 1499 l2desc_addr, currState->isSecure ? "s" : "ns"); 1500 1501 // Trickbox address check 1502 currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 1503 currState->l1Desc.domain(), L2); 1504 1505 if (currState->fault) { 1506 if (!currState->timing) { 1507 currState->tc = NULL; 1508 currState->req = NULL; 1509 } 1510 return; 1511 } 1512 1513 Request::Flags flag = Request::PT_WALK; 1514 if (currState->isSecure) 1515 flag.set(Request::SECURE); 1516 1517 bool delayed; 1518 delayed = fetchDescriptor(l2desc_addr, 1519 (uint8_t*)&currState->l2Desc.data, 1520 sizeof(uint32_t), flag, -1, &doL2DescEvent, 1521 &TableWalker::doL2Descriptor); 1522 if (delayed) { 1523 currState->delayed = true; 1524 } 1525 1526 return; 1527 } 1528 default: 1529 panic("A new type in a 2 bit field?\n"); 1530 } 1531} 1532 1533void 1534TableWalker::doLongDescriptor() 1535{ 1536 if (currState->fault != NoFault) { 1537 return; 1538 } 1539 1540 currState->longDesc.data = htog(currState->longDesc.data, 1541 byteOrder(currState->tc)); 1542 1543 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 1544 currState->longDesc.lookupLevel, currState->vaddr_tainted, 1545 currState->longDesc.data, 1546 currState->aarch64 ? "AArch64" : "long-desc."); 1547 1548 if ((currState->longDesc.type() == LongDescriptor::Block) || 1549 (currState->longDesc.type() == LongDescriptor::Page)) { 1550 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 1551 "xn: %d, ap: %d, af: %d, type: %d\n", 1552 currState->longDesc.lookupLevel, 1553 currState->longDesc.data, 1554 currState->longDesc.pxn(), 1555 currState->longDesc.xn(), 1556 currState->longDesc.ap(), 1557 currState->longDesc.af(), 1558 currState->longDesc.type()); 1559 } else { 1560 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 1561 currState->longDesc.lookupLevel, 1562 currState->longDesc.data, 1563 currState->longDesc.type()); 1564 } 1565 1566 TlbEntry te; 1567 1568 switch (currState->longDesc.type()) { 1569 case LongDescriptor::Invalid: 1570 if (!currState->timing) { 1571 currState->tc = NULL; 1572 currState->req = NULL; 1573 } 1574 1575 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 1576 currState->longDesc.lookupLevel, 1577 ArmFault::TranslationLL + currState->longDesc.lookupLevel); 1578 if (currState->isFetch) 1579 currState->fault = std::make_shared<PrefetchAbort>( 1580 currState->vaddr_tainted, 1581 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1582 isStage2, 1583 ArmFault::LpaeTran); 1584 else 1585 currState->fault = std::make_shared<DataAbort>( 1586 currState->vaddr_tainted, 1587 TlbEntry::DomainType::NoAccess, 1588 currState->isWrite, 1589 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1590 isStage2, 1591 ArmFault::LpaeTran); 1592 return; 1593 case LongDescriptor::Block: 1594 case LongDescriptor::Page: 1595 { 1596 bool fault = false; 1597 bool aff = false; 1598 // Check for address size fault 1599 if (checkAddrSizeFaultAArch64( 1600 mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 1601 currState->longDesc.offsetBits()), 1602 currState->physAddrRange)) { 1603 fault = true; 1604 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1605 currState->longDesc.lookupLevel); 1606 // Check for access fault 1607 } else if (currState->longDesc.af() == 0) { 1608 fault = true; 1609 DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 1610 currState->longDesc.lookupLevel); 1611 aff = true; 1612 } 1613 if (fault) { 1614 if (currState->isFetch) 1615 currState->fault = std::make_shared<PrefetchAbort>( 1616 currState->vaddr_tainted, 1617 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1618 currState->longDesc.lookupLevel, 1619 isStage2, 1620 ArmFault::LpaeTran); 1621 else 1622 currState->fault = std::make_shared<DataAbort>( 1623 currState->vaddr_tainted, 1624 TlbEntry::DomainType::NoAccess, currState->isWrite, 1625 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1626 currState->longDesc.lookupLevel, 1627 isStage2, 1628 ArmFault::LpaeTran); 1629 } else { 1630 insertTableEntry(currState->longDesc, true); 1631 } 1632 } 1633 return; 1634 case LongDescriptor::Table: 1635 { 1636 // Set hierarchical permission flags 1637 currState->secureLookup = currState->secureLookup && 1638 currState->longDesc.secureTable(); 1639 currState->rwTable = currState->rwTable && 1640 currState->longDesc.rwTable(); 1641 currState->userTable = currState->userTable && 1642 currState->longDesc.userTable(); 1643 currState->xnTable = currState->xnTable || 1644 currState->longDesc.xnTable(); 1645 currState->pxnTable = currState->pxnTable || 1646 currState->longDesc.pxnTable(); 1647 1648 // Set up next level lookup 1649 Addr next_desc_addr = currState->longDesc.nextDescAddr( 1650 currState->vaddr); 1651 1652 DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 1653 currState->longDesc.lookupLevel, 1654 currState->longDesc.lookupLevel + 1, 1655 next_desc_addr, 1656 currState->secureLookup ? "s" : "ns"); 1657 1658 // Check for address size fault 1659 if (currState->aarch64 && checkAddrSizeFaultAArch64( 1660 next_desc_addr, currState->physAddrRange)) { 1661 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1662 currState->longDesc.lookupLevel); 1663 if (currState->isFetch) 1664 currState->fault = std::make_shared<PrefetchAbort>( 1665 currState->vaddr_tainted, 1666 ArmFault::AddressSizeLL 1667 + currState->longDesc.lookupLevel, 1668 isStage2, 1669 ArmFault::LpaeTran); 1670 else 1671 currState->fault = std::make_shared<DataAbort>( 1672 currState->vaddr_tainted, 1673 TlbEntry::DomainType::NoAccess, currState->isWrite, 1674 ArmFault::AddressSizeLL 1675 + currState->longDesc.lookupLevel, 1676 isStage2, 1677 ArmFault::LpaeTran); 1678 return; 1679 } 1680 1681 // Trickbox address check 1682 currState->fault = testWalk( 1683 next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 1684 toLookupLevel(currState->longDesc.lookupLevel +1)); 1685 1686 if (currState->fault) { 1687 if (!currState->timing) { 1688 currState->tc = NULL; 1689 currState->req = NULL; 1690 } 1691 return; 1692 } 1693 1694 Request::Flags flag = Request::PT_WALK; 1695 if (currState->secureLookup) 1696 flag.set(Request::SECURE); 1697 1698 LookupLevel L = currState->longDesc.lookupLevel = 1699 (LookupLevel) (currState->longDesc.lookupLevel + 1); 1700 Event *event = NULL; 1701 switch (L) { 1702 case L1: 1703 assert(currState->aarch64); 1704 case L2: 1705 case L3: 1706 event = LongDescEventByLevel[L]; 1707 break; 1708 default: 1709 panic("Wrong lookup level in table walk\n"); 1710 break; 1711 } 1712 1713 bool delayed; 1714 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 1715 sizeof(uint64_t), flag, -1, event, 1716 &TableWalker::doLongDescriptor); 1717 if (delayed) { 1718 currState->delayed = true; 1719 } 1720 } 1721 return; 1722 default: 1723 panic("A new type in a 2 bit field?\n"); 1724 } 1725} 1726 1727void 1728TableWalker::doL2Descriptor() 1729{ 1730 if (currState->fault != NoFault) { 1731 return; 1732 } 1733 1734 currState->l2Desc.data = htog(currState->l2Desc.data, 1735 byteOrder(currState->tc)); 1736 1737 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 1738 currState->vaddr_tainted, currState->l2Desc.data); 1739 TlbEntry te; 1740 1741 if (currState->l2Desc.invalid()) { 1742 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 1743 if (!currState->timing) { 1744 currState->tc = NULL; 1745 currState->req = NULL; 1746 } 1747 if (currState->isFetch) 1748 currState->fault = std::make_shared<PrefetchAbort>( 1749 currState->vaddr_tainted, 1750 ArmFault::TranslationLL + L2, 1751 isStage2, 1752 ArmFault::VmsaTran); 1753 else 1754 currState->fault = std::make_shared<DataAbort>( 1755 currState->vaddr_tainted, currState->l1Desc.domain(), 1756 currState->isWrite, ArmFault::TranslationLL + L2, 1757 isStage2, 1758 ArmFault::VmsaTran); 1759 return; 1760 } 1761 1762 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 1763 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 1764 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 1765 */ 1766 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 1767 currState->sctlr.afe, currState->l2Desc.ap()); 1768 1769 currState->fault = std::make_shared<DataAbort>( 1770 currState->vaddr_tainted, 1771 TlbEntry::DomainType::NoAccess, currState->isWrite, 1772 ArmFault::AccessFlagLL + L2, isStage2, 1773 ArmFault::VmsaTran); 1774 } 1775 1776 insertTableEntry(currState->l2Desc, false); 1777} 1778 1779void 1780TableWalker::doL1DescriptorWrapper() 1781{ 1782 currState = stateQueues[L1].front(); 1783 currState->delayed = false; 1784 // if there's a stage2 translation object we don't need it any more 1785 if (currState->stage2Tran) { 1786 delete currState->stage2Tran; 1787 currState->stage2Tran = NULL; 1788 } 1789 1790 1791 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 1792 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 1793 1794 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 1795 doL1Descriptor(); 1796 1797 stateQueues[L1].pop_front(); 1798 // Check if fault was generated 1799 if (currState->fault != NoFault) { 1800 currState->transState->finish(currState->fault, currState->req, 1801 currState->tc, currState->mode); 1802 statWalksShortTerminatedAtLevel[0]++; 1803 1804 pending = false; 1805 nextWalk(currState->tc); 1806 1807 currState->req = NULL; 1808 currState->tc = NULL; 1809 currState->delayed = false; 1810 delete currState; 1811 } 1812 else if (!currState->delayed) { 1813 // delay is not set so there is no L2 to do 1814 // Don't finish the translation if a stage 2 look up is underway 1815 statWalkServiceTime.sample(curTick() - currState->startTime); 1816 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1817 tlb->translateTiming(currState->req, currState->tc, 1818 currState->transState, currState->mode); 1819 statWalksShortTerminatedAtLevel[0]++; 1820 1821 pending = false; 1822 nextWalk(currState->tc); 1823 1824 currState->req = NULL; 1825 currState->tc = NULL; 1826 currState->delayed = false; 1827 delete currState; 1828 } else { 1829 // need to do L2 descriptor 1830 stateQueues[L2].push_back(currState); 1831 } 1832 currState = NULL; 1833} 1834 1835void 1836TableWalker::doL2DescriptorWrapper() 1837{ 1838 currState = stateQueues[L2].front(); 1839 assert(currState->delayed); 1840 // if there's a stage2 translation object we don't need it any more 1841 if (currState->stage2Tran) { 1842 delete currState->stage2Tran; 1843 currState->stage2Tran = NULL; 1844 } 1845 1846 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 1847 currState->vaddr_tainted); 1848 doL2Descriptor(); 1849 1850 // Check if fault was generated 1851 if (currState->fault != NoFault) { 1852 currState->transState->finish(currState->fault, currState->req, 1853 currState->tc, currState->mode); 1854 statWalksShortTerminatedAtLevel[1]++; 1855 } else { 1856 statWalkServiceTime.sample(curTick() - currState->startTime); 1857 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1858 tlb->translateTiming(currState->req, currState->tc, 1859 currState->transState, currState->mode); 1860 statWalksShortTerminatedAtLevel[1]++; 1861 } 1862 1863 1864 stateQueues[L2].pop_front(); 1865 pending = false; 1866 nextWalk(currState->tc); 1867 1868 currState->req = NULL; 1869 currState->tc = NULL; 1870 currState->delayed = false; 1871 1872 delete currState; 1873 currState = NULL; 1874} 1875 1876void 1877TableWalker::doL0LongDescriptorWrapper() 1878{ 1879 doLongDescriptorWrapper(L0); 1880} 1881 1882void 1883TableWalker::doL1LongDescriptorWrapper() 1884{ 1885 doLongDescriptorWrapper(L1); 1886} 1887 1888void 1889TableWalker::doL2LongDescriptorWrapper() 1890{ 1891 doLongDescriptorWrapper(L2); 1892} 1893 1894void 1895TableWalker::doL3LongDescriptorWrapper() 1896{ 1897 doLongDescriptorWrapper(L3); 1898} 1899 1900void 1901TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 1902{ 1903 currState = stateQueues[curr_lookup_level].front(); 1904 assert(curr_lookup_level == currState->longDesc.lookupLevel); 1905 currState->delayed = false; 1906 1907 // if there's a stage2 translation object we don't need it any more 1908 if (currState->stage2Tran) { 1909 delete currState->stage2Tran; 1910 currState->stage2Tran = NULL; 1911 } 1912 1913 DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 1914 currState->vaddr_tainted); 1915 doLongDescriptor(); 1916 1917 stateQueues[curr_lookup_level].pop_front(); 1918 1919 if (currState->fault != NoFault) { 1920 // A fault was generated 1921 currState->transState->finish(currState->fault, currState->req, 1922 currState->tc, currState->mode); 1923 1924 pending = false; 1925 nextWalk(currState->tc); 1926 1927 currState->req = NULL; 1928 currState->tc = NULL; 1929 currState->delayed = false; 1930 delete currState; 1931 } else if (!currState->delayed) { 1932 // No additional lookups required 1933 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1934 statWalkServiceTime.sample(curTick() - currState->startTime); 1935 tlb->translateTiming(currState->req, currState->tc, 1936 currState->transState, currState->mode); 1937 statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 1938 1939 pending = false; 1940 nextWalk(currState->tc); 1941 1942 currState->req = NULL; 1943 currState->tc = NULL; 1944 currState->delayed = false; 1945 delete currState; 1946 } else { 1947 if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 1948 panic("Max. number of lookups already reached in table walk\n"); 1949 // Need to perform additional lookups 1950 stateQueues[currState->longDesc.lookupLevel].push_back(currState); 1951 } 1952 currState = NULL; 1953} 1954 1955 1956void 1957TableWalker::nextWalk(ThreadContext *tc) 1958{ 1959 if (pendingQueue.size()) 1960 schedule(doProcessEvent, clockEdge(Cycles(1))); 1961 else 1962 completeDrain(); 1963} 1964 1965bool 1966TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 1967 Request::Flags flags, int queueIndex, Event *event, 1968 void (TableWalker::*doDescriptor)()) 1969{ 1970 bool isTiming = currState->timing; 1971 1972 DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 1973 descAddr, currState->stage2Req); 1974 1975 // If this translation has a stage 2 then we know descAddr is an IPA and 1976 // needs to be translated before we can access the page table. Do that 1977 // check here. 1978 if (currState->stage2Req) { 1979 Fault fault; 1980 flags = flags | TLB::MustBeOne; 1981 1982 if (isTiming) { 1983 Stage2MMU::Stage2Translation *tran = new 1984 Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 1985 currState->vaddr); 1986 currState->stage2Tran = tran; 1987 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 1988 flags); 1989 fault = tran->fault; 1990 } else { 1991 fault = stage2Mmu->readDataUntimed(currState->tc, 1992 currState->vaddr, descAddr, data, numBytes, flags, 1993 currState->functional); 1994 } 1995 1996 if (fault != NoFault) { 1997 currState->fault = fault; 1998 } 1999 if (isTiming) { 2000 if (queueIndex >= 0) { 2001 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 2002 stateQueues[queueIndex].size()); 2003 stateQueues[queueIndex].push_back(currState); 2004 currState = NULL; 2005 } 2006 } else { 2007 (this->*doDescriptor)(); 2008 } 2009 } else { 2010 if (isTiming) { 2011 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 2012 currState->tc->getCpuPtr()->clockPeriod(),flags); 2013 if (queueIndex >= 0) { 2014 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 2015 stateQueues[queueIndex].size()); 2016 stateQueues[queueIndex].push_back(currState); 2017 currState = NULL; 2018 } 2019 } else if (!currState->functional) { 2020 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 2021 currState->tc->getCpuPtr()->clockPeriod(), flags); 2022 (this->*doDescriptor)(); 2023 } else { 2024 RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 2025 req->taskId(ContextSwitchTaskId::DMA); 2026 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2027 pkt->dataStatic(data); 2028 port->sendFunctional(pkt); 2029 (this->*doDescriptor)(); 2030 delete req; 2031 delete pkt; 2032 } 2033 } 2034 return (isTiming); 2035} 2036 2037void 2038TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 2039{ 2040 TlbEntry te; 2041 2042 // Create and fill a new page table entry 2043 te.valid = true; 2044 te.longDescFormat = longDescriptor; 2045 te.isHyp = currState->isHyp; 2046 te.asid = currState->asid; 2047 te.vmid = currState->vmid; 2048 te.N = descriptor.offsetBits(); 2049 te.vpn = currState->vaddr >> te.N; 2050 te.size = (1<<te.N) - 1; 2051 te.pfn = descriptor.pfn(); 2052 te.domain = descriptor.domain(); 2053 te.lookupLevel = descriptor.lookupLevel; 2054 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 2055 te.nstid = !currState->isSecure; 2056 te.xn = descriptor.xn(); 2057 if (currState->aarch64) 2058 te.el = currState->el; 2059 else 2060 te.el = 1; 2061 2062 statPageSizes[pageSizeNtoStatBin(te.N)]++; 2063 statRequestOrigin[COMPLETED][currState->isFetch]++; 2064 2065 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 2066 // as global 2067 te.global = descriptor.global(currState) || isStage2; 2068 if (longDescriptor) { 2069 LongDescriptor lDescriptor = 2070 dynamic_cast<LongDescriptor &>(descriptor); 2071 2072 te.xn |= currState->xnTable; 2073 te.pxn = currState->pxnTable || lDescriptor.pxn(); 2074 if (isStage2) { 2075 // this is actually the HAP field, but its stored in the same bit 2076 // possitions as the AP field in a stage 1 translation. 2077 te.hap = lDescriptor.ap(); 2078 } else { 2079 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 2080 (currState->userTable && (descriptor.ap() & 0x1)); 2081 } 2082 if (currState->aarch64) 2083 memAttrsAArch64(currState->tc, te, lDescriptor); 2084 else 2085 memAttrsLPAE(currState->tc, te, lDescriptor); 2086 } else { 2087 te.ap = descriptor.ap(); 2088 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 2089 descriptor.shareable()); 2090 } 2091 2092 // Debug output 2093 DPRINTF(TLB, descriptor.dbgHeader().c_str()); 2094 DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 2095 te.N, te.pfn, te.size, te.global, te.valid); 2096 DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 2097 "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 2098 te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 2099 te.nonCacheable, te.ns); 2100 DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 2101 descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 2102 descriptor.getRawData()); 2103 2104 // Insert the entry into the TLB 2105 tlb->insert(currState->vaddr, te); 2106 if (!currState->timing) { 2107 currState->tc = NULL; 2108 currState->req = NULL; 2109 } 2110} 2111 2112ArmISA::TableWalker * 2113ArmTableWalkerParams::create() 2114{ 2115 return new ArmISA::TableWalker(this); 2116} 2117 2118LookupLevel 2119TableWalker::toLookupLevel(uint8_t lookup_level_as_int) 2120{ 2121 switch (lookup_level_as_int) { 2122 case L1: 2123 return L1; 2124 case L2: 2125 return L2; 2126 case L3: 2127 return L3; 2128 default: 2129 panic("Invalid lookup level conversion"); 2130 } 2131} 2132 2133/* this method keeps track of the table walker queue's residency, so 2134 * needs to be called whenever requests start and complete. */ 2135void 2136TableWalker::pendingChange() 2137{ 2138 unsigned n = pendingQueue.size(); 2139 if ((currState != NULL) && (currState != pendingQueue.front())) { 2140 ++n; 2141 } 2142 2143 if (n != pendingReqs) { 2144 Tick now = curTick(); 2145 statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 2146 pendingReqs = n; 2147 pendingChangeTick = now; 2148 } 2149} 2150 2151Fault 2152TableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 2153 LookupLevel lookup_level) 2154{ 2155 return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 2156 currState->mode, domain, lookup_level); 2157} 2158 2159 2160uint8_t 2161TableWalker::pageSizeNtoStatBin(uint8_t N) 2162{ 2163 /* for statPageSizes */ 2164 switch(N) { 2165 case 12: return 0; // 4K 2166 case 14: return 1; // 16K (using 16K granule in v8-64) 2167 case 16: return 2; // 64K 2168 case 20: return 3; // 1M 2169 case 21: return 4; // 2M-LPAE 2170 case 24: return 5; // 16M 2171 case 25: return 6; // 32M (using 16K granule in v8-64) 2172 case 29: return 7; // 512M (using 64K granule in v8-64) 2173 case 30: return 8; // 1G-LPAE 2174 default: 2175 panic("unknown page size"); 2176 return 255; 2177 } 2178} 2179 2180void 2181TableWalker::regStats() 2182{ 2183 ClockedObject::regStats(); 2184 2185 statWalks 2186 .name(name() + ".walks") 2187 .desc("Table walker walks requested") 2188 ; 2189 2190 statWalksShortDescriptor 2191 .name(name() + ".walksShort") 2192 .desc("Table walker walks initiated with short descriptors") 2193 .flags(Stats::nozero) 2194 ; 2195 2196 statWalksLongDescriptor 2197 .name(name() + ".walksLong") 2198 .desc("Table walker walks initiated with long descriptors") 2199 .flags(Stats::nozero) 2200 ; 2201 2202 statWalksShortTerminatedAtLevel 2203 .init(2) 2204 .name(name() + ".walksShortTerminationLevel") 2205 .desc("Level at which table walker walks " 2206 "with short descriptors terminate") 2207 .flags(Stats::nozero) 2208 ; 2209 statWalksShortTerminatedAtLevel.subname(0, "Level1"); 2210 statWalksShortTerminatedAtLevel.subname(1, "Level2"); 2211 2212 statWalksLongTerminatedAtLevel 2213 .init(4) 2214 .name(name() + ".walksLongTerminationLevel") 2215 .desc("Level at which table walker walks " 2216 "with long descriptors terminate") 2217 .flags(Stats::nozero) 2218 ; 2219 statWalksLongTerminatedAtLevel.subname(0, "Level0"); 2220 statWalksLongTerminatedAtLevel.subname(1, "Level1"); 2221 statWalksLongTerminatedAtLevel.subname(2, "Level2"); 2222 statWalksLongTerminatedAtLevel.subname(3, "Level3"); 2223 2224 statSquashedBefore 2225 .name(name() + ".walksSquashedBefore") 2226 .desc("Table walks squashed before starting") 2227 .flags(Stats::nozero) 2228 ; 2229 2230 statSquashedAfter 2231 .name(name() + ".walksSquashedAfter") 2232 .desc("Table walks squashed after completion") 2233 .flags(Stats::nozero) 2234 ; 2235 2236 statWalkWaitTime 2237 .init(16) 2238 .name(name() + ".walkWaitTime") 2239 .desc("Table walker wait (enqueue to first request) latency") 2240 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2241 ; 2242 2243 statWalkServiceTime 2244 .init(16) 2245 .name(name() + ".walkCompletionTime") 2246 .desc("Table walker service (enqueue to completion) latency") 2247 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2248 ; 2249 2250 statPendingWalks 2251 .init(16) 2252 .name(name() + ".walksPending") 2253 .desc("Table walker pending requests distribution") 2254 .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 2255 ; 2256 2257 statPageSizes // see DDI 0487A D4-1661 2258 .init(9) 2259 .name(name() + ".walkPageSizes") 2260 .desc("Table walker page sizes translated") 2261 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 2262 ; 2263 statPageSizes.subname(0, "4K"); 2264 statPageSizes.subname(1, "16K"); 2265 statPageSizes.subname(2, "64K"); 2266 statPageSizes.subname(3, "1M"); 2267 statPageSizes.subname(4, "2M"); 2268 statPageSizes.subname(5, "16M"); 2269 statPageSizes.subname(6, "32M"); 2270 statPageSizes.subname(7, "512M"); 2271 statPageSizes.subname(8, "1G"); 2272 2273 statRequestOrigin 2274 .init(2,2) // Instruction/Data, requests/completed 2275 .name(name() + ".walkRequestOrigin") 2276 .desc("Table walker requests started/completed, data/inst") 2277 .flags(Stats::total) 2278 ; 2279 statRequestOrigin.subname(0,"Requested"); 2280 statRequestOrigin.subname(1,"Completed"); 2281 statRequestOrigin.ysubname(0,"Data"); 2282 statRequestOrigin.ysubname(1,"Inst"); 2283} 2284