table_walker.cc revision 9524
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437728SAli.Saidi@ARM.com#include "cpu/base.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 458245Snate@binkert.org#include "debug/Checkpoint.hh" 469152Satgutier@umich.edu#include "debug/Drain.hh" 478245Snate@binkert.org#include "debug/TLB.hh" 488245Snate@binkert.org#include "debug/TLBVerbose.hh" 497748SAli.Saidi@ARM.com#include "sim/system.hh" 507404SAli.Saidi@ARM.com 517404SAli.Saidi@ARM.comusing namespace ArmISA; 527404SAli.Saidi@ARM.com 537404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 549342SAndreas.Sandberg@arm.com : MemObject(p), port(this, params()->sys), drainManager(NULL), 558851Sandreas.hansson@arm.com tlb(NULL), currState(NULL), pending(false), 568832SAli.Saidi@ARM.com masterId(p->sys->getMasterId(name())), 579258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 587728SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 597439Sdam.sunwoo@arm.com{ 607576SAli.Saidi@ARM.com sctlr = 0; 617439Sdam.sunwoo@arm.com} 627404SAli.Saidi@ARM.com 637404SAli.Saidi@ARM.comTableWalker::~TableWalker() 647404SAli.Saidi@ARM.com{ 657404SAli.Saidi@ARM.com ; 667404SAli.Saidi@ARM.com} 677404SAli.Saidi@ARM.com 689152Satgutier@umich.eduvoid 699152Satgutier@umich.eduTableWalker::completeDrain() 709152Satgutier@umich.edu{ 719342SAndreas.Sandberg@arm.com if (drainManager && stateQueueL1.empty() && stateQueueL2.empty() && 729152Satgutier@umich.edu pendingQueue.empty()) { 739342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 749152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 759342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 769342SAndreas.Sandberg@arm.com drainManager = NULL; 779152Satgutier@umich.edu } 789152Satgutier@umich.edu} 799152Satgutier@umich.edu 807748SAli.Saidi@ARM.comunsigned int 819342SAndreas.Sandberg@arm.comTableWalker::drain(DrainManager *dm) 827404SAli.Saidi@ARM.com{ 839342SAndreas.Sandberg@arm.com unsigned int count = port.drain(dm); 849152Satgutier@umich.edu 859152Satgutier@umich.edu if (stateQueueL1.empty() && stateQueueL2.empty() && 869152Satgutier@umich.edu pendingQueue.empty()) { 879342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 889152Satgutier@umich.edu DPRINTF(Drain, "TableWalker free, no need to drain\n"); 899152Satgutier@umich.edu 909152Satgutier@umich.edu // table walker is drained, but its ports may still need to be drained 919152Satgutier@umich.edu return count; 929152Satgutier@umich.edu } else { 939342SAndreas.Sandberg@arm.com drainManager = dm; 949342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 959152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 969152Satgutier@umich.edu 979152Satgutier@umich.edu // return port drain count plus the table walker itself needs to drain 989152Satgutier@umich.edu return count + 1; 999152Satgutier@umich.edu 1007733SAli.Saidi@ARM.com } 1017404SAli.Saidi@ARM.com} 1027404SAli.Saidi@ARM.com 1037748SAli.Saidi@ARM.comvoid 1049342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1057748SAli.Saidi@ARM.com{ 1069342SAndreas.Sandberg@arm.com Drainable::drainResume(); 1079524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1089152Satgutier@umich.edu delete currState; 1099152Satgutier@umich.edu currState = NULL; 1107748SAli.Saidi@ARM.com } 1117748SAli.Saidi@ARM.com} 1127748SAli.Saidi@ARM.com 1139294Sandreas.hansson@arm.comBaseMasterPort& 1149294Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 1157404SAli.Saidi@ARM.com{ 1167404SAli.Saidi@ARM.com if (if_name == "port") { 1178922Swilliam.wang@arm.com return port; 1187404SAli.Saidi@ARM.com } 1198922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1207404SAli.Saidi@ARM.com} 1217404SAli.Saidi@ARM.com 1227404SAli.Saidi@ARM.comFault 1237437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 1248733Sgeoffrey.blake@arm.com TLB::Translation *_trans, bool _timing, bool _functional) 1257404SAli.Saidi@ARM.com{ 1268733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 1277439Sdam.sunwoo@arm.com if (!currState) { 1287439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1297439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1307439Sdam.sunwoo@arm.com // TLB miss. 1317439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1327404SAli.Saidi@ARM.com 1337439Sdam.sunwoo@arm.com currState = new WalkerState(); 1347439Sdam.sunwoo@arm.com currState->tableWalker = this; 1358202SAli.Saidi@ARM.com } else if (_timing) { 1368202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 1378202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 1388202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 1398202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 1408202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 1418202SAli.Saidi@ARM.com // up everything. 1428202SAli.Saidi@ARM.com if (currState->vaddr == _req->getVaddr()) { 1438202SAli.Saidi@ARM.com return new ReExec; 1448202SAli.Saidi@ARM.com } 1457439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 1467439Sdam.sunwoo@arm.com } 1477439Sdam.sunwoo@arm.com 1487439Sdam.sunwoo@arm.com currState->tc = _tc; 1497439Sdam.sunwoo@arm.com currState->transState = _trans; 1507439Sdam.sunwoo@arm.com currState->req = _req; 1517439Sdam.sunwoo@arm.com currState->fault = NoFault; 1527439Sdam.sunwoo@arm.com currState->contextId = _cid; 1537439Sdam.sunwoo@arm.com currState->timing = _timing; 1548733Sgeoffrey.blake@arm.com currState->functional = _functional; 1557439Sdam.sunwoo@arm.com currState->mode = _mode; 1567404SAli.Saidi@ARM.com 1577436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1587436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1597720Sgblack@eecs.umich.edu currState->vaddr = currState->req->getVaddr(); 1607439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1617439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1627439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1637439Sdam.sunwoo@arm.com 1647439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1657439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1667439Sdam.sunwoo@arm.com 1677728SAli.Saidi@ARM.com 1687728SAli.Saidi@ARM.com if (!currState->timing) 1697728SAli.Saidi@ARM.com return processWalk(); 1707728SAli.Saidi@ARM.com 1718067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 1727728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 1737728SAli.Saidi@ARM.com currState = NULL; 1747728SAli.Saidi@ARM.com } else { 1757728SAli.Saidi@ARM.com pending = true; 1768067SAli.Saidi@ARM.com return processWalk(); 1777728SAli.Saidi@ARM.com } 1787728SAli.Saidi@ARM.com 1797728SAli.Saidi@ARM.com return NoFault; 1807728SAli.Saidi@ARM.com} 1817728SAli.Saidi@ARM.com 1827728SAli.Saidi@ARM.comvoid 1837728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 1847728SAli.Saidi@ARM.com{ 1857728SAli.Saidi@ARM.com assert(!currState); 1867728SAli.Saidi@ARM.com assert(pendingQueue.size()); 1877728SAli.Saidi@ARM.com currState = pendingQueue.front(); 1889258SAli.Saidi@ARM.com 1899258SAli.Saidi@ARM.com 1909258SAli.Saidi@ARM.com if (!currState->transState->squashed()) { 1919258SAli.Saidi@ARM.com // We've got a valid request, lets process it 1929258SAli.Saidi@ARM.com pending = true; 1939258SAli.Saidi@ARM.com pendingQueue.pop_front(); 1949258SAli.Saidi@ARM.com processWalk(); 1959258SAli.Saidi@ARM.com return; 1969258SAli.Saidi@ARM.com } 1979258SAli.Saidi@ARM.com 1989258SAli.Saidi@ARM.com 1999258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 2009258SAli.Saidi@ARM.com // squashed we shouldn't bother. 2019258SAli.Saidi@ARM.com unsigned num_squashed = 0; 2029258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 2039258SAli.Saidi@ARM.com assert(currState->transState->squashed()); 2049258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 2059258SAli.Saidi@ARM.com currState->transState->squashed()) { 2069258SAli.Saidi@ARM.com pendingQueue.pop_front(); 2079258SAli.Saidi@ARM.com num_squashed++; 2089258SAli.Saidi@ARM.com 2099258SAli.Saidi@ARM.com DPRINTF(TLB, "Squashing table walk for address %#x\n", currState->vaddr); 2109258SAli.Saidi@ARM.com 2119258SAli.Saidi@ARM.com // finish the translation which will delete the translation object 2129258SAli.Saidi@ARM.com currState->transState->finish(new UnimpFault("Squashed Inst"), 2139258SAli.Saidi@ARM.com currState->req, currState->tc, currState->mode); 2149258SAli.Saidi@ARM.com 2159258SAli.Saidi@ARM.com // delete the current request 2169258SAli.Saidi@ARM.com delete currState; 2179258SAli.Saidi@ARM.com 2189258SAli.Saidi@ARM.com // peak at the next one 2199258SAli.Saidi@ARM.com if (pendingQueue.size()) 2209258SAli.Saidi@ARM.com currState = pendingQueue.front(); 2219258SAli.Saidi@ARM.com else 2229258SAli.Saidi@ARM.com currState = NULL; 2239258SAli.Saidi@ARM.com } 2249258SAli.Saidi@ARM.com 2259258SAli.Saidi@ARM.com // if we've still got pending translations schedule more work 2269258SAli.Saidi@ARM.com nextWalk(tc); 2279258SAli.Saidi@ARM.com currState = NULL; 2289438SAndreas.Sandberg@ARM.com completeDrain(); 2297728SAli.Saidi@ARM.com} 2307728SAli.Saidi@ARM.com 2317728SAli.Saidi@ARM.comFault 2327728SAli.Saidi@ARM.comTableWalker::processWalk() 2337728SAli.Saidi@ARM.com{ 2347404SAli.Saidi@ARM.com Addr ttbr = 0; 2357404SAli.Saidi@ARM.com 2367404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 2377439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 2387404SAli.Saidi@ARM.com 2397406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 2407439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 2417439Sdam.sunwoo@arm.com 32-currState->N)); 2427406SAli.Saidi@ARM.com 2437439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 2447406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 2457439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 2467404SAli.Saidi@ARM.com } else { 2477406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 2487439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 2497439Sdam.sunwoo@arm.com currState->N = 0; 2507404SAli.Saidi@ARM.com } 2517404SAli.Saidi@ARM.com 2527439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 2537439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 2547406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 2557404SAli.Saidi@ARM.com 2567404SAli.Saidi@ARM.com 2577404SAli.Saidi@ARM.com // Trickbox address check 2587439Sdam.sunwoo@arm.com Fault f; 2597439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 2607439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 2617439Sdam.sunwoo@arm.com if (f) { 2628067SAli.Saidi@ARM.com DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr); 2637579Sminkyu.jeong@arm.com if (currState->timing) { 2647728SAli.Saidi@ARM.com pending = false; 2657728SAli.Saidi@ARM.com nextWalk(currState->tc); 2667579Sminkyu.jeong@arm.com currState = NULL; 2677579Sminkyu.jeong@arm.com } else { 2687579Sminkyu.jeong@arm.com currState->tc = NULL; 2697579Sminkyu.jeong@arm.com currState->req = NULL; 2707579Sminkyu.jeong@arm.com } 2717579Sminkyu.jeong@arm.com return f; 2727404SAli.Saidi@ARM.com } 2737404SAli.Saidi@ARM.com 2747946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 2757946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 2767946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 2777946SGiacomo.Gabrielli@arm.com } 2787946SGiacomo.Gabrielli@arm.com 2797439Sdam.sunwoo@arm.com if (currState->timing) { 2808851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2818851Sandreas.hansson@arm.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 2829180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 2839180Sandreas.hansson@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before " 2849180Sandreas.hansson@arm.com "adding: %d\n", 2857653Sgene.wu@arm.com stateQueueL1.size()); 2867653Sgene.wu@arm.com stateQueueL1.push_back(currState); 2877439Sdam.sunwoo@arm.com currState = NULL; 2888733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 2898851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2908851Sandreas.hansson@arm.com NULL, (uint8_t*)&currState->l1Desc.data, 2919180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 2927404SAli.Saidi@ARM.com doL1Descriptor(); 2937439Sdam.sunwoo@arm.com f = currState->fault; 2948733Sgeoffrey.blake@arm.com } else { 2958832SAli.Saidi@ARM.com RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId); 2968949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2978733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l1Desc.data); 2988851Sandreas.hansson@arm.com port.sendFunctional(pkt); 2998733Sgeoffrey.blake@arm.com doL1Descriptor(); 3008733Sgeoffrey.blake@arm.com delete req; 3018733Sgeoffrey.blake@arm.com delete pkt; 3028733Sgeoffrey.blake@arm.com f = currState->fault; 3037404SAli.Saidi@ARM.com } 3047404SAli.Saidi@ARM.com 3057439Sdam.sunwoo@arm.com return f; 3067404SAli.Saidi@ARM.com} 3077404SAli.Saidi@ARM.com 3087404SAli.Saidi@ARM.comvoid 3097439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 3107439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 3117404SAli.Saidi@ARM.com{ 3127439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 3137439Sdam.sunwoo@arm.com // variables 3147436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 3157436Sdam.sunwoo@arm.com te.shareable = false; // default value 3167582SAli.Saidi@arm.com te.nonCacheable = false; 3177436Sdam.sunwoo@arm.com bool outer_shareable = false; 3187439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 3197404SAli.Saidi@ARM.com switch(texcb) { 3207436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 3217404SAli.Saidi@ARM.com te.nonCacheable = true; 3227436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3237436Sdam.sunwoo@arm.com te.shareable = true; 3247436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3257436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3267404SAli.Saidi@ARM.com break; 3277436Sdam.sunwoo@arm.com case 1: // Shareable Device 3287436Sdam.sunwoo@arm.com te.nonCacheable = true; 3297436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3307436Sdam.sunwoo@arm.com te.shareable = true; 3317436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3337436Sdam.sunwoo@arm.com break; 3347436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 3357436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3367436Sdam.sunwoo@arm.com te.shareable = s; 3377436Sdam.sunwoo@arm.com te.innerAttrs = 6; 3387436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 3397436Sdam.sunwoo@arm.com break; 3407436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 3417436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3427436Sdam.sunwoo@arm.com te.shareable = s; 3437436Sdam.sunwoo@arm.com te.innerAttrs = 7; 3447436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 3457436Sdam.sunwoo@arm.com break; 3467436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 3477436Sdam.sunwoo@arm.com te.nonCacheable = true; 3487436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3497436Sdam.sunwoo@arm.com te.shareable = s; 3507436Sdam.sunwoo@arm.com te.innerAttrs = 0; 3517436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 3527436Sdam.sunwoo@arm.com break; 3537436Sdam.sunwoo@arm.com case 5: // Reserved 3547439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3557436Sdam.sunwoo@arm.com break; 3567436Sdam.sunwoo@arm.com case 6: // Implementation Defined 3577439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 3587436Sdam.sunwoo@arm.com break; 3597436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 3607436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3617436Sdam.sunwoo@arm.com te.shareable = s; 3627436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3637436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3647436Sdam.sunwoo@arm.com break; 3657436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 3667436Sdam.sunwoo@arm.com te.nonCacheable = true; 3677436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3687436Sdam.sunwoo@arm.com te.shareable = false; 3697436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3707436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3717436Sdam.sunwoo@arm.com break; 3727436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 3737439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3747436Sdam.sunwoo@arm.com break; 3757436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 3767436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3777436Sdam.sunwoo@arm.com te.shareable = s; 3787404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 3797404SAli.Saidi@ARM.com te.nonCacheable = true; 3807436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 3817436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 3827404SAli.Saidi@ARM.com break; 3837436Sdam.sunwoo@arm.com default: 3847436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 3857404SAli.Saidi@ARM.com } 3867404SAli.Saidi@ARM.com } else { 3877438SAli.Saidi@ARM.com assert(tc); 3887404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3897404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3907436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 3917582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 3927404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 3937404SAli.Saidi@ARM.com case 0: 3947436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 3957436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 3967436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 3977436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 3987404SAli.Saidi@ARM.com break; 3997404SAli.Saidi@ARM.com case 1: 4007436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 4017436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 4027436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 4037436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 4047404SAli.Saidi@ARM.com break; 4057404SAli.Saidi@ARM.com case 2: 4067436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 4077436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 4087436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 4097436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 4107404SAli.Saidi@ARM.com break; 4117404SAli.Saidi@ARM.com case 3: 4127436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 4137436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 4147436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 4157436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 4167404SAli.Saidi@ARM.com break; 4177404SAli.Saidi@ARM.com case 4: 4187436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 4197436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 4207436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 4217436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 4227404SAli.Saidi@ARM.com break; 4237404SAli.Saidi@ARM.com case 5: 4247436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 4257436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 4267436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 4277436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 4287404SAli.Saidi@ARM.com break; 4297404SAli.Saidi@ARM.com case 6: 4307404SAli.Saidi@ARM.com panic("Imp defined type\n"); 4317404SAli.Saidi@ARM.com case 7: 4327436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 4337436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 4347436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 4357436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 4367404SAli.Saidi@ARM.com break; 4377404SAli.Saidi@ARM.com } 4387436Sdam.sunwoo@arm.com 4397436Sdam.sunwoo@arm.com switch(curr_tr) { 4407436Sdam.sunwoo@arm.com case 0: 4417436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 4427436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 4437436Sdam.sunwoo@arm.com te.nonCacheable = true; 4447436Sdam.sunwoo@arm.com te.innerAttrs = 1; 4457436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4467436Sdam.sunwoo@arm.com te.shareable = true; 4477436Sdam.sunwoo@arm.com break; 4487436Sdam.sunwoo@arm.com case 1: 4497436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 4507436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 4517436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 4527436Sdam.sunwoo@arm.com te.nonCacheable = true; 4537436Sdam.sunwoo@arm.com te.innerAttrs = 3; 4547436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4557436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 4567436Sdam.sunwoo@arm.com te.shareable = true; 4577436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 4587436Sdam.sunwoo@arm.com te.shareable = true; 4597436Sdam.sunwoo@arm.com break; 4607436Sdam.sunwoo@arm.com case 2: 4617436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 4627436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 4637436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 4647436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 4657436Sdam.sunwoo@arm.com te.shareable = true; 4667436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 4677436Sdam.sunwoo@arm.com te.shareable = true; 4687436Sdam.sunwoo@arm.com break; 4697436Sdam.sunwoo@arm.com case 3: 4707436Sdam.sunwoo@arm.com panic("Reserved type"); 4717436Sdam.sunwoo@arm.com } 4727436Sdam.sunwoo@arm.com 4737436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 4747436Sdam.sunwoo@arm.com switch(curr_ir) { 4757436Sdam.sunwoo@arm.com case 0: 4767436Sdam.sunwoo@arm.com te.nonCacheable = true; 4777436Sdam.sunwoo@arm.com te.innerAttrs = 0; 4787436Sdam.sunwoo@arm.com break; 4797436Sdam.sunwoo@arm.com case 1: 4807436Sdam.sunwoo@arm.com te.innerAttrs = 5; 4817436Sdam.sunwoo@arm.com break; 4827436Sdam.sunwoo@arm.com case 2: 4837436Sdam.sunwoo@arm.com te.innerAttrs = 6; 4847436Sdam.sunwoo@arm.com break; 4857436Sdam.sunwoo@arm.com case 3: 4867436Sdam.sunwoo@arm.com te.innerAttrs = 7; 4877436Sdam.sunwoo@arm.com break; 4887436Sdam.sunwoo@arm.com } 4897436Sdam.sunwoo@arm.com 4907436Sdam.sunwoo@arm.com switch(curr_or) { 4917436Sdam.sunwoo@arm.com case 0: 4927436Sdam.sunwoo@arm.com te.nonCacheable = true; 4937436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4947436Sdam.sunwoo@arm.com break; 4957436Sdam.sunwoo@arm.com case 1: 4967436Sdam.sunwoo@arm.com te.outerAttrs = 1; 4977436Sdam.sunwoo@arm.com break; 4987436Sdam.sunwoo@arm.com case 2: 4997436Sdam.sunwoo@arm.com te.outerAttrs = 2; 5007436Sdam.sunwoo@arm.com break; 5017436Sdam.sunwoo@arm.com case 3: 5027436Sdam.sunwoo@arm.com te.outerAttrs = 3; 5037436Sdam.sunwoo@arm.com break; 5047436Sdam.sunwoo@arm.com } 5057436Sdam.sunwoo@arm.com } 5067404SAli.Saidi@ARM.com } 5077439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 5087439Sdam.sunwoo@arm.com outerAttrs: %d\n", 5097439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 5107436Sdam.sunwoo@arm.com 5117436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 5127436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 5137436Sdam.sunwoo@arm.com * PAR: 5147436Sdam.sunwoo@arm.com * PA [31:12] 5157436Sdam.sunwoo@arm.com * Reserved [11] 5167436Sdam.sunwoo@arm.com * TLB info [10:1] 5177436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 5187436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 5197436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 5207436Sdam.sunwoo@arm.com * SH [7] (Sharable) 5217436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 5227436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 5237436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 5247436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 5257436Sdam.sunwoo@arm.com */ 5267436Sdam.sunwoo@arm.com te.attributes = ( 5277436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 5287436Sdam.sunwoo@arm.com // TODO: NS Bit 5297436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 5307436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 5317436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 5327436Sdam.sunwoo@arm.com // TODO: Supersection bit 5337436Sdam.sunwoo@arm.com // TODO: Fault bit 5347436Sdam.sunwoo@arm.com ); 5357436Sdam.sunwoo@arm.com 5367436Sdam.sunwoo@arm.com 5377404SAli.Saidi@ARM.com} 5387404SAli.Saidi@ARM.com 5397404SAli.Saidi@ARM.comvoid 5407404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 5417404SAli.Saidi@ARM.com{ 5427439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 5437439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 5447404SAli.Saidi@ARM.com TlbEntry te; 5457404SAli.Saidi@ARM.com 5467439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 5477404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 5487404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 5497946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 5507439Sdam.sunwoo@arm.com currState->tc = NULL; 5517439Sdam.sunwoo@arm.com currState->req = NULL; 5527437Sdam.sunwoo@arm.com } 5537406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 5547439Sdam.sunwoo@arm.com if (currState->isFetch) 5557439Sdam.sunwoo@arm.com currState->fault = 5567439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 5577406SAli.Saidi@ARM.com else 5587439Sdam.sunwoo@arm.com currState->fault = 5597576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5607436Sdam.sunwoo@arm.com ArmFault::Translation0); 5617404SAli.Saidi@ARM.com return; 5627404SAli.Saidi@ARM.com case L1Descriptor::Section: 5637439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 5647436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 5657436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 5667436Sdam.sunwoo@arm.com * AccessFlag0 5677436Sdam.sunwoo@arm.com */ 5687436Sdam.sunwoo@arm.com 5697611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 5707611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 5717436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 5727436Sdam.sunwoo@arm.com } 5737439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 5747404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 5757404SAli.Saidi@ARM.com } 5767404SAli.Saidi@ARM.com te.N = 20; 5777439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 5787404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 5797439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 5807404SAli.Saidi@ARM.com te.valid = true; 5817439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5827404SAli.Saidi@ARM.com te.sNp = true; 5837439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 5847439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 5857439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5867439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5877439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 5887439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 5897404SAli.Saidi@ARM.com 5907404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 5917582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 5927404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 5937582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 5947582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 5957582SAli.Saidi@arm.com te.nonCacheable); 5967404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 5977439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 5987439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 5997404SAli.Saidi@ARM.com 6007439Sdam.sunwoo@arm.com if (!currState->timing) { 6017439Sdam.sunwoo@arm.com currState->tc = NULL; 6027439Sdam.sunwoo@arm.com currState->req = NULL; 6037437Sdam.sunwoo@arm.com } 6047439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 6057404SAli.Saidi@ARM.com 6067404SAli.Saidi@ARM.com return; 6077404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 6087404SAli.Saidi@ARM.com Addr l2desc_addr; 6097439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 6107439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 6117436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 6127436Sdam.sunwoo@arm.com l2desc_addr); 6137404SAli.Saidi@ARM.com 6147404SAli.Saidi@ARM.com // Trickbox address check 6157439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 6167439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 6177439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 6187439Sdam.sunwoo@arm.com 6197439Sdam.sunwoo@arm.com if (currState->fault) { 6207439Sdam.sunwoo@arm.com if (!currState->timing) { 6217439Sdam.sunwoo@arm.com currState->tc = NULL; 6227439Sdam.sunwoo@arm.com currState->req = NULL; 6237437Sdam.sunwoo@arm.com } 6247437Sdam.sunwoo@arm.com return; 6257404SAli.Saidi@ARM.com } 6267404SAli.Saidi@ARM.com 6277404SAli.Saidi@ARM.com 6287439Sdam.sunwoo@arm.com if (currState->timing) { 6297439Sdam.sunwoo@arm.com currState->delayed = true; 6308851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 6319180Sandreas.hansson@arm.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 6329180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod()); 6338733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 6348851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 6359180Sandreas.hansson@arm.com NULL, (uint8_t*)&currState->l2Desc.data, 6369180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod()); 6377404SAli.Saidi@ARM.com doL2Descriptor(); 6388733Sgeoffrey.blake@arm.com } else { 6398949Sandreas.hansson@arm.com RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, 6408949Sandreas.hansson@arm.com masterId); 6418949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 6428733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l2Desc.data); 6438851Sandreas.hansson@arm.com port.sendFunctional(pkt); 6448733Sgeoffrey.blake@arm.com doL2Descriptor(); 6458733Sgeoffrey.blake@arm.com delete req; 6468733Sgeoffrey.blake@arm.com delete pkt; 6477404SAli.Saidi@ARM.com } 6487404SAli.Saidi@ARM.com return; 6497404SAli.Saidi@ARM.com default: 6507404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 6517404SAli.Saidi@ARM.com } 6527404SAli.Saidi@ARM.com} 6537404SAli.Saidi@ARM.com 6547404SAli.Saidi@ARM.comvoid 6557404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 6567404SAli.Saidi@ARM.com{ 6577439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 6587439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 6597404SAli.Saidi@ARM.com TlbEntry te; 6607404SAli.Saidi@ARM.com 6617439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 6627404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 6637946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6647439Sdam.sunwoo@arm.com currState->tc = NULL; 6657439Sdam.sunwoo@arm.com currState->req = NULL; 6667437Sdam.sunwoo@arm.com } 6677439Sdam.sunwoo@arm.com if (currState->isFetch) 6687439Sdam.sunwoo@arm.com currState->fault = 6697439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 6707406SAli.Saidi@ARM.com else 6717439Sdam.sunwoo@arm.com currState->fault = 6727439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 6737439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 6747404SAli.Saidi@ARM.com return; 6757404SAli.Saidi@ARM.com } 6767404SAli.Saidi@ARM.com 6777439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 6787436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 6797436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 6807436Sdam.sunwoo@arm.com */ 6817436Sdam.sunwoo@arm.com 6827439Sdam.sunwoo@arm.com currState->fault = 6837576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 6847439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 6857439Sdam.sunwoo@arm.com 6867436Sdam.sunwoo@arm.com } 6877436Sdam.sunwoo@arm.com 6887439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 6897404SAli.Saidi@ARM.com te.N = 16; 6907439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6917404SAli.Saidi@ARM.com } else { 6927404SAli.Saidi@ARM.com te.N = 12; 6937439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6947404SAli.Saidi@ARM.com } 6957404SAli.Saidi@ARM.com 6967404SAli.Saidi@ARM.com te.valid = true; 6977404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 6987439Sdam.sunwoo@arm.com te.asid = currState->contextId; 6997404SAli.Saidi@ARM.com te.sNp = false; 7007439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 7017439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 7027439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 7037439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 7047439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 7057439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 7067439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 7077404SAli.Saidi@ARM.com 7087946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 7097439Sdam.sunwoo@arm.com currState->tc = NULL; 7107439Sdam.sunwoo@arm.com currState->req = NULL; 7117437Sdam.sunwoo@arm.com } 7127439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 7137437Sdam.sunwoo@arm.com} 7147437Sdam.sunwoo@arm.com 7157437Sdam.sunwoo@arm.comvoid 7167437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 7177437Sdam.sunwoo@arm.com{ 7187653Sgene.wu@arm.com currState = stateQueueL1.front(); 7197439Sdam.sunwoo@arm.com currState->delayed = false; 7207437Sdam.sunwoo@arm.com 7217578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 7227578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 7237578Sdam.sunwoo@arm.com 7247439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 7257437Sdam.sunwoo@arm.com doL1Descriptor(); 7267437Sdam.sunwoo@arm.com 7277653Sgene.wu@arm.com stateQueueL1.pop_front(); 7289152Satgutier@umich.edu completeDrain(); 7297437Sdam.sunwoo@arm.com // Check if fault was generated 7307439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 7317439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 7327439Sdam.sunwoo@arm.com currState->tc, currState->mode); 7337437Sdam.sunwoo@arm.com 7347728SAli.Saidi@ARM.com pending = false; 7357728SAli.Saidi@ARM.com nextWalk(currState->tc); 7367728SAli.Saidi@ARM.com 7377439Sdam.sunwoo@arm.com currState->req = NULL; 7387439Sdam.sunwoo@arm.com currState->tc = NULL; 7397439Sdam.sunwoo@arm.com currState->delayed = false; 7408510SAli.Saidi@ARM.com delete currState; 7417437Sdam.sunwoo@arm.com } 7427439Sdam.sunwoo@arm.com else if (!currState->delayed) { 7437653Sgene.wu@arm.com // delay is not set so there is no L2 to do 7447437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7457439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7467439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7477437Sdam.sunwoo@arm.com 7487728SAli.Saidi@ARM.com pending = false; 7497728SAli.Saidi@ARM.com nextWalk(currState->tc); 7507728SAli.Saidi@ARM.com 7517439Sdam.sunwoo@arm.com currState->req = NULL; 7527439Sdam.sunwoo@arm.com currState->tc = NULL; 7537439Sdam.sunwoo@arm.com currState->delayed = false; 7547653Sgene.wu@arm.com delete currState; 7557653Sgene.wu@arm.com } else { 7567653Sgene.wu@arm.com // need to do L2 descriptor 7577653Sgene.wu@arm.com stateQueueL2.push_back(currState); 7587437Sdam.sunwoo@arm.com } 7597439Sdam.sunwoo@arm.com currState = NULL; 7607437Sdam.sunwoo@arm.com} 7617437Sdam.sunwoo@arm.com 7627437Sdam.sunwoo@arm.comvoid 7637437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 7647437Sdam.sunwoo@arm.com{ 7657653Sgene.wu@arm.com currState = stateQueueL2.front(); 7667439Sdam.sunwoo@arm.com assert(currState->delayed); 7677437Sdam.sunwoo@arm.com 7687439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 7697439Sdam.sunwoo@arm.com currState->vaddr); 7707437Sdam.sunwoo@arm.com doL2Descriptor(); 7717437Sdam.sunwoo@arm.com 7727437Sdam.sunwoo@arm.com // Check if fault was generated 7737439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 7747439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 7757439Sdam.sunwoo@arm.com currState->tc, currState->mode); 7767437Sdam.sunwoo@arm.com } 7777437Sdam.sunwoo@arm.com else { 7787437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7797439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7807439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7817437Sdam.sunwoo@arm.com } 7827437Sdam.sunwoo@arm.com 7837728SAli.Saidi@ARM.com 7847728SAli.Saidi@ARM.com stateQueueL2.pop_front(); 7859152Satgutier@umich.edu completeDrain(); 7867728SAli.Saidi@ARM.com pending = false; 7877728SAli.Saidi@ARM.com nextWalk(currState->tc); 7887728SAli.Saidi@ARM.com 7897439Sdam.sunwoo@arm.com currState->req = NULL; 7907439Sdam.sunwoo@arm.com currState->tc = NULL; 7917439Sdam.sunwoo@arm.com currState->delayed = false; 7927439Sdam.sunwoo@arm.com 7937653Sgene.wu@arm.com delete currState; 7947439Sdam.sunwoo@arm.com currState = NULL; 7957404SAli.Saidi@ARM.com} 7967404SAli.Saidi@ARM.com 7977728SAli.Saidi@ARM.comvoid 7987728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 7997728SAli.Saidi@ARM.com{ 8007728SAli.Saidi@ARM.com if (pendingQueue.size()) 8019309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 8027728SAli.Saidi@ARM.com} 8037728SAli.Saidi@ARM.com 8047728SAli.Saidi@ARM.com 8057728SAli.Saidi@ARM.com 8067404SAli.Saidi@ARM.comArmISA::TableWalker * 8077404SAli.Saidi@ARM.comArmTableWalkerParams::create() 8087404SAli.Saidi@ARM.com{ 8097404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 8107404SAli.Saidi@ARM.com} 8117404SAli.Saidi@ARM.com 812