table_walker.cc revision 9180
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437728SAli.Saidi@ARM.com#include "cpu/base.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 458245Snate@binkert.org#include "debug/Checkpoint.hh" 469152Satgutier@umich.edu#include "debug/Drain.hh" 478245Snate@binkert.org#include "debug/TLB.hh" 488245Snate@binkert.org#include "debug/TLBVerbose.hh" 497748SAli.Saidi@ARM.com#include "sim/system.hh" 507404SAli.Saidi@ARM.com 517404SAli.Saidi@ARM.comusing namespace ArmISA; 527404SAli.Saidi@ARM.com 537404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 549165Sandreas.hansson@arm.com : MemObject(p), port(this, params()->sys), drainEvent(NULL), 558851Sandreas.hansson@arm.com tlb(NULL), currState(NULL), pending(false), 568832SAli.Saidi@ARM.com masterId(p->sys->getMasterId(name())), 577728SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 587439Sdam.sunwoo@arm.com{ 597576SAli.Saidi@ARM.com sctlr = 0; 607439Sdam.sunwoo@arm.com} 617404SAli.Saidi@ARM.com 627404SAli.Saidi@ARM.comTableWalker::~TableWalker() 637404SAli.Saidi@ARM.com{ 647404SAli.Saidi@ARM.com ; 657404SAli.Saidi@ARM.com} 667404SAli.Saidi@ARM.com 679152Satgutier@umich.eduvoid 689152Satgutier@umich.eduTableWalker::completeDrain() 699152Satgutier@umich.edu{ 709152Satgutier@umich.edu if (drainEvent && stateQueueL1.empty() && stateQueueL2.empty() && 719152Satgutier@umich.edu pendingQueue.empty()) { 729152Satgutier@umich.edu changeState(Drained); 739152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 749152Satgutier@umich.edu drainEvent->process(); 759152Satgutier@umich.edu drainEvent = NULL; 769152Satgutier@umich.edu } 779152Satgutier@umich.edu} 789152Satgutier@umich.edu 797748SAli.Saidi@ARM.comunsigned int 807748SAli.Saidi@ARM.comTableWalker::drain(Event *de) 817404SAli.Saidi@ARM.com{ 829152Satgutier@umich.edu unsigned int count = port.drain(de); 839152Satgutier@umich.edu 849152Satgutier@umich.edu if (stateQueueL1.empty() && stateQueueL2.empty() && 859152Satgutier@umich.edu pendingQueue.empty()) { 869152Satgutier@umich.edu changeState(Drained); 879152Satgutier@umich.edu DPRINTF(Drain, "TableWalker free, no need to drain\n"); 889152Satgutier@umich.edu 899152Satgutier@umich.edu // table walker is drained, but its ports may still need to be drained 909152Satgutier@umich.edu return count; 919152Satgutier@umich.edu } else { 929152Satgutier@umich.edu drainEvent = de; 937733SAli.Saidi@ARM.com changeState(Draining); 949152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 959152Satgutier@umich.edu 969152Satgutier@umich.edu // return port drain count plus the table walker itself needs to drain 979152Satgutier@umich.edu return count + 1; 989152Satgutier@umich.edu 997733SAli.Saidi@ARM.com } 1007404SAli.Saidi@ARM.com} 1017404SAli.Saidi@ARM.com 1027748SAli.Saidi@ARM.comvoid 1037748SAli.Saidi@ARM.comTableWalker::resume() 1047748SAli.Saidi@ARM.com{ 1057748SAli.Saidi@ARM.com MemObject::resume(); 1067748SAli.Saidi@ARM.com if ((params()->sys->getMemoryMode() == Enums::timing) && currState) { 1079152Satgutier@umich.edu delete currState; 1089152Satgutier@umich.edu currState = NULL; 1097748SAli.Saidi@ARM.com } 1107748SAli.Saidi@ARM.com} 1117748SAli.Saidi@ARM.com 1128922Swilliam.wang@arm.comMasterPort& 1138922Swilliam.wang@arm.comTableWalker::getMasterPort(const std::string &if_name, int idx) 1147404SAli.Saidi@ARM.com{ 1157404SAli.Saidi@ARM.com if (if_name == "port") { 1168922Swilliam.wang@arm.com return port; 1177404SAli.Saidi@ARM.com } 1188922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1197404SAli.Saidi@ARM.com} 1207404SAli.Saidi@ARM.com 1217404SAli.Saidi@ARM.comFault 1227437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 1238733Sgeoffrey.blake@arm.com TLB::Translation *_trans, bool _timing, bool _functional) 1247404SAli.Saidi@ARM.com{ 1258733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 1267439Sdam.sunwoo@arm.com if (!currState) { 1277439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1287439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1297439Sdam.sunwoo@arm.com // TLB miss. 1307439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1317404SAli.Saidi@ARM.com 1327439Sdam.sunwoo@arm.com currState = new WalkerState(); 1337439Sdam.sunwoo@arm.com currState->tableWalker = this; 1348202SAli.Saidi@ARM.com } else if (_timing) { 1358202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 1368202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 1378202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 1388202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 1398202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 1408202SAli.Saidi@ARM.com // up everything. 1418202SAli.Saidi@ARM.com if (currState->vaddr == _req->getVaddr()) { 1428202SAli.Saidi@ARM.com return new ReExec; 1438202SAli.Saidi@ARM.com } 1447439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 1457439Sdam.sunwoo@arm.com } 1467439Sdam.sunwoo@arm.com 1477439Sdam.sunwoo@arm.com currState->tc = _tc; 1487439Sdam.sunwoo@arm.com currState->transState = _trans; 1497439Sdam.sunwoo@arm.com currState->req = _req; 1507439Sdam.sunwoo@arm.com currState->fault = NoFault; 1517439Sdam.sunwoo@arm.com currState->contextId = _cid; 1527439Sdam.sunwoo@arm.com currState->timing = _timing; 1538733Sgeoffrey.blake@arm.com currState->functional = _functional; 1547439Sdam.sunwoo@arm.com currState->mode = _mode; 1557404SAli.Saidi@ARM.com 1567436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1577436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1587720Sgblack@eecs.umich.edu currState->vaddr = currState->req->getVaddr(); 1597439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1607439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1617439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1627439Sdam.sunwoo@arm.com 1637439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1647439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1657439Sdam.sunwoo@arm.com 1667728SAli.Saidi@ARM.com 1677728SAli.Saidi@ARM.com if (!currState->timing) 1687728SAli.Saidi@ARM.com return processWalk(); 1697728SAli.Saidi@ARM.com 1708067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 1717728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 1727728SAli.Saidi@ARM.com currState = NULL; 1737728SAli.Saidi@ARM.com } else { 1747728SAli.Saidi@ARM.com pending = true; 1758067SAli.Saidi@ARM.com return processWalk(); 1767728SAli.Saidi@ARM.com } 1777728SAli.Saidi@ARM.com 1787728SAli.Saidi@ARM.com return NoFault; 1797728SAli.Saidi@ARM.com} 1807728SAli.Saidi@ARM.com 1817728SAli.Saidi@ARM.comvoid 1827728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 1837728SAli.Saidi@ARM.com{ 1847728SAli.Saidi@ARM.com assert(!currState); 1857728SAli.Saidi@ARM.com assert(pendingQueue.size()); 1867728SAli.Saidi@ARM.com currState = pendingQueue.front(); 1877728SAli.Saidi@ARM.com pendingQueue.pop_front(); 1887728SAli.Saidi@ARM.com pending = true; 1897728SAli.Saidi@ARM.com processWalk(); 1907728SAli.Saidi@ARM.com} 1917728SAli.Saidi@ARM.com 1927728SAli.Saidi@ARM.comFault 1937728SAli.Saidi@ARM.comTableWalker::processWalk() 1947728SAli.Saidi@ARM.com{ 1957404SAli.Saidi@ARM.com Addr ttbr = 0; 1967404SAli.Saidi@ARM.com 1977404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1987439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1997404SAli.Saidi@ARM.com 2007406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 2017439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 2027439Sdam.sunwoo@arm.com 32-currState->N)); 2037406SAli.Saidi@ARM.com 2047439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 2057406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 2067439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 2077404SAli.Saidi@ARM.com } else { 2087406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 2097439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 2107439Sdam.sunwoo@arm.com currState->N = 0; 2117404SAli.Saidi@ARM.com } 2127404SAli.Saidi@ARM.com 2137439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 2147439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 2157406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 2167404SAli.Saidi@ARM.com 2177404SAli.Saidi@ARM.com 2187404SAli.Saidi@ARM.com // Trickbox address check 2197439Sdam.sunwoo@arm.com Fault f; 2207439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 2217439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 2227439Sdam.sunwoo@arm.com if (f) { 2238067SAli.Saidi@ARM.com DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr); 2247579Sminkyu.jeong@arm.com if (currState->timing) { 2257728SAli.Saidi@ARM.com pending = false; 2267728SAli.Saidi@ARM.com nextWalk(currState->tc); 2277579Sminkyu.jeong@arm.com currState = NULL; 2287579Sminkyu.jeong@arm.com } else { 2297579Sminkyu.jeong@arm.com currState->tc = NULL; 2307579Sminkyu.jeong@arm.com currState->req = NULL; 2317579Sminkyu.jeong@arm.com } 2327579Sminkyu.jeong@arm.com return f; 2337404SAli.Saidi@ARM.com } 2347404SAli.Saidi@ARM.com 2357946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 2367946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 2377946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 2387946SGiacomo.Gabrielli@arm.com } 2397946SGiacomo.Gabrielli@arm.com 2407439Sdam.sunwoo@arm.com if (currState->timing) { 2418851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2428851Sandreas.hansson@arm.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 2439180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 2449180Sandreas.hansson@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before " 2459180Sandreas.hansson@arm.com "adding: %d\n", 2467653Sgene.wu@arm.com stateQueueL1.size()); 2477653Sgene.wu@arm.com stateQueueL1.push_back(currState); 2487439Sdam.sunwoo@arm.com currState = NULL; 2498733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 2508851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2518851Sandreas.hansson@arm.com NULL, (uint8_t*)&currState->l1Desc.data, 2529180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 2537404SAli.Saidi@ARM.com doL1Descriptor(); 2547439Sdam.sunwoo@arm.com f = currState->fault; 2558733Sgeoffrey.blake@arm.com } else { 2568832SAli.Saidi@ARM.com RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId); 2578949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2588733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l1Desc.data); 2598851Sandreas.hansson@arm.com port.sendFunctional(pkt); 2608733Sgeoffrey.blake@arm.com doL1Descriptor(); 2618733Sgeoffrey.blake@arm.com delete req; 2628733Sgeoffrey.blake@arm.com delete pkt; 2638733Sgeoffrey.blake@arm.com f = currState->fault; 2647404SAli.Saidi@ARM.com } 2657404SAli.Saidi@ARM.com 2667439Sdam.sunwoo@arm.com return f; 2677404SAli.Saidi@ARM.com} 2687404SAli.Saidi@ARM.com 2697404SAli.Saidi@ARM.comvoid 2707439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 2717439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 2727404SAli.Saidi@ARM.com{ 2737439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 2747439Sdam.sunwoo@arm.com // variables 2757436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 2767436Sdam.sunwoo@arm.com te.shareable = false; // default value 2777582SAli.Saidi@arm.com te.nonCacheable = false; 2787436Sdam.sunwoo@arm.com bool outer_shareable = false; 2797439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 2807404SAli.Saidi@ARM.com switch(texcb) { 2817436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 2827404SAli.Saidi@ARM.com te.nonCacheable = true; 2837436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 2847436Sdam.sunwoo@arm.com te.shareable = true; 2857436Sdam.sunwoo@arm.com te.innerAttrs = 1; 2867436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2877404SAli.Saidi@ARM.com break; 2887436Sdam.sunwoo@arm.com case 1: // Shareable Device 2897436Sdam.sunwoo@arm.com te.nonCacheable = true; 2907436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2917436Sdam.sunwoo@arm.com te.shareable = true; 2927436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2937436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2947436Sdam.sunwoo@arm.com break; 2957436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 2967436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2977436Sdam.sunwoo@arm.com te.shareable = s; 2987436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2997436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 3007436Sdam.sunwoo@arm.com break; 3017436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 3027436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3037436Sdam.sunwoo@arm.com te.shareable = s; 3047436Sdam.sunwoo@arm.com te.innerAttrs = 7; 3057436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 3067436Sdam.sunwoo@arm.com break; 3077436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 3087436Sdam.sunwoo@arm.com te.nonCacheable = true; 3097436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3107436Sdam.sunwoo@arm.com te.shareable = s; 3117436Sdam.sunwoo@arm.com te.innerAttrs = 0; 3127436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 3137436Sdam.sunwoo@arm.com break; 3147436Sdam.sunwoo@arm.com case 5: // Reserved 3157439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3167436Sdam.sunwoo@arm.com break; 3177436Sdam.sunwoo@arm.com case 6: // Implementation Defined 3187439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 3197436Sdam.sunwoo@arm.com break; 3207436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 3217436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3227436Sdam.sunwoo@arm.com te.shareable = s; 3237436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3247436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3257436Sdam.sunwoo@arm.com break; 3267436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 3277436Sdam.sunwoo@arm.com te.nonCacheable = true; 3287436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3297436Sdam.sunwoo@arm.com te.shareable = false; 3307436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3317436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3327436Sdam.sunwoo@arm.com break; 3337436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 3347439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3357436Sdam.sunwoo@arm.com break; 3367436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 3377436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3387436Sdam.sunwoo@arm.com te.shareable = s; 3397404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 3407404SAli.Saidi@ARM.com te.nonCacheable = true; 3417436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 3427436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 3437404SAli.Saidi@ARM.com break; 3447436Sdam.sunwoo@arm.com default: 3457436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 3467404SAli.Saidi@ARM.com } 3477404SAli.Saidi@ARM.com } else { 3487438SAli.Saidi@ARM.com assert(tc); 3497404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3507404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3517436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 3527582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 3537404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 3547404SAli.Saidi@ARM.com case 0: 3557436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 3567436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 3577436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 3587436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 3597404SAli.Saidi@ARM.com break; 3607404SAli.Saidi@ARM.com case 1: 3617436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 3627436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 3637436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 3647436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 3657404SAli.Saidi@ARM.com break; 3667404SAli.Saidi@ARM.com case 2: 3677436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 3687436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 3697436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 3707436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 3717404SAli.Saidi@ARM.com break; 3727404SAli.Saidi@ARM.com case 3: 3737436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 3747436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 3757436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 3767436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 3777404SAli.Saidi@ARM.com break; 3787404SAli.Saidi@ARM.com case 4: 3797436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 3807436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 3817436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 3827436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 3837404SAli.Saidi@ARM.com break; 3847404SAli.Saidi@ARM.com case 5: 3857436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 3867436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 3877436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 3887436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 3897404SAli.Saidi@ARM.com break; 3907404SAli.Saidi@ARM.com case 6: 3917404SAli.Saidi@ARM.com panic("Imp defined type\n"); 3927404SAli.Saidi@ARM.com case 7: 3937436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 3947436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 3957436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 3967436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 3977404SAli.Saidi@ARM.com break; 3987404SAli.Saidi@ARM.com } 3997436Sdam.sunwoo@arm.com 4007436Sdam.sunwoo@arm.com switch(curr_tr) { 4017436Sdam.sunwoo@arm.com case 0: 4027436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 4037436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 4047436Sdam.sunwoo@arm.com te.nonCacheable = true; 4057436Sdam.sunwoo@arm.com te.innerAttrs = 1; 4067436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4077436Sdam.sunwoo@arm.com te.shareable = true; 4087436Sdam.sunwoo@arm.com break; 4097436Sdam.sunwoo@arm.com case 1: 4107436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 4117436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 4127436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 4137436Sdam.sunwoo@arm.com te.nonCacheable = true; 4147436Sdam.sunwoo@arm.com te.innerAttrs = 3; 4157436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4167436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 4177436Sdam.sunwoo@arm.com te.shareable = true; 4187436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 4197436Sdam.sunwoo@arm.com te.shareable = true; 4207436Sdam.sunwoo@arm.com break; 4217436Sdam.sunwoo@arm.com case 2: 4227436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 4237436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 4247436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 4257436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 4267436Sdam.sunwoo@arm.com te.shareable = true; 4277436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 4287436Sdam.sunwoo@arm.com te.shareable = true; 4297436Sdam.sunwoo@arm.com break; 4307436Sdam.sunwoo@arm.com case 3: 4317436Sdam.sunwoo@arm.com panic("Reserved type"); 4327436Sdam.sunwoo@arm.com } 4337436Sdam.sunwoo@arm.com 4347436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 4357436Sdam.sunwoo@arm.com switch(curr_ir) { 4367436Sdam.sunwoo@arm.com case 0: 4377436Sdam.sunwoo@arm.com te.nonCacheable = true; 4387436Sdam.sunwoo@arm.com te.innerAttrs = 0; 4397436Sdam.sunwoo@arm.com break; 4407436Sdam.sunwoo@arm.com case 1: 4417436Sdam.sunwoo@arm.com te.innerAttrs = 5; 4427436Sdam.sunwoo@arm.com break; 4437436Sdam.sunwoo@arm.com case 2: 4447436Sdam.sunwoo@arm.com te.innerAttrs = 6; 4457436Sdam.sunwoo@arm.com break; 4467436Sdam.sunwoo@arm.com case 3: 4477436Sdam.sunwoo@arm.com te.innerAttrs = 7; 4487436Sdam.sunwoo@arm.com break; 4497436Sdam.sunwoo@arm.com } 4507436Sdam.sunwoo@arm.com 4517436Sdam.sunwoo@arm.com switch(curr_or) { 4527436Sdam.sunwoo@arm.com case 0: 4537436Sdam.sunwoo@arm.com te.nonCacheable = true; 4547436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4557436Sdam.sunwoo@arm.com break; 4567436Sdam.sunwoo@arm.com case 1: 4577436Sdam.sunwoo@arm.com te.outerAttrs = 1; 4587436Sdam.sunwoo@arm.com break; 4597436Sdam.sunwoo@arm.com case 2: 4607436Sdam.sunwoo@arm.com te.outerAttrs = 2; 4617436Sdam.sunwoo@arm.com break; 4627436Sdam.sunwoo@arm.com case 3: 4637436Sdam.sunwoo@arm.com te.outerAttrs = 3; 4647436Sdam.sunwoo@arm.com break; 4657436Sdam.sunwoo@arm.com } 4667436Sdam.sunwoo@arm.com } 4677404SAli.Saidi@ARM.com } 4687439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 4697439Sdam.sunwoo@arm.com outerAttrs: %d\n", 4707439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 4717436Sdam.sunwoo@arm.com 4727436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 4737436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 4747436Sdam.sunwoo@arm.com * PAR: 4757436Sdam.sunwoo@arm.com * PA [31:12] 4767436Sdam.sunwoo@arm.com * Reserved [11] 4777436Sdam.sunwoo@arm.com * TLB info [10:1] 4787436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 4797436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 4807436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 4817436Sdam.sunwoo@arm.com * SH [7] (Sharable) 4827436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 4837436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 4847436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 4857436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 4867436Sdam.sunwoo@arm.com */ 4877436Sdam.sunwoo@arm.com te.attributes = ( 4887436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 4897436Sdam.sunwoo@arm.com // TODO: NS Bit 4907436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 4917436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 4927436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 4937436Sdam.sunwoo@arm.com // TODO: Supersection bit 4947436Sdam.sunwoo@arm.com // TODO: Fault bit 4957436Sdam.sunwoo@arm.com ); 4967436Sdam.sunwoo@arm.com 4977436Sdam.sunwoo@arm.com 4987404SAli.Saidi@ARM.com} 4997404SAli.Saidi@ARM.com 5007404SAli.Saidi@ARM.comvoid 5017404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 5027404SAli.Saidi@ARM.com{ 5037439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 5047439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 5057404SAli.Saidi@ARM.com TlbEntry te; 5067404SAli.Saidi@ARM.com 5077439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 5087404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 5097404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 5107946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 5117439Sdam.sunwoo@arm.com currState->tc = NULL; 5127439Sdam.sunwoo@arm.com currState->req = NULL; 5137437Sdam.sunwoo@arm.com } 5147406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 5157439Sdam.sunwoo@arm.com if (currState->isFetch) 5167439Sdam.sunwoo@arm.com currState->fault = 5177439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 5187406SAli.Saidi@ARM.com else 5197439Sdam.sunwoo@arm.com currState->fault = 5207576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5217436Sdam.sunwoo@arm.com ArmFault::Translation0); 5227404SAli.Saidi@ARM.com return; 5237404SAli.Saidi@ARM.com case L1Descriptor::Section: 5247439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 5257436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 5267436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 5277436Sdam.sunwoo@arm.com * AccessFlag0 5287436Sdam.sunwoo@arm.com */ 5297436Sdam.sunwoo@arm.com 5307611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 5317611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 5327436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 5337436Sdam.sunwoo@arm.com } 5347439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 5357404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 5367404SAli.Saidi@ARM.com } 5377404SAli.Saidi@ARM.com te.N = 20; 5387439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 5397404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 5407439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 5417404SAli.Saidi@ARM.com te.valid = true; 5427439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5437404SAli.Saidi@ARM.com te.sNp = true; 5447439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 5457439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 5467439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5477439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5487439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 5497439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 5507404SAli.Saidi@ARM.com 5517404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 5527582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 5537404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 5547582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 5557582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 5567582SAli.Saidi@arm.com te.nonCacheable); 5577404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 5587439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 5597439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 5607404SAli.Saidi@ARM.com 5617439Sdam.sunwoo@arm.com if (!currState->timing) { 5627439Sdam.sunwoo@arm.com currState->tc = NULL; 5637439Sdam.sunwoo@arm.com currState->req = NULL; 5647437Sdam.sunwoo@arm.com } 5657439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5667404SAli.Saidi@ARM.com 5677404SAli.Saidi@ARM.com return; 5687404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 5697404SAli.Saidi@ARM.com Addr l2desc_addr; 5707439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 5717439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 5727436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 5737436Sdam.sunwoo@arm.com l2desc_addr); 5747404SAli.Saidi@ARM.com 5757404SAli.Saidi@ARM.com // Trickbox address check 5767439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 5777439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 5787439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 5797439Sdam.sunwoo@arm.com 5807439Sdam.sunwoo@arm.com if (currState->fault) { 5817439Sdam.sunwoo@arm.com if (!currState->timing) { 5827439Sdam.sunwoo@arm.com currState->tc = NULL; 5837439Sdam.sunwoo@arm.com currState->req = NULL; 5847437Sdam.sunwoo@arm.com } 5857437Sdam.sunwoo@arm.com return; 5867404SAli.Saidi@ARM.com } 5877404SAli.Saidi@ARM.com 5887404SAli.Saidi@ARM.com 5897439Sdam.sunwoo@arm.com if (currState->timing) { 5907439Sdam.sunwoo@arm.com currState->delayed = true; 5918851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5929180Sandreas.hansson@arm.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 5939180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod()); 5948733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 5958851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5969180Sandreas.hansson@arm.com NULL, (uint8_t*)&currState->l2Desc.data, 5979180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod()); 5987404SAli.Saidi@ARM.com doL2Descriptor(); 5998733Sgeoffrey.blake@arm.com } else { 6008949Sandreas.hansson@arm.com RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, 6018949Sandreas.hansson@arm.com masterId); 6028949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 6038733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l2Desc.data); 6048851Sandreas.hansson@arm.com port.sendFunctional(pkt); 6058733Sgeoffrey.blake@arm.com doL2Descriptor(); 6068733Sgeoffrey.blake@arm.com delete req; 6078733Sgeoffrey.blake@arm.com delete pkt; 6087404SAli.Saidi@ARM.com } 6097404SAli.Saidi@ARM.com return; 6107404SAli.Saidi@ARM.com default: 6117404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 6127404SAli.Saidi@ARM.com } 6137404SAli.Saidi@ARM.com} 6147404SAli.Saidi@ARM.com 6157404SAli.Saidi@ARM.comvoid 6167404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 6177404SAli.Saidi@ARM.com{ 6187439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 6197439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 6207404SAli.Saidi@ARM.com TlbEntry te; 6217404SAli.Saidi@ARM.com 6227439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 6237404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 6247946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6257439Sdam.sunwoo@arm.com currState->tc = NULL; 6267439Sdam.sunwoo@arm.com currState->req = NULL; 6277437Sdam.sunwoo@arm.com } 6287439Sdam.sunwoo@arm.com if (currState->isFetch) 6297439Sdam.sunwoo@arm.com currState->fault = 6307439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 6317406SAli.Saidi@ARM.com else 6327439Sdam.sunwoo@arm.com currState->fault = 6337439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 6347439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 6357404SAli.Saidi@ARM.com return; 6367404SAli.Saidi@ARM.com } 6377404SAli.Saidi@ARM.com 6387439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 6397436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 6407436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 6417436Sdam.sunwoo@arm.com */ 6427436Sdam.sunwoo@arm.com 6437439Sdam.sunwoo@arm.com currState->fault = 6447576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 6457439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 6467439Sdam.sunwoo@arm.com 6477436Sdam.sunwoo@arm.com } 6487436Sdam.sunwoo@arm.com 6497439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 6507404SAli.Saidi@ARM.com te.N = 16; 6517439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6527404SAli.Saidi@ARM.com } else { 6537404SAli.Saidi@ARM.com te.N = 12; 6547439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6557404SAli.Saidi@ARM.com } 6567404SAli.Saidi@ARM.com 6577404SAli.Saidi@ARM.com te.valid = true; 6587404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 6597439Sdam.sunwoo@arm.com te.asid = currState->contextId; 6607404SAli.Saidi@ARM.com te.sNp = false; 6617439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 6627439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 6637439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 6647439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 6657439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 6667439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 6677439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 6687404SAli.Saidi@ARM.com 6697946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6707439Sdam.sunwoo@arm.com currState->tc = NULL; 6717439Sdam.sunwoo@arm.com currState->req = NULL; 6727437Sdam.sunwoo@arm.com } 6737439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 6747437Sdam.sunwoo@arm.com} 6757437Sdam.sunwoo@arm.com 6767437Sdam.sunwoo@arm.comvoid 6777437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 6787437Sdam.sunwoo@arm.com{ 6797653Sgene.wu@arm.com currState = stateQueueL1.front(); 6807439Sdam.sunwoo@arm.com currState->delayed = false; 6817437Sdam.sunwoo@arm.com 6827578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 6837578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 6847578Sdam.sunwoo@arm.com 6857439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 6867437Sdam.sunwoo@arm.com doL1Descriptor(); 6877437Sdam.sunwoo@arm.com 6887653Sgene.wu@arm.com stateQueueL1.pop_front(); 6899152Satgutier@umich.edu completeDrain(); 6907437Sdam.sunwoo@arm.com // Check if fault was generated 6917439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6927439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6937439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6947437Sdam.sunwoo@arm.com 6957728SAli.Saidi@ARM.com pending = false; 6967728SAli.Saidi@ARM.com nextWalk(currState->tc); 6977728SAli.Saidi@ARM.com 6987439Sdam.sunwoo@arm.com currState->req = NULL; 6997439Sdam.sunwoo@arm.com currState->tc = NULL; 7007439Sdam.sunwoo@arm.com currState->delayed = false; 7018510SAli.Saidi@ARM.com delete currState; 7027437Sdam.sunwoo@arm.com } 7037439Sdam.sunwoo@arm.com else if (!currState->delayed) { 7047653Sgene.wu@arm.com // delay is not set so there is no L2 to do 7057437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7067439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7077439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7087437Sdam.sunwoo@arm.com 7097728SAli.Saidi@ARM.com pending = false; 7107728SAli.Saidi@ARM.com nextWalk(currState->tc); 7117728SAli.Saidi@ARM.com 7127439Sdam.sunwoo@arm.com currState->req = NULL; 7137439Sdam.sunwoo@arm.com currState->tc = NULL; 7147439Sdam.sunwoo@arm.com currState->delayed = false; 7157653Sgene.wu@arm.com delete currState; 7167653Sgene.wu@arm.com } else { 7177653Sgene.wu@arm.com // need to do L2 descriptor 7187653Sgene.wu@arm.com stateQueueL2.push_back(currState); 7197437Sdam.sunwoo@arm.com } 7207439Sdam.sunwoo@arm.com currState = NULL; 7217437Sdam.sunwoo@arm.com} 7227437Sdam.sunwoo@arm.com 7237437Sdam.sunwoo@arm.comvoid 7247437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 7257437Sdam.sunwoo@arm.com{ 7267653Sgene.wu@arm.com currState = stateQueueL2.front(); 7277439Sdam.sunwoo@arm.com assert(currState->delayed); 7287437Sdam.sunwoo@arm.com 7297439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 7307439Sdam.sunwoo@arm.com currState->vaddr); 7317437Sdam.sunwoo@arm.com doL2Descriptor(); 7327437Sdam.sunwoo@arm.com 7337437Sdam.sunwoo@arm.com // Check if fault was generated 7347439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 7357439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 7367439Sdam.sunwoo@arm.com currState->tc, currState->mode); 7377437Sdam.sunwoo@arm.com } 7387437Sdam.sunwoo@arm.com else { 7397437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7407439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7417439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7427437Sdam.sunwoo@arm.com } 7437437Sdam.sunwoo@arm.com 7447728SAli.Saidi@ARM.com 7457728SAli.Saidi@ARM.com stateQueueL2.pop_front(); 7469152Satgutier@umich.edu completeDrain(); 7477728SAli.Saidi@ARM.com pending = false; 7487728SAli.Saidi@ARM.com nextWalk(currState->tc); 7497728SAli.Saidi@ARM.com 7507439Sdam.sunwoo@arm.com currState->req = NULL; 7517439Sdam.sunwoo@arm.com currState->tc = NULL; 7527439Sdam.sunwoo@arm.com currState->delayed = false; 7537439Sdam.sunwoo@arm.com 7547653Sgene.wu@arm.com delete currState; 7557439Sdam.sunwoo@arm.com currState = NULL; 7567404SAli.Saidi@ARM.com} 7577404SAli.Saidi@ARM.com 7587728SAli.Saidi@ARM.comvoid 7597728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 7607728SAli.Saidi@ARM.com{ 7617728SAli.Saidi@ARM.com if (pendingQueue.size()) 7629180Sandreas.hansson@arm.com schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(Cycles(1))); 7637728SAli.Saidi@ARM.com} 7647728SAli.Saidi@ARM.com 7657728SAli.Saidi@ARM.com 7667728SAli.Saidi@ARM.com 7677404SAli.Saidi@ARM.comArmISA::TableWalker * 7687404SAli.Saidi@ARM.comArmTableWalkerParams::create() 7697404SAli.Saidi@ARM.com{ 7707404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 7717404SAli.Saidi@ARM.com} 7727404SAli.Saidi@ARM.com 773