table_walker.cc revision 8949
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437728SAli.Saidi@ARM.com#include "cpu/base.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 458245Snate@binkert.org#include "debug/Checkpoint.hh" 468245Snate@binkert.org#include "debug/TLB.hh" 478245Snate@binkert.org#include "debug/TLBVerbose.hh" 487748SAli.Saidi@ARM.com#include "sim/system.hh" 497404SAli.Saidi@ARM.com 507404SAli.Saidi@ARM.comusing namespace ArmISA; 517404SAli.Saidi@ARM.com 527404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 538851Sandreas.hansson@arm.com : MemObject(p), port(this, params()->sys, params()->min_backoff, 548851Sandreas.hansson@arm.com params()->max_backoff, true), 558851Sandreas.hansson@arm.com tlb(NULL), currState(NULL), pending(false), 568832SAli.Saidi@ARM.com masterId(p->sys->getMasterId(name())), 577728SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 587439Sdam.sunwoo@arm.com{ 597576SAli.Saidi@ARM.com sctlr = 0; 607439Sdam.sunwoo@arm.com} 617404SAli.Saidi@ARM.com 627404SAli.Saidi@ARM.comTableWalker::~TableWalker() 637404SAli.Saidi@ARM.com{ 647404SAli.Saidi@ARM.com ; 657404SAli.Saidi@ARM.com} 667404SAli.Saidi@ARM.com 677748SAli.Saidi@ARM.comunsigned int 687748SAli.Saidi@ARM.comTableWalker::drain(Event *de) 697404SAli.Saidi@ARM.com{ 707748SAli.Saidi@ARM.com if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size()) 717733SAli.Saidi@ARM.com { 727733SAli.Saidi@ARM.com changeState(Draining); 737733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n"); 747733SAli.Saidi@ARM.com return 1; 757733SAli.Saidi@ARM.com } 767733SAli.Saidi@ARM.com else 777733SAli.Saidi@ARM.com { 787733SAli.Saidi@ARM.com changeState(Drained); 797733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "TableWalker free, no need to drain\n"); 807733SAli.Saidi@ARM.com return 0; 817733SAli.Saidi@ARM.com } 827404SAli.Saidi@ARM.com} 837404SAli.Saidi@ARM.com 847748SAli.Saidi@ARM.comvoid 857748SAli.Saidi@ARM.comTableWalker::resume() 867748SAli.Saidi@ARM.com{ 877748SAli.Saidi@ARM.com MemObject::resume(); 887748SAli.Saidi@ARM.com if ((params()->sys->getMemoryMode() == Enums::timing) && currState) { 897748SAli.Saidi@ARM.com delete currState; 907748SAli.Saidi@ARM.com currState = NULL; 917748SAli.Saidi@ARM.com } 927748SAli.Saidi@ARM.com} 937748SAli.Saidi@ARM.com 948922Swilliam.wang@arm.comMasterPort& 958922Swilliam.wang@arm.comTableWalker::getMasterPort(const std::string &if_name, int idx) 967404SAli.Saidi@ARM.com{ 977404SAli.Saidi@ARM.com if (if_name == "port") { 988922Swilliam.wang@arm.com return port; 997404SAli.Saidi@ARM.com } 1008922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1017404SAli.Saidi@ARM.com} 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.comFault 1047437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 1058733Sgeoffrey.blake@arm.com TLB::Translation *_trans, bool _timing, bool _functional) 1067404SAli.Saidi@ARM.com{ 1078733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 1087439Sdam.sunwoo@arm.com if (!currState) { 1097439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1107439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1117439Sdam.sunwoo@arm.com // TLB miss. 1127439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1137404SAli.Saidi@ARM.com 1147439Sdam.sunwoo@arm.com currState = new WalkerState(); 1157439Sdam.sunwoo@arm.com currState->tableWalker = this; 1168202SAli.Saidi@ARM.com } else if (_timing) { 1178202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 1188202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 1198202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 1208202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 1218202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 1228202SAli.Saidi@ARM.com // up everything. 1238202SAli.Saidi@ARM.com if (currState->vaddr == _req->getVaddr()) { 1248202SAli.Saidi@ARM.com return new ReExec; 1258202SAli.Saidi@ARM.com } 1267439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 1277439Sdam.sunwoo@arm.com } 1287439Sdam.sunwoo@arm.com 1297439Sdam.sunwoo@arm.com currState->tc = _tc; 1307439Sdam.sunwoo@arm.com currState->transState = _trans; 1317439Sdam.sunwoo@arm.com currState->req = _req; 1327439Sdam.sunwoo@arm.com currState->fault = NoFault; 1337439Sdam.sunwoo@arm.com currState->contextId = _cid; 1347439Sdam.sunwoo@arm.com currState->timing = _timing; 1358733Sgeoffrey.blake@arm.com currState->functional = _functional; 1367439Sdam.sunwoo@arm.com currState->mode = _mode; 1377404SAli.Saidi@ARM.com 1387436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1397436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1407720Sgblack@eecs.umich.edu currState->vaddr = currState->req->getVaddr(); 1417439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1427439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1437439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1447439Sdam.sunwoo@arm.com 1457439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1467439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1477439Sdam.sunwoo@arm.com 1487728SAli.Saidi@ARM.com 1497728SAli.Saidi@ARM.com if (!currState->timing) 1507728SAli.Saidi@ARM.com return processWalk(); 1517728SAli.Saidi@ARM.com 1528067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 1537728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 1547728SAli.Saidi@ARM.com currState = NULL; 1557728SAli.Saidi@ARM.com } else { 1567728SAli.Saidi@ARM.com pending = true; 1578067SAli.Saidi@ARM.com return processWalk(); 1587728SAli.Saidi@ARM.com } 1597728SAli.Saidi@ARM.com 1607728SAli.Saidi@ARM.com return NoFault; 1617728SAli.Saidi@ARM.com} 1627728SAli.Saidi@ARM.com 1637728SAli.Saidi@ARM.comvoid 1647728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 1657728SAli.Saidi@ARM.com{ 1667728SAli.Saidi@ARM.com assert(!currState); 1677728SAli.Saidi@ARM.com assert(pendingQueue.size()); 1687728SAli.Saidi@ARM.com currState = pendingQueue.front(); 1697728SAli.Saidi@ARM.com pendingQueue.pop_front(); 1707728SAli.Saidi@ARM.com pending = true; 1717728SAli.Saidi@ARM.com processWalk(); 1727728SAli.Saidi@ARM.com} 1737728SAli.Saidi@ARM.com 1747728SAli.Saidi@ARM.comFault 1757728SAli.Saidi@ARM.comTableWalker::processWalk() 1767728SAli.Saidi@ARM.com{ 1777404SAli.Saidi@ARM.com Addr ttbr = 0; 1787404SAli.Saidi@ARM.com 1797404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1807439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1817404SAli.Saidi@ARM.com 1827406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1837439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 1847439Sdam.sunwoo@arm.com 32-currState->N)); 1857406SAli.Saidi@ARM.com 1867439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 1877406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1887439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 1897404SAli.Saidi@ARM.com } else { 1907406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1917439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 1927439Sdam.sunwoo@arm.com currState->N = 0; 1937404SAli.Saidi@ARM.com } 1947404SAli.Saidi@ARM.com 1957439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 1967439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 1977406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1987404SAli.Saidi@ARM.com 1997404SAli.Saidi@ARM.com 2007404SAli.Saidi@ARM.com // Trickbox address check 2017439Sdam.sunwoo@arm.com Fault f; 2027439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 2037439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 2047439Sdam.sunwoo@arm.com if (f) { 2058067SAli.Saidi@ARM.com DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr); 2067579Sminkyu.jeong@arm.com if (currState->timing) { 2077728SAli.Saidi@ARM.com pending = false; 2087728SAli.Saidi@ARM.com nextWalk(currState->tc); 2097579Sminkyu.jeong@arm.com currState = NULL; 2107579Sminkyu.jeong@arm.com } else { 2117579Sminkyu.jeong@arm.com currState->tc = NULL; 2127579Sminkyu.jeong@arm.com currState->req = NULL; 2137579Sminkyu.jeong@arm.com } 2147579Sminkyu.jeong@arm.com return f; 2157404SAli.Saidi@ARM.com } 2167404SAli.Saidi@ARM.com 2177946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 2187946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 2197946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 2207946SGiacomo.Gabrielli@arm.com } 2217946SGiacomo.Gabrielli@arm.com 2227439Sdam.sunwoo@arm.com if (currState->timing) { 2238851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2248851Sandreas.hansson@arm.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 2258851Sandreas.hansson@arm.com currState->tc->getCpuPtr()->ticks(1), flag); 2267578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 2277653Sgene.wu@arm.com stateQueueL1.size()); 2287653Sgene.wu@arm.com stateQueueL1.push_back(currState); 2297439Sdam.sunwoo@arm.com currState = NULL; 2308733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 2318851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2328851Sandreas.hansson@arm.com NULL, (uint8_t*)&currState->l1Desc.data, 2338851Sandreas.hansson@arm.com currState->tc->getCpuPtr()->ticks(1), flag); 2347404SAli.Saidi@ARM.com doL1Descriptor(); 2357439Sdam.sunwoo@arm.com f = currState->fault; 2368733Sgeoffrey.blake@arm.com } else { 2378832SAli.Saidi@ARM.com RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId); 2388949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2398733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l1Desc.data); 2408851Sandreas.hansson@arm.com port.sendFunctional(pkt); 2418733Sgeoffrey.blake@arm.com doL1Descriptor(); 2428733Sgeoffrey.blake@arm.com delete req; 2438733Sgeoffrey.blake@arm.com delete pkt; 2448733Sgeoffrey.blake@arm.com f = currState->fault; 2457404SAli.Saidi@ARM.com } 2467404SAli.Saidi@ARM.com 2477439Sdam.sunwoo@arm.com return f; 2487404SAli.Saidi@ARM.com} 2497404SAli.Saidi@ARM.com 2507404SAli.Saidi@ARM.comvoid 2517439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 2527439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 2537404SAli.Saidi@ARM.com{ 2547439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 2557439Sdam.sunwoo@arm.com // variables 2567436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 2577436Sdam.sunwoo@arm.com te.shareable = false; // default value 2587582SAli.Saidi@arm.com te.nonCacheable = false; 2597436Sdam.sunwoo@arm.com bool outer_shareable = false; 2607439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 2617404SAli.Saidi@ARM.com switch(texcb) { 2627436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 2637404SAli.Saidi@ARM.com te.nonCacheable = true; 2647436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 2657436Sdam.sunwoo@arm.com te.shareable = true; 2667436Sdam.sunwoo@arm.com te.innerAttrs = 1; 2677436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2687404SAli.Saidi@ARM.com break; 2697436Sdam.sunwoo@arm.com case 1: // Shareable Device 2707436Sdam.sunwoo@arm.com te.nonCacheable = true; 2717436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2727436Sdam.sunwoo@arm.com te.shareable = true; 2737436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2747436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2757436Sdam.sunwoo@arm.com break; 2767436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 2777436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2787436Sdam.sunwoo@arm.com te.shareable = s; 2797436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2807436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2817436Sdam.sunwoo@arm.com break; 2827436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 2837436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2847436Sdam.sunwoo@arm.com te.shareable = s; 2857436Sdam.sunwoo@arm.com te.innerAttrs = 7; 2867436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2877436Sdam.sunwoo@arm.com break; 2887436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 2897436Sdam.sunwoo@arm.com te.nonCacheable = true; 2907436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2917436Sdam.sunwoo@arm.com te.shareable = s; 2927436Sdam.sunwoo@arm.com te.innerAttrs = 0; 2937436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2947436Sdam.sunwoo@arm.com break; 2957436Sdam.sunwoo@arm.com case 5: // Reserved 2967439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2977436Sdam.sunwoo@arm.com break; 2987436Sdam.sunwoo@arm.com case 6: // Implementation Defined 2997439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 3007436Sdam.sunwoo@arm.com break; 3017436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 3027436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3037436Sdam.sunwoo@arm.com te.shareable = s; 3047436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3057436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3067436Sdam.sunwoo@arm.com break; 3077436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 3087436Sdam.sunwoo@arm.com te.nonCacheable = true; 3097436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3107436Sdam.sunwoo@arm.com te.shareable = false; 3117436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3127436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3137436Sdam.sunwoo@arm.com break; 3147436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 3157439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3167436Sdam.sunwoo@arm.com break; 3177436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 3187436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3197436Sdam.sunwoo@arm.com te.shareable = s; 3207404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 3217404SAli.Saidi@ARM.com te.nonCacheable = true; 3227436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 3237436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 3247404SAli.Saidi@ARM.com break; 3257436Sdam.sunwoo@arm.com default: 3267436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 3277404SAli.Saidi@ARM.com } 3287404SAli.Saidi@ARM.com } else { 3297438SAli.Saidi@ARM.com assert(tc); 3307404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3317404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3327436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 3337582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 3347404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 3357404SAli.Saidi@ARM.com case 0: 3367436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 3377436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 3387436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 3397436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 3407404SAli.Saidi@ARM.com break; 3417404SAli.Saidi@ARM.com case 1: 3427436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 3437436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 3447436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 3457436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 3467404SAli.Saidi@ARM.com break; 3477404SAli.Saidi@ARM.com case 2: 3487436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 3497436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 3507436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 3517436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 3527404SAli.Saidi@ARM.com break; 3537404SAli.Saidi@ARM.com case 3: 3547436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 3557436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 3567436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 3577436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 3587404SAli.Saidi@ARM.com break; 3597404SAli.Saidi@ARM.com case 4: 3607436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 3617436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 3627436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 3637436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 3647404SAli.Saidi@ARM.com break; 3657404SAli.Saidi@ARM.com case 5: 3667436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 3677436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 3687436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 3697436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 3707404SAli.Saidi@ARM.com break; 3717404SAli.Saidi@ARM.com case 6: 3727404SAli.Saidi@ARM.com panic("Imp defined type\n"); 3737404SAli.Saidi@ARM.com case 7: 3747436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 3757436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 3767436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 3777436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 3787404SAli.Saidi@ARM.com break; 3797404SAli.Saidi@ARM.com } 3807436Sdam.sunwoo@arm.com 3817436Sdam.sunwoo@arm.com switch(curr_tr) { 3827436Sdam.sunwoo@arm.com case 0: 3837436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 3847436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3857436Sdam.sunwoo@arm.com te.nonCacheable = true; 3867436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3877436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3887436Sdam.sunwoo@arm.com te.shareable = true; 3897436Sdam.sunwoo@arm.com break; 3907436Sdam.sunwoo@arm.com case 1: 3917436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 3927436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 3937436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3947436Sdam.sunwoo@arm.com te.nonCacheable = true; 3957436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3967436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3977436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 3987436Sdam.sunwoo@arm.com te.shareable = true; 3997436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 4007436Sdam.sunwoo@arm.com te.shareable = true; 4017436Sdam.sunwoo@arm.com break; 4027436Sdam.sunwoo@arm.com case 2: 4037436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 4047436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 4057436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 4067436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 4077436Sdam.sunwoo@arm.com te.shareable = true; 4087436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 4097436Sdam.sunwoo@arm.com te.shareable = true; 4107436Sdam.sunwoo@arm.com break; 4117436Sdam.sunwoo@arm.com case 3: 4127436Sdam.sunwoo@arm.com panic("Reserved type"); 4137436Sdam.sunwoo@arm.com } 4147436Sdam.sunwoo@arm.com 4157436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 4167436Sdam.sunwoo@arm.com switch(curr_ir) { 4177436Sdam.sunwoo@arm.com case 0: 4187436Sdam.sunwoo@arm.com te.nonCacheable = true; 4197436Sdam.sunwoo@arm.com te.innerAttrs = 0; 4207436Sdam.sunwoo@arm.com break; 4217436Sdam.sunwoo@arm.com case 1: 4227436Sdam.sunwoo@arm.com te.innerAttrs = 5; 4237436Sdam.sunwoo@arm.com break; 4247436Sdam.sunwoo@arm.com case 2: 4257436Sdam.sunwoo@arm.com te.innerAttrs = 6; 4267436Sdam.sunwoo@arm.com break; 4277436Sdam.sunwoo@arm.com case 3: 4287436Sdam.sunwoo@arm.com te.innerAttrs = 7; 4297436Sdam.sunwoo@arm.com break; 4307436Sdam.sunwoo@arm.com } 4317436Sdam.sunwoo@arm.com 4327436Sdam.sunwoo@arm.com switch(curr_or) { 4337436Sdam.sunwoo@arm.com case 0: 4347436Sdam.sunwoo@arm.com te.nonCacheable = true; 4357436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4367436Sdam.sunwoo@arm.com break; 4377436Sdam.sunwoo@arm.com case 1: 4387436Sdam.sunwoo@arm.com te.outerAttrs = 1; 4397436Sdam.sunwoo@arm.com break; 4407436Sdam.sunwoo@arm.com case 2: 4417436Sdam.sunwoo@arm.com te.outerAttrs = 2; 4427436Sdam.sunwoo@arm.com break; 4437436Sdam.sunwoo@arm.com case 3: 4447436Sdam.sunwoo@arm.com te.outerAttrs = 3; 4457436Sdam.sunwoo@arm.com break; 4467436Sdam.sunwoo@arm.com } 4477436Sdam.sunwoo@arm.com } 4487404SAli.Saidi@ARM.com } 4497439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 4507439Sdam.sunwoo@arm.com outerAttrs: %d\n", 4517439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 4527436Sdam.sunwoo@arm.com 4537436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 4547436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 4557436Sdam.sunwoo@arm.com * PAR: 4567436Sdam.sunwoo@arm.com * PA [31:12] 4577436Sdam.sunwoo@arm.com * Reserved [11] 4587436Sdam.sunwoo@arm.com * TLB info [10:1] 4597436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 4607436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 4617436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 4627436Sdam.sunwoo@arm.com * SH [7] (Sharable) 4637436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 4647436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 4657436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 4667436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 4677436Sdam.sunwoo@arm.com */ 4687436Sdam.sunwoo@arm.com te.attributes = ( 4697436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 4707436Sdam.sunwoo@arm.com // TODO: NS Bit 4717436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 4727436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 4737436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 4747436Sdam.sunwoo@arm.com // TODO: Supersection bit 4757436Sdam.sunwoo@arm.com // TODO: Fault bit 4767436Sdam.sunwoo@arm.com ); 4777436Sdam.sunwoo@arm.com 4787436Sdam.sunwoo@arm.com 4797404SAli.Saidi@ARM.com} 4807404SAli.Saidi@ARM.com 4817404SAli.Saidi@ARM.comvoid 4827404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 4837404SAli.Saidi@ARM.com{ 4847439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 4857439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 4867404SAli.Saidi@ARM.com TlbEntry te; 4877404SAli.Saidi@ARM.com 4887439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 4897404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 4907404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 4917946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 4927439Sdam.sunwoo@arm.com currState->tc = NULL; 4937439Sdam.sunwoo@arm.com currState->req = NULL; 4947437Sdam.sunwoo@arm.com } 4957406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 4967439Sdam.sunwoo@arm.com if (currState->isFetch) 4977439Sdam.sunwoo@arm.com currState->fault = 4987439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 4997406SAli.Saidi@ARM.com else 5007439Sdam.sunwoo@arm.com currState->fault = 5017576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5027436Sdam.sunwoo@arm.com ArmFault::Translation0); 5037404SAli.Saidi@ARM.com return; 5047404SAli.Saidi@ARM.com case L1Descriptor::Section: 5057439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 5067436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 5077436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 5087436Sdam.sunwoo@arm.com * AccessFlag0 5097436Sdam.sunwoo@arm.com */ 5107436Sdam.sunwoo@arm.com 5117611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 5127611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 5137436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 5147436Sdam.sunwoo@arm.com } 5157439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 5167404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 5177404SAli.Saidi@ARM.com } 5187404SAli.Saidi@ARM.com te.N = 20; 5197439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 5207404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 5217439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 5227404SAli.Saidi@ARM.com te.valid = true; 5237439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5247404SAli.Saidi@ARM.com te.sNp = true; 5257439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 5267439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 5277439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5287439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5297439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 5307439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 5317404SAli.Saidi@ARM.com 5327404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 5337582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 5347404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 5357582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 5367582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 5377582SAli.Saidi@arm.com te.nonCacheable); 5387404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 5397439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 5407439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 5417404SAli.Saidi@ARM.com 5427439Sdam.sunwoo@arm.com if (!currState->timing) { 5437439Sdam.sunwoo@arm.com currState->tc = NULL; 5447439Sdam.sunwoo@arm.com currState->req = NULL; 5457437Sdam.sunwoo@arm.com } 5467439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5477404SAli.Saidi@ARM.com 5487404SAli.Saidi@ARM.com return; 5497404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 5507404SAli.Saidi@ARM.com Addr l2desc_addr; 5517439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 5527439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 5537436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 5547436Sdam.sunwoo@arm.com l2desc_addr); 5557404SAli.Saidi@ARM.com 5567404SAli.Saidi@ARM.com // Trickbox address check 5577439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 5587439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 5597439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 5607439Sdam.sunwoo@arm.com 5617439Sdam.sunwoo@arm.com if (currState->fault) { 5627439Sdam.sunwoo@arm.com if (!currState->timing) { 5637439Sdam.sunwoo@arm.com currState->tc = NULL; 5647439Sdam.sunwoo@arm.com currState->req = NULL; 5657437Sdam.sunwoo@arm.com } 5667437Sdam.sunwoo@arm.com return; 5677404SAli.Saidi@ARM.com } 5687404SAli.Saidi@ARM.com 5697404SAli.Saidi@ARM.com 5707439Sdam.sunwoo@arm.com if (currState->timing) { 5717439Sdam.sunwoo@arm.com currState->delayed = true; 5728851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5737728SAli.Saidi@ARM.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 5747728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5758733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 5768851Sandreas.hansson@arm.com port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5777728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l2Desc.data, 5787728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5797404SAli.Saidi@ARM.com doL2Descriptor(); 5808733Sgeoffrey.blake@arm.com } else { 5818949Sandreas.hansson@arm.com RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, 5828949Sandreas.hansson@arm.com masterId); 5838949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 5848733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l2Desc.data); 5858851Sandreas.hansson@arm.com port.sendFunctional(pkt); 5868733Sgeoffrey.blake@arm.com doL2Descriptor(); 5878733Sgeoffrey.blake@arm.com delete req; 5888733Sgeoffrey.blake@arm.com delete pkt; 5897404SAli.Saidi@ARM.com } 5907404SAli.Saidi@ARM.com return; 5917404SAli.Saidi@ARM.com default: 5927404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 5937404SAli.Saidi@ARM.com } 5947404SAli.Saidi@ARM.com} 5957404SAli.Saidi@ARM.com 5967404SAli.Saidi@ARM.comvoid 5977404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 5987404SAli.Saidi@ARM.com{ 5997439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 6007439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 6017404SAli.Saidi@ARM.com TlbEntry te; 6027404SAli.Saidi@ARM.com 6037439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 6047404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 6057946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6067439Sdam.sunwoo@arm.com currState->tc = NULL; 6077439Sdam.sunwoo@arm.com currState->req = NULL; 6087437Sdam.sunwoo@arm.com } 6097439Sdam.sunwoo@arm.com if (currState->isFetch) 6107439Sdam.sunwoo@arm.com currState->fault = 6117439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 6127406SAli.Saidi@ARM.com else 6137439Sdam.sunwoo@arm.com currState->fault = 6147439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 6157439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 6167404SAli.Saidi@ARM.com return; 6177404SAli.Saidi@ARM.com } 6187404SAli.Saidi@ARM.com 6197439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 6207436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 6217436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 6227436Sdam.sunwoo@arm.com */ 6237436Sdam.sunwoo@arm.com 6247439Sdam.sunwoo@arm.com currState->fault = 6257576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 6267439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 6277439Sdam.sunwoo@arm.com 6287436Sdam.sunwoo@arm.com } 6297436Sdam.sunwoo@arm.com 6307439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 6317404SAli.Saidi@ARM.com te.N = 16; 6327439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6337404SAli.Saidi@ARM.com } else { 6347404SAli.Saidi@ARM.com te.N = 12; 6357439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6367404SAli.Saidi@ARM.com } 6377404SAli.Saidi@ARM.com 6387404SAli.Saidi@ARM.com te.valid = true; 6397404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 6407439Sdam.sunwoo@arm.com te.asid = currState->contextId; 6417404SAli.Saidi@ARM.com te.sNp = false; 6427439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 6437439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 6447439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 6457439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 6467439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 6477439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 6487439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 6497404SAli.Saidi@ARM.com 6507946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6517439Sdam.sunwoo@arm.com currState->tc = NULL; 6527439Sdam.sunwoo@arm.com currState->req = NULL; 6537437Sdam.sunwoo@arm.com } 6547439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 6557437Sdam.sunwoo@arm.com} 6567437Sdam.sunwoo@arm.com 6577437Sdam.sunwoo@arm.comvoid 6587437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 6597437Sdam.sunwoo@arm.com{ 6607653Sgene.wu@arm.com currState = stateQueueL1.front(); 6617439Sdam.sunwoo@arm.com currState->delayed = false; 6627437Sdam.sunwoo@arm.com 6637578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 6647578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 6657578Sdam.sunwoo@arm.com 6667439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 6677437Sdam.sunwoo@arm.com doL1Descriptor(); 6687437Sdam.sunwoo@arm.com 6697653Sgene.wu@arm.com stateQueueL1.pop_front(); 6707437Sdam.sunwoo@arm.com // Check if fault was generated 6717439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6727439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6737439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6747437Sdam.sunwoo@arm.com 6757728SAli.Saidi@ARM.com pending = false; 6767728SAli.Saidi@ARM.com nextWalk(currState->tc); 6777728SAli.Saidi@ARM.com 6787439Sdam.sunwoo@arm.com currState->req = NULL; 6797439Sdam.sunwoo@arm.com currState->tc = NULL; 6807439Sdam.sunwoo@arm.com currState->delayed = false; 6818510SAli.Saidi@ARM.com delete currState; 6827437Sdam.sunwoo@arm.com } 6837439Sdam.sunwoo@arm.com else if (!currState->delayed) { 6847653Sgene.wu@arm.com // delay is not set so there is no L2 to do 6857437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6867439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6877439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6887437Sdam.sunwoo@arm.com 6897728SAli.Saidi@ARM.com pending = false; 6907728SAli.Saidi@ARM.com nextWalk(currState->tc); 6917728SAli.Saidi@ARM.com 6927439Sdam.sunwoo@arm.com currState->req = NULL; 6937439Sdam.sunwoo@arm.com currState->tc = NULL; 6947439Sdam.sunwoo@arm.com currState->delayed = false; 6957653Sgene.wu@arm.com delete currState; 6967653Sgene.wu@arm.com } else { 6977653Sgene.wu@arm.com // need to do L2 descriptor 6987653Sgene.wu@arm.com stateQueueL2.push_back(currState); 6997437Sdam.sunwoo@arm.com } 7007439Sdam.sunwoo@arm.com currState = NULL; 7017437Sdam.sunwoo@arm.com} 7027437Sdam.sunwoo@arm.com 7037437Sdam.sunwoo@arm.comvoid 7047437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 7057437Sdam.sunwoo@arm.com{ 7067653Sgene.wu@arm.com currState = stateQueueL2.front(); 7077439Sdam.sunwoo@arm.com assert(currState->delayed); 7087437Sdam.sunwoo@arm.com 7097439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 7107439Sdam.sunwoo@arm.com currState->vaddr); 7117437Sdam.sunwoo@arm.com doL2Descriptor(); 7127437Sdam.sunwoo@arm.com 7137437Sdam.sunwoo@arm.com // Check if fault was generated 7147439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 7157439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 7167439Sdam.sunwoo@arm.com currState->tc, currState->mode); 7177437Sdam.sunwoo@arm.com } 7187437Sdam.sunwoo@arm.com else { 7197437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7207439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7217439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7227437Sdam.sunwoo@arm.com } 7237437Sdam.sunwoo@arm.com 7247728SAli.Saidi@ARM.com 7257728SAli.Saidi@ARM.com stateQueueL2.pop_front(); 7267728SAli.Saidi@ARM.com pending = false; 7277728SAli.Saidi@ARM.com nextWalk(currState->tc); 7287728SAli.Saidi@ARM.com 7297439Sdam.sunwoo@arm.com currState->req = NULL; 7307439Sdam.sunwoo@arm.com currState->tc = NULL; 7317439Sdam.sunwoo@arm.com currState->delayed = false; 7327439Sdam.sunwoo@arm.com 7337653Sgene.wu@arm.com delete currState; 7347439Sdam.sunwoo@arm.com currState = NULL; 7357404SAli.Saidi@ARM.com} 7367404SAli.Saidi@ARM.com 7377728SAli.Saidi@ARM.comvoid 7387728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 7397728SAli.Saidi@ARM.com{ 7407728SAli.Saidi@ARM.com if (pendingQueue.size()) 7417823Ssteve.reinhardt@amd.com schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1)); 7427728SAli.Saidi@ARM.com} 7437728SAli.Saidi@ARM.com 7447728SAli.Saidi@ARM.com 7457728SAli.Saidi@ARM.com 7467404SAli.Saidi@ARM.comArmISA::TableWalker * 7477404SAli.Saidi@ARM.comArmTableWalkerParams::create() 7487404SAli.Saidi@ARM.com{ 7497404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 7507404SAli.Saidi@ARM.com} 7517404SAli.Saidi@ARM.com 752