table_walker.cc revision 8733
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437728SAli.Saidi@ARM.com#include "cpu/base.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 458245Snate@binkert.org#include "debug/Checkpoint.hh" 468245Snate@binkert.org#include "debug/TLB.hh" 478245Snate@binkert.org#include "debug/TLBVerbose.hh" 488229Snate@binkert.org#include "dev/io_device.hh" 497748SAli.Saidi@ARM.com#include "sim/system.hh" 507404SAli.Saidi@ARM.com 517404SAli.Saidi@ARM.comusing namespace ArmISA; 527404SAli.Saidi@ARM.com 537404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 547728SAli.Saidi@ARM.com : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false), 557728SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 567439Sdam.sunwoo@arm.com{ 577576SAli.Saidi@ARM.com sctlr = 0; 587439Sdam.sunwoo@arm.com} 597404SAli.Saidi@ARM.com 607404SAli.Saidi@ARM.comTableWalker::~TableWalker() 617404SAli.Saidi@ARM.com{ 627404SAli.Saidi@ARM.com ; 637404SAli.Saidi@ARM.com} 647404SAli.Saidi@ARM.com 657404SAli.Saidi@ARM.com 667748SAli.Saidi@ARM.comunsigned int 677748SAli.Saidi@ARM.comTableWalker::drain(Event *de) 687404SAli.Saidi@ARM.com{ 697748SAli.Saidi@ARM.com if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size()) 707733SAli.Saidi@ARM.com { 717733SAli.Saidi@ARM.com changeState(Draining); 727733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n"); 737733SAli.Saidi@ARM.com return 1; 747733SAli.Saidi@ARM.com } 757733SAli.Saidi@ARM.com else 767733SAli.Saidi@ARM.com { 777733SAli.Saidi@ARM.com changeState(Drained); 787733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "TableWalker free, no need to drain\n"); 797733SAli.Saidi@ARM.com return 0; 807733SAli.Saidi@ARM.com } 817404SAli.Saidi@ARM.com} 827404SAli.Saidi@ARM.com 837748SAli.Saidi@ARM.comvoid 847748SAli.Saidi@ARM.comTableWalker::resume() 857748SAli.Saidi@ARM.com{ 867748SAli.Saidi@ARM.com MemObject::resume(); 877748SAli.Saidi@ARM.com if ((params()->sys->getMemoryMode() == Enums::timing) && currState) { 887748SAli.Saidi@ARM.com delete currState; 897748SAli.Saidi@ARM.com currState = NULL; 907748SAli.Saidi@ARM.com } 917748SAli.Saidi@ARM.com} 927748SAli.Saidi@ARM.com 937404SAli.Saidi@ARM.comPort* 947404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 957404SAli.Saidi@ARM.com{ 967404SAli.Saidi@ARM.com if (if_name == "port") { 977404SAli.Saidi@ARM.com if (port != NULL) 987781SAli.Saidi@ARM.com return port; 997404SAli.Saidi@ARM.com System *sys = params()->sys; 1007404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 1017404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 1028630SMitchell.Hayenga@ARM.com port = new DmaPort(this, sys, minb, maxb, true); 1037404SAli.Saidi@ARM.com return port; 1047404SAli.Saidi@ARM.com } 1057404SAli.Saidi@ARM.com return NULL; 1067404SAli.Saidi@ARM.com} 1077404SAli.Saidi@ARM.com 1087404SAli.Saidi@ARM.comFault 1097437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 1108733Sgeoffrey.blake@arm.com TLB::Translation *_trans, bool _timing, bool _functional) 1117404SAli.Saidi@ARM.com{ 1128733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 1137439Sdam.sunwoo@arm.com if (!currState) { 1147439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1157439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1167439Sdam.sunwoo@arm.com // TLB miss. 1177439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1187404SAli.Saidi@ARM.com 1197439Sdam.sunwoo@arm.com currState = new WalkerState(); 1207439Sdam.sunwoo@arm.com currState->tableWalker = this; 1218202SAli.Saidi@ARM.com } else if (_timing) { 1228202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 1238202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 1248202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 1258202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 1268202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 1278202SAli.Saidi@ARM.com // up everything. 1288202SAli.Saidi@ARM.com if (currState->vaddr == _req->getVaddr()) { 1298202SAli.Saidi@ARM.com return new ReExec; 1308202SAli.Saidi@ARM.com } 1317439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 1327439Sdam.sunwoo@arm.com } 1337439Sdam.sunwoo@arm.com 1347439Sdam.sunwoo@arm.com currState->tc = _tc; 1357439Sdam.sunwoo@arm.com currState->transState = _trans; 1367439Sdam.sunwoo@arm.com currState->req = _req; 1377439Sdam.sunwoo@arm.com currState->fault = NoFault; 1387439Sdam.sunwoo@arm.com currState->contextId = _cid; 1397439Sdam.sunwoo@arm.com currState->timing = _timing; 1408733Sgeoffrey.blake@arm.com currState->functional = _functional; 1417439Sdam.sunwoo@arm.com currState->mode = _mode; 1427404SAli.Saidi@ARM.com 1437436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1447436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1457720Sgblack@eecs.umich.edu currState->vaddr = currState->req->getVaddr(); 1467439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1477439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1487439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1497439Sdam.sunwoo@arm.com 1507439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1517439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1527439Sdam.sunwoo@arm.com 1537728SAli.Saidi@ARM.com 1547728SAli.Saidi@ARM.com if (!currState->timing) 1557728SAli.Saidi@ARM.com return processWalk(); 1567728SAli.Saidi@ARM.com 1578067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 1587728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 1597728SAli.Saidi@ARM.com currState = NULL; 1607728SAli.Saidi@ARM.com } else { 1617728SAli.Saidi@ARM.com pending = true; 1628067SAli.Saidi@ARM.com return processWalk(); 1637728SAli.Saidi@ARM.com } 1647728SAli.Saidi@ARM.com 1657728SAli.Saidi@ARM.com return NoFault; 1667728SAli.Saidi@ARM.com} 1677728SAli.Saidi@ARM.com 1687728SAli.Saidi@ARM.comvoid 1697728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 1707728SAli.Saidi@ARM.com{ 1717728SAli.Saidi@ARM.com assert(!currState); 1727728SAli.Saidi@ARM.com assert(pendingQueue.size()); 1737728SAli.Saidi@ARM.com currState = pendingQueue.front(); 1747728SAli.Saidi@ARM.com pendingQueue.pop_front(); 1757728SAli.Saidi@ARM.com pending = true; 1767728SAli.Saidi@ARM.com processWalk(); 1777728SAli.Saidi@ARM.com} 1787728SAli.Saidi@ARM.com 1797728SAli.Saidi@ARM.comFault 1807728SAli.Saidi@ARM.comTableWalker::processWalk() 1817728SAli.Saidi@ARM.com{ 1827404SAli.Saidi@ARM.com Addr ttbr = 0; 1837404SAli.Saidi@ARM.com 1847404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1857439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1867404SAli.Saidi@ARM.com 1877406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1887439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 1897439Sdam.sunwoo@arm.com 32-currState->N)); 1907406SAli.Saidi@ARM.com 1917439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 1927406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1937439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 1947404SAli.Saidi@ARM.com } else { 1957406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1967439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 1977439Sdam.sunwoo@arm.com currState->N = 0; 1987404SAli.Saidi@ARM.com } 1997404SAli.Saidi@ARM.com 2007439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 2017439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 2027406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 2037404SAli.Saidi@ARM.com 2047404SAli.Saidi@ARM.com 2057404SAli.Saidi@ARM.com // Trickbox address check 2067439Sdam.sunwoo@arm.com Fault f; 2077439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 2087439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 2097439Sdam.sunwoo@arm.com if (f) { 2108067SAli.Saidi@ARM.com DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr); 2117579Sminkyu.jeong@arm.com if (currState->timing) { 2127728SAli.Saidi@ARM.com pending = false; 2137728SAli.Saidi@ARM.com nextWalk(currState->tc); 2147579Sminkyu.jeong@arm.com currState = NULL; 2157579Sminkyu.jeong@arm.com } else { 2167579Sminkyu.jeong@arm.com currState->tc = NULL; 2177579Sminkyu.jeong@arm.com currState->req = NULL; 2187579Sminkyu.jeong@arm.com } 2197579Sminkyu.jeong@arm.com return f; 2207404SAli.Saidi@ARM.com } 2217404SAli.Saidi@ARM.com 2227946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 2237946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 2247946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 2257946SGiacomo.Gabrielli@arm.com } 2267946SGiacomo.Gabrielli@arm.com 2277439Sdam.sunwoo@arm.com if (currState->timing) { 2287404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2297728SAli.Saidi@ARM.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 2307946SGiacomo.Gabrielli@arm.com currState->tc->getCpuPtr()->ticks(1), flag); 2317578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 2327653Sgene.wu@arm.com stateQueueL1.size()); 2337653Sgene.wu@arm.com stateQueueL1.push_back(currState); 2347439Sdam.sunwoo@arm.com currState = NULL; 2358733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 2367404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2377728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l1Desc.data, 2387728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1), flag); 2397404SAli.Saidi@ARM.com doL1Descriptor(); 2407439Sdam.sunwoo@arm.com f = currState->fault; 2418733Sgeoffrey.blake@arm.com } else { 2428733Sgeoffrey.blake@arm.com RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag); 2438733Sgeoffrey.blake@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 2448733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l1Desc.data); 2458733Sgeoffrey.blake@arm.com port->sendFunctional(pkt); 2468733Sgeoffrey.blake@arm.com doL1Descriptor(); 2478733Sgeoffrey.blake@arm.com delete req; 2488733Sgeoffrey.blake@arm.com delete pkt; 2498733Sgeoffrey.blake@arm.com f = currState->fault; 2507404SAli.Saidi@ARM.com } 2517404SAli.Saidi@ARM.com 2527439Sdam.sunwoo@arm.com return f; 2537404SAli.Saidi@ARM.com} 2547404SAli.Saidi@ARM.com 2557404SAli.Saidi@ARM.comvoid 2567439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 2577439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 2587404SAli.Saidi@ARM.com{ 2597439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 2607439Sdam.sunwoo@arm.com // variables 2617436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 2627436Sdam.sunwoo@arm.com te.shareable = false; // default value 2637582SAli.Saidi@arm.com te.nonCacheable = false; 2647436Sdam.sunwoo@arm.com bool outer_shareable = false; 2657439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 2667404SAli.Saidi@ARM.com switch(texcb) { 2677436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 2687404SAli.Saidi@ARM.com te.nonCacheable = true; 2697436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 2707436Sdam.sunwoo@arm.com te.shareable = true; 2717436Sdam.sunwoo@arm.com te.innerAttrs = 1; 2727436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2737404SAli.Saidi@ARM.com break; 2747436Sdam.sunwoo@arm.com case 1: // Shareable Device 2757436Sdam.sunwoo@arm.com te.nonCacheable = true; 2767436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2777436Sdam.sunwoo@arm.com te.shareable = true; 2787436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2797436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2807436Sdam.sunwoo@arm.com break; 2817436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 2827436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2837436Sdam.sunwoo@arm.com te.shareable = s; 2847436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2857436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2867436Sdam.sunwoo@arm.com break; 2877436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 2887436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2897436Sdam.sunwoo@arm.com te.shareable = s; 2907436Sdam.sunwoo@arm.com te.innerAttrs = 7; 2917436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2927436Sdam.sunwoo@arm.com break; 2937436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 2947436Sdam.sunwoo@arm.com te.nonCacheable = true; 2957436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2967436Sdam.sunwoo@arm.com te.shareable = s; 2977436Sdam.sunwoo@arm.com te.innerAttrs = 0; 2987436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2997436Sdam.sunwoo@arm.com break; 3007436Sdam.sunwoo@arm.com case 5: // Reserved 3017439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3027436Sdam.sunwoo@arm.com break; 3037436Sdam.sunwoo@arm.com case 6: // Implementation Defined 3047439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 3057436Sdam.sunwoo@arm.com break; 3067436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 3077436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3087436Sdam.sunwoo@arm.com te.shareable = s; 3097436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3107436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3117436Sdam.sunwoo@arm.com break; 3127436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 3137436Sdam.sunwoo@arm.com te.nonCacheable = true; 3147436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3157436Sdam.sunwoo@arm.com te.shareable = false; 3167436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3177436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3187436Sdam.sunwoo@arm.com break; 3197436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 3207439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3217436Sdam.sunwoo@arm.com break; 3227436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 3237436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3247436Sdam.sunwoo@arm.com te.shareable = s; 3257404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 3267404SAli.Saidi@ARM.com te.nonCacheable = true; 3277436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 3287436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 3297404SAli.Saidi@ARM.com break; 3307436Sdam.sunwoo@arm.com default: 3317436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 3327404SAli.Saidi@ARM.com } 3337404SAli.Saidi@ARM.com } else { 3347438SAli.Saidi@ARM.com assert(tc); 3357404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3367404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3377436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 3387582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 3397404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 3407404SAli.Saidi@ARM.com case 0: 3417436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 3427436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 3437436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 3447436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 3457404SAli.Saidi@ARM.com break; 3467404SAli.Saidi@ARM.com case 1: 3477436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 3487436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 3497436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 3507436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 3517404SAli.Saidi@ARM.com break; 3527404SAli.Saidi@ARM.com case 2: 3537436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 3547436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 3557436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 3567436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 3577404SAli.Saidi@ARM.com break; 3587404SAli.Saidi@ARM.com case 3: 3597436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 3607436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 3617436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 3627436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 3637404SAli.Saidi@ARM.com break; 3647404SAli.Saidi@ARM.com case 4: 3657436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 3667436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 3677436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 3687436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 3697404SAli.Saidi@ARM.com break; 3707404SAli.Saidi@ARM.com case 5: 3717436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 3727436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 3737436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 3747436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 3757404SAli.Saidi@ARM.com break; 3767404SAli.Saidi@ARM.com case 6: 3777404SAli.Saidi@ARM.com panic("Imp defined type\n"); 3787404SAli.Saidi@ARM.com case 7: 3797436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 3807436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 3817436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 3827436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 3837404SAli.Saidi@ARM.com break; 3847404SAli.Saidi@ARM.com } 3857436Sdam.sunwoo@arm.com 3867436Sdam.sunwoo@arm.com switch(curr_tr) { 3877436Sdam.sunwoo@arm.com case 0: 3887436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 3897436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3907436Sdam.sunwoo@arm.com te.nonCacheable = true; 3917436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3927436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3937436Sdam.sunwoo@arm.com te.shareable = true; 3947436Sdam.sunwoo@arm.com break; 3957436Sdam.sunwoo@arm.com case 1: 3967436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 3977436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 3987436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3997436Sdam.sunwoo@arm.com te.nonCacheable = true; 4007436Sdam.sunwoo@arm.com te.innerAttrs = 3; 4017436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4027436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 4037436Sdam.sunwoo@arm.com te.shareable = true; 4047436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 4057436Sdam.sunwoo@arm.com te.shareable = true; 4067436Sdam.sunwoo@arm.com break; 4077436Sdam.sunwoo@arm.com case 2: 4087436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 4097436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 4107436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 4117436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 4127436Sdam.sunwoo@arm.com te.shareable = true; 4137436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 4147436Sdam.sunwoo@arm.com te.shareable = true; 4157436Sdam.sunwoo@arm.com break; 4167436Sdam.sunwoo@arm.com case 3: 4177436Sdam.sunwoo@arm.com panic("Reserved type"); 4187436Sdam.sunwoo@arm.com } 4197436Sdam.sunwoo@arm.com 4207436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 4217436Sdam.sunwoo@arm.com switch(curr_ir) { 4227436Sdam.sunwoo@arm.com case 0: 4237436Sdam.sunwoo@arm.com te.nonCacheable = true; 4247436Sdam.sunwoo@arm.com te.innerAttrs = 0; 4257436Sdam.sunwoo@arm.com break; 4267436Sdam.sunwoo@arm.com case 1: 4277436Sdam.sunwoo@arm.com te.innerAttrs = 5; 4287436Sdam.sunwoo@arm.com break; 4297436Sdam.sunwoo@arm.com case 2: 4307436Sdam.sunwoo@arm.com te.innerAttrs = 6; 4317436Sdam.sunwoo@arm.com break; 4327436Sdam.sunwoo@arm.com case 3: 4337436Sdam.sunwoo@arm.com te.innerAttrs = 7; 4347436Sdam.sunwoo@arm.com break; 4357436Sdam.sunwoo@arm.com } 4367436Sdam.sunwoo@arm.com 4377436Sdam.sunwoo@arm.com switch(curr_or) { 4387436Sdam.sunwoo@arm.com case 0: 4397436Sdam.sunwoo@arm.com te.nonCacheable = true; 4407436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4417436Sdam.sunwoo@arm.com break; 4427436Sdam.sunwoo@arm.com case 1: 4437436Sdam.sunwoo@arm.com te.outerAttrs = 1; 4447436Sdam.sunwoo@arm.com break; 4457436Sdam.sunwoo@arm.com case 2: 4467436Sdam.sunwoo@arm.com te.outerAttrs = 2; 4477436Sdam.sunwoo@arm.com break; 4487436Sdam.sunwoo@arm.com case 3: 4497436Sdam.sunwoo@arm.com te.outerAttrs = 3; 4507436Sdam.sunwoo@arm.com break; 4517436Sdam.sunwoo@arm.com } 4527436Sdam.sunwoo@arm.com } 4537404SAli.Saidi@ARM.com } 4547439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 4557439Sdam.sunwoo@arm.com outerAttrs: %d\n", 4567439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 4577436Sdam.sunwoo@arm.com 4587436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 4597436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 4607436Sdam.sunwoo@arm.com * PAR: 4617436Sdam.sunwoo@arm.com * PA [31:12] 4627436Sdam.sunwoo@arm.com * Reserved [11] 4637436Sdam.sunwoo@arm.com * TLB info [10:1] 4647436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 4657436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 4667436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 4677436Sdam.sunwoo@arm.com * SH [7] (Sharable) 4687436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 4697436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 4707436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 4717436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 4727436Sdam.sunwoo@arm.com */ 4737436Sdam.sunwoo@arm.com te.attributes = ( 4747436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 4757436Sdam.sunwoo@arm.com // TODO: NS Bit 4767436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 4777436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 4787436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 4797436Sdam.sunwoo@arm.com // TODO: Supersection bit 4807436Sdam.sunwoo@arm.com // TODO: Fault bit 4817436Sdam.sunwoo@arm.com ); 4827436Sdam.sunwoo@arm.com 4837436Sdam.sunwoo@arm.com 4847404SAli.Saidi@ARM.com} 4857404SAli.Saidi@ARM.com 4867404SAli.Saidi@ARM.comvoid 4877404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 4887404SAli.Saidi@ARM.com{ 4897439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 4907439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 4917404SAli.Saidi@ARM.com TlbEntry te; 4927404SAli.Saidi@ARM.com 4937439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 4947404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 4957404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 4967946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 4977439Sdam.sunwoo@arm.com currState->tc = NULL; 4987439Sdam.sunwoo@arm.com currState->req = NULL; 4997437Sdam.sunwoo@arm.com } 5007406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 5017439Sdam.sunwoo@arm.com if (currState->isFetch) 5027439Sdam.sunwoo@arm.com currState->fault = 5037439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 5047406SAli.Saidi@ARM.com else 5057439Sdam.sunwoo@arm.com currState->fault = 5067576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5077436Sdam.sunwoo@arm.com ArmFault::Translation0); 5087404SAli.Saidi@ARM.com return; 5097404SAli.Saidi@ARM.com case L1Descriptor::Section: 5107439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 5117436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 5127436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 5137436Sdam.sunwoo@arm.com * AccessFlag0 5147436Sdam.sunwoo@arm.com */ 5157436Sdam.sunwoo@arm.com 5167611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 5177611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 5187436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 5197436Sdam.sunwoo@arm.com } 5207439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 5217404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 5227404SAli.Saidi@ARM.com } 5237404SAli.Saidi@ARM.com te.N = 20; 5247439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 5257404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 5267439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 5277404SAli.Saidi@ARM.com te.valid = true; 5287439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5297404SAli.Saidi@ARM.com te.sNp = true; 5307439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 5317439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 5327439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5337439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5347439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 5357439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 5367404SAli.Saidi@ARM.com 5377404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 5387582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 5397404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 5407582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 5417582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 5427582SAli.Saidi@arm.com te.nonCacheable); 5437404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 5447439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 5457439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 5467404SAli.Saidi@ARM.com 5477439Sdam.sunwoo@arm.com if (!currState->timing) { 5487439Sdam.sunwoo@arm.com currState->tc = NULL; 5497439Sdam.sunwoo@arm.com currState->req = NULL; 5507437Sdam.sunwoo@arm.com } 5517439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5527404SAli.Saidi@ARM.com 5537404SAli.Saidi@ARM.com return; 5547404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 5557404SAli.Saidi@ARM.com Addr l2desc_addr; 5567439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 5577439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 5587436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 5597436Sdam.sunwoo@arm.com l2desc_addr); 5607404SAli.Saidi@ARM.com 5617404SAli.Saidi@ARM.com // Trickbox address check 5627439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 5637439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 5647439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 5657439Sdam.sunwoo@arm.com 5667439Sdam.sunwoo@arm.com if (currState->fault) { 5677439Sdam.sunwoo@arm.com if (!currState->timing) { 5687439Sdam.sunwoo@arm.com currState->tc = NULL; 5697439Sdam.sunwoo@arm.com currState->req = NULL; 5707437Sdam.sunwoo@arm.com } 5717437Sdam.sunwoo@arm.com return; 5727404SAli.Saidi@ARM.com } 5737404SAli.Saidi@ARM.com 5747404SAli.Saidi@ARM.com 5757439Sdam.sunwoo@arm.com if (currState->timing) { 5767439Sdam.sunwoo@arm.com currState->delayed = true; 5777404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5787728SAli.Saidi@ARM.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 5797728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5808733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 5817404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5827728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l2Desc.data, 5837728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5847404SAli.Saidi@ARM.com doL2Descriptor(); 5858733Sgeoffrey.blake@arm.com } else { 5868733Sgeoffrey.blake@arm.com RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0); 5878733Sgeoffrey.blake@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 5888733Sgeoffrey.blake@arm.com pkt->dataStatic((uint8_t*)&currState->l2Desc.data); 5898733Sgeoffrey.blake@arm.com port->sendFunctional(pkt); 5908733Sgeoffrey.blake@arm.com doL2Descriptor(); 5918733Sgeoffrey.blake@arm.com delete req; 5928733Sgeoffrey.blake@arm.com delete pkt; 5937404SAli.Saidi@ARM.com } 5947404SAli.Saidi@ARM.com return; 5957404SAli.Saidi@ARM.com default: 5967404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 5977404SAli.Saidi@ARM.com } 5987404SAli.Saidi@ARM.com} 5997404SAli.Saidi@ARM.com 6007404SAli.Saidi@ARM.comvoid 6017404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 6027404SAli.Saidi@ARM.com{ 6037439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 6047439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 6057404SAli.Saidi@ARM.com TlbEntry te; 6067404SAli.Saidi@ARM.com 6077439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 6087404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 6097946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6107439Sdam.sunwoo@arm.com currState->tc = NULL; 6117439Sdam.sunwoo@arm.com currState->req = NULL; 6127437Sdam.sunwoo@arm.com } 6137439Sdam.sunwoo@arm.com if (currState->isFetch) 6147439Sdam.sunwoo@arm.com currState->fault = 6157439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 6167406SAli.Saidi@ARM.com else 6177439Sdam.sunwoo@arm.com currState->fault = 6187439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 6197439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 6207404SAli.Saidi@ARM.com return; 6217404SAli.Saidi@ARM.com } 6227404SAli.Saidi@ARM.com 6237439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 6247436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 6257436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 6267436Sdam.sunwoo@arm.com */ 6277436Sdam.sunwoo@arm.com 6287439Sdam.sunwoo@arm.com currState->fault = 6297576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 6307439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 6317439Sdam.sunwoo@arm.com 6327436Sdam.sunwoo@arm.com } 6337436Sdam.sunwoo@arm.com 6347439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 6357404SAli.Saidi@ARM.com te.N = 16; 6367439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6377404SAli.Saidi@ARM.com } else { 6387404SAli.Saidi@ARM.com te.N = 12; 6397439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6407404SAli.Saidi@ARM.com } 6417404SAli.Saidi@ARM.com 6427404SAli.Saidi@ARM.com te.valid = true; 6437404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 6447439Sdam.sunwoo@arm.com te.asid = currState->contextId; 6457404SAli.Saidi@ARM.com te.sNp = false; 6467439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 6477439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 6487439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 6497439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 6507439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 6517439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 6527439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 6537404SAli.Saidi@ARM.com 6547946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6557439Sdam.sunwoo@arm.com currState->tc = NULL; 6567439Sdam.sunwoo@arm.com currState->req = NULL; 6577437Sdam.sunwoo@arm.com } 6587439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 6597437Sdam.sunwoo@arm.com} 6607437Sdam.sunwoo@arm.com 6617437Sdam.sunwoo@arm.comvoid 6627437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 6637437Sdam.sunwoo@arm.com{ 6647653Sgene.wu@arm.com currState = stateQueueL1.front(); 6657439Sdam.sunwoo@arm.com currState->delayed = false; 6667437Sdam.sunwoo@arm.com 6677578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 6687578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 6697578Sdam.sunwoo@arm.com 6707439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 6717437Sdam.sunwoo@arm.com doL1Descriptor(); 6727437Sdam.sunwoo@arm.com 6737653Sgene.wu@arm.com stateQueueL1.pop_front(); 6747437Sdam.sunwoo@arm.com // Check if fault was generated 6757439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6767439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6777439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6787437Sdam.sunwoo@arm.com 6797728SAli.Saidi@ARM.com pending = false; 6807728SAli.Saidi@ARM.com nextWalk(currState->tc); 6817728SAli.Saidi@ARM.com 6827439Sdam.sunwoo@arm.com currState->req = NULL; 6837439Sdam.sunwoo@arm.com currState->tc = NULL; 6847439Sdam.sunwoo@arm.com currState->delayed = false; 6858510SAli.Saidi@ARM.com delete currState; 6867437Sdam.sunwoo@arm.com } 6877439Sdam.sunwoo@arm.com else if (!currState->delayed) { 6887653Sgene.wu@arm.com // delay is not set so there is no L2 to do 6897437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6907439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6917439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6927437Sdam.sunwoo@arm.com 6937728SAli.Saidi@ARM.com pending = false; 6947728SAli.Saidi@ARM.com nextWalk(currState->tc); 6957728SAli.Saidi@ARM.com 6967439Sdam.sunwoo@arm.com currState->req = NULL; 6977439Sdam.sunwoo@arm.com currState->tc = NULL; 6987439Sdam.sunwoo@arm.com currState->delayed = false; 6997653Sgene.wu@arm.com delete currState; 7007653Sgene.wu@arm.com } else { 7017653Sgene.wu@arm.com // need to do L2 descriptor 7027653Sgene.wu@arm.com stateQueueL2.push_back(currState); 7037437Sdam.sunwoo@arm.com } 7047439Sdam.sunwoo@arm.com currState = NULL; 7057437Sdam.sunwoo@arm.com} 7067437Sdam.sunwoo@arm.com 7077437Sdam.sunwoo@arm.comvoid 7087437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 7097437Sdam.sunwoo@arm.com{ 7107653Sgene.wu@arm.com currState = stateQueueL2.front(); 7117439Sdam.sunwoo@arm.com assert(currState->delayed); 7127437Sdam.sunwoo@arm.com 7137439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 7147439Sdam.sunwoo@arm.com currState->vaddr); 7157437Sdam.sunwoo@arm.com doL2Descriptor(); 7167437Sdam.sunwoo@arm.com 7177437Sdam.sunwoo@arm.com // Check if fault was generated 7187439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 7197439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 7207439Sdam.sunwoo@arm.com currState->tc, currState->mode); 7217437Sdam.sunwoo@arm.com } 7227437Sdam.sunwoo@arm.com else { 7237437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7247439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7257439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7267437Sdam.sunwoo@arm.com } 7277437Sdam.sunwoo@arm.com 7287728SAli.Saidi@ARM.com 7297728SAli.Saidi@ARM.com stateQueueL2.pop_front(); 7307728SAli.Saidi@ARM.com pending = false; 7317728SAli.Saidi@ARM.com nextWalk(currState->tc); 7327728SAli.Saidi@ARM.com 7337439Sdam.sunwoo@arm.com currState->req = NULL; 7347439Sdam.sunwoo@arm.com currState->tc = NULL; 7357439Sdam.sunwoo@arm.com currState->delayed = false; 7367439Sdam.sunwoo@arm.com 7377653Sgene.wu@arm.com delete currState; 7387439Sdam.sunwoo@arm.com currState = NULL; 7397404SAli.Saidi@ARM.com} 7407404SAli.Saidi@ARM.com 7417728SAli.Saidi@ARM.comvoid 7427728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 7437728SAli.Saidi@ARM.com{ 7447728SAli.Saidi@ARM.com if (pendingQueue.size()) 7457823Ssteve.reinhardt@amd.com schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1)); 7467728SAli.Saidi@ARM.com} 7477728SAli.Saidi@ARM.com 7487728SAli.Saidi@ARM.com 7497728SAli.Saidi@ARM.com 7507404SAli.Saidi@ARM.comArmISA::TableWalker * 7517404SAli.Saidi@ARM.comArmTableWalkerParams::create() 7527404SAli.Saidi@ARM.com{ 7537404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 7547404SAli.Saidi@ARM.com} 7557404SAli.Saidi@ARM.com 756