table_walker.cc revision 8202
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437404SAli.Saidi@ARM.com#include "dev/io_device.hh" 447728SAli.Saidi@ARM.com#include "cpu/base.hh" 457404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 467748SAli.Saidi@ARM.com#include "sim/system.hh" 477404SAli.Saidi@ARM.com 487404SAli.Saidi@ARM.comusing namespace ArmISA; 497404SAli.Saidi@ARM.com 507404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 517728SAli.Saidi@ARM.com : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false), 527728SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 537439Sdam.sunwoo@arm.com{ 547576SAli.Saidi@ARM.com sctlr = 0; 557439Sdam.sunwoo@arm.com} 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comTableWalker::~TableWalker() 587404SAli.Saidi@ARM.com{ 597404SAli.Saidi@ARM.com ; 607404SAli.Saidi@ARM.com} 617404SAli.Saidi@ARM.com 627404SAli.Saidi@ARM.com 637748SAli.Saidi@ARM.comunsigned int 647748SAli.Saidi@ARM.comTableWalker::drain(Event *de) 657404SAli.Saidi@ARM.com{ 667748SAli.Saidi@ARM.com if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size()) 677733SAli.Saidi@ARM.com { 687733SAli.Saidi@ARM.com changeState(Draining); 697733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n"); 707733SAli.Saidi@ARM.com return 1; 717733SAli.Saidi@ARM.com } 727733SAli.Saidi@ARM.com else 737733SAli.Saidi@ARM.com { 747733SAli.Saidi@ARM.com changeState(Drained); 757733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "TableWalker free, no need to drain\n"); 767733SAli.Saidi@ARM.com return 0; 777733SAli.Saidi@ARM.com } 787404SAli.Saidi@ARM.com} 797404SAli.Saidi@ARM.com 807748SAli.Saidi@ARM.comvoid 817748SAli.Saidi@ARM.comTableWalker::resume() 827748SAli.Saidi@ARM.com{ 837748SAli.Saidi@ARM.com MemObject::resume(); 847748SAli.Saidi@ARM.com if ((params()->sys->getMemoryMode() == Enums::timing) && currState) { 857748SAli.Saidi@ARM.com delete currState; 867748SAli.Saidi@ARM.com currState = NULL; 877748SAli.Saidi@ARM.com } 887748SAli.Saidi@ARM.com} 897748SAli.Saidi@ARM.com 907404SAli.Saidi@ARM.comPort* 917404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 927404SAli.Saidi@ARM.com{ 937404SAli.Saidi@ARM.com if (if_name == "port") { 947404SAli.Saidi@ARM.com if (port != NULL) 957781SAli.Saidi@ARM.com return port; 967404SAli.Saidi@ARM.com System *sys = params()->sys; 977404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 987404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 997404SAli.Saidi@ARM.com port = new DmaPort(this, sys, minb, maxb); 1007404SAli.Saidi@ARM.com return port; 1017404SAli.Saidi@ARM.com } 1027404SAli.Saidi@ARM.com return NULL; 1037404SAli.Saidi@ARM.com} 1047404SAli.Saidi@ARM.com 1057404SAli.Saidi@ARM.comFault 1067437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 1077404SAli.Saidi@ARM.com TLB::Translation *_trans, bool _timing) 1087404SAli.Saidi@ARM.com{ 1097439Sdam.sunwoo@arm.com if (!currState) { 1107439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1117439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1127439Sdam.sunwoo@arm.com // TLB miss. 1137439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1147404SAli.Saidi@ARM.com 1157439Sdam.sunwoo@arm.com currState = new WalkerState(); 1167439Sdam.sunwoo@arm.com currState->tableWalker = this; 1178202SAli.Saidi@ARM.com } else if (_timing) { 1188202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 1198202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 1208202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 1218202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 1228202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 1238202SAli.Saidi@ARM.com // up everything. 1248202SAli.Saidi@ARM.com if (currState->vaddr == _req->getVaddr()) { 1258202SAli.Saidi@ARM.com return new ReExec; 1268202SAli.Saidi@ARM.com } 1277439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 1287439Sdam.sunwoo@arm.com } 1297439Sdam.sunwoo@arm.com 1307439Sdam.sunwoo@arm.com currState->tc = _tc; 1317439Sdam.sunwoo@arm.com currState->transState = _trans; 1327439Sdam.sunwoo@arm.com currState->req = _req; 1337439Sdam.sunwoo@arm.com currState->fault = NoFault; 1347439Sdam.sunwoo@arm.com currState->contextId = _cid; 1357439Sdam.sunwoo@arm.com currState->timing = _timing; 1367439Sdam.sunwoo@arm.com currState->mode = _mode; 1377404SAli.Saidi@ARM.com 1387436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1397436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1407720Sgblack@eecs.umich.edu currState->vaddr = currState->req->getVaddr(); 1417439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1427439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1437439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1447439Sdam.sunwoo@arm.com 1457439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1467439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1477439Sdam.sunwoo@arm.com 1487728SAli.Saidi@ARM.com 1497728SAli.Saidi@ARM.com if (!currState->timing) 1507728SAli.Saidi@ARM.com return processWalk(); 1517728SAli.Saidi@ARM.com 1528067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 1537728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 1547728SAli.Saidi@ARM.com currState = NULL; 1557728SAli.Saidi@ARM.com } else { 1567728SAli.Saidi@ARM.com pending = true; 1578067SAli.Saidi@ARM.com return processWalk(); 1587728SAli.Saidi@ARM.com } 1597728SAli.Saidi@ARM.com 1607728SAli.Saidi@ARM.com return NoFault; 1617728SAli.Saidi@ARM.com} 1627728SAli.Saidi@ARM.com 1637728SAli.Saidi@ARM.comvoid 1647728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 1657728SAli.Saidi@ARM.com{ 1667728SAli.Saidi@ARM.com assert(!currState); 1677728SAli.Saidi@ARM.com assert(pendingQueue.size()); 1687728SAli.Saidi@ARM.com currState = pendingQueue.front(); 1697728SAli.Saidi@ARM.com pendingQueue.pop_front(); 1707728SAli.Saidi@ARM.com pending = true; 1717728SAli.Saidi@ARM.com processWalk(); 1727728SAli.Saidi@ARM.com} 1737728SAli.Saidi@ARM.com 1747728SAli.Saidi@ARM.comFault 1757728SAli.Saidi@ARM.comTableWalker::processWalk() 1767728SAli.Saidi@ARM.com{ 1777404SAli.Saidi@ARM.com Addr ttbr = 0; 1787404SAli.Saidi@ARM.com 1797404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1807439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1817404SAli.Saidi@ARM.com 1827406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1837439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 1847439Sdam.sunwoo@arm.com 32-currState->N)); 1857406SAli.Saidi@ARM.com 1867439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 1877406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1887439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 1897404SAli.Saidi@ARM.com } else { 1907406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1917439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 1927439Sdam.sunwoo@arm.com currState->N = 0; 1937404SAli.Saidi@ARM.com } 1947404SAli.Saidi@ARM.com 1957439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 1967439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 1977406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1987404SAli.Saidi@ARM.com 1997404SAli.Saidi@ARM.com 2007404SAli.Saidi@ARM.com // Trickbox address check 2017439Sdam.sunwoo@arm.com Fault f; 2027439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 2037439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 2047439Sdam.sunwoo@arm.com if (f) { 2058067SAli.Saidi@ARM.com DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr); 2067579Sminkyu.jeong@arm.com if (currState->timing) { 2077728SAli.Saidi@ARM.com pending = false; 2087728SAli.Saidi@ARM.com nextWalk(currState->tc); 2097579Sminkyu.jeong@arm.com currState = NULL; 2107579Sminkyu.jeong@arm.com } else { 2117579Sminkyu.jeong@arm.com currState->tc = NULL; 2127579Sminkyu.jeong@arm.com currState->req = NULL; 2137579Sminkyu.jeong@arm.com } 2147579Sminkyu.jeong@arm.com return f; 2157404SAli.Saidi@ARM.com } 2167404SAli.Saidi@ARM.com 2177946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 2187946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 2197946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 2207946SGiacomo.Gabrielli@arm.com } 2217946SGiacomo.Gabrielli@arm.com 2227439Sdam.sunwoo@arm.com if (currState->timing) { 2237404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2247728SAli.Saidi@ARM.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 2257946SGiacomo.Gabrielli@arm.com currState->tc->getCpuPtr()->ticks(1), flag); 2267578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 2277653Sgene.wu@arm.com stateQueueL1.size()); 2287653Sgene.wu@arm.com stateQueueL1.push_back(currState); 2297439Sdam.sunwoo@arm.com currState = NULL; 2307404SAli.Saidi@ARM.com } else { 2317404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2327728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l1Desc.data, 2337728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1), flag); 2347404SAli.Saidi@ARM.com doL1Descriptor(); 2357439Sdam.sunwoo@arm.com f = currState->fault; 2367404SAli.Saidi@ARM.com } 2377404SAli.Saidi@ARM.com 2387439Sdam.sunwoo@arm.com return f; 2397404SAli.Saidi@ARM.com} 2407404SAli.Saidi@ARM.com 2417404SAli.Saidi@ARM.comvoid 2427439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 2437439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 2447404SAli.Saidi@ARM.com{ 2457439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 2467439Sdam.sunwoo@arm.com // variables 2477436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 2487436Sdam.sunwoo@arm.com te.shareable = false; // default value 2497582SAli.Saidi@arm.com te.nonCacheable = false; 2507436Sdam.sunwoo@arm.com bool outer_shareable = false; 2517439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 2527404SAli.Saidi@ARM.com switch(texcb) { 2537436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 2547404SAli.Saidi@ARM.com te.nonCacheable = true; 2557436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 2567436Sdam.sunwoo@arm.com te.shareable = true; 2577436Sdam.sunwoo@arm.com te.innerAttrs = 1; 2587436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2597404SAli.Saidi@ARM.com break; 2607436Sdam.sunwoo@arm.com case 1: // Shareable Device 2617436Sdam.sunwoo@arm.com te.nonCacheable = true; 2627436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2637436Sdam.sunwoo@arm.com te.shareable = true; 2647436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2657436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2667436Sdam.sunwoo@arm.com break; 2677436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 2687436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2697436Sdam.sunwoo@arm.com te.shareable = s; 2707436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2717436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2727436Sdam.sunwoo@arm.com break; 2737436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 2747436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2757436Sdam.sunwoo@arm.com te.shareable = s; 2767436Sdam.sunwoo@arm.com te.innerAttrs = 7; 2777436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2787436Sdam.sunwoo@arm.com break; 2797436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 2807436Sdam.sunwoo@arm.com te.nonCacheable = true; 2817436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2827436Sdam.sunwoo@arm.com te.shareable = s; 2837436Sdam.sunwoo@arm.com te.innerAttrs = 0; 2847436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2857436Sdam.sunwoo@arm.com break; 2867436Sdam.sunwoo@arm.com case 5: // Reserved 2877439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2887436Sdam.sunwoo@arm.com break; 2897436Sdam.sunwoo@arm.com case 6: // Implementation Defined 2907439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 2917436Sdam.sunwoo@arm.com break; 2927436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 2937436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2947436Sdam.sunwoo@arm.com te.shareable = s; 2957436Sdam.sunwoo@arm.com te.innerAttrs = 5; 2967436Sdam.sunwoo@arm.com te.outerAttrs = 1; 2977436Sdam.sunwoo@arm.com break; 2987436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 2997436Sdam.sunwoo@arm.com te.nonCacheable = true; 3007436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3017436Sdam.sunwoo@arm.com te.shareable = false; 3027436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3037436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3047436Sdam.sunwoo@arm.com break; 3057436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 3067439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 3077436Sdam.sunwoo@arm.com break; 3087436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 3097436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3107436Sdam.sunwoo@arm.com te.shareable = s; 3117404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 3127404SAli.Saidi@ARM.com te.nonCacheable = true; 3137436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 3147436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 3157404SAli.Saidi@ARM.com break; 3167436Sdam.sunwoo@arm.com default: 3177436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 3187404SAli.Saidi@ARM.com } 3197404SAli.Saidi@ARM.com } else { 3207438SAli.Saidi@ARM.com assert(tc); 3217404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 3227404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 3237436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 3247582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 3257404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 3267404SAli.Saidi@ARM.com case 0: 3277436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 3287436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 3297436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 3307436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 3317404SAli.Saidi@ARM.com break; 3327404SAli.Saidi@ARM.com case 1: 3337436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 3347436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 3357436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 3367436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 3377404SAli.Saidi@ARM.com break; 3387404SAli.Saidi@ARM.com case 2: 3397436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 3407436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 3417436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 3427436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 3437404SAli.Saidi@ARM.com break; 3447404SAli.Saidi@ARM.com case 3: 3457436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 3467436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 3477436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 3487436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 3497404SAli.Saidi@ARM.com break; 3507404SAli.Saidi@ARM.com case 4: 3517436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 3527436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 3537436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 3547436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 3557404SAli.Saidi@ARM.com break; 3567404SAli.Saidi@ARM.com case 5: 3577436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 3587436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 3597436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 3607436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 3617404SAli.Saidi@ARM.com break; 3627404SAli.Saidi@ARM.com case 6: 3637404SAli.Saidi@ARM.com panic("Imp defined type\n"); 3647404SAli.Saidi@ARM.com case 7: 3657436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 3667436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 3677436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 3687436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 3697404SAli.Saidi@ARM.com break; 3707404SAli.Saidi@ARM.com } 3717436Sdam.sunwoo@arm.com 3727436Sdam.sunwoo@arm.com switch(curr_tr) { 3737436Sdam.sunwoo@arm.com case 0: 3747436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 3757436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3767436Sdam.sunwoo@arm.com te.nonCacheable = true; 3777436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3787436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3797436Sdam.sunwoo@arm.com te.shareable = true; 3807436Sdam.sunwoo@arm.com break; 3817436Sdam.sunwoo@arm.com case 1: 3827436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 3837436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 3847436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3857436Sdam.sunwoo@arm.com te.nonCacheable = true; 3867436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3877436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3887436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 3897436Sdam.sunwoo@arm.com te.shareable = true; 3907436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 3917436Sdam.sunwoo@arm.com te.shareable = true; 3927436Sdam.sunwoo@arm.com break; 3937436Sdam.sunwoo@arm.com case 2: 3947436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 3957436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 3967436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3977436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 3987436Sdam.sunwoo@arm.com te.shareable = true; 3997436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 4007436Sdam.sunwoo@arm.com te.shareable = true; 4017436Sdam.sunwoo@arm.com break; 4027436Sdam.sunwoo@arm.com case 3: 4037436Sdam.sunwoo@arm.com panic("Reserved type"); 4047436Sdam.sunwoo@arm.com } 4057436Sdam.sunwoo@arm.com 4067436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 4077436Sdam.sunwoo@arm.com switch(curr_ir) { 4087436Sdam.sunwoo@arm.com case 0: 4097436Sdam.sunwoo@arm.com te.nonCacheable = true; 4107436Sdam.sunwoo@arm.com te.innerAttrs = 0; 4117436Sdam.sunwoo@arm.com break; 4127436Sdam.sunwoo@arm.com case 1: 4137436Sdam.sunwoo@arm.com te.innerAttrs = 5; 4147436Sdam.sunwoo@arm.com break; 4157436Sdam.sunwoo@arm.com case 2: 4167436Sdam.sunwoo@arm.com te.innerAttrs = 6; 4177436Sdam.sunwoo@arm.com break; 4187436Sdam.sunwoo@arm.com case 3: 4197436Sdam.sunwoo@arm.com te.innerAttrs = 7; 4207436Sdam.sunwoo@arm.com break; 4217436Sdam.sunwoo@arm.com } 4227436Sdam.sunwoo@arm.com 4237436Sdam.sunwoo@arm.com switch(curr_or) { 4247436Sdam.sunwoo@arm.com case 0: 4257436Sdam.sunwoo@arm.com te.nonCacheable = true; 4267436Sdam.sunwoo@arm.com te.outerAttrs = 0; 4277436Sdam.sunwoo@arm.com break; 4287436Sdam.sunwoo@arm.com case 1: 4297436Sdam.sunwoo@arm.com te.outerAttrs = 1; 4307436Sdam.sunwoo@arm.com break; 4317436Sdam.sunwoo@arm.com case 2: 4327436Sdam.sunwoo@arm.com te.outerAttrs = 2; 4337436Sdam.sunwoo@arm.com break; 4347436Sdam.sunwoo@arm.com case 3: 4357436Sdam.sunwoo@arm.com te.outerAttrs = 3; 4367436Sdam.sunwoo@arm.com break; 4377436Sdam.sunwoo@arm.com } 4387436Sdam.sunwoo@arm.com } 4397404SAli.Saidi@ARM.com } 4407439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 4417439Sdam.sunwoo@arm.com outerAttrs: %d\n", 4427439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 4437436Sdam.sunwoo@arm.com 4447436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 4457436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 4467436Sdam.sunwoo@arm.com * PAR: 4477436Sdam.sunwoo@arm.com * PA [31:12] 4487436Sdam.sunwoo@arm.com * Reserved [11] 4497436Sdam.sunwoo@arm.com * TLB info [10:1] 4507436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 4517436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 4527436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 4537436Sdam.sunwoo@arm.com * SH [7] (Sharable) 4547436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 4557436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 4567436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 4577436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 4587436Sdam.sunwoo@arm.com */ 4597436Sdam.sunwoo@arm.com te.attributes = ( 4607436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 4617436Sdam.sunwoo@arm.com // TODO: NS Bit 4627436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 4637436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 4647436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 4657436Sdam.sunwoo@arm.com // TODO: Supersection bit 4667436Sdam.sunwoo@arm.com // TODO: Fault bit 4677436Sdam.sunwoo@arm.com ); 4687436Sdam.sunwoo@arm.com 4697436Sdam.sunwoo@arm.com 4707404SAli.Saidi@ARM.com} 4717404SAli.Saidi@ARM.com 4727404SAli.Saidi@ARM.comvoid 4737404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 4747404SAli.Saidi@ARM.com{ 4757439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 4767439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 4777404SAli.Saidi@ARM.com TlbEntry te; 4787404SAli.Saidi@ARM.com 4797439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 4807404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 4817404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 4827946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 4837439Sdam.sunwoo@arm.com currState->tc = NULL; 4847439Sdam.sunwoo@arm.com currState->req = NULL; 4857437Sdam.sunwoo@arm.com } 4867406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 4877439Sdam.sunwoo@arm.com if (currState->isFetch) 4887439Sdam.sunwoo@arm.com currState->fault = 4897439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 4907406SAli.Saidi@ARM.com else 4917439Sdam.sunwoo@arm.com currState->fault = 4927576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 4937436Sdam.sunwoo@arm.com ArmFault::Translation0); 4947404SAli.Saidi@ARM.com return; 4957404SAli.Saidi@ARM.com case L1Descriptor::Section: 4967439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 4977436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 4987436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 4997436Sdam.sunwoo@arm.com * AccessFlag0 5007436Sdam.sunwoo@arm.com */ 5017436Sdam.sunwoo@arm.com 5027611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 5037611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 5047436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 5057436Sdam.sunwoo@arm.com } 5067439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 5077404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 5087404SAli.Saidi@ARM.com } 5097404SAli.Saidi@ARM.com te.N = 20; 5107439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 5117404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 5127439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 5137404SAli.Saidi@ARM.com te.valid = true; 5147439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5157404SAli.Saidi@ARM.com te.sNp = true; 5167439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 5177439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 5187439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5197439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5207439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 5217439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 5227404SAli.Saidi@ARM.com 5237404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 5247582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 5257404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 5267582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 5277582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 5287582SAli.Saidi@arm.com te.nonCacheable); 5297404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 5307439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 5317439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 5327404SAli.Saidi@ARM.com 5337439Sdam.sunwoo@arm.com if (!currState->timing) { 5347439Sdam.sunwoo@arm.com currState->tc = NULL; 5357439Sdam.sunwoo@arm.com currState->req = NULL; 5367437Sdam.sunwoo@arm.com } 5377439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5387404SAli.Saidi@ARM.com 5397404SAli.Saidi@ARM.com return; 5407404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 5417404SAli.Saidi@ARM.com Addr l2desc_addr; 5427439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 5437439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 5447436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 5457436Sdam.sunwoo@arm.com l2desc_addr); 5467404SAli.Saidi@ARM.com 5477404SAli.Saidi@ARM.com // Trickbox address check 5487439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 5497439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 5507439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 5517439Sdam.sunwoo@arm.com 5527439Sdam.sunwoo@arm.com if (currState->fault) { 5537439Sdam.sunwoo@arm.com if (!currState->timing) { 5547439Sdam.sunwoo@arm.com currState->tc = NULL; 5557439Sdam.sunwoo@arm.com currState->req = NULL; 5567437Sdam.sunwoo@arm.com } 5577437Sdam.sunwoo@arm.com return; 5587404SAli.Saidi@ARM.com } 5597404SAli.Saidi@ARM.com 5607404SAli.Saidi@ARM.com 5617439Sdam.sunwoo@arm.com if (currState->timing) { 5627439Sdam.sunwoo@arm.com currState->delayed = true; 5637404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5647728SAli.Saidi@ARM.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 5657728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5667404SAli.Saidi@ARM.com } else { 5677404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5687728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l2Desc.data, 5697728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5707404SAli.Saidi@ARM.com doL2Descriptor(); 5717404SAli.Saidi@ARM.com } 5727404SAli.Saidi@ARM.com return; 5737404SAli.Saidi@ARM.com default: 5747404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 5757404SAli.Saidi@ARM.com } 5767404SAli.Saidi@ARM.com} 5777404SAli.Saidi@ARM.com 5787404SAli.Saidi@ARM.comvoid 5797404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 5807404SAli.Saidi@ARM.com{ 5817439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 5827439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 5837404SAli.Saidi@ARM.com TlbEntry te; 5847404SAli.Saidi@ARM.com 5857439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 5867404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 5877946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 5887439Sdam.sunwoo@arm.com currState->tc = NULL; 5897439Sdam.sunwoo@arm.com currState->req = NULL; 5907437Sdam.sunwoo@arm.com } 5917439Sdam.sunwoo@arm.com if (currState->isFetch) 5927439Sdam.sunwoo@arm.com currState->fault = 5937439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 5947406SAli.Saidi@ARM.com else 5957439Sdam.sunwoo@arm.com currState->fault = 5967439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 5977439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 5987404SAli.Saidi@ARM.com return; 5997404SAli.Saidi@ARM.com } 6007404SAli.Saidi@ARM.com 6017439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 6027436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 6037436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 6047436Sdam.sunwoo@arm.com */ 6057436Sdam.sunwoo@arm.com 6067439Sdam.sunwoo@arm.com currState->fault = 6077576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 6087439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 6097439Sdam.sunwoo@arm.com 6107436Sdam.sunwoo@arm.com } 6117436Sdam.sunwoo@arm.com 6127439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 6137404SAli.Saidi@ARM.com te.N = 16; 6147439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6157404SAli.Saidi@ARM.com } else { 6167404SAli.Saidi@ARM.com te.N = 12; 6177439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 6187404SAli.Saidi@ARM.com } 6197404SAli.Saidi@ARM.com 6207404SAli.Saidi@ARM.com te.valid = true; 6217404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 6227439Sdam.sunwoo@arm.com te.asid = currState->contextId; 6237404SAli.Saidi@ARM.com te.sNp = false; 6247439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 6257439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 6267439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 6277439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 6287439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 6297439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 6307439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 6317404SAli.Saidi@ARM.com 6327946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 6337439Sdam.sunwoo@arm.com currState->tc = NULL; 6347439Sdam.sunwoo@arm.com currState->req = NULL; 6357437Sdam.sunwoo@arm.com } 6367439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 6377437Sdam.sunwoo@arm.com} 6387437Sdam.sunwoo@arm.com 6397437Sdam.sunwoo@arm.comvoid 6407437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 6417437Sdam.sunwoo@arm.com{ 6427653Sgene.wu@arm.com currState = stateQueueL1.front(); 6437439Sdam.sunwoo@arm.com currState->delayed = false; 6447437Sdam.sunwoo@arm.com 6457578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 6467578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 6477578Sdam.sunwoo@arm.com 6487439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 6497437Sdam.sunwoo@arm.com doL1Descriptor(); 6507437Sdam.sunwoo@arm.com 6517653Sgene.wu@arm.com stateQueueL1.pop_front(); 6527437Sdam.sunwoo@arm.com // Check if fault was generated 6537439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6547439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6557439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6567437Sdam.sunwoo@arm.com 6577728SAli.Saidi@ARM.com pending = false; 6587728SAli.Saidi@ARM.com nextWalk(currState->tc); 6597728SAli.Saidi@ARM.com 6607439Sdam.sunwoo@arm.com currState->req = NULL; 6617439Sdam.sunwoo@arm.com currState->tc = NULL; 6627439Sdam.sunwoo@arm.com currState->delayed = false; 6637439Sdam.sunwoo@arm.com 6647437Sdam.sunwoo@arm.com } 6657439Sdam.sunwoo@arm.com else if (!currState->delayed) { 6667653Sgene.wu@arm.com // delay is not set so there is no L2 to do 6677437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6687439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6697439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6707437Sdam.sunwoo@arm.com 6717728SAli.Saidi@ARM.com pending = false; 6727728SAli.Saidi@ARM.com nextWalk(currState->tc); 6737728SAli.Saidi@ARM.com 6747439Sdam.sunwoo@arm.com currState->req = NULL; 6757439Sdam.sunwoo@arm.com currState->tc = NULL; 6767439Sdam.sunwoo@arm.com currState->delayed = false; 6777653Sgene.wu@arm.com delete currState; 6787653Sgene.wu@arm.com } else { 6797653Sgene.wu@arm.com // need to do L2 descriptor 6807653Sgene.wu@arm.com stateQueueL2.push_back(currState); 6817437Sdam.sunwoo@arm.com } 6827439Sdam.sunwoo@arm.com currState = NULL; 6837437Sdam.sunwoo@arm.com} 6847437Sdam.sunwoo@arm.com 6857437Sdam.sunwoo@arm.comvoid 6867437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 6877437Sdam.sunwoo@arm.com{ 6887653Sgene.wu@arm.com currState = stateQueueL2.front(); 6897439Sdam.sunwoo@arm.com assert(currState->delayed); 6907437Sdam.sunwoo@arm.com 6917439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 6927439Sdam.sunwoo@arm.com currState->vaddr); 6937437Sdam.sunwoo@arm.com doL2Descriptor(); 6947437Sdam.sunwoo@arm.com 6957437Sdam.sunwoo@arm.com // Check if fault was generated 6967439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6977439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6987439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6997437Sdam.sunwoo@arm.com } 7007437Sdam.sunwoo@arm.com else { 7017437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 7027439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 7037439Sdam.sunwoo@arm.com currState->transState, currState->mode); 7047437Sdam.sunwoo@arm.com } 7057437Sdam.sunwoo@arm.com 7067728SAli.Saidi@ARM.com 7077728SAli.Saidi@ARM.com stateQueueL2.pop_front(); 7087728SAli.Saidi@ARM.com pending = false; 7097728SAli.Saidi@ARM.com nextWalk(currState->tc); 7107728SAli.Saidi@ARM.com 7117439Sdam.sunwoo@arm.com currState->req = NULL; 7127439Sdam.sunwoo@arm.com currState->tc = NULL; 7137439Sdam.sunwoo@arm.com currState->delayed = false; 7147439Sdam.sunwoo@arm.com 7157653Sgene.wu@arm.com delete currState; 7167439Sdam.sunwoo@arm.com currState = NULL; 7177404SAli.Saidi@ARM.com} 7187404SAli.Saidi@ARM.com 7197728SAli.Saidi@ARM.comvoid 7207728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 7217728SAli.Saidi@ARM.com{ 7227728SAli.Saidi@ARM.com if (pendingQueue.size()) 7237823Ssteve.reinhardt@amd.com schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1)); 7247728SAli.Saidi@ARM.com} 7257728SAli.Saidi@ARM.com 7267728SAli.Saidi@ARM.com 7277728SAli.Saidi@ARM.com 7287404SAli.Saidi@ARM.comArmISA::TableWalker * 7297404SAli.Saidi@ARM.comArmTableWalkerParams::create() 7307404SAli.Saidi@ARM.com{ 7317404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 7327404SAli.Saidi@ARM.com} 7337404SAli.Saidi@ARM.com 734