table_walker.cc revision 7728
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437404SAli.Saidi@ARM.com#include "dev/io_device.hh" 447728SAli.Saidi@ARM.com#include "cpu/base.hh" 457404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 467404SAli.Saidi@ARM.com 477404SAli.Saidi@ARM.comusing namespace ArmISA; 487404SAli.Saidi@ARM.com 497404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 507728SAli.Saidi@ARM.com : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false), 517728SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 527439Sdam.sunwoo@arm.com{ 537576SAli.Saidi@ARM.com sctlr = 0; 547439Sdam.sunwoo@arm.com} 557404SAli.Saidi@ARM.com 567404SAli.Saidi@ARM.comTableWalker::~TableWalker() 577404SAli.Saidi@ARM.com{ 587404SAli.Saidi@ARM.com ; 597404SAli.Saidi@ARM.com} 607404SAli.Saidi@ARM.com 617404SAli.Saidi@ARM.com 627404SAli.Saidi@ARM.comunsigned int 637404SAli.Saidi@ARM.comdrain(Event *de) 647404SAli.Saidi@ARM.com{ 657404SAli.Saidi@ARM.com panic("Not implemented\n"); 667404SAli.Saidi@ARM.com} 677404SAli.Saidi@ARM.com 687404SAli.Saidi@ARM.comPort* 697404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 707404SAli.Saidi@ARM.com{ 717404SAli.Saidi@ARM.com if (if_name == "port") { 727404SAli.Saidi@ARM.com if (port != NULL) 737404SAli.Saidi@ARM.com fatal("%s: port already connected to %s", 747404SAli.Saidi@ARM.com name(), port->getPeer()->name()); 757404SAli.Saidi@ARM.com System *sys = params()->sys; 767404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 777404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 787404SAli.Saidi@ARM.com port = new DmaPort(this, sys, minb, maxb); 797404SAli.Saidi@ARM.com return port; 807404SAli.Saidi@ARM.com } 817404SAli.Saidi@ARM.com return NULL; 827404SAli.Saidi@ARM.com} 837404SAli.Saidi@ARM.com 847404SAli.Saidi@ARM.comFault 857437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 867404SAli.Saidi@ARM.com TLB::Translation *_trans, bool _timing) 877404SAli.Saidi@ARM.com{ 887439Sdam.sunwoo@arm.com if (!currState) { 897439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 907439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 917439Sdam.sunwoo@arm.com // TLB miss. 927439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 937404SAli.Saidi@ARM.com 947439Sdam.sunwoo@arm.com currState = new WalkerState(); 957439Sdam.sunwoo@arm.com currState->tableWalker = this; 967439Sdam.sunwoo@arm.com } 977439Sdam.sunwoo@arm.com else if (_timing) { 987439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 997439Sdam.sunwoo@arm.com } 1007439Sdam.sunwoo@arm.com 1017439Sdam.sunwoo@arm.com currState->tc = _tc; 1027439Sdam.sunwoo@arm.com currState->transState = _trans; 1037439Sdam.sunwoo@arm.com currState->req = _req; 1047439Sdam.sunwoo@arm.com currState->fault = NoFault; 1057439Sdam.sunwoo@arm.com currState->contextId = _cid; 1067439Sdam.sunwoo@arm.com currState->timing = _timing; 1077439Sdam.sunwoo@arm.com currState->mode = _mode; 1087404SAli.Saidi@ARM.com 1097436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1107436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1117720Sgblack@eecs.umich.edu currState->vaddr = currState->req->getVaddr(); 1127439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1137439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1147439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1157439Sdam.sunwoo@arm.com 1167439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1177439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1187439Sdam.sunwoo@arm.com 1197728SAli.Saidi@ARM.com 1207728SAli.Saidi@ARM.com if (!currState->timing) 1217728SAli.Saidi@ARM.com return processWalk(); 1227728SAli.Saidi@ARM.com 1237728SAli.Saidi@ARM.com if (pending) { 1247728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 1257728SAli.Saidi@ARM.com currState = NULL; 1267728SAli.Saidi@ARM.com } else { 1277728SAli.Saidi@ARM.com pending = true; 1287728SAli.Saidi@ARM.com processWalk(); 1297728SAli.Saidi@ARM.com } 1307728SAli.Saidi@ARM.com 1317728SAli.Saidi@ARM.com return NoFault; 1327728SAli.Saidi@ARM.com} 1337728SAli.Saidi@ARM.com 1347728SAli.Saidi@ARM.comvoid 1357728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 1367728SAli.Saidi@ARM.com{ 1377728SAli.Saidi@ARM.com assert(!currState); 1387728SAli.Saidi@ARM.com assert(pendingQueue.size()); 1397728SAli.Saidi@ARM.com currState = pendingQueue.front(); 1407728SAli.Saidi@ARM.com pendingQueue.pop_front(); 1417728SAli.Saidi@ARM.com pending = true; 1427728SAli.Saidi@ARM.com processWalk(); 1437728SAli.Saidi@ARM.com} 1447728SAli.Saidi@ARM.com 1457728SAli.Saidi@ARM.comFault 1467728SAli.Saidi@ARM.comTableWalker::processWalk() 1477728SAli.Saidi@ARM.com{ 1487404SAli.Saidi@ARM.com Addr ttbr = 0; 1497404SAli.Saidi@ARM.com 1507404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1517439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1527404SAli.Saidi@ARM.com 1537406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1547439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 1557439Sdam.sunwoo@arm.com 32-currState->N)); 1567406SAli.Saidi@ARM.com 1577439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 1587406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1597439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 1607404SAli.Saidi@ARM.com } else { 1617406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1627439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 1637439Sdam.sunwoo@arm.com currState->N = 0; 1647404SAli.Saidi@ARM.com } 1657404SAli.Saidi@ARM.com 1667439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 1677439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 1687406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1697404SAli.Saidi@ARM.com 1707404SAli.Saidi@ARM.com 1717404SAli.Saidi@ARM.com // Trickbox address check 1727439Sdam.sunwoo@arm.com Fault f; 1737439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 1747439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 1757439Sdam.sunwoo@arm.com if (f) { 1767579Sminkyu.jeong@arm.com if (currState->timing) { 1777579Sminkyu.jeong@arm.com currState->transState->finish(f, currState->req, 1787579Sminkyu.jeong@arm.com currState->tc, currState->mode); 1797728SAli.Saidi@ARM.com 1807728SAli.Saidi@ARM.com pending = false; 1817728SAli.Saidi@ARM.com nextWalk(currState->tc); 1827579Sminkyu.jeong@arm.com currState = NULL; 1837579Sminkyu.jeong@arm.com } else { 1847579Sminkyu.jeong@arm.com currState->tc = NULL; 1857579Sminkyu.jeong@arm.com currState->req = NULL; 1867579Sminkyu.jeong@arm.com } 1877579Sminkyu.jeong@arm.com return f; 1887404SAli.Saidi@ARM.com } 1897404SAli.Saidi@ARM.com 1907439Sdam.sunwoo@arm.com if (currState->timing) { 1917404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1927728SAli.Saidi@ARM.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 1937728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 1947578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1957653Sgene.wu@arm.com stateQueueL1.size()); 1967653Sgene.wu@arm.com stateQueueL1.push_back(currState); 1977439Sdam.sunwoo@arm.com currState = NULL; 1987404SAli.Saidi@ARM.com } else { 1997608SGene.Wu@arm.com Request::Flags flag = 0; 2007608SGene.Wu@arm.com if (currState->sctlr.c == 0){ 2017608SGene.Wu@arm.com flag = Request::UNCACHEABLE; 2027608SGene.Wu@arm.com } 2037404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 2047728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l1Desc.data, 2057728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1), flag); 2067404SAli.Saidi@ARM.com doL1Descriptor(); 2077439Sdam.sunwoo@arm.com f = currState->fault; 2087404SAli.Saidi@ARM.com } 2097404SAli.Saidi@ARM.com 2107439Sdam.sunwoo@arm.com return f; 2117404SAli.Saidi@ARM.com} 2127404SAli.Saidi@ARM.com 2137404SAli.Saidi@ARM.comvoid 2147439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 2157439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 2167404SAli.Saidi@ARM.com{ 2177439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 2187439Sdam.sunwoo@arm.com // variables 2197436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 2207436Sdam.sunwoo@arm.com te.shareable = false; // default value 2217582SAli.Saidi@arm.com te.nonCacheable = false; 2227436Sdam.sunwoo@arm.com bool outer_shareable = false; 2237439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 2247404SAli.Saidi@ARM.com switch(texcb) { 2257436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 2267404SAli.Saidi@ARM.com te.nonCacheable = true; 2277436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 2287436Sdam.sunwoo@arm.com te.shareable = true; 2297436Sdam.sunwoo@arm.com te.innerAttrs = 1; 2307436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2317404SAli.Saidi@ARM.com break; 2327436Sdam.sunwoo@arm.com case 1: // Shareable Device 2337436Sdam.sunwoo@arm.com te.nonCacheable = true; 2347436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2357436Sdam.sunwoo@arm.com te.shareable = true; 2367436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2377436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2387436Sdam.sunwoo@arm.com break; 2397436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 2407436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2417436Sdam.sunwoo@arm.com te.shareable = s; 2427436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2437436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2447436Sdam.sunwoo@arm.com break; 2457436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 2467436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2477436Sdam.sunwoo@arm.com te.shareable = s; 2487436Sdam.sunwoo@arm.com te.innerAttrs = 7; 2497436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2507436Sdam.sunwoo@arm.com break; 2517436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 2527436Sdam.sunwoo@arm.com te.nonCacheable = true; 2537436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2547436Sdam.sunwoo@arm.com te.shareable = s; 2557436Sdam.sunwoo@arm.com te.innerAttrs = 0; 2567436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2577436Sdam.sunwoo@arm.com break; 2587436Sdam.sunwoo@arm.com case 5: // Reserved 2597439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2607436Sdam.sunwoo@arm.com break; 2617436Sdam.sunwoo@arm.com case 6: // Implementation Defined 2627439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 2637436Sdam.sunwoo@arm.com break; 2647436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 2657436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2667436Sdam.sunwoo@arm.com te.shareable = s; 2677436Sdam.sunwoo@arm.com te.innerAttrs = 5; 2687436Sdam.sunwoo@arm.com te.outerAttrs = 1; 2697436Sdam.sunwoo@arm.com break; 2707436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 2717436Sdam.sunwoo@arm.com te.nonCacheable = true; 2727436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2737436Sdam.sunwoo@arm.com te.shareable = false; 2747436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2757436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2767436Sdam.sunwoo@arm.com break; 2777436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 2787439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2797436Sdam.sunwoo@arm.com break; 2807436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 2817436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2827436Sdam.sunwoo@arm.com te.shareable = s; 2837404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 2847404SAli.Saidi@ARM.com te.nonCacheable = true; 2857436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 2867436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 2877404SAli.Saidi@ARM.com break; 2887436Sdam.sunwoo@arm.com default: 2897436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 2907404SAli.Saidi@ARM.com } 2917404SAli.Saidi@ARM.com } else { 2927438SAli.Saidi@ARM.com assert(tc); 2937404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 2947404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 2957436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 2967582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 2977404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 2987404SAli.Saidi@ARM.com case 0: 2997436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 3007436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 3017436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 3027436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 3037404SAli.Saidi@ARM.com break; 3047404SAli.Saidi@ARM.com case 1: 3057436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 3067436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 3077436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 3087436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 3097404SAli.Saidi@ARM.com break; 3107404SAli.Saidi@ARM.com case 2: 3117436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 3127436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 3137436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 3147436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 3157404SAli.Saidi@ARM.com break; 3167404SAli.Saidi@ARM.com case 3: 3177436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 3187436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 3197436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 3207436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 3217404SAli.Saidi@ARM.com break; 3227404SAli.Saidi@ARM.com case 4: 3237436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 3247436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 3257436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 3267436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 3277404SAli.Saidi@ARM.com break; 3287404SAli.Saidi@ARM.com case 5: 3297436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 3307436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 3317436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 3327436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 3337404SAli.Saidi@ARM.com break; 3347404SAli.Saidi@ARM.com case 6: 3357404SAli.Saidi@ARM.com panic("Imp defined type\n"); 3367404SAli.Saidi@ARM.com case 7: 3377436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 3387436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 3397436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 3407436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 3417404SAli.Saidi@ARM.com break; 3427404SAli.Saidi@ARM.com } 3437436Sdam.sunwoo@arm.com 3447436Sdam.sunwoo@arm.com switch(curr_tr) { 3457436Sdam.sunwoo@arm.com case 0: 3467436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 3477436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3487436Sdam.sunwoo@arm.com te.nonCacheable = true; 3497436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3507436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3517436Sdam.sunwoo@arm.com te.shareable = true; 3527436Sdam.sunwoo@arm.com break; 3537436Sdam.sunwoo@arm.com case 1: 3547436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 3557436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 3567436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3577436Sdam.sunwoo@arm.com te.nonCacheable = true; 3587436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3597436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3607436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 3617436Sdam.sunwoo@arm.com te.shareable = true; 3627436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 3637436Sdam.sunwoo@arm.com te.shareable = true; 3647436Sdam.sunwoo@arm.com break; 3657436Sdam.sunwoo@arm.com case 2: 3667436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 3677436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 3687436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3697436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 3707436Sdam.sunwoo@arm.com te.shareable = true; 3717436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 3727436Sdam.sunwoo@arm.com te.shareable = true; 3737436Sdam.sunwoo@arm.com break; 3747436Sdam.sunwoo@arm.com case 3: 3757436Sdam.sunwoo@arm.com panic("Reserved type"); 3767436Sdam.sunwoo@arm.com } 3777436Sdam.sunwoo@arm.com 3787436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 3797436Sdam.sunwoo@arm.com switch(curr_ir) { 3807436Sdam.sunwoo@arm.com case 0: 3817436Sdam.sunwoo@arm.com te.nonCacheable = true; 3827436Sdam.sunwoo@arm.com te.innerAttrs = 0; 3837436Sdam.sunwoo@arm.com break; 3847436Sdam.sunwoo@arm.com case 1: 3857436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3867436Sdam.sunwoo@arm.com break; 3877436Sdam.sunwoo@arm.com case 2: 3887436Sdam.sunwoo@arm.com te.innerAttrs = 6; 3897436Sdam.sunwoo@arm.com break; 3907436Sdam.sunwoo@arm.com case 3: 3917436Sdam.sunwoo@arm.com te.innerAttrs = 7; 3927436Sdam.sunwoo@arm.com break; 3937436Sdam.sunwoo@arm.com } 3947436Sdam.sunwoo@arm.com 3957436Sdam.sunwoo@arm.com switch(curr_or) { 3967436Sdam.sunwoo@arm.com case 0: 3977436Sdam.sunwoo@arm.com te.nonCacheable = true; 3987436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3997436Sdam.sunwoo@arm.com break; 4007436Sdam.sunwoo@arm.com case 1: 4017436Sdam.sunwoo@arm.com te.outerAttrs = 1; 4027436Sdam.sunwoo@arm.com break; 4037436Sdam.sunwoo@arm.com case 2: 4047436Sdam.sunwoo@arm.com te.outerAttrs = 2; 4057436Sdam.sunwoo@arm.com break; 4067436Sdam.sunwoo@arm.com case 3: 4077436Sdam.sunwoo@arm.com te.outerAttrs = 3; 4087436Sdam.sunwoo@arm.com break; 4097436Sdam.sunwoo@arm.com } 4107436Sdam.sunwoo@arm.com } 4117404SAli.Saidi@ARM.com } 4127439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 4137439Sdam.sunwoo@arm.com outerAttrs: %d\n", 4147439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 4157436Sdam.sunwoo@arm.com 4167436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 4177436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 4187436Sdam.sunwoo@arm.com * PAR: 4197436Sdam.sunwoo@arm.com * PA [31:12] 4207436Sdam.sunwoo@arm.com * Reserved [11] 4217436Sdam.sunwoo@arm.com * TLB info [10:1] 4227436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 4237436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 4247436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 4257436Sdam.sunwoo@arm.com * SH [7] (Sharable) 4267436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 4277436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 4287436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 4297436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 4307436Sdam.sunwoo@arm.com */ 4317436Sdam.sunwoo@arm.com te.attributes = ( 4327436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 4337436Sdam.sunwoo@arm.com // TODO: NS Bit 4347436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 4357436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 4367436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 4377436Sdam.sunwoo@arm.com // TODO: Supersection bit 4387436Sdam.sunwoo@arm.com // TODO: Fault bit 4397436Sdam.sunwoo@arm.com ); 4407436Sdam.sunwoo@arm.com 4417436Sdam.sunwoo@arm.com 4427404SAli.Saidi@ARM.com} 4437404SAli.Saidi@ARM.com 4447404SAli.Saidi@ARM.comvoid 4457404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 4467404SAli.Saidi@ARM.com{ 4477439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 4487439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 4497404SAli.Saidi@ARM.com TlbEntry te; 4507404SAli.Saidi@ARM.com 4517439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 4527404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 4537404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 4547439Sdam.sunwoo@arm.com if (!currState->delayed) { 4557439Sdam.sunwoo@arm.com currState->tc = NULL; 4567439Sdam.sunwoo@arm.com currState->req = NULL; 4577437Sdam.sunwoo@arm.com } 4587406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 4597439Sdam.sunwoo@arm.com if (currState->isFetch) 4607439Sdam.sunwoo@arm.com currState->fault = 4617439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 4627406SAli.Saidi@ARM.com else 4637439Sdam.sunwoo@arm.com currState->fault = 4647576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 4657436Sdam.sunwoo@arm.com ArmFault::Translation0); 4667404SAli.Saidi@ARM.com return; 4677404SAli.Saidi@ARM.com case L1Descriptor::Section: 4687439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 4697436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 4707436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 4717436Sdam.sunwoo@arm.com * AccessFlag0 4727436Sdam.sunwoo@arm.com */ 4737436Sdam.sunwoo@arm.com 4747611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 4757611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 4767436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 4777436Sdam.sunwoo@arm.com } 4787439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 4797404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 4807404SAli.Saidi@ARM.com } 4817404SAli.Saidi@ARM.com te.N = 20; 4827439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 4837404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 4847439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 4857404SAli.Saidi@ARM.com te.valid = true; 4867439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 4877404SAli.Saidi@ARM.com te.sNp = true; 4887439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 4897439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 4907439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 4917439Sdam.sunwoo@arm.com te.asid = currState->contextId; 4927439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 4937439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 4947404SAli.Saidi@ARM.com 4957404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 4967582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 4977404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 4987582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 4997582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 5007582SAli.Saidi@arm.com te.nonCacheable); 5017404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 5027439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 5037439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 5047404SAli.Saidi@ARM.com 5057439Sdam.sunwoo@arm.com if (!currState->timing) { 5067439Sdam.sunwoo@arm.com currState->tc = NULL; 5077439Sdam.sunwoo@arm.com currState->req = NULL; 5087437Sdam.sunwoo@arm.com } 5097439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5107404SAli.Saidi@ARM.com 5117404SAli.Saidi@ARM.com return; 5127404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 5137404SAli.Saidi@ARM.com Addr l2desc_addr; 5147439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 5157439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 5167436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 5177436Sdam.sunwoo@arm.com l2desc_addr); 5187404SAli.Saidi@ARM.com 5197404SAli.Saidi@ARM.com // Trickbox address check 5207439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 5217439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 5227439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 5237439Sdam.sunwoo@arm.com 5247439Sdam.sunwoo@arm.com if (currState->fault) { 5257439Sdam.sunwoo@arm.com if (!currState->timing) { 5267439Sdam.sunwoo@arm.com currState->tc = NULL; 5277439Sdam.sunwoo@arm.com currState->req = NULL; 5287437Sdam.sunwoo@arm.com } 5297437Sdam.sunwoo@arm.com return; 5307404SAli.Saidi@ARM.com } 5317404SAli.Saidi@ARM.com 5327404SAli.Saidi@ARM.com 5337439Sdam.sunwoo@arm.com if (currState->timing) { 5347439Sdam.sunwoo@arm.com currState->delayed = true; 5357404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5367728SAli.Saidi@ARM.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 5377728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5387404SAli.Saidi@ARM.com } else { 5397404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5407728SAli.Saidi@ARM.com NULL, (uint8_t*)&currState->l2Desc.data, 5417728SAli.Saidi@ARM.com currState->tc->getCpuPtr()->ticks(1)); 5427404SAli.Saidi@ARM.com doL2Descriptor(); 5437404SAli.Saidi@ARM.com } 5447404SAli.Saidi@ARM.com return; 5457404SAli.Saidi@ARM.com default: 5467404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 5477404SAli.Saidi@ARM.com } 5487404SAli.Saidi@ARM.com} 5497404SAli.Saidi@ARM.com 5507404SAli.Saidi@ARM.comvoid 5517404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 5527404SAli.Saidi@ARM.com{ 5537439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 5547439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 5557404SAli.Saidi@ARM.com TlbEntry te; 5567404SAli.Saidi@ARM.com 5577439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 5587404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 5597439Sdam.sunwoo@arm.com if (!currState->delayed) { 5607439Sdam.sunwoo@arm.com currState->tc = NULL; 5617439Sdam.sunwoo@arm.com currState->req = NULL; 5627437Sdam.sunwoo@arm.com } 5637439Sdam.sunwoo@arm.com if (currState->isFetch) 5647439Sdam.sunwoo@arm.com currState->fault = 5657439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 5667406SAli.Saidi@ARM.com else 5677439Sdam.sunwoo@arm.com currState->fault = 5687439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 5697439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 5707404SAli.Saidi@ARM.com return; 5717404SAli.Saidi@ARM.com } 5727404SAli.Saidi@ARM.com 5737439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 5747436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 5757436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 5767436Sdam.sunwoo@arm.com */ 5777436Sdam.sunwoo@arm.com 5787439Sdam.sunwoo@arm.com currState->fault = 5797576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5807439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 5817439Sdam.sunwoo@arm.com 5827436Sdam.sunwoo@arm.com } 5837436Sdam.sunwoo@arm.com 5847439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 5857404SAli.Saidi@ARM.com te.N = 16; 5867439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 5877404SAli.Saidi@ARM.com } else { 5887404SAli.Saidi@ARM.com te.N = 12; 5897439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 5907404SAli.Saidi@ARM.com } 5917404SAli.Saidi@ARM.com 5927404SAli.Saidi@ARM.com te.valid = true; 5937404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 5947439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5957404SAli.Saidi@ARM.com te.sNp = false; 5967439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5977439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 5987439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 5997439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 6007439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 6017439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 6027439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 6037404SAli.Saidi@ARM.com 6047439Sdam.sunwoo@arm.com if (!currState->delayed) { 6057439Sdam.sunwoo@arm.com currState->tc = NULL; 6067439Sdam.sunwoo@arm.com currState->req = NULL; 6077437Sdam.sunwoo@arm.com } 6087439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 6097437Sdam.sunwoo@arm.com} 6107437Sdam.sunwoo@arm.com 6117437Sdam.sunwoo@arm.comvoid 6127437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 6137437Sdam.sunwoo@arm.com{ 6147653Sgene.wu@arm.com currState = stateQueueL1.front(); 6157439Sdam.sunwoo@arm.com currState->delayed = false; 6167437Sdam.sunwoo@arm.com 6177578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 6187578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 6197578Sdam.sunwoo@arm.com 6207439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 6217437Sdam.sunwoo@arm.com doL1Descriptor(); 6227437Sdam.sunwoo@arm.com 6237653Sgene.wu@arm.com stateQueueL1.pop_front(); 6247437Sdam.sunwoo@arm.com // Check if fault was generated 6257439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6267439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6277439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6287437Sdam.sunwoo@arm.com 6297728SAli.Saidi@ARM.com pending = false; 6307728SAli.Saidi@ARM.com nextWalk(currState->tc); 6317728SAli.Saidi@ARM.com 6327439Sdam.sunwoo@arm.com currState->req = NULL; 6337439Sdam.sunwoo@arm.com currState->tc = NULL; 6347439Sdam.sunwoo@arm.com currState->delayed = false; 6357439Sdam.sunwoo@arm.com 6367437Sdam.sunwoo@arm.com } 6377439Sdam.sunwoo@arm.com else if (!currState->delayed) { 6387653Sgene.wu@arm.com // delay is not set so there is no L2 to do 6397437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6407439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6417439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6427437Sdam.sunwoo@arm.com 6437728SAli.Saidi@ARM.com pending = false; 6447728SAli.Saidi@ARM.com nextWalk(currState->tc); 6457728SAli.Saidi@ARM.com 6467439Sdam.sunwoo@arm.com currState->req = NULL; 6477439Sdam.sunwoo@arm.com currState->tc = NULL; 6487439Sdam.sunwoo@arm.com currState->delayed = false; 6497653Sgene.wu@arm.com delete currState; 6507653Sgene.wu@arm.com } else { 6517653Sgene.wu@arm.com // need to do L2 descriptor 6527653Sgene.wu@arm.com stateQueueL2.push_back(currState); 6537437Sdam.sunwoo@arm.com } 6547439Sdam.sunwoo@arm.com currState = NULL; 6557437Sdam.sunwoo@arm.com} 6567437Sdam.sunwoo@arm.com 6577437Sdam.sunwoo@arm.comvoid 6587437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 6597437Sdam.sunwoo@arm.com{ 6607653Sgene.wu@arm.com currState = stateQueueL2.front(); 6617439Sdam.sunwoo@arm.com assert(currState->delayed); 6627437Sdam.sunwoo@arm.com 6637439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 6647439Sdam.sunwoo@arm.com currState->vaddr); 6657437Sdam.sunwoo@arm.com doL2Descriptor(); 6667437Sdam.sunwoo@arm.com 6677437Sdam.sunwoo@arm.com // Check if fault was generated 6687439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6697439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6707439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6717437Sdam.sunwoo@arm.com } 6727437Sdam.sunwoo@arm.com else { 6737437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6747439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6757439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6767437Sdam.sunwoo@arm.com } 6777437Sdam.sunwoo@arm.com 6787728SAli.Saidi@ARM.com 6797728SAli.Saidi@ARM.com stateQueueL2.pop_front(); 6807728SAli.Saidi@ARM.com pending = false; 6817728SAli.Saidi@ARM.com nextWalk(currState->tc); 6827728SAli.Saidi@ARM.com 6837439Sdam.sunwoo@arm.com currState->req = NULL; 6847439Sdam.sunwoo@arm.com currState->tc = NULL; 6857439Sdam.sunwoo@arm.com currState->delayed = false; 6867439Sdam.sunwoo@arm.com 6877653Sgene.wu@arm.com delete currState; 6887439Sdam.sunwoo@arm.com currState = NULL; 6897404SAli.Saidi@ARM.com} 6907404SAli.Saidi@ARM.com 6917728SAli.Saidi@ARM.comvoid 6927728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 6937728SAli.Saidi@ARM.com{ 6947728SAli.Saidi@ARM.com if (pendingQueue.size()) 6957728SAli.Saidi@ARM.com schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick+1)); 6967728SAli.Saidi@ARM.com} 6977728SAli.Saidi@ARM.com 6987728SAli.Saidi@ARM.com 6997728SAli.Saidi@ARM.com 7007404SAli.Saidi@ARM.comArmISA::TableWalker * 7017404SAli.Saidi@ARM.comArmTableWalkerParams::create() 7027404SAli.Saidi@ARM.com{ 7037404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 7047404SAli.Saidi@ARM.com} 7057404SAli.Saidi@ARM.com 706