table_walker.cc revision 7611
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437404SAli.Saidi@ARM.com#include "dev/io_device.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 457404SAli.Saidi@ARM.com 467404SAli.Saidi@ARM.comusing namespace ArmISA; 477404SAli.Saidi@ARM.com 487404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 497578Sdam.sunwoo@arm.com : MemObject(p), port(NULL), tlb(NULL), 507439Sdam.sunwoo@arm.com currState(NULL), doL1DescEvent(this), doL2DescEvent(this) 517439Sdam.sunwoo@arm.com{ 527576SAli.Saidi@ARM.com sctlr = 0; 537439Sdam.sunwoo@arm.com} 547404SAli.Saidi@ARM.com 557404SAli.Saidi@ARM.comTableWalker::~TableWalker() 567404SAli.Saidi@ARM.com{ 577404SAli.Saidi@ARM.com ; 587404SAli.Saidi@ARM.com} 597404SAli.Saidi@ARM.com 607404SAli.Saidi@ARM.com 617404SAli.Saidi@ARM.comunsigned int 627404SAli.Saidi@ARM.comdrain(Event *de) 637404SAli.Saidi@ARM.com{ 647404SAli.Saidi@ARM.com panic("Not implemented\n"); 657404SAli.Saidi@ARM.com} 667404SAli.Saidi@ARM.com 677404SAli.Saidi@ARM.comPort* 687404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 697404SAli.Saidi@ARM.com{ 707404SAli.Saidi@ARM.com if (if_name == "port") { 717404SAli.Saidi@ARM.com if (port != NULL) 727404SAli.Saidi@ARM.com fatal("%s: port already connected to %s", 737404SAli.Saidi@ARM.com name(), port->getPeer()->name()); 747404SAli.Saidi@ARM.com System *sys = params()->sys; 757404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 767404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 777404SAli.Saidi@ARM.com port = new DmaPort(this, sys, minb, maxb); 787404SAli.Saidi@ARM.com return port; 797404SAli.Saidi@ARM.com } 807404SAli.Saidi@ARM.com return NULL; 817404SAli.Saidi@ARM.com} 827404SAli.Saidi@ARM.com 837404SAli.Saidi@ARM.comFault 847437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 857404SAli.Saidi@ARM.com TLB::Translation *_trans, bool _timing) 867404SAli.Saidi@ARM.com{ 877439Sdam.sunwoo@arm.com if (!currState) { 887439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 897439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 907439Sdam.sunwoo@arm.com // TLB miss. 917439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 927404SAli.Saidi@ARM.com 937439Sdam.sunwoo@arm.com currState = new WalkerState(); 947439Sdam.sunwoo@arm.com currState->tableWalker = this; 957439Sdam.sunwoo@arm.com } 967439Sdam.sunwoo@arm.com else if (_timing) { 977439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 987439Sdam.sunwoo@arm.com } 997439Sdam.sunwoo@arm.com 1007439Sdam.sunwoo@arm.com currState->tc = _tc; 1017439Sdam.sunwoo@arm.com currState->transState = _trans; 1027439Sdam.sunwoo@arm.com currState->req = _req; 1037439Sdam.sunwoo@arm.com currState->fault = NoFault; 1047439Sdam.sunwoo@arm.com currState->contextId = _cid; 1057439Sdam.sunwoo@arm.com currState->timing = _timing; 1067439Sdam.sunwoo@arm.com currState->mode = _mode; 1077404SAli.Saidi@ARM.com 1087436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1097436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1107439Sdam.sunwoo@arm.com currState->vaddr = currState->req->getVaddr() & ~PcModeMask; 1117439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1127439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1137439Sdam.sunwoo@arm.com currState->cpsr = currState->tc->readMiscReg(MISCREG_CPSR); 1147439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1157439Sdam.sunwoo@arm.com 1167439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1177439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1187439Sdam.sunwoo@arm.com currState->isPriv = (currState->cpsr.mode != MODE_USER); 1197439Sdam.sunwoo@arm.com 1207404SAli.Saidi@ARM.com Addr ttbr = 0; 1217404SAli.Saidi@ARM.com 1227404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1237439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1247404SAli.Saidi@ARM.com 1257406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1267439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 1277439Sdam.sunwoo@arm.com 32-currState->N)); 1287406SAli.Saidi@ARM.com 1297439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 1307406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1317439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 1327404SAli.Saidi@ARM.com } else { 1337406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1347439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 1357439Sdam.sunwoo@arm.com currState->N = 0; 1367404SAli.Saidi@ARM.com } 1377404SAli.Saidi@ARM.com 1387439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 1397439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 1407406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1417404SAli.Saidi@ARM.com 1427404SAli.Saidi@ARM.com 1437404SAli.Saidi@ARM.com // Trickbox address check 1447439Sdam.sunwoo@arm.com Fault f; 1457439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 1467439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 1477439Sdam.sunwoo@arm.com if (f) { 1487579Sminkyu.jeong@arm.com if (currState->timing) { 1497579Sminkyu.jeong@arm.com currState->transState->finish(f, currState->req, 1507579Sminkyu.jeong@arm.com currState->tc, currState->mode); 1517579Sminkyu.jeong@arm.com currState = NULL; 1527579Sminkyu.jeong@arm.com } else { 1537579Sminkyu.jeong@arm.com currState->tc = NULL; 1547579Sminkyu.jeong@arm.com currState->req = NULL; 1557579Sminkyu.jeong@arm.com } 1567579Sminkyu.jeong@arm.com return f; 1577404SAli.Saidi@ARM.com } 1587404SAli.Saidi@ARM.com 1597439Sdam.sunwoo@arm.com if (currState->timing) { 1607404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1617439Sdam.sunwoo@arm.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0); 1627578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1637578Sdam.sunwoo@arm.com stateQueue.size()); 1647578Sdam.sunwoo@arm.com stateQueue.push_back(currState); 1657578Sdam.sunwoo@arm.com assert(stateQueue.size() < 5); 1667439Sdam.sunwoo@arm.com currState = NULL; 1677404SAli.Saidi@ARM.com } else { 1687608SGene.Wu@arm.com Request::Flags flag = 0; 1697608SGene.Wu@arm.com if (currState->sctlr.c == 0){ 1707608SGene.Wu@arm.com flag = Request::UNCACHEABLE; 1717608SGene.Wu@arm.com } 1727404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1737608SGene.Wu@arm.com NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag); 1747404SAli.Saidi@ARM.com doL1Descriptor(); 1757439Sdam.sunwoo@arm.com f = currState->fault; 1767404SAli.Saidi@ARM.com } 1777404SAli.Saidi@ARM.com 1787439Sdam.sunwoo@arm.com return f; 1797404SAli.Saidi@ARM.com} 1807404SAli.Saidi@ARM.com 1817404SAli.Saidi@ARM.comvoid 1827439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 1837439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 1847404SAli.Saidi@ARM.com{ 1857439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 1867439Sdam.sunwoo@arm.com // variables 1877436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1887436Sdam.sunwoo@arm.com te.shareable = false; // default value 1897582SAli.Saidi@arm.com te.nonCacheable = false; 1907436Sdam.sunwoo@arm.com bool outer_shareable = false; 1917439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 1927404SAli.Saidi@ARM.com switch(texcb) { 1937436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 1947404SAli.Saidi@ARM.com te.nonCacheable = true; 1957436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 1967436Sdam.sunwoo@arm.com te.shareable = true; 1977436Sdam.sunwoo@arm.com te.innerAttrs = 1; 1987436Sdam.sunwoo@arm.com te.outerAttrs = 0; 1997404SAli.Saidi@ARM.com break; 2007436Sdam.sunwoo@arm.com case 1: // Shareable Device 2017436Sdam.sunwoo@arm.com te.nonCacheable = true; 2027436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2037436Sdam.sunwoo@arm.com te.shareable = true; 2047436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2057436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2067436Sdam.sunwoo@arm.com break; 2077436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 2087436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2097436Sdam.sunwoo@arm.com te.shareable = s; 2107436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2117436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2127436Sdam.sunwoo@arm.com break; 2137436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 2147436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2157436Sdam.sunwoo@arm.com te.shareable = s; 2167436Sdam.sunwoo@arm.com te.innerAttrs = 7; 2177436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2187436Sdam.sunwoo@arm.com break; 2197436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 2207436Sdam.sunwoo@arm.com te.nonCacheable = true; 2217436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2227436Sdam.sunwoo@arm.com te.shareable = s; 2237436Sdam.sunwoo@arm.com te.innerAttrs = 0; 2247436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2257436Sdam.sunwoo@arm.com break; 2267436Sdam.sunwoo@arm.com case 5: // Reserved 2277439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2287436Sdam.sunwoo@arm.com break; 2297436Sdam.sunwoo@arm.com case 6: // Implementation Defined 2307439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 2317436Sdam.sunwoo@arm.com break; 2327436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 2337436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2347436Sdam.sunwoo@arm.com te.shareable = s; 2357436Sdam.sunwoo@arm.com te.innerAttrs = 5; 2367436Sdam.sunwoo@arm.com te.outerAttrs = 1; 2377436Sdam.sunwoo@arm.com break; 2387436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 2397436Sdam.sunwoo@arm.com te.nonCacheable = true; 2407436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2417436Sdam.sunwoo@arm.com te.shareable = false; 2427436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2437436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2447436Sdam.sunwoo@arm.com break; 2457436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 2467439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2477436Sdam.sunwoo@arm.com break; 2487436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 2497436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2507436Sdam.sunwoo@arm.com te.shareable = s; 2517404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 2527404SAli.Saidi@ARM.com te.nonCacheable = true; 2537436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 2547436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 2557404SAli.Saidi@ARM.com break; 2567436Sdam.sunwoo@arm.com default: 2577436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 2587404SAli.Saidi@ARM.com } 2597404SAli.Saidi@ARM.com } else { 2607438SAli.Saidi@ARM.com assert(tc); 2617404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 2627404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 2637436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 2647582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 2657404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 2667404SAli.Saidi@ARM.com case 0: 2677436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 2687436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 2697436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 2707436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 2717404SAli.Saidi@ARM.com break; 2727404SAli.Saidi@ARM.com case 1: 2737436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 2747436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 2757436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 2767436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 2777404SAli.Saidi@ARM.com break; 2787404SAli.Saidi@ARM.com case 2: 2797436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 2807436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 2817436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 2827436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 2837404SAli.Saidi@ARM.com break; 2847404SAli.Saidi@ARM.com case 3: 2857436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 2867436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 2877436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 2887436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 2897404SAli.Saidi@ARM.com break; 2907404SAli.Saidi@ARM.com case 4: 2917436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 2927436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 2937436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 2947436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 2957404SAli.Saidi@ARM.com break; 2967404SAli.Saidi@ARM.com case 5: 2977436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 2987436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 2997436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 3007436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 3017404SAli.Saidi@ARM.com break; 3027404SAli.Saidi@ARM.com case 6: 3037404SAli.Saidi@ARM.com panic("Imp defined type\n"); 3047404SAli.Saidi@ARM.com case 7: 3057436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 3067436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 3077436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 3087436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 3097404SAli.Saidi@ARM.com break; 3107404SAli.Saidi@ARM.com } 3117436Sdam.sunwoo@arm.com 3127436Sdam.sunwoo@arm.com switch(curr_tr) { 3137436Sdam.sunwoo@arm.com case 0: 3147436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 3157436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3167436Sdam.sunwoo@arm.com te.nonCacheable = true; 3177436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3187436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3197436Sdam.sunwoo@arm.com te.shareable = true; 3207436Sdam.sunwoo@arm.com break; 3217436Sdam.sunwoo@arm.com case 1: 3227436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 3237436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 3247436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3257436Sdam.sunwoo@arm.com te.nonCacheable = true; 3267436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3277436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3287436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 3297436Sdam.sunwoo@arm.com te.shareable = true; 3307436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 3317436Sdam.sunwoo@arm.com te.shareable = true; 3327436Sdam.sunwoo@arm.com break; 3337436Sdam.sunwoo@arm.com case 2: 3347436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 3357436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 3367436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3377436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 3387436Sdam.sunwoo@arm.com te.shareable = true; 3397436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 3407436Sdam.sunwoo@arm.com te.shareable = true; 3417436Sdam.sunwoo@arm.com break; 3427436Sdam.sunwoo@arm.com case 3: 3437436Sdam.sunwoo@arm.com panic("Reserved type"); 3447436Sdam.sunwoo@arm.com } 3457436Sdam.sunwoo@arm.com 3467436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 3477436Sdam.sunwoo@arm.com switch(curr_ir) { 3487436Sdam.sunwoo@arm.com case 0: 3497436Sdam.sunwoo@arm.com te.nonCacheable = true; 3507436Sdam.sunwoo@arm.com te.innerAttrs = 0; 3517436Sdam.sunwoo@arm.com break; 3527436Sdam.sunwoo@arm.com case 1: 3537436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3547436Sdam.sunwoo@arm.com break; 3557436Sdam.sunwoo@arm.com case 2: 3567436Sdam.sunwoo@arm.com te.innerAttrs = 6; 3577436Sdam.sunwoo@arm.com break; 3587436Sdam.sunwoo@arm.com case 3: 3597436Sdam.sunwoo@arm.com te.innerAttrs = 7; 3607436Sdam.sunwoo@arm.com break; 3617436Sdam.sunwoo@arm.com } 3627436Sdam.sunwoo@arm.com 3637436Sdam.sunwoo@arm.com switch(curr_or) { 3647436Sdam.sunwoo@arm.com case 0: 3657436Sdam.sunwoo@arm.com te.nonCacheable = true; 3667436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3677436Sdam.sunwoo@arm.com break; 3687436Sdam.sunwoo@arm.com case 1: 3697436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3707436Sdam.sunwoo@arm.com break; 3717436Sdam.sunwoo@arm.com case 2: 3727436Sdam.sunwoo@arm.com te.outerAttrs = 2; 3737436Sdam.sunwoo@arm.com break; 3747436Sdam.sunwoo@arm.com case 3: 3757436Sdam.sunwoo@arm.com te.outerAttrs = 3; 3767436Sdam.sunwoo@arm.com break; 3777436Sdam.sunwoo@arm.com } 3787436Sdam.sunwoo@arm.com } 3797404SAli.Saidi@ARM.com } 3807439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 3817439Sdam.sunwoo@arm.com outerAttrs: %d\n", 3827439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 3837436Sdam.sunwoo@arm.com 3847436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 3857436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 3867436Sdam.sunwoo@arm.com * PAR: 3877436Sdam.sunwoo@arm.com * PA [31:12] 3887436Sdam.sunwoo@arm.com * Reserved [11] 3897436Sdam.sunwoo@arm.com * TLB info [10:1] 3907436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 3917436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 3927436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 3937436Sdam.sunwoo@arm.com * SH [7] (Sharable) 3947436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 3957436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 3967436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 3977436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 3987436Sdam.sunwoo@arm.com */ 3997436Sdam.sunwoo@arm.com te.attributes = ( 4007436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 4017436Sdam.sunwoo@arm.com // TODO: NS Bit 4027436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 4037436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 4047436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 4057436Sdam.sunwoo@arm.com // TODO: Supersection bit 4067436Sdam.sunwoo@arm.com // TODO: Fault bit 4077436Sdam.sunwoo@arm.com ); 4087436Sdam.sunwoo@arm.com 4097436Sdam.sunwoo@arm.com 4107404SAli.Saidi@ARM.com} 4117404SAli.Saidi@ARM.com 4127404SAli.Saidi@ARM.comvoid 4137404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 4147404SAli.Saidi@ARM.com{ 4157439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 4167439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 4177404SAli.Saidi@ARM.com TlbEntry te; 4187404SAli.Saidi@ARM.com 4197439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 4207404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 4217404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 4227439Sdam.sunwoo@arm.com if (!currState->delayed) { 4237439Sdam.sunwoo@arm.com currState->tc = NULL; 4247439Sdam.sunwoo@arm.com currState->req = NULL; 4257437Sdam.sunwoo@arm.com } 4267406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 4277439Sdam.sunwoo@arm.com if (currState->isFetch) 4287439Sdam.sunwoo@arm.com currState->fault = 4297439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 4307406SAli.Saidi@ARM.com else 4317439Sdam.sunwoo@arm.com currState->fault = 4327576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 4337436Sdam.sunwoo@arm.com ArmFault::Translation0); 4347404SAli.Saidi@ARM.com return; 4357404SAli.Saidi@ARM.com case L1Descriptor::Section: 4367439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 4377436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 4387436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 4397436Sdam.sunwoo@arm.com * AccessFlag0 4407436Sdam.sunwoo@arm.com */ 4417436Sdam.sunwoo@arm.com 4427611SGene.Wu@arm.com currState->fault = new DataAbort(currState->vaddr, 4437611SGene.Wu@arm.com currState->l1Desc.domain(), currState->isWrite, 4447436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 4457436Sdam.sunwoo@arm.com } 4467439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 4477404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 4487404SAli.Saidi@ARM.com } 4497404SAli.Saidi@ARM.com te.N = 20; 4507439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 4517404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 4527439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 4537404SAli.Saidi@ARM.com te.valid = true; 4547439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 4557404SAli.Saidi@ARM.com te.sNp = true; 4567439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 4577439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 4587439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 4597439Sdam.sunwoo@arm.com te.asid = currState->contextId; 4607439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 4617439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 4627404SAli.Saidi@ARM.com 4637404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 4647582SAli.Saidi@arm.com DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n", 4657404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 4667582SAli.Saidi@arm.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n", 4677582SAli.Saidi@arm.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid, 4687582SAli.Saidi@arm.com te.nonCacheable); 4697404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 4707439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 4717439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 4727404SAli.Saidi@ARM.com 4737439Sdam.sunwoo@arm.com if (!currState->timing) { 4747439Sdam.sunwoo@arm.com currState->tc = NULL; 4757439Sdam.sunwoo@arm.com currState->req = NULL; 4767437Sdam.sunwoo@arm.com } 4777439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 4787404SAli.Saidi@ARM.com 4797404SAli.Saidi@ARM.com return; 4807404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 4817404SAli.Saidi@ARM.com Addr l2desc_addr; 4827439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 4837439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 4847436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 4857436Sdam.sunwoo@arm.com l2desc_addr); 4867404SAli.Saidi@ARM.com 4877404SAli.Saidi@ARM.com // Trickbox address check 4887439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 4897439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 4907439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 4917439Sdam.sunwoo@arm.com 4927439Sdam.sunwoo@arm.com if (currState->fault) { 4937439Sdam.sunwoo@arm.com if (!currState->timing) { 4947439Sdam.sunwoo@arm.com currState->tc = NULL; 4957439Sdam.sunwoo@arm.com currState->req = NULL; 4967437Sdam.sunwoo@arm.com } 4977437Sdam.sunwoo@arm.com return; 4987404SAli.Saidi@ARM.com } 4997404SAli.Saidi@ARM.com 5007404SAli.Saidi@ARM.com 5017439Sdam.sunwoo@arm.com if (currState->timing) { 5027439Sdam.sunwoo@arm.com currState->delayed = true; 5037404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5047439Sdam.sunwoo@arm.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 0); 5057404SAli.Saidi@ARM.com } else { 5067404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 5077439Sdam.sunwoo@arm.com NULL, (uint8_t*)&currState->l2Desc.data, 0); 5087404SAli.Saidi@ARM.com doL2Descriptor(); 5097404SAli.Saidi@ARM.com } 5107404SAli.Saidi@ARM.com return; 5117404SAli.Saidi@ARM.com default: 5127404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 5137404SAli.Saidi@ARM.com } 5147404SAli.Saidi@ARM.com} 5157404SAli.Saidi@ARM.com 5167404SAli.Saidi@ARM.comvoid 5177404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 5187404SAli.Saidi@ARM.com{ 5197439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 5207439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 5217404SAli.Saidi@ARM.com TlbEntry te; 5227404SAli.Saidi@ARM.com 5237439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 5247404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 5257439Sdam.sunwoo@arm.com if (!currState->delayed) { 5267439Sdam.sunwoo@arm.com currState->tc = NULL; 5277439Sdam.sunwoo@arm.com currState->req = NULL; 5287437Sdam.sunwoo@arm.com } 5297439Sdam.sunwoo@arm.com if (currState->isFetch) 5307439Sdam.sunwoo@arm.com currState->fault = 5317439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 5327406SAli.Saidi@ARM.com else 5337439Sdam.sunwoo@arm.com currState->fault = 5347439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 5357439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 5367404SAli.Saidi@ARM.com return; 5377404SAli.Saidi@ARM.com } 5387404SAli.Saidi@ARM.com 5397439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 5407436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 5417436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 5427436Sdam.sunwoo@arm.com */ 5437436Sdam.sunwoo@arm.com 5447439Sdam.sunwoo@arm.com currState->fault = 5457576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5467439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 5477439Sdam.sunwoo@arm.com 5487436Sdam.sunwoo@arm.com } 5497436Sdam.sunwoo@arm.com 5507439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 5517404SAli.Saidi@ARM.com te.N = 16; 5527439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 5537404SAli.Saidi@ARM.com } else { 5547404SAli.Saidi@ARM.com te.N = 12; 5557439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 5567404SAli.Saidi@ARM.com } 5577404SAli.Saidi@ARM.com 5587404SAli.Saidi@ARM.com te.valid = true; 5597404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 5607439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5617404SAli.Saidi@ARM.com te.sNp = false; 5627439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5637439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 5647439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 5657439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 5667439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5677439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 5687439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 5697404SAli.Saidi@ARM.com 5707439Sdam.sunwoo@arm.com if (!currState->delayed) { 5717439Sdam.sunwoo@arm.com currState->tc = NULL; 5727439Sdam.sunwoo@arm.com currState->req = NULL; 5737437Sdam.sunwoo@arm.com } 5747439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5757437Sdam.sunwoo@arm.com} 5767437Sdam.sunwoo@arm.com 5777437Sdam.sunwoo@arm.comvoid 5787437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 5797437Sdam.sunwoo@arm.com{ 5807578Sdam.sunwoo@arm.com currState = stateQueue.front(); 5817439Sdam.sunwoo@arm.com currState->delayed = false; 5827437Sdam.sunwoo@arm.com 5837578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 5847578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 5857578Sdam.sunwoo@arm.com 5867439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 5877437Sdam.sunwoo@arm.com doL1Descriptor(); 5887437Sdam.sunwoo@arm.com 5897437Sdam.sunwoo@arm.com // Check if fault was generated 5907439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 5917439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 5927439Sdam.sunwoo@arm.com currState->tc, currState->mode); 5937437Sdam.sunwoo@arm.com 5947439Sdam.sunwoo@arm.com currState->req = NULL; 5957439Sdam.sunwoo@arm.com currState->tc = NULL; 5967439Sdam.sunwoo@arm.com currState->delayed = false; 5977439Sdam.sunwoo@arm.com 5987578Sdam.sunwoo@arm.com stateQueue.pop_front(); 5997437Sdam.sunwoo@arm.com } 6007439Sdam.sunwoo@arm.com else if (!currState->delayed) { 6017437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6027439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6037439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6047437Sdam.sunwoo@arm.com 6057439Sdam.sunwoo@arm.com currState->req = NULL; 6067439Sdam.sunwoo@arm.com currState->tc = NULL; 6077439Sdam.sunwoo@arm.com currState->delayed = false; 6087439Sdam.sunwoo@arm.com 6097578Sdam.sunwoo@arm.com stateQueue.pop_front(); 6107437Sdam.sunwoo@arm.com } 6117439Sdam.sunwoo@arm.com currState = NULL; 6127437Sdam.sunwoo@arm.com} 6137437Sdam.sunwoo@arm.com 6147437Sdam.sunwoo@arm.comvoid 6157437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 6167437Sdam.sunwoo@arm.com{ 6177578Sdam.sunwoo@arm.com currState = stateQueue.front(); 6187439Sdam.sunwoo@arm.com assert(currState->delayed); 6197437Sdam.sunwoo@arm.com 6207439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 6217439Sdam.sunwoo@arm.com currState->vaddr); 6227437Sdam.sunwoo@arm.com doL2Descriptor(); 6237437Sdam.sunwoo@arm.com 6247437Sdam.sunwoo@arm.com // Check if fault was generated 6257439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6267439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6277439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6287437Sdam.sunwoo@arm.com } 6297437Sdam.sunwoo@arm.com else { 6307437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6317439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6327439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6337437Sdam.sunwoo@arm.com } 6347437Sdam.sunwoo@arm.com 6357439Sdam.sunwoo@arm.com currState->req = NULL; 6367439Sdam.sunwoo@arm.com currState->tc = NULL; 6377439Sdam.sunwoo@arm.com currState->delayed = false; 6387439Sdam.sunwoo@arm.com 6397578Sdam.sunwoo@arm.com stateQueue.pop_front(); 6407439Sdam.sunwoo@arm.com currState = NULL; 6417404SAli.Saidi@ARM.com} 6427404SAli.Saidi@ARM.com 6437404SAli.Saidi@ARM.comArmISA::TableWalker * 6447404SAli.Saidi@ARM.comArmTableWalkerParams::create() 6457404SAli.Saidi@ARM.com{ 6467404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 6477404SAli.Saidi@ARM.com} 6487404SAli.Saidi@ARM.com 649