table_walker.cc revision 7578
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437404SAli.Saidi@ARM.com#include "dev/io_device.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 457404SAli.Saidi@ARM.com 467404SAli.Saidi@ARM.comusing namespace ArmISA; 477404SAli.Saidi@ARM.com 487404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 497578Sdam.sunwoo@arm.com : MemObject(p), port(NULL), tlb(NULL), 507439Sdam.sunwoo@arm.com currState(NULL), doL1DescEvent(this), doL2DescEvent(this) 517439Sdam.sunwoo@arm.com{ 527576SAli.Saidi@ARM.com sctlr = 0; 537439Sdam.sunwoo@arm.com} 547404SAli.Saidi@ARM.com 557404SAli.Saidi@ARM.comTableWalker::~TableWalker() 567404SAli.Saidi@ARM.com{ 577404SAli.Saidi@ARM.com ; 587404SAli.Saidi@ARM.com} 597404SAli.Saidi@ARM.com 607404SAli.Saidi@ARM.com 617404SAli.Saidi@ARM.comunsigned int 627404SAli.Saidi@ARM.comdrain(Event *de) 637404SAli.Saidi@ARM.com{ 647404SAli.Saidi@ARM.com panic("Not implemented\n"); 657404SAli.Saidi@ARM.com} 667404SAli.Saidi@ARM.com 677404SAli.Saidi@ARM.comPort* 687404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 697404SAli.Saidi@ARM.com{ 707404SAli.Saidi@ARM.com if (if_name == "port") { 717404SAli.Saidi@ARM.com if (port != NULL) 727404SAli.Saidi@ARM.com fatal("%s: port already connected to %s", 737404SAli.Saidi@ARM.com name(), port->getPeer()->name()); 747404SAli.Saidi@ARM.com System *sys = params()->sys; 757404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 767404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 777404SAli.Saidi@ARM.com port = new DmaPort(this, sys, minb, maxb); 787404SAli.Saidi@ARM.com return port; 797404SAli.Saidi@ARM.com } 807404SAli.Saidi@ARM.com return NULL; 817404SAli.Saidi@ARM.com} 827404SAli.Saidi@ARM.com 837404SAli.Saidi@ARM.comFault 847437Sdam.sunwoo@arm.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 857404SAli.Saidi@ARM.com TLB::Translation *_trans, bool _timing) 867404SAli.Saidi@ARM.com{ 877439Sdam.sunwoo@arm.com if (!currState) { 887439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 897439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 907439Sdam.sunwoo@arm.com // TLB miss. 917439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 927404SAli.Saidi@ARM.com 937439Sdam.sunwoo@arm.com currState = new WalkerState(); 947439Sdam.sunwoo@arm.com currState->tableWalker = this; 957439Sdam.sunwoo@arm.com } 967439Sdam.sunwoo@arm.com else if (_timing) { 977439Sdam.sunwoo@arm.com panic("currState should always be empty in timing mode!\n"); 987439Sdam.sunwoo@arm.com } 997439Sdam.sunwoo@arm.com 1007439Sdam.sunwoo@arm.com currState->tc = _tc; 1017439Sdam.sunwoo@arm.com currState->transState = _trans; 1027439Sdam.sunwoo@arm.com currState->req = _req; 1037439Sdam.sunwoo@arm.com currState->fault = NoFault; 1047439Sdam.sunwoo@arm.com currState->contextId = _cid; 1057439Sdam.sunwoo@arm.com currState->timing = _timing; 1067439Sdam.sunwoo@arm.com currState->mode = _mode; 1077404SAli.Saidi@ARM.com 1087436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1097436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1107439Sdam.sunwoo@arm.com currState->vaddr = currState->req->getVaddr() & ~PcModeMask; 1117439Sdam.sunwoo@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 1127439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 1137439Sdam.sunwoo@arm.com currState->cpsr = currState->tc->readMiscReg(MISCREG_CPSR); 1147439Sdam.sunwoo@arm.com currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); 1157439Sdam.sunwoo@arm.com 1167439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 1177439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 1187439Sdam.sunwoo@arm.com currState->isPriv = (currState->cpsr.mode != MODE_USER); 1197439Sdam.sunwoo@arm.com 1207404SAli.Saidi@ARM.com Addr ttbr = 0; 1217404SAli.Saidi@ARM.com 1227404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1237439Sdam.sunwoo@arm.com assert(currState->sctlr.m); 1247404SAli.Saidi@ARM.com 1257406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1267439Sdam.sunwoo@arm.com currState->vaddr, currState->N, mbits(currState->vaddr, 31, 1277439Sdam.sunwoo@arm.com 32-currState->N)); 1287406SAli.Saidi@ARM.com 1297439Sdam.sunwoo@arm.com if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { 1307406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1317439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); 1327404SAli.Saidi@ARM.com } else { 1337406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1347439Sdam.sunwoo@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 1357439Sdam.sunwoo@arm.com currState->N = 0; 1367404SAli.Saidi@ARM.com } 1377404SAli.Saidi@ARM.com 1387439Sdam.sunwoo@arm.com Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 1397439Sdam.sunwoo@arm.com (bits(currState->vaddr,31-currState->N,20) << 2); 1407406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1417404SAli.Saidi@ARM.com 1427404SAli.Saidi@ARM.com 1437404SAli.Saidi@ARM.com // Trickbox address check 1447439Sdam.sunwoo@arm.com Fault f; 1457439Sdam.sunwoo@arm.com f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 1467439Sdam.sunwoo@arm.com currState->isFetch, currState->isWrite, 0, true); 1477439Sdam.sunwoo@arm.com if (f) { 1487439Sdam.sunwoo@arm.com currState->tc = NULL; 1497439Sdam.sunwoo@arm.com currState->req = NULL; 1507439Sdam.sunwoo@arm.com return f; 1517404SAli.Saidi@ARM.com } 1527404SAli.Saidi@ARM.com 1537439Sdam.sunwoo@arm.com if (currState->timing) { 1547404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1557439Sdam.sunwoo@arm.com &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0); 1567578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1577578Sdam.sunwoo@arm.com stateQueue.size()); 1587578Sdam.sunwoo@arm.com stateQueue.push_back(currState); 1597578Sdam.sunwoo@arm.com assert(stateQueue.size() < 5); 1607439Sdam.sunwoo@arm.com currState = NULL; 1617404SAli.Saidi@ARM.com } else { 1627404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1637439Sdam.sunwoo@arm.com NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0); 1647404SAli.Saidi@ARM.com doL1Descriptor(); 1657439Sdam.sunwoo@arm.com f = currState->fault; 1667404SAli.Saidi@ARM.com } 1677404SAli.Saidi@ARM.com 1687439Sdam.sunwoo@arm.com return f; 1697404SAli.Saidi@ARM.com} 1707404SAli.Saidi@ARM.com 1717404SAli.Saidi@ARM.comvoid 1727439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 1737439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 1747404SAli.Saidi@ARM.com{ 1757439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 1767439Sdam.sunwoo@arm.com // variables 1777436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1787436Sdam.sunwoo@arm.com te.shareable = false; // default value 1797436Sdam.sunwoo@arm.com bool outer_shareable = false; 1807439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 1817404SAli.Saidi@ARM.com switch(texcb) { 1827436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 1837404SAli.Saidi@ARM.com te.nonCacheable = true; 1847436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 1857436Sdam.sunwoo@arm.com te.shareable = true; 1867436Sdam.sunwoo@arm.com te.innerAttrs = 1; 1877436Sdam.sunwoo@arm.com te.outerAttrs = 0; 1887404SAli.Saidi@ARM.com break; 1897436Sdam.sunwoo@arm.com case 1: // Shareable Device 1907436Sdam.sunwoo@arm.com te.nonCacheable = true; 1917436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 1927436Sdam.sunwoo@arm.com te.shareable = true; 1937436Sdam.sunwoo@arm.com te.innerAttrs = 3; 1947436Sdam.sunwoo@arm.com te.outerAttrs = 0; 1957436Sdam.sunwoo@arm.com break; 1967436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 1977436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 1987436Sdam.sunwoo@arm.com te.shareable = s; 1997436Sdam.sunwoo@arm.com te.innerAttrs = 6; 2007436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2017436Sdam.sunwoo@arm.com break; 2027436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 2037436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2047436Sdam.sunwoo@arm.com te.shareable = s; 2057436Sdam.sunwoo@arm.com te.innerAttrs = 7; 2067436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2077436Sdam.sunwoo@arm.com break; 2087436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 2097436Sdam.sunwoo@arm.com te.nonCacheable = true; 2107436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2117436Sdam.sunwoo@arm.com te.shareable = s; 2127436Sdam.sunwoo@arm.com te.innerAttrs = 0; 2137436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 2147436Sdam.sunwoo@arm.com break; 2157436Sdam.sunwoo@arm.com case 5: // Reserved 2167439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2177436Sdam.sunwoo@arm.com break; 2187436Sdam.sunwoo@arm.com case 6: // Implementation Defined 2197439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 2207436Sdam.sunwoo@arm.com break; 2217436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 2227436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2237436Sdam.sunwoo@arm.com te.shareable = s; 2247436Sdam.sunwoo@arm.com te.innerAttrs = 5; 2257436Sdam.sunwoo@arm.com te.outerAttrs = 1; 2267436Sdam.sunwoo@arm.com break; 2277436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 2287436Sdam.sunwoo@arm.com te.nonCacheable = true; 2297436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2307436Sdam.sunwoo@arm.com te.shareable = false; 2317436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2337436Sdam.sunwoo@arm.com break; 2347436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 2357439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 2367436Sdam.sunwoo@arm.com break; 2377436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 2387436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2397436Sdam.sunwoo@arm.com te.shareable = s; 2407404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 2417404SAli.Saidi@ARM.com te.nonCacheable = true; 2427436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 2437436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 2447404SAli.Saidi@ARM.com break; 2457436Sdam.sunwoo@arm.com default: 2467436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 2477404SAli.Saidi@ARM.com } 2487404SAli.Saidi@ARM.com } else { 2497438SAli.Saidi@ARM.com assert(tc); 2507404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 2517404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 2527436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 2537436Sdam.sunwoo@arm.com uint8_t curr_tr, curr_ir, curr_or; 2547404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 2557404SAli.Saidi@ARM.com case 0: 2567436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 2577436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 2587436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 2597436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 2607404SAli.Saidi@ARM.com break; 2617404SAli.Saidi@ARM.com case 1: 2627436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 2637436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 2647436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 2657436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 2667404SAli.Saidi@ARM.com break; 2677404SAli.Saidi@ARM.com case 2: 2687436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 2697436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 2707436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 2717436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 2727404SAli.Saidi@ARM.com break; 2737404SAli.Saidi@ARM.com case 3: 2747436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 2757436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 2767436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 2777436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 2787404SAli.Saidi@ARM.com break; 2797404SAli.Saidi@ARM.com case 4: 2807436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 2817436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 2827436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 2837436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 2847404SAli.Saidi@ARM.com break; 2857404SAli.Saidi@ARM.com case 5: 2867436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 2877436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 2887436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 2897436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 2907404SAli.Saidi@ARM.com break; 2917404SAli.Saidi@ARM.com case 6: 2927404SAli.Saidi@ARM.com panic("Imp defined type\n"); 2937404SAli.Saidi@ARM.com case 7: 2947436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 2957436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 2967436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 2977436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 2987404SAli.Saidi@ARM.com break; 2997404SAli.Saidi@ARM.com } 3007436Sdam.sunwoo@arm.com 3017436Sdam.sunwoo@arm.com switch(curr_tr) { 3027436Sdam.sunwoo@arm.com case 0: 3037436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 3047436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 3057436Sdam.sunwoo@arm.com te.nonCacheable = true; 3067436Sdam.sunwoo@arm.com te.innerAttrs = 1; 3077436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3087436Sdam.sunwoo@arm.com te.shareable = true; 3097436Sdam.sunwoo@arm.com break; 3107436Sdam.sunwoo@arm.com case 1: 3117436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 3127436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 3137436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 3147436Sdam.sunwoo@arm.com te.nonCacheable = true; 3157436Sdam.sunwoo@arm.com te.innerAttrs = 3; 3167436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3177436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 3187436Sdam.sunwoo@arm.com te.shareable = true; 3197436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 3207436Sdam.sunwoo@arm.com te.shareable = true; 3217436Sdam.sunwoo@arm.com break; 3227436Sdam.sunwoo@arm.com case 2: 3237436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 3247436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 3257436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 3267436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 3277436Sdam.sunwoo@arm.com te.shareable = true; 3287436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 3297436Sdam.sunwoo@arm.com te.shareable = true; 3307436Sdam.sunwoo@arm.com break; 3317436Sdam.sunwoo@arm.com case 3: 3327436Sdam.sunwoo@arm.com panic("Reserved type"); 3337436Sdam.sunwoo@arm.com } 3347436Sdam.sunwoo@arm.com 3357436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 3367436Sdam.sunwoo@arm.com switch(curr_ir) { 3377436Sdam.sunwoo@arm.com case 0: 3387436Sdam.sunwoo@arm.com te.nonCacheable = true; 3397436Sdam.sunwoo@arm.com te.innerAttrs = 0; 3407436Sdam.sunwoo@arm.com break; 3417436Sdam.sunwoo@arm.com case 1: 3427436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3437436Sdam.sunwoo@arm.com break; 3447436Sdam.sunwoo@arm.com case 2: 3457436Sdam.sunwoo@arm.com te.innerAttrs = 6; 3467436Sdam.sunwoo@arm.com break; 3477436Sdam.sunwoo@arm.com case 3: 3487436Sdam.sunwoo@arm.com te.innerAttrs = 7; 3497436Sdam.sunwoo@arm.com break; 3507436Sdam.sunwoo@arm.com } 3517436Sdam.sunwoo@arm.com 3527436Sdam.sunwoo@arm.com switch(curr_or) { 3537436Sdam.sunwoo@arm.com case 0: 3547436Sdam.sunwoo@arm.com te.nonCacheable = true; 3557436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3567436Sdam.sunwoo@arm.com break; 3577436Sdam.sunwoo@arm.com case 1: 3587436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3597436Sdam.sunwoo@arm.com break; 3607436Sdam.sunwoo@arm.com case 2: 3617436Sdam.sunwoo@arm.com te.outerAttrs = 2; 3627436Sdam.sunwoo@arm.com break; 3637436Sdam.sunwoo@arm.com case 3: 3647436Sdam.sunwoo@arm.com te.outerAttrs = 3; 3657436Sdam.sunwoo@arm.com break; 3667436Sdam.sunwoo@arm.com } 3677436Sdam.sunwoo@arm.com } 3687404SAli.Saidi@ARM.com } 3697439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 3707439Sdam.sunwoo@arm.com outerAttrs: %d\n", 3717439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 3727436Sdam.sunwoo@arm.com 3737436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 3747436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 3757436Sdam.sunwoo@arm.com * PAR: 3767436Sdam.sunwoo@arm.com * PA [31:12] 3777436Sdam.sunwoo@arm.com * Reserved [11] 3787436Sdam.sunwoo@arm.com * TLB info [10:1] 3797436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 3807436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 3817436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 3827436Sdam.sunwoo@arm.com * SH [7] (Sharable) 3837436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 3847436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 3857436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 3867436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 3877436Sdam.sunwoo@arm.com */ 3887436Sdam.sunwoo@arm.com te.attributes = ( 3897436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 3907436Sdam.sunwoo@arm.com // TODO: NS Bit 3917436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 3927436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 3937436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 3947436Sdam.sunwoo@arm.com // TODO: Supersection bit 3957436Sdam.sunwoo@arm.com // TODO: Fault bit 3967436Sdam.sunwoo@arm.com ); 3977436Sdam.sunwoo@arm.com 3987436Sdam.sunwoo@arm.com 3997404SAli.Saidi@ARM.com} 4007404SAli.Saidi@ARM.com 4017404SAli.Saidi@ARM.comvoid 4027404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 4037404SAli.Saidi@ARM.com{ 4047439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 4057439Sdam.sunwoo@arm.com currState->vaddr, currState->l1Desc.data); 4067404SAli.Saidi@ARM.com TlbEntry te; 4077404SAli.Saidi@ARM.com 4087439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 4097404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 4107404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 4117439Sdam.sunwoo@arm.com if (!currState->delayed) { 4127439Sdam.sunwoo@arm.com currState->tc = NULL; 4137439Sdam.sunwoo@arm.com currState->req = NULL; 4147437Sdam.sunwoo@arm.com } 4157406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 4167439Sdam.sunwoo@arm.com if (currState->isFetch) 4177439Sdam.sunwoo@arm.com currState->fault = 4187439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 4197406SAli.Saidi@ARM.com else 4207439Sdam.sunwoo@arm.com currState->fault = 4217576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 4227436Sdam.sunwoo@arm.com ArmFault::Translation0); 4237404SAli.Saidi@ARM.com return; 4247404SAli.Saidi@ARM.com case L1Descriptor::Section: 4257439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 4267436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 4277436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 4287436Sdam.sunwoo@arm.com * AccessFlag0 4297436Sdam.sunwoo@arm.com */ 4307436Sdam.sunwoo@arm.com 4317439Sdam.sunwoo@arm.com currState->fault = 4327439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, NULL, currState->isWrite, 4337436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 4347436Sdam.sunwoo@arm.com } 4357404SAli.Saidi@ARM.com 4367439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 4377404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 4387404SAli.Saidi@ARM.com } 4397404SAli.Saidi@ARM.com te.N = 20; 4407439Sdam.sunwoo@arm.com te.pfn = currState->l1Desc.pfn(); 4417404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 4427439Sdam.sunwoo@arm.com te.global = !currState->l1Desc.global(); 4437404SAli.Saidi@ARM.com te.valid = true; 4447439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 4457404SAli.Saidi@ARM.com te.sNp = true; 4467439Sdam.sunwoo@arm.com te.xn = currState->l1Desc.xn(); 4477439Sdam.sunwoo@arm.com te.ap = currState->l1Desc.ap(); 4487439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 4497439Sdam.sunwoo@arm.com te.asid = currState->contextId; 4507439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, 4517439Sdam.sunwoo@arm.com currState->l1Desc.texcb(), currState->l1Desc.shareable()); 4527404SAli.Saidi@ARM.com 4537404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 4547404SAli.Saidi@ARM.com DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n", 4557404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 4567404SAli.Saidi@ARM.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n", 4577404SAli.Saidi@ARM.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid); 4587404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 4597439Sdam.sunwoo@arm.com currState->l1Desc.domain(), currState->l1Desc.data, 4607439Sdam.sunwoo@arm.com (currState->l1Desc.data >> 5) & 0xF ); 4617404SAli.Saidi@ARM.com 4627439Sdam.sunwoo@arm.com if (!currState->timing) { 4637439Sdam.sunwoo@arm.com currState->tc = NULL; 4647439Sdam.sunwoo@arm.com currState->req = NULL; 4657437Sdam.sunwoo@arm.com } 4667439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 4677404SAli.Saidi@ARM.com 4687404SAli.Saidi@ARM.com return; 4697404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 4707404SAli.Saidi@ARM.com Addr l2desc_addr; 4717439Sdam.sunwoo@arm.com l2desc_addr = currState->l1Desc.l2Addr() | 4727439Sdam.sunwoo@arm.com (bits(currState->vaddr, 19,12) << 2); 4737436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 4747436Sdam.sunwoo@arm.com l2desc_addr); 4757404SAli.Saidi@ARM.com 4767404SAli.Saidi@ARM.com // Trickbox address check 4777439Sdam.sunwoo@arm.com currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 4787439Sdam.sunwoo@arm.com sizeof(uint32_t), currState->isFetch, currState->isWrite, 4797439Sdam.sunwoo@arm.com currState->l1Desc.domain(), false); 4807439Sdam.sunwoo@arm.com 4817439Sdam.sunwoo@arm.com if (currState->fault) { 4827439Sdam.sunwoo@arm.com if (!currState->timing) { 4837439Sdam.sunwoo@arm.com currState->tc = NULL; 4847439Sdam.sunwoo@arm.com currState->req = NULL; 4857437Sdam.sunwoo@arm.com } 4867437Sdam.sunwoo@arm.com return; 4877404SAli.Saidi@ARM.com } 4887404SAli.Saidi@ARM.com 4897404SAli.Saidi@ARM.com 4907439Sdam.sunwoo@arm.com if (currState->timing) { 4917439Sdam.sunwoo@arm.com currState->delayed = true; 4927404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 4937439Sdam.sunwoo@arm.com &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 0); 4947404SAli.Saidi@ARM.com } else { 4957404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 4967439Sdam.sunwoo@arm.com NULL, (uint8_t*)&currState->l2Desc.data, 0); 4977404SAli.Saidi@ARM.com doL2Descriptor(); 4987404SAli.Saidi@ARM.com } 4997404SAli.Saidi@ARM.com return; 5007404SAli.Saidi@ARM.com default: 5017404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 5027404SAli.Saidi@ARM.com } 5037404SAli.Saidi@ARM.com} 5047404SAli.Saidi@ARM.com 5057404SAli.Saidi@ARM.comvoid 5067404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 5077404SAli.Saidi@ARM.com{ 5087439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 5097439Sdam.sunwoo@arm.com currState->vaddr, currState->l2Desc.data); 5107404SAli.Saidi@ARM.com TlbEntry te; 5117404SAli.Saidi@ARM.com 5127439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 5137404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 5147439Sdam.sunwoo@arm.com if (!currState->delayed) { 5157439Sdam.sunwoo@arm.com currState->tc = NULL; 5167439Sdam.sunwoo@arm.com currState->req = NULL; 5177437Sdam.sunwoo@arm.com } 5187439Sdam.sunwoo@arm.com if (currState->isFetch) 5197439Sdam.sunwoo@arm.com currState->fault = 5207439Sdam.sunwoo@arm.com new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 5217406SAli.Saidi@ARM.com else 5227439Sdam.sunwoo@arm.com currState->fault = 5237439Sdam.sunwoo@arm.com new DataAbort(currState->vaddr, currState->l1Desc.domain(), 5247439Sdam.sunwoo@arm.com currState->isWrite, ArmFault::Translation1); 5257404SAli.Saidi@ARM.com return; 5267404SAli.Saidi@ARM.com } 5277404SAli.Saidi@ARM.com 5287439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 5297436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 5307436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 5317436Sdam.sunwoo@arm.com */ 5327436Sdam.sunwoo@arm.com 5337439Sdam.sunwoo@arm.com currState->fault = 5347576SAli.Saidi@ARM.com new DataAbort(currState->vaddr, 0, currState->isWrite, 5357439Sdam.sunwoo@arm.com ArmFault::AccessFlag1); 5367439Sdam.sunwoo@arm.com 5377436Sdam.sunwoo@arm.com } 5387436Sdam.sunwoo@arm.com 5397439Sdam.sunwoo@arm.com if (currState->l2Desc.large()) { 5407404SAli.Saidi@ARM.com te.N = 16; 5417439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 5427404SAli.Saidi@ARM.com } else { 5437404SAli.Saidi@ARM.com te.N = 12; 5447439Sdam.sunwoo@arm.com te.pfn = currState->l2Desc.pfn(); 5457404SAli.Saidi@ARM.com } 5467404SAli.Saidi@ARM.com 5477404SAli.Saidi@ARM.com te.valid = true; 5487404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 5497439Sdam.sunwoo@arm.com te.asid = currState->contextId; 5507404SAli.Saidi@ARM.com te.sNp = false; 5517439Sdam.sunwoo@arm.com te.vpn = currState->vaddr >> te.N; 5527439Sdam.sunwoo@arm.com te.global = currState->l2Desc.global(); 5537439Sdam.sunwoo@arm.com te.xn = currState->l2Desc.xn(); 5547439Sdam.sunwoo@arm.com te.ap = currState->l2Desc.ap(); 5557439Sdam.sunwoo@arm.com te.domain = currState->l1Desc.domain(); 5567439Sdam.sunwoo@arm.com memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 5577439Sdam.sunwoo@arm.com currState->l2Desc.shareable()); 5587404SAli.Saidi@ARM.com 5597439Sdam.sunwoo@arm.com if (!currState->delayed) { 5607439Sdam.sunwoo@arm.com currState->tc = NULL; 5617439Sdam.sunwoo@arm.com currState->req = NULL; 5627437Sdam.sunwoo@arm.com } 5637439Sdam.sunwoo@arm.com tlb->insert(currState->vaddr, te); 5647437Sdam.sunwoo@arm.com} 5657437Sdam.sunwoo@arm.com 5667437Sdam.sunwoo@arm.comvoid 5677437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 5687437Sdam.sunwoo@arm.com{ 5697578Sdam.sunwoo@arm.com currState = stateQueue.front(); 5707439Sdam.sunwoo@arm.com currState->delayed = false; 5717437Sdam.sunwoo@arm.com 5727578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 5737578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 5747578Sdam.sunwoo@arm.com 5757439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 5767437Sdam.sunwoo@arm.com doL1Descriptor(); 5777437Sdam.sunwoo@arm.com 5787437Sdam.sunwoo@arm.com // Check if fault was generated 5797439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 5807439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 5817439Sdam.sunwoo@arm.com currState->tc, currState->mode); 5827437Sdam.sunwoo@arm.com 5837439Sdam.sunwoo@arm.com currState->req = NULL; 5847439Sdam.sunwoo@arm.com currState->tc = NULL; 5857439Sdam.sunwoo@arm.com currState->delayed = false; 5867439Sdam.sunwoo@arm.com 5877578Sdam.sunwoo@arm.com stateQueue.pop_front(); 5887437Sdam.sunwoo@arm.com } 5897439Sdam.sunwoo@arm.com else if (!currState->delayed) { 5907437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 5917439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 5927439Sdam.sunwoo@arm.com currState->transState, currState->mode); 5937437Sdam.sunwoo@arm.com 5947439Sdam.sunwoo@arm.com currState->req = NULL; 5957439Sdam.sunwoo@arm.com currState->tc = NULL; 5967439Sdam.sunwoo@arm.com currState->delayed = false; 5977439Sdam.sunwoo@arm.com 5987578Sdam.sunwoo@arm.com stateQueue.pop_front(); 5997437Sdam.sunwoo@arm.com } 6007439Sdam.sunwoo@arm.com currState = NULL; 6017437Sdam.sunwoo@arm.com} 6027437Sdam.sunwoo@arm.com 6037437Sdam.sunwoo@arm.comvoid 6047437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 6057437Sdam.sunwoo@arm.com{ 6067578Sdam.sunwoo@arm.com currState = stateQueue.front(); 6077439Sdam.sunwoo@arm.com assert(currState->delayed); 6087437Sdam.sunwoo@arm.com 6097439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 6107439Sdam.sunwoo@arm.com currState->vaddr); 6117437Sdam.sunwoo@arm.com doL2Descriptor(); 6127437Sdam.sunwoo@arm.com 6137437Sdam.sunwoo@arm.com // Check if fault was generated 6147439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 6157439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 6167439Sdam.sunwoo@arm.com currState->tc, currState->mode); 6177437Sdam.sunwoo@arm.com } 6187437Sdam.sunwoo@arm.com else { 6197437Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 6207439Sdam.sunwoo@arm.com currState->fault = tlb->translateTiming(currState->req, currState->tc, 6217439Sdam.sunwoo@arm.com currState->transState, currState->mode); 6227437Sdam.sunwoo@arm.com } 6237437Sdam.sunwoo@arm.com 6247439Sdam.sunwoo@arm.com currState->req = NULL; 6257439Sdam.sunwoo@arm.com currState->tc = NULL; 6267439Sdam.sunwoo@arm.com currState->delayed = false; 6277439Sdam.sunwoo@arm.com 6287578Sdam.sunwoo@arm.com stateQueue.pop_front(); 6297439Sdam.sunwoo@arm.com currState = NULL; 6307404SAli.Saidi@ARM.com} 6317404SAli.Saidi@ARM.com 6327404SAli.Saidi@ARM.comArmISA::TableWalker * 6337404SAli.Saidi@ARM.comArmTableWalkerParams::create() 6347404SAli.Saidi@ARM.com{ 6357404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 6367404SAli.Saidi@ARM.com} 6377404SAli.Saidi@ARM.com 638