table_walker.cc revision 7436
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437404SAli.Saidi@ARM.com#include "dev/io_device.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 457404SAli.Saidi@ARM.com 467404SAli.Saidi@ARM.com 477404SAli.Saidi@ARM.comusing namespace ArmISA; 487404SAli.Saidi@ARM.com 497404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 507404SAli.Saidi@ARM.com : MemObject(p), port(NULL), tlb(NULL), tc(NULL), req(NULL), 517404SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this) 527404SAli.Saidi@ARM.com{} 537404SAli.Saidi@ARM.com 547404SAli.Saidi@ARM.comTableWalker::~TableWalker() 557404SAli.Saidi@ARM.com{ 567404SAli.Saidi@ARM.com ; 577404SAli.Saidi@ARM.com} 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.com 607404SAli.Saidi@ARM.comunsigned int 617404SAli.Saidi@ARM.comdrain(Event *de) 627404SAli.Saidi@ARM.com{ 637404SAli.Saidi@ARM.com panic("Not implemented\n"); 647404SAli.Saidi@ARM.com} 657404SAli.Saidi@ARM.com 667404SAli.Saidi@ARM.comPort* 677404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 687404SAli.Saidi@ARM.com{ 697404SAli.Saidi@ARM.com if (if_name == "port") { 707404SAli.Saidi@ARM.com if (port != NULL) 717404SAli.Saidi@ARM.com fatal("%s: port already connected to %s", 727404SAli.Saidi@ARM.com name(), port->getPeer()->name()); 737404SAli.Saidi@ARM.com System *sys = params()->sys; 747404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 757404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 767404SAli.Saidi@ARM.com port = new DmaPort(this, sys, minb, maxb); 777404SAli.Saidi@ARM.com return port; 787404SAli.Saidi@ARM.com } 797404SAli.Saidi@ARM.com return NULL; 807404SAli.Saidi@ARM.com} 817404SAli.Saidi@ARM.com 827404SAli.Saidi@ARM.comFault 837404SAli.Saidi@ARM.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode mode, 847404SAli.Saidi@ARM.com TLB::Translation *_trans, bool _timing) 857404SAli.Saidi@ARM.com{ 867404SAli.Saidi@ARM.com // Right now 1 CPU == 1 TLB == 1 TLB walker 877404SAli.Saidi@ARM.com // In the future we might want to change this as multiple 887404SAli.Saidi@ARM.com // threads/contexts could share a walker and/or a TLB 897404SAli.Saidi@ARM.com if (tc || req) 907404SAli.Saidi@ARM.com panic("Overlapping TLB walks attempted\n"); 917404SAli.Saidi@ARM.com 927404SAli.Saidi@ARM.com tc = _tc; 937404SAli.Saidi@ARM.com transState = _trans; 947404SAli.Saidi@ARM.com req = _req; 957404SAli.Saidi@ARM.com fault = NoFault; 967404SAli.Saidi@ARM.com contextId = _cid; 977404SAli.Saidi@ARM.com timing = _timing; 987404SAli.Saidi@ARM.com 997436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 1007436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 1017404SAli.Saidi@ARM.com vaddr = req->getVaddr() & ~PcModeMask; 1027404SAli.Saidi@ARM.com sctlr = tc->readMiscReg(MISCREG_SCTLR); 1037404SAli.Saidi@ARM.com cpsr = tc->readMiscReg(MISCREG_CPSR); 1047404SAli.Saidi@ARM.com N = tc->readMiscReg(MISCREG_TTBCR); 1057404SAli.Saidi@ARM.com Addr ttbr = 0; 1067404SAli.Saidi@ARM.com 1077404SAli.Saidi@ARM.com isFetch = (mode == TLB::Execute); 1087404SAli.Saidi@ARM.com isWrite = (mode == TLB::Write); 1097404SAli.Saidi@ARM.com isPriv = (cpsr.mode != MODE_USER); 1107404SAli.Saidi@ARM.com 1117404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1127404SAli.Saidi@ARM.com assert(sctlr.m); 1137404SAli.Saidi@ARM.com 1147406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1157406SAli.Saidi@ARM.com vaddr, N, mbits(vaddr, 31, 32-N)); 1167406SAli.Saidi@ARM.com 1177406SAli.Saidi@ARM.com if (N == 0 || !mbits(vaddr, 31, 32-N)) { 1187406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1197404SAli.Saidi@ARM.com ttbr = tc->readMiscReg(MISCREG_TTBR0); 1207404SAli.Saidi@ARM.com } else { 1217406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1227406SAli.Saidi@ARM.com ttbr = tc->readMiscReg(MISCREG_TTBR1); 1237404SAli.Saidi@ARM.com N = 0; 1247404SAli.Saidi@ARM.com } 1257404SAli.Saidi@ARM.com 1267404SAli.Saidi@ARM.com Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(vaddr,31-N,20) << 2); 1277406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1287404SAli.Saidi@ARM.com 1297404SAli.Saidi@ARM.com 1307404SAli.Saidi@ARM.com // Trickbox address check 1317404SAli.Saidi@ARM.com fault = tlb->walkTrickBoxCheck(l1desc_addr, vaddr, sizeof(uint32_t), 1327406SAli.Saidi@ARM.com isFetch, isWrite, 0, true); 1337404SAli.Saidi@ARM.com if (fault) { 1347404SAli.Saidi@ARM.com tc = NULL; 1357404SAli.Saidi@ARM.com req = NULL; 1367404SAli.Saidi@ARM.com return fault; 1377404SAli.Saidi@ARM.com } 1387404SAli.Saidi@ARM.com 1397404SAli.Saidi@ARM.com if (timing) { 1407404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1417404SAli.Saidi@ARM.com &doL1DescEvent, (uint8_t*)&l1Desc.data, (Tick)0); 1427404SAli.Saidi@ARM.com } else { 1437404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1447404SAli.Saidi@ARM.com NULL, (uint8_t*)&l1Desc.data, (Tick)0); 1457404SAli.Saidi@ARM.com doL1Descriptor(); 1467404SAli.Saidi@ARM.com } 1477404SAli.Saidi@ARM.com 1487404SAli.Saidi@ARM.com return fault; 1497404SAli.Saidi@ARM.com} 1507404SAli.Saidi@ARM.com 1517404SAli.Saidi@ARM.comvoid 1527436Sdam.sunwoo@arm.comTableWalker::memAttrs(TlbEntry &te, uint8_t texcb, bool s) 1537404SAli.Saidi@ARM.com{ 1547436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1557436Sdam.sunwoo@arm.com te.shareable = false; // default value 1567436Sdam.sunwoo@arm.com bool outer_shareable = false; 1577404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 1587404SAli.Saidi@ARM.com switch(texcb) { 1597436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 1607404SAli.Saidi@ARM.com te.nonCacheable = true; 1617436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 1627436Sdam.sunwoo@arm.com te.shareable = true; 1637436Sdam.sunwoo@arm.com te.innerAttrs = 1; 1647436Sdam.sunwoo@arm.com te.outerAttrs = 0; 1657404SAli.Saidi@ARM.com break; 1667436Sdam.sunwoo@arm.com case 1: // Shareable Device 1677436Sdam.sunwoo@arm.com te.nonCacheable = true; 1687436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 1697436Sdam.sunwoo@arm.com te.shareable = true; 1707436Sdam.sunwoo@arm.com te.innerAttrs = 3; 1717436Sdam.sunwoo@arm.com te.outerAttrs = 0; 1727436Sdam.sunwoo@arm.com break; 1737436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 1747436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 1757436Sdam.sunwoo@arm.com te.shareable = s; 1767436Sdam.sunwoo@arm.com te.innerAttrs = 6; 1777436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 1787436Sdam.sunwoo@arm.com break; 1797436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 1807436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 1817436Sdam.sunwoo@arm.com te.shareable = s; 1827436Sdam.sunwoo@arm.com te.innerAttrs = 7; 1837436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 1847436Sdam.sunwoo@arm.com break; 1857436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 1867436Sdam.sunwoo@arm.com te.nonCacheable = true; 1877436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 1887436Sdam.sunwoo@arm.com te.shareable = s; 1897436Sdam.sunwoo@arm.com te.innerAttrs = 0; 1907436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 1917436Sdam.sunwoo@arm.com break; 1927436Sdam.sunwoo@arm.com case 5: // Reserved 1937436Sdam.sunwoo@arm.com break; 1947436Sdam.sunwoo@arm.com case 6: // Implementation Defined 1957436Sdam.sunwoo@arm.com break; 1967436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 1977436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 1987436Sdam.sunwoo@arm.com te.shareable = s; 1997436Sdam.sunwoo@arm.com te.innerAttrs = 5; 2007436Sdam.sunwoo@arm.com te.outerAttrs = 1; 2017436Sdam.sunwoo@arm.com break; 2027436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 2037436Sdam.sunwoo@arm.com te.nonCacheable = true; 2047436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2057436Sdam.sunwoo@arm.com te.shareable = false; 2067436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2077436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2087436Sdam.sunwoo@arm.com break; 2097436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 2107436Sdam.sunwoo@arm.com break; 2117436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 2127436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2137436Sdam.sunwoo@arm.com te.shareable = s; 2147404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 2157404SAli.Saidi@ARM.com te.nonCacheable = true; 2167436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 2177436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 2187404SAli.Saidi@ARM.com break; 2197436Sdam.sunwoo@arm.com default: 2207436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 2217404SAli.Saidi@ARM.com } 2227404SAli.Saidi@ARM.com } else { 2237404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 2247404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 2257436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 2267436Sdam.sunwoo@arm.com uint8_t curr_tr, curr_ir, curr_or; 2277404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 2287404SAli.Saidi@ARM.com case 0: 2297436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 2307436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 2317436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 2327436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos0 == 0); 2337404SAli.Saidi@ARM.com break; 2347404SAli.Saidi@ARM.com case 1: 2357436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 2367436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 2377436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 2387436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos1 == 0); 2397404SAli.Saidi@ARM.com break; 2407404SAli.Saidi@ARM.com case 2: 2417436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 2427436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 2437436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 2447436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos2 == 0); 2457404SAli.Saidi@ARM.com break; 2467404SAli.Saidi@ARM.com case 3: 2477436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 2487436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 2497436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 2507436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos3 == 0); 2517404SAli.Saidi@ARM.com break; 2527404SAli.Saidi@ARM.com case 4: 2537436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 2547436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 2557436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 2567436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos4 == 0); 2577404SAli.Saidi@ARM.com break; 2587404SAli.Saidi@ARM.com case 5: 2597436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 2607436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 2617436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 2627436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos5 == 0); 2637404SAli.Saidi@ARM.com break; 2647404SAli.Saidi@ARM.com case 6: 2657404SAli.Saidi@ARM.com panic("Imp defined type\n"); 2667404SAli.Saidi@ARM.com case 7: 2677436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 2687436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 2697436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 2707436Sdam.sunwoo@arm.com outer_shareable = (prrr.nos7 == 0); 2717404SAli.Saidi@ARM.com break; 2727404SAli.Saidi@ARM.com } 2737436Sdam.sunwoo@arm.com 2747436Sdam.sunwoo@arm.com switch(curr_tr) { 2757436Sdam.sunwoo@arm.com case 0: 2767436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 2777436Sdam.sunwoo@arm.com te.mtype = TlbEntry::StronglyOrdered; 2787436Sdam.sunwoo@arm.com te.nonCacheable = true; 2797436Sdam.sunwoo@arm.com te.innerAttrs = 1; 2807436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2817436Sdam.sunwoo@arm.com te.shareable = true; 2827436Sdam.sunwoo@arm.com break; 2837436Sdam.sunwoo@arm.com case 1: 2847436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 2857436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 2867436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Device; 2877436Sdam.sunwoo@arm.com te.nonCacheable = true; 2887436Sdam.sunwoo@arm.com te.innerAttrs = 3; 2897436Sdam.sunwoo@arm.com te.outerAttrs = 0; 2907436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 2917436Sdam.sunwoo@arm.com te.shareable = true; 2927436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 2937436Sdam.sunwoo@arm.com te.shareable = true; 2947436Sdam.sunwoo@arm.com break; 2957436Sdam.sunwoo@arm.com case 2: 2967436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 2977436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 2987436Sdam.sunwoo@arm.com te.mtype = TlbEntry::Normal; 2997436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 3007436Sdam.sunwoo@arm.com te.shareable = true; 3017436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 3027436Sdam.sunwoo@arm.com te.shareable = true; 3037436Sdam.sunwoo@arm.com //te.shareable = outer_shareable; 3047436Sdam.sunwoo@arm.com break; 3057436Sdam.sunwoo@arm.com case 3: 3067436Sdam.sunwoo@arm.com panic("Reserved type"); 3077436Sdam.sunwoo@arm.com } 3087436Sdam.sunwoo@arm.com 3097436Sdam.sunwoo@arm.com if (te.mtype == TlbEntry::Normal){ 3107436Sdam.sunwoo@arm.com switch(curr_ir) { 3117436Sdam.sunwoo@arm.com case 0: 3127436Sdam.sunwoo@arm.com te.nonCacheable = true; 3137436Sdam.sunwoo@arm.com te.innerAttrs = 0; 3147436Sdam.sunwoo@arm.com break; 3157436Sdam.sunwoo@arm.com case 1: 3167436Sdam.sunwoo@arm.com te.innerAttrs = 5; 3177436Sdam.sunwoo@arm.com break; 3187436Sdam.sunwoo@arm.com case 2: 3197436Sdam.sunwoo@arm.com te.innerAttrs = 6; 3207436Sdam.sunwoo@arm.com break; 3217436Sdam.sunwoo@arm.com case 3: 3227436Sdam.sunwoo@arm.com te.innerAttrs = 7; 3237436Sdam.sunwoo@arm.com break; 3247436Sdam.sunwoo@arm.com } 3257436Sdam.sunwoo@arm.com 3267436Sdam.sunwoo@arm.com switch(curr_or) { 3277436Sdam.sunwoo@arm.com case 0: 3287436Sdam.sunwoo@arm.com te.nonCacheable = true; 3297436Sdam.sunwoo@arm.com te.outerAttrs = 0; 3307436Sdam.sunwoo@arm.com break; 3317436Sdam.sunwoo@arm.com case 1: 3327436Sdam.sunwoo@arm.com te.outerAttrs = 1; 3337436Sdam.sunwoo@arm.com break; 3347436Sdam.sunwoo@arm.com case 2: 3357436Sdam.sunwoo@arm.com te.outerAttrs = 2; 3367436Sdam.sunwoo@arm.com break; 3377436Sdam.sunwoo@arm.com case 3: 3387436Sdam.sunwoo@arm.com te.outerAttrs = 3; 3397436Sdam.sunwoo@arm.com break; 3407436Sdam.sunwoo@arm.com } 3417436Sdam.sunwoo@arm.com } 3427404SAli.Saidi@ARM.com } 3437436Sdam.sunwoo@arm.com 3447436Sdam.sunwoo@arm.com /** Formatting for Physical Address Register (PAR) 3457436Sdam.sunwoo@arm.com * Only including lower bits (TLB info here) 3467436Sdam.sunwoo@arm.com * PAR: 3477436Sdam.sunwoo@arm.com * PA [31:12] 3487436Sdam.sunwoo@arm.com * Reserved [11] 3497436Sdam.sunwoo@arm.com * TLB info [10:1] 3507436Sdam.sunwoo@arm.com * NOS [10] (Not Outer Sharable) 3517436Sdam.sunwoo@arm.com * NS [9] (Non-Secure) 3527436Sdam.sunwoo@arm.com * -- [8] (Implementation Defined) 3537436Sdam.sunwoo@arm.com * SH [7] (Sharable) 3547436Sdam.sunwoo@arm.com * Inner[6:4](Inner memory attributes) 3557436Sdam.sunwoo@arm.com * Outer[3:2](Outer memory attributes) 3567436Sdam.sunwoo@arm.com * SS [1] (SuperSection) 3577436Sdam.sunwoo@arm.com * F [0] (Fault, Fault Status in [6:1] if faulted) 3587436Sdam.sunwoo@arm.com */ 3597436Sdam.sunwoo@arm.com te.attributes = ( 3607436Sdam.sunwoo@arm.com ((outer_shareable ? 0:1) << 10) | 3617436Sdam.sunwoo@arm.com // TODO: NS Bit 3627436Sdam.sunwoo@arm.com ((te.shareable ? 1:0) << 7) | 3637436Sdam.sunwoo@arm.com (te.innerAttrs << 4) | 3647436Sdam.sunwoo@arm.com (te.outerAttrs << 2) 3657436Sdam.sunwoo@arm.com // TODO: Supersection bit 3667436Sdam.sunwoo@arm.com // TODO: Fault bit 3677436Sdam.sunwoo@arm.com ); 3687436Sdam.sunwoo@arm.com 3697436Sdam.sunwoo@arm.com 3707404SAli.Saidi@ARM.com} 3717404SAli.Saidi@ARM.com 3727404SAli.Saidi@ARM.comvoid 3737404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 3747404SAli.Saidi@ARM.com{ 3757404SAli.Saidi@ARM.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", vaddr, l1Desc.data); 3767404SAli.Saidi@ARM.com TlbEntry te; 3777404SAli.Saidi@ARM.com 3787404SAli.Saidi@ARM.com switch (l1Desc.type()) { 3797404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 3807404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 3817404SAli.Saidi@ARM.com tc = NULL; 3827404SAli.Saidi@ARM.com req = NULL; 3837406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 3847406SAli.Saidi@ARM.com if (isFetch) 3857406SAli.Saidi@ARM.com fault = new PrefetchAbort(vaddr, ArmFault::Translation0); 3867406SAli.Saidi@ARM.com else 3877436Sdam.sunwoo@arm.com fault = new DataAbort(vaddr, NULL, isWrite, 3887436Sdam.sunwoo@arm.com ArmFault::Translation0); 3897404SAli.Saidi@ARM.com return; 3907404SAli.Saidi@ARM.com case L1Descriptor::Section: 3917436Sdam.sunwoo@arm.com if (sctlr.afe && bits(l1Desc.ap(), 0) == 0) { 3927436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 3937436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 3947436Sdam.sunwoo@arm.com * AccessFlag0 3957436Sdam.sunwoo@arm.com */ 3967436Sdam.sunwoo@arm.com 3977436Sdam.sunwoo@arm.com fault = new DataAbort(vaddr, NULL, isWrite, 3987436Sdam.sunwoo@arm.com ArmFault::AccessFlag0); 3997436Sdam.sunwoo@arm.com } 4007404SAli.Saidi@ARM.com 4017404SAli.Saidi@ARM.com if (l1Desc.supersection()) { 4027404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 4037404SAli.Saidi@ARM.com } 4047404SAli.Saidi@ARM.com te.N = 20; 4057404SAli.Saidi@ARM.com te.pfn = l1Desc.pfn(); 4067404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 4077404SAli.Saidi@ARM.com te.global = !l1Desc.global(); 4087404SAli.Saidi@ARM.com te.valid = true; 4097404SAli.Saidi@ARM.com te.vpn = vaddr >> te.N; 4107404SAli.Saidi@ARM.com te.sNp = true; 4117404SAli.Saidi@ARM.com te.xn = l1Desc.xn(); 4127404SAli.Saidi@ARM.com te.ap = l1Desc.ap(); 4137404SAli.Saidi@ARM.com te.domain = l1Desc.domain(); 4147404SAli.Saidi@ARM.com te.asid = contextId; 4157436Sdam.sunwoo@arm.com memAttrs(te, l1Desc.texcb(), l1Desc.shareable()); 4167404SAli.Saidi@ARM.com 4177404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 4187404SAli.Saidi@ARM.com DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n", 4197404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 4207404SAli.Saidi@ARM.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n", 4217404SAli.Saidi@ARM.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid); 4227404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 4237404SAli.Saidi@ARM.com l1Desc.domain(), l1Desc.data, (l1Desc.data >> 5) & 0xF ); 4247404SAli.Saidi@ARM.com 4257404SAli.Saidi@ARM.com tc = NULL; 4267404SAli.Saidi@ARM.com req = NULL; 4277404SAli.Saidi@ARM.com tlb->insert(vaddr, te); 4287404SAli.Saidi@ARM.com 4297404SAli.Saidi@ARM.com return; 4307404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 4317404SAli.Saidi@ARM.com Addr l2desc_addr; 4327404SAli.Saidi@ARM.com l2desc_addr = l1Desc.l2Addr() | (bits(vaddr, 19,12) << 2); 4337436Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 4347436Sdam.sunwoo@arm.com l2desc_addr); 4357404SAli.Saidi@ARM.com 4367404SAli.Saidi@ARM.com // Trickbox address check 4377404SAli.Saidi@ARM.com fault = tlb->walkTrickBoxCheck(l2desc_addr, vaddr, sizeof(uint32_t), 4387406SAli.Saidi@ARM.com isFetch, isWrite, l1Desc.domain(), false); 4397404SAli.Saidi@ARM.com if (fault) { 4407404SAli.Saidi@ARM.com tc = NULL; 4417404SAli.Saidi@ARM.com req = NULL; 4427404SAli.Saidi@ARM.com return; 4437404SAli.Saidi@ARM.com } 4447404SAli.Saidi@ARM.com 4457404SAli.Saidi@ARM.com 4467404SAli.Saidi@ARM.com if (timing) { 4477404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 4487404SAli.Saidi@ARM.com &doL2DescEvent, (uint8_t*)&l2Desc.data, 0); 4497404SAli.Saidi@ARM.com } else { 4507404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 4517404SAli.Saidi@ARM.com NULL, (uint8_t*)&l2Desc.data, 0); 4527404SAli.Saidi@ARM.com doL2Descriptor(); 4537404SAli.Saidi@ARM.com } 4547404SAli.Saidi@ARM.com return; 4557404SAli.Saidi@ARM.com default: 4567404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 4577404SAli.Saidi@ARM.com } 4587404SAli.Saidi@ARM.com} 4597404SAli.Saidi@ARM.com 4607404SAli.Saidi@ARM.comvoid 4617404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 4627404SAli.Saidi@ARM.com{ 4637404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", vaddr, l2Desc.data); 4647404SAli.Saidi@ARM.com TlbEntry te; 4657404SAli.Saidi@ARM.com 4667404SAli.Saidi@ARM.com if (l2Desc.invalid()) { 4677404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 4687404SAli.Saidi@ARM.com tc = NULL; 4697404SAli.Saidi@ARM.com req = NULL; 4707406SAli.Saidi@ARM.com if (isFetch) 4717406SAli.Saidi@ARM.com fault = new PrefetchAbort(vaddr, ArmFault::Translation1); 4727406SAli.Saidi@ARM.com else 4737436Sdam.sunwoo@arm.com fault = new DataAbort(vaddr, l1Desc.domain(), isWrite, 4747436Sdam.sunwoo@arm.com ArmFault::Translation1); 4757404SAli.Saidi@ARM.com return; 4767404SAli.Saidi@ARM.com } 4777404SAli.Saidi@ARM.com 4787436Sdam.sunwoo@arm.com if (sctlr.afe && bits(l2Desc.ap(), 0) == 0) { 4797436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 4807436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 4817436Sdam.sunwoo@arm.com */ 4827436Sdam.sunwoo@arm.com 4837436Sdam.sunwoo@arm.com fault = new DataAbort(vaddr, NULL, isWrite, ArmFault::AccessFlag1); 4847436Sdam.sunwoo@arm.com } 4857436Sdam.sunwoo@arm.com 4867404SAli.Saidi@ARM.com if (l2Desc.large()) { 4877404SAli.Saidi@ARM.com te.N = 16; 4887404SAli.Saidi@ARM.com te.pfn = l2Desc.pfn(); 4897404SAli.Saidi@ARM.com } else { 4907404SAli.Saidi@ARM.com te.N = 12; 4917404SAli.Saidi@ARM.com te.pfn = l2Desc.pfn(); 4927404SAli.Saidi@ARM.com } 4937404SAli.Saidi@ARM.com 4947404SAli.Saidi@ARM.com te.valid = true; 4957404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 4967404SAli.Saidi@ARM.com te.asid = contextId; 4977404SAli.Saidi@ARM.com te.sNp = false; 4987404SAli.Saidi@ARM.com te.vpn = vaddr >> te.N; 4997404SAli.Saidi@ARM.com te.global = l2Desc.global(); 5007404SAli.Saidi@ARM.com te.xn = l2Desc.xn(); 5017404SAli.Saidi@ARM.com te.ap = l2Desc.ap(); 5027404SAli.Saidi@ARM.com te.domain = l1Desc.domain(); 5037436Sdam.sunwoo@arm.com memAttrs(te, l2Desc.texcb(), l2Desc.shareable()); 5047404SAli.Saidi@ARM.com 5057404SAli.Saidi@ARM.com tc = NULL; 5067404SAli.Saidi@ARM.com req = NULL; 5077404SAli.Saidi@ARM.com tlb->insert(vaddr, te); 5087404SAli.Saidi@ARM.com} 5097404SAli.Saidi@ARM.com 5107404SAli.Saidi@ARM.comArmISA::TableWalker * 5117404SAli.Saidi@ARM.comArmTableWalkerParams::create() 5127404SAli.Saidi@ARM.com{ 5137404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 5147404SAli.Saidi@ARM.com} 5157404SAli.Saidi@ARM.com 516