table_walker.cc revision 7406
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com */ 397404SAli.Saidi@ARM.com 407404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 417404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 427404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 437404SAli.Saidi@ARM.com#include "dev/io_device.hh" 447404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 457404SAli.Saidi@ARM.com 467404SAli.Saidi@ARM.com 477404SAli.Saidi@ARM.comusing namespace ArmISA; 487404SAli.Saidi@ARM.com 497404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 507404SAli.Saidi@ARM.com : MemObject(p), port(NULL), tlb(NULL), tc(NULL), req(NULL), 517404SAli.Saidi@ARM.com doL1DescEvent(this), doL2DescEvent(this) 527404SAli.Saidi@ARM.com{} 537404SAli.Saidi@ARM.com 547404SAli.Saidi@ARM.comTableWalker::~TableWalker() 557404SAli.Saidi@ARM.com{ 567404SAli.Saidi@ARM.com ; 577404SAli.Saidi@ARM.com} 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.com 607404SAli.Saidi@ARM.comunsigned int 617404SAli.Saidi@ARM.comdrain(Event *de) 627404SAli.Saidi@ARM.com{ 637404SAli.Saidi@ARM.com panic("Not implemented\n"); 647404SAli.Saidi@ARM.com} 657404SAli.Saidi@ARM.com 667404SAli.Saidi@ARM.comPort* 677404SAli.Saidi@ARM.comTableWalker::getPort(const std::string &if_name, int idx) 687404SAli.Saidi@ARM.com{ 697404SAli.Saidi@ARM.com if (if_name == "port") { 707404SAli.Saidi@ARM.com if (port != NULL) 717404SAli.Saidi@ARM.com fatal("%s: port already connected to %s", 727404SAli.Saidi@ARM.com name(), port->getPeer()->name()); 737404SAli.Saidi@ARM.com System *sys = params()->sys; 747404SAli.Saidi@ARM.com Tick minb = params()->min_backoff; 757404SAli.Saidi@ARM.com Tick maxb = params()->max_backoff; 767404SAli.Saidi@ARM.com port = new DmaPort(this, sys, minb, maxb); 777404SAli.Saidi@ARM.com return port; 787404SAli.Saidi@ARM.com } 797404SAli.Saidi@ARM.com return NULL; 807404SAli.Saidi@ARM.com} 817404SAli.Saidi@ARM.com 827404SAli.Saidi@ARM.comFault 837404SAli.Saidi@ARM.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode mode, 847404SAli.Saidi@ARM.com TLB::Translation *_trans, bool _timing) 857404SAli.Saidi@ARM.com{ 867404SAli.Saidi@ARM.com // Right now 1 CPU == 1 TLB == 1 TLB walker 877404SAli.Saidi@ARM.com // In the future we might want to change this as multiple 887404SAli.Saidi@ARM.com // threads/contexts could share a walker and/or a TLB 897404SAli.Saidi@ARM.com if (tc || req) 907404SAli.Saidi@ARM.com panic("Overlapping TLB walks attempted\n"); 917404SAli.Saidi@ARM.com 927404SAli.Saidi@ARM.com tc = _tc; 937404SAli.Saidi@ARM.com transState = _trans; 947404SAli.Saidi@ARM.com req = _req; 957404SAli.Saidi@ARM.com fault = NoFault; 967404SAli.Saidi@ARM.com contextId = _cid; 977404SAli.Saidi@ARM.com timing = _timing; 987404SAli.Saidi@ARM.com 997404SAli.Saidi@ARM.com // XXX These should be cached or grabbed from cached copies in 1007404SAli.Saidi@ARM.com // the TLB, all these miscreg reads are expensive 1017404SAli.Saidi@ARM.com vaddr = req->getVaddr() & ~PcModeMask; 1027404SAli.Saidi@ARM.com sctlr = tc->readMiscReg(MISCREG_SCTLR); 1037404SAli.Saidi@ARM.com cpsr = tc->readMiscReg(MISCREG_CPSR); 1047404SAli.Saidi@ARM.com N = tc->readMiscReg(MISCREG_TTBCR); 1057404SAli.Saidi@ARM.com Addr ttbr = 0; 1067404SAli.Saidi@ARM.com 1077404SAli.Saidi@ARM.com isFetch = (mode == TLB::Execute); 1087404SAli.Saidi@ARM.com isWrite = (mode == TLB::Write); 1097404SAli.Saidi@ARM.com isPriv = (cpsr.mode != MODE_USER); 1107404SAli.Saidi@ARM.com 1117404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 1127404SAli.Saidi@ARM.com assert(sctlr.m); 1137404SAli.Saidi@ARM.com 1147406SAli.Saidi@ARM.com DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", 1157406SAli.Saidi@ARM.com vaddr, N, mbits(vaddr, 31, 32-N)); 1167406SAli.Saidi@ARM.com 1177406SAli.Saidi@ARM.com if (N == 0 || !mbits(vaddr, 31, 32-N)) { 1187406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 1197404SAli.Saidi@ARM.com ttbr = tc->readMiscReg(MISCREG_TTBR0); 1207404SAli.Saidi@ARM.com } else { 1217406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 1227406SAli.Saidi@ARM.com ttbr = tc->readMiscReg(MISCREG_TTBR1); 1237404SAli.Saidi@ARM.com N = 0; 1247404SAli.Saidi@ARM.com } 1257404SAli.Saidi@ARM.com 1267404SAli.Saidi@ARM.com Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(vaddr,31-N,20) << 2); 1277406SAli.Saidi@ARM.com DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 1287404SAli.Saidi@ARM.com 1297404SAli.Saidi@ARM.com 1307404SAli.Saidi@ARM.com // Trickbox address check 1317404SAli.Saidi@ARM.com fault = tlb->walkTrickBoxCheck(l1desc_addr, vaddr, sizeof(uint32_t), 1327406SAli.Saidi@ARM.com isFetch, isWrite, 0, true); 1337404SAli.Saidi@ARM.com if (fault) { 1347404SAli.Saidi@ARM.com tc = NULL; 1357404SAli.Saidi@ARM.com req = NULL; 1367404SAli.Saidi@ARM.com return fault; 1377404SAli.Saidi@ARM.com } 1387404SAli.Saidi@ARM.com 1397404SAli.Saidi@ARM.com if (timing) { 1407404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1417404SAli.Saidi@ARM.com &doL1DescEvent, (uint8_t*)&l1Desc.data, (Tick)0); 1427404SAli.Saidi@ARM.com } else { 1437404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 1447404SAli.Saidi@ARM.com NULL, (uint8_t*)&l1Desc.data, (Tick)0); 1457404SAli.Saidi@ARM.com doL1Descriptor(); 1467404SAli.Saidi@ARM.com } 1477404SAli.Saidi@ARM.com 1487404SAli.Saidi@ARM.com return fault; 1497404SAli.Saidi@ARM.com} 1507404SAli.Saidi@ARM.com 1517404SAli.Saidi@ARM.comvoid 1527404SAli.Saidi@ARM.comTableWalker::memAttrs(TlbEntry &te, uint8_t texcb) 1537404SAli.Saidi@ARM.com{ 1547404SAli.Saidi@ARM.com 1557404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 1567404SAli.Saidi@ARM.com switch(texcb) { 1577404SAli.Saidi@ARM.com case 0: 1587404SAli.Saidi@ARM.com case 1: 1597404SAli.Saidi@ARM.com case 4: 1607404SAli.Saidi@ARM.com case 8: 1617404SAli.Saidi@ARM.com te.nonCacheable = true; 1627404SAli.Saidi@ARM.com break; 1637404SAli.Saidi@ARM.com case 16: 1647404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 1657404SAli.Saidi@ARM.com te.nonCacheable = true; 1667404SAli.Saidi@ARM.com break; 1677404SAli.Saidi@ARM.com } 1687404SAli.Saidi@ARM.com } else { 1697404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 1707404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 1717404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 1727404SAli.Saidi@ARM.com case 0: 1737404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 1747404SAli.Saidi@ARM.com te.nonCacheable = true; 1757404SAli.Saidi@ARM.com break; 1767404SAli.Saidi@ARM.com case 1: 1777404SAli.Saidi@ARM.com if (nmrr.ir1 == 0 || nmrr.or1 == 0 || prrr.tr1 != 0x2) 1787404SAli.Saidi@ARM.com te.nonCacheable = true; 1797404SAli.Saidi@ARM.com break; 1807404SAli.Saidi@ARM.com case 2: 1817404SAli.Saidi@ARM.com if (nmrr.ir2 == 0 || nmrr.or2 == 0 || prrr.tr2 != 0x2) 1827404SAli.Saidi@ARM.com te.nonCacheable = true; 1837404SAli.Saidi@ARM.com break; 1847404SAli.Saidi@ARM.com case 3: 1857404SAli.Saidi@ARM.com if (nmrr.ir3 == 0 || nmrr.or3 == 0 || prrr.tr3 != 0x2) 1867404SAli.Saidi@ARM.com te.nonCacheable = true; 1877404SAli.Saidi@ARM.com break; 1887404SAli.Saidi@ARM.com case 4: 1897404SAli.Saidi@ARM.com if (nmrr.ir4 == 0 || nmrr.or4 == 0 || prrr.tr4 != 0x2) 1907404SAli.Saidi@ARM.com te.nonCacheable = true; 1917404SAli.Saidi@ARM.com break; 1927404SAli.Saidi@ARM.com case 5: 1937404SAli.Saidi@ARM.com if (nmrr.ir5 == 0 || nmrr.or5 == 0 || prrr.tr5 != 0x2) 1947404SAli.Saidi@ARM.com te.nonCacheable = true; 1957404SAli.Saidi@ARM.com break; 1967404SAli.Saidi@ARM.com case 6: 1977404SAli.Saidi@ARM.com panic("Imp defined type\n"); 1987404SAli.Saidi@ARM.com case 7: 1997404SAli.Saidi@ARM.com if (nmrr.ir7 == 0 || nmrr.or7 == 0 || prrr.tr7 != 0x2) 2007404SAli.Saidi@ARM.com te.nonCacheable = true; 2017404SAli.Saidi@ARM.com break; 2027404SAli.Saidi@ARM.com } 2037404SAli.Saidi@ARM.com } 2047404SAli.Saidi@ARM.com} 2057404SAli.Saidi@ARM.com 2067404SAli.Saidi@ARM.comvoid 2077404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 2087404SAli.Saidi@ARM.com{ 2097404SAli.Saidi@ARM.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", vaddr, l1Desc.data); 2107404SAli.Saidi@ARM.com TlbEntry te; 2117404SAli.Saidi@ARM.com 2127404SAli.Saidi@ARM.com switch (l1Desc.type()) { 2137404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 2147404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 2157404SAli.Saidi@ARM.com tc = NULL; 2167404SAli.Saidi@ARM.com req = NULL; 2177406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 2187406SAli.Saidi@ARM.com if (isFetch) 2197406SAli.Saidi@ARM.com fault = new PrefetchAbort(vaddr, ArmFault::Translation0); 2207406SAli.Saidi@ARM.com else 2217406SAli.Saidi@ARM.com fault = new DataAbort(vaddr, NULL, isWrite, ArmFault::Translation0); 2227404SAli.Saidi@ARM.com return; 2237404SAli.Saidi@ARM.com case L1Descriptor::Section: 2247404SAli.Saidi@ARM.com if (sctlr.afe && bits(l1Desc.ap(), 0) == 0) 2257404SAli.Saidi@ARM.com panic("Haven't implemented AFE\n"); 2267404SAli.Saidi@ARM.com 2277404SAli.Saidi@ARM.com if (l1Desc.supersection()) { 2287404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 2297404SAli.Saidi@ARM.com } 2307404SAli.Saidi@ARM.com te.N = 20; 2317404SAli.Saidi@ARM.com te.pfn = l1Desc.pfn(); 2327404SAli.Saidi@ARM.com te.size = (1<<te.N) - 1; 2337404SAli.Saidi@ARM.com te.global = !l1Desc.global(); 2347404SAli.Saidi@ARM.com te.valid = true; 2357404SAli.Saidi@ARM.com te.vpn = vaddr >> te.N; 2367404SAli.Saidi@ARM.com te.sNp = true; 2377404SAli.Saidi@ARM.com te.xn = l1Desc.xn(); 2387404SAli.Saidi@ARM.com te.ap = l1Desc.ap(); 2397404SAli.Saidi@ARM.com te.domain = l1Desc.domain(); 2407404SAli.Saidi@ARM.com te.asid = contextId; 2417404SAli.Saidi@ARM.com memAttrs(te, l1Desc.texcb()); 2427404SAli.Saidi@ARM.com 2437404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 2447404SAli.Saidi@ARM.com DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n", 2457404SAli.Saidi@ARM.com te.N, te.pfn, te.size, te.global, te.valid); 2467404SAli.Saidi@ARM.com DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n", 2477404SAli.Saidi@ARM.com te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid); 2487404SAli.Saidi@ARM.com DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", 2497404SAli.Saidi@ARM.com l1Desc.domain(), l1Desc.data, (l1Desc.data >> 5) & 0xF ); 2507404SAli.Saidi@ARM.com 2517404SAli.Saidi@ARM.com tc = NULL; 2527404SAli.Saidi@ARM.com req = NULL; 2537404SAli.Saidi@ARM.com tlb->insert(vaddr, te); 2547404SAli.Saidi@ARM.com 2557404SAli.Saidi@ARM.com return; 2567404SAli.Saidi@ARM.com case L1Descriptor::PageTable: 2577404SAli.Saidi@ARM.com Addr l2desc_addr; 2587404SAli.Saidi@ARM.com l2desc_addr = l1Desc.l2Addr() | (bits(vaddr, 19,12) << 2); 2597404SAli.Saidi@ARM.com DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", l2desc_addr); 2607404SAli.Saidi@ARM.com 2617404SAli.Saidi@ARM.com // Trickbox address check 2627404SAli.Saidi@ARM.com fault = tlb->walkTrickBoxCheck(l2desc_addr, vaddr, sizeof(uint32_t), 2637406SAli.Saidi@ARM.com isFetch, isWrite, l1Desc.domain(), false); 2647404SAli.Saidi@ARM.com if (fault) { 2657404SAli.Saidi@ARM.com tc = NULL; 2667404SAli.Saidi@ARM.com req = NULL; 2677404SAli.Saidi@ARM.com return; 2687404SAli.Saidi@ARM.com } 2697404SAli.Saidi@ARM.com 2707404SAli.Saidi@ARM.com 2717404SAli.Saidi@ARM.com if (timing) { 2727404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 2737404SAli.Saidi@ARM.com &doL2DescEvent, (uint8_t*)&l2Desc.data, 0); 2747404SAli.Saidi@ARM.com } else { 2757404SAli.Saidi@ARM.com port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 2767404SAli.Saidi@ARM.com NULL, (uint8_t*)&l2Desc.data, 0); 2777404SAli.Saidi@ARM.com doL2Descriptor(); 2787404SAli.Saidi@ARM.com } 2797404SAli.Saidi@ARM.com return; 2807404SAli.Saidi@ARM.com default: 2817404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 2827404SAli.Saidi@ARM.com } 2837404SAli.Saidi@ARM.com} 2847404SAli.Saidi@ARM.com 2857404SAli.Saidi@ARM.comvoid 2867404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 2877404SAli.Saidi@ARM.com{ 2887404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", vaddr, l2Desc.data); 2897404SAli.Saidi@ARM.com TlbEntry te; 2907404SAli.Saidi@ARM.com 2917404SAli.Saidi@ARM.com if (sctlr.afe && bits(l1Desc.ap(), 0) == 0) 2927404SAli.Saidi@ARM.com panic("Haven't implemented AFE\n"); 2937404SAli.Saidi@ARM.com 2947404SAli.Saidi@ARM.com if (l2Desc.invalid()) { 2957404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 2967404SAli.Saidi@ARM.com tc = NULL; 2977404SAli.Saidi@ARM.com req = NULL; 2987406SAli.Saidi@ARM.com if (isFetch) 2997406SAli.Saidi@ARM.com fault = new PrefetchAbort(vaddr, ArmFault::Translation1); 3007406SAli.Saidi@ARM.com else 3017406SAli.Saidi@ARM.com fault = new DataAbort(vaddr, l1Desc.domain(), isWrite, ArmFault::Translation1); 3027404SAli.Saidi@ARM.com return; 3037404SAli.Saidi@ARM.com } 3047404SAli.Saidi@ARM.com 3057404SAli.Saidi@ARM.com if (l2Desc.large()) { 3067404SAli.Saidi@ARM.com te.N = 16; 3077404SAli.Saidi@ARM.com te.pfn = l2Desc.pfn(); 3087404SAli.Saidi@ARM.com } else { 3097404SAli.Saidi@ARM.com te.N = 12; 3107404SAli.Saidi@ARM.com te.pfn = l2Desc.pfn(); 3117404SAli.Saidi@ARM.com } 3127404SAli.Saidi@ARM.com 3137404SAli.Saidi@ARM.com te.valid = true; 3147404SAli.Saidi@ARM.com te.size = (1 << te.N) - 1; 3157404SAli.Saidi@ARM.com te.asid = contextId; 3167404SAli.Saidi@ARM.com te.sNp = false; 3177404SAli.Saidi@ARM.com te.vpn = vaddr >> te.N; 3187404SAli.Saidi@ARM.com te.global = l2Desc.global(); 3197404SAli.Saidi@ARM.com te.xn = l2Desc.xn(); 3207404SAli.Saidi@ARM.com te.ap = l2Desc.ap(); 3217404SAli.Saidi@ARM.com te.domain = l1Desc.domain(); 3227404SAli.Saidi@ARM.com memAttrs(te, l2Desc.texcb()); 3237404SAli.Saidi@ARM.com 3247404SAli.Saidi@ARM.com tc = NULL; 3257404SAli.Saidi@ARM.com req = NULL; 3267404SAli.Saidi@ARM.com tlb->insert(vaddr, te); 3277404SAli.Saidi@ARM.com} 3287404SAli.Saidi@ARM.com 3297404SAli.Saidi@ARM.comArmISA::TableWalker * 3307404SAli.Saidi@ARM.comArmTableWalkerParams::create() 3317404SAli.Saidi@ARM.com{ 3327404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 3337404SAli.Saidi@ARM.com} 3347404SAli.Saidi@ARM.com 335