table_walker.cc revision 14095
17404SAli.Saidi@ARM.com/* 214095Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2019 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 4010873Sandreas.sandberg@arm.com#include "arch/arm/table_walker.hh" 417404SAli.Saidi@ARM.com 4210474Sandreas.hansson@arm.com#include <memory> 4310474Sandreas.hansson@arm.com 447404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4510037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4610037SARM gem5 Developers#include "arch/arm/system.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 487728SAli.Saidi@ARM.com#include "cpu/base.hh" 497404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 508245Snate@binkert.org#include "debug/Checkpoint.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528245Snate@binkert.org#include "debug/TLB.hh" 538245Snate@binkert.org#include "debug/TLBVerbose.hh" 5410873Sandreas.sandberg@arm.com#include "dev/dma_device.hh" 557748SAli.Saidi@ARM.com#include "sim/system.hh" 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comusing namespace ArmISA; 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 6013892Sgabeblack@google.com : ClockedObject(p), 6110717Sandreas.hansson@arm.com stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 6210717Sandreas.hansson@arm.com isStage2(p->is_stage2), tlb(NULL), 6310717Sandreas.hansson@arm.com currState(NULL), pending(false), 649258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6510621SCurtis.Dunham@arm.com pendingReqs(0), 6610621SCurtis.Dunham@arm.com pendingChangeTick(curTick()), 6712086Sspwilson2@wisc.edu doL1DescEvent([this]{ doL1DescriptorWrapper(); }, name()), 6812086Sspwilson2@wisc.edu doL2DescEvent([this]{ doL2DescriptorWrapper(); }, name()), 6912086Sspwilson2@wisc.edu doL0LongDescEvent([this]{ doL0LongDescriptorWrapper(); }, name()), 7012086Sspwilson2@wisc.edu doL1LongDescEvent([this]{ doL1LongDescriptorWrapper(); }, name()), 7112086Sspwilson2@wisc.edu doL2LongDescEvent([this]{ doL2LongDescriptorWrapper(); }, name()), 7212086Sspwilson2@wisc.edu doL3LongDescEvent([this]{ doL3LongDescriptorWrapper(); }, name()), 7311588SCurtis.Dunham@arm.com LongDescEventByLevel { &doL0LongDescEvent, &doL1LongDescEvent, 7411588SCurtis.Dunham@arm.com &doL2LongDescEvent, &doL3LongDescEvent }, 7512086Sspwilson2@wisc.edu doProcessEvent([this]{ processWalkWrapper(); }, name()) 767439Sdam.sunwoo@arm.com{ 777576SAli.Saidi@ARM.com sctlr = 0; 7810037SARM gem5 Developers 7910037SARM gem5 Developers // Cache system-level properties 8010037SARM gem5 Developers if (FullSystem) { 8110717Sandreas.hansson@arm.com ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 8210037SARM gem5 Developers assert(armSys); 8310037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 8410037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 8510037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 8610037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 8710037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 8810037SARM gem5 Developers } else { 8910037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 9010037SARM gem5 Developers _haveLargeAsid64 = false; 9110037SARM gem5 Developers physAddrRange = 32; 9210037SARM gem5 Developers } 9310037SARM gem5 Developers 947439Sdam.sunwoo@arm.com} 957404SAli.Saidi@ARM.com 967404SAli.Saidi@ARM.comTableWalker::~TableWalker() 977404SAli.Saidi@ARM.com{ 987404SAli.Saidi@ARM.com ; 997404SAli.Saidi@ARM.com} 1007404SAli.Saidi@ARM.com 10110717Sandreas.hansson@arm.comvoid 10210717Sandreas.hansson@arm.comTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 10310717Sandreas.hansson@arm.com{ 10410717Sandreas.hansson@arm.com stage2Mmu = m; 10513795SAndrea.Mondelli@ucf.edu port = &m->getDMAPort(); 10610717Sandreas.hansson@arm.com masterId = master_id; 10710717Sandreas.hansson@arm.com} 10810717Sandreas.hansson@arm.com 10910717Sandreas.hansson@arm.comvoid 11010717Sandreas.hansson@arm.comTableWalker::init() 11110717Sandreas.hansson@arm.com{ 11210717Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 11310717Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 11410717Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 11510717Sandreas.hansson@arm.com} 11610717Sandreas.hansson@arm.com 11713784Sgabeblack@google.comPort & 11813784Sgabeblack@google.comTableWalker::getPort(const std::string &if_name, PortID idx) 11910717Sandreas.hansson@arm.com{ 12010717Sandreas.hansson@arm.com if (if_name == "port") { 12110717Sandreas.hansson@arm.com if (!isStage2) { 12210717Sandreas.hansson@arm.com return *port; 12310717Sandreas.hansson@arm.com } else { 12410717Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 12510717Sandreas.hansson@arm.com } 12610717Sandreas.hansson@arm.com } 12713892Sgabeblack@google.com return ClockedObject::getPort(if_name, idx); 12810717Sandreas.hansson@arm.com} 12910717Sandreas.hansson@arm.com 13010537Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 13110537Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 13210537Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 13314040Sgiacomo.travaglini@arm.com vaddr(0), vaddr_tainted(0), 13414040Sgiacomo.travaglini@arm.com sctlr(0), scr(0), cpsr(0), tcr(0), 13514040Sgiacomo.travaglini@arm.com htcr(0), hcr(0), vtcr(0), 13614040Sgiacomo.travaglini@arm.com isWrite(false), isFetch(false), isSecure(false), 13710537Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 13814095Sgiacomo.travaglini@arm.com pxnTable(false), hpd(false), stage2Req(false), 13910537Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 14010537Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 14110537Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 14210037SARM gem5 Developers{ 14310037SARM gem5 Developers} 14410037SARM gem5 Developers 1459152Satgutier@umich.eduvoid 1469152Satgutier@umich.eduTableWalker::completeDrain() 1479152Satgutier@umich.edu{ 14810913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 14911588SCurtis.Dunham@arm.com stateQueues[L0].empty() && stateQueues[L1].empty() && 15011588SCurtis.Dunham@arm.com stateQueues[L2].empty() && stateQueues[L3].empty() && 1519152Satgutier@umich.edu pendingQueue.empty()) { 15210913Sandreas.sandberg@arm.com 1539152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 15410913Sandreas.sandberg@arm.com signalDrainDone(); 1559152Satgutier@umich.edu } 1569152Satgutier@umich.edu} 1579152Satgutier@umich.edu 15810913Sandreas.sandberg@arm.comDrainState 15910913Sandreas.sandberg@arm.comTableWalker::drain() 1607404SAli.Saidi@ARM.com{ 16110037SARM gem5 Developers bool state_queues_not_empty = false; 1629152Satgutier@umich.edu 16310037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 16410037SARM gem5 Developers if (!stateQueues[i].empty()) { 16510037SARM gem5 Developers state_queues_not_empty = true; 16610037SARM gem5 Developers break; 16710037SARM gem5 Developers } 16810037SARM gem5 Developers } 16910037SARM gem5 Developers 17010037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1719152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 17210913Sandreas.sandberg@arm.com return DrainState::Draining; 17310037SARM gem5 Developers } else { 17410037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 17510913Sandreas.sandberg@arm.com return DrainState::Drained; 1767733SAli.Saidi@ARM.com } 1777404SAli.Saidi@ARM.com} 1787404SAli.Saidi@ARM.com 1797748SAli.Saidi@ARM.comvoid 1809342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1817748SAli.Saidi@ARM.com{ 1829524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1839152Satgutier@umich.edu delete currState; 1849152Satgutier@umich.edu currState = NULL; 18510621SCurtis.Dunham@arm.com pendingChange(); 1867748SAli.Saidi@ARM.com } 1877748SAli.Saidi@ARM.com} 1887748SAli.Saidi@ARM.com 1897404SAli.Saidi@ARM.comFault 19012749Sgiacomo.travaglini@arm.comTableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, 19110037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 19210037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 19311580SDylan.Johnson@ARM.com bool secure, TLB::ArmTranslationType tranType, 19411580SDylan.Johnson@ARM.com bool _stage2Req) 1957404SAli.Saidi@ARM.com{ 1968733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 19710621SCurtis.Dunham@arm.com ++statWalks; 19810621SCurtis.Dunham@arm.com 19910109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 20010037SARM gem5 Developers 20110109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 2027439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 2037439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 2047439Sdam.sunwoo@arm.com // TLB miss. 2057439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 2067404SAli.Saidi@ARM.com 2077439Sdam.sunwoo@arm.com currState = new WalkerState(); 2087439Sdam.sunwoo@arm.com currState->tableWalker = this; 20910109SGeoffrey.Blake@arm.com } else if (_functional) { 21010109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 21110109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 21210109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 21310109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 21410109SGeoffrey.Blake@arm.com savedCurrState = currState; 21510109SGeoffrey.Blake@arm.com currState = new WalkerState(); 21610109SGeoffrey.Blake@arm.com currState->tableWalker = this; 2178202SAli.Saidi@ARM.com } else if (_timing) { 2188202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 2198202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 2208202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 2218202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 2228202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 2238202SAli.Saidi@ARM.com // up everything. 22410037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 22510621SCurtis.Dunham@arm.com ++statSquashedBefore; 22610474Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 2278202SAli.Saidi@ARM.com } 2287439Sdam.sunwoo@arm.com } 22910621SCurtis.Dunham@arm.com pendingChange(); 2307439Sdam.sunwoo@arm.com 23110621SCurtis.Dunham@arm.com currState->startTime = curTick(); 2327439Sdam.sunwoo@arm.com currState->tc = _tc; 23311517SCurtis.Dunham@arm.com // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 23411517SCurtis.Dunham@arm.com // aarch32/translation/translation/AArch32.TranslateAddress dictates 23511517SCurtis.Dunham@arm.com // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 23612735Sandreas.sandberg@arm.com if (isStage2) { 23712735Sandreas.sandberg@arm.com currState->el = EL1; 23812735Sandreas.sandberg@arm.com currState->aarch64 = ELIs64(_tc, EL2); 23912735Sandreas.sandberg@arm.com } else { 24012735Sandreas.sandberg@arm.com currState->el = 24112735Sandreas.sandberg@arm.com TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType); 24212735Sandreas.sandberg@arm.com currState->aarch64 = 24312735Sandreas.sandberg@arm.com ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el); 24412735Sandreas.sandberg@arm.com } 2457439Sdam.sunwoo@arm.com currState->transState = _trans; 2467439Sdam.sunwoo@arm.com currState->req = _req; 2477439Sdam.sunwoo@arm.com currState->fault = NoFault; 24810037SARM gem5 Developers currState->asid = _asid; 24910037SARM gem5 Developers currState->vmid = _vmid; 25010037SARM gem5 Developers currState->isHyp = _isHyp; 2517439Sdam.sunwoo@arm.com currState->timing = _timing; 2528733Sgeoffrey.blake@arm.com currState->functional = _functional; 2537439Sdam.sunwoo@arm.com currState->mode = _mode; 25410037SARM gem5 Developers currState->tranType = tranType; 25510037SARM gem5 Developers currState->isSecure = secure; 25610037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2577404SAli.Saidi@ARM.com 2587436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2597436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 26010037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 26110037SARM gem5 Developers if (currState->aarch64) 26210037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 26310037SARM gem5 Developers currState->tc, currState->el); 26410037SARM gem5 Developers else 26510037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 26610037SARM gem5 Developers 26710037SARM gem5 Developers if (currState->aarch64) { 26811575SDylan.Johnson@ARM.com if (isStage2) { 26911575SDylan.Johnson@ARM.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 27011575SDylan.Johnson@ARM.com currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 27111575SDylan.Johnson@ARM.com } else switch (currState->el) { 27210037SARM gem5 Developers case EL0: 27310037SARM gem5 Developers case EL1: 27410037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 27510324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 27610037SARM gem5 Developers break; 27711574SCurtis.Dunham@arm.com case EL2: 27811574SCurtis.Dunham@arm.com assert(_haveVirtualization); 27911574SCurtis.Dunham@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 28011574SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 28111574SCurtis.Dunham@arm.com break; 28210037SARM gem5 Developers case EL3: 28310037SARM gem5 Developers assert(haveSecurity); 28410037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 28510324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 28610037SARM gem5 Developers break; 28710037SARM gem5 Developers default: 28810037SARM gem5 Developers panic("Invalid exception level"); 28910037SARM gem5 Developers break; 29010037SARM gem5 Developers } 29111575SDylan.Johnson@ARM.com currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 29210037SARM gem5 Developers } else { 29312499Sgiacomo.travaglini@arm.com currState->sctlr = currState->tc->readMiscReg(snsBankedIndex( 29410037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 29512499Sgiacomo.travaglini@arm.com currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex( 29610037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 29710037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 29810037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 29910037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 30010037SARM gem5 Developers } 3017439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 3027439Sdam.sunwoo@arm.com 3037439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 3047439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 3057439Sdam.sunwoo@arm.com 30610621SCurtis.Dunham@arm.com statRequestOrigin[REQUESTED][currState->isFetch]++; 30710621SCurtis.Dunham@arm.com 30811580SDylan.Johnson@ARM.com currState->stage2Req = _stage2Req && !isStage2; 3097728SAli.Saidi@ARM.com 31011517SCurtis.Dunham@arm.com bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 31111517SCurtis.Dunham@arm.com longDescFormatInUse(currState->tc); 31210037SARM gem5 Developers 31310037SARM gem5 Developers if (long_desc_format) { 31410037SARM gem5 Developers // Helper variables used for hierarchical permissions 31510037SARM gem5 Developers currState->secureLookup = currState->isSecure; 31610037SARM gem5 Developers currState->rwTable = true; 31710037SARM gem5 Developers currState->userTable = true; 31810037SARM gem5 Developers currState->xnTable = false; 31910037SARM gem5 Developers currState->pxnTable = false; 32010621SCurtis.Dunham@arm.com 32110621SCurtis.Dunham@arm.com ++statWalksLongDescriptor; 32210621SCurtis.Dunham@arm.com } else { 32310621SCurtis.Dunham@arm.com ++statWalksShortDescriptor; 32410037SARM gem5 Developers } 32510037SARM gem5 Developers 32610037SARM gem5 Developers if (!currState->timing) { 32710109SGeoffrey.Blake@arm.com Fault fault = NoFault; 32810037SARM gem5 Developers if (currState->aarch64) 32910109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 33010037SARM gem5 Developers else if (long_desc_format) 33110109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 33210037SARM gem5 Developers else 33310109SGeoffrey.Blake@arm.com fault = processWalk(); 33410109SGeoffrey.Blake@arm.com 33510109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 33610109SGeoffrey.Blake@arm.com // how we found it. 33710109SGeoffrey.Blake@arm.com if (currState->functional) { 33810109SGeoffrey.Blake@arm.com delete currState; 33910109SGeoffrey.Blake@arm.com currState = savedCurrState; 34010109SGeoffrey.Blake@arm.com } 34110109SGeoffrey.Blake@arm.com return fault; 34210037SARM gem5 Developers } 3437728SAli.Saidi@ARM.com 3448067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 3457728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 3467728SAli.Saidi@ARM.com currState = NULL; 34710621SCurtis.Dunham@arm.com pendingChange(); 3487728SAli.Saidi@ARM.com } else { 3497728SAli.Saidi@ARM.com pending = true; 35010621SCurtis.Dunham@arm.com pendingChange(); 35110037SARM gem5 Developers if (currState->aarch64) 35210037SARM gem5 Developers return processWalkAArch64(); 35310037SARM gem5 Developers else if (long_desc_format) 35410037SARM gem5 Developers return processWalkLPAE(); 35510037SARM gem5 Developers else 35610037SARM gem5 Developers return processWalk(); 3577728SAli.Saidi@ARM.com } 3587728SAli.Saidi@ARM.com 3597728SAli.Saidi@ARM.com return NoFault; 3607728SAli.Saidi@ARM.com} 3617728SAli.Saidi@ARM.com 3627728SAli.Saidi@ARM.comvoid 3637728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3647728SAli.Saidi@ARM.com{ 3657728SAli.Saidi@ARM.com assert(!currState); 3667728SAli.Saidi@ARM.com assert(pendingQueue.size()); 36710621SCurtis.Dunham@arm.com pendingChange(); 3687728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3699258SAli.Saidi@ARM.com 3709535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 37110037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 37210037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 37310037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 37412735Sandreas.sandberg@arm.com currState->el); 3759258SAli.Saidi@ARM.com 3769535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3779535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3789535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3799535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3809535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3819535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3829258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3839258SAli.Saidi@ARM.com pending = true; 3849258SAli.Saidi@ARM.com pendingQueue.pop_front(); 38510579SAndrew.Bardsley@arm.com // Keep currState in case one of the processWalk... calls NULLs it 38610579SAndrew.Bardsley@arm.com WalkerState *curr_state_copy = currState; 38710579SAndrew.Bardsley@arm.com Fault f; 38810037SARM gem5 Developers if (currState->aarch64) 38910579SAndrew.Bardsley@arm.com f = processWalkAArch64(); 39011517SCurtis.Dunham@arm.com else if (longDescFormatInUse(currState->tc) || 39111517SCurtis.Dunham@arm.com currState->isHyp || isStage2) 39210579SAndrew.Bardsley@arm.com f = processWalkLPAE(); 39310037SARM gem5 Developers else 39410579SAndrew.Bardsley@arm.com f = processWalk(); 39510579SAndrew.Bardsley@arm.com 39610579SAndrew.Bardsley@arm.com if (f != NoFault) { 39710579SAndrew.Bardsley@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 39810579SAndrew.Bardsley@arm.com curr_state_copy->tc, curr_state_copy->mode); 39910579SAndrew.Bardsley@arm.com 40010579SAndrew.Bardsley@arm.com delete curr_state_copy; 40110579SAndrew.Bardsley@arm.com } 4029258SAli.Saidi@ARM.com return; 4039258SAli.Saidi@ARM.com } 4049258SAli.Saidi@ARM.com 4059258SAli.Saidi@ARM.com 4069258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 4079258SAli.Saidi@ARM.com // squashed we shouldn't bother. 4089258SAli.Saidi@ARM.com unsigned num_squashed = 0; 4099258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 4109258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 4119535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 4129258SAli.Saidi@ARM.com pendingQueue.pop_front(); 4139258SAli.Saidi@ARM.com num_squashed++; 41410621SCurtis.Dunham@arm.com statSquashedBefore++; 4159258SAli.Saidi@ARM.com 41610037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 41710037SARM gem5 Developers currState->vaddr_tainted); 4189258SAli.Saidi@ARM.com 4199535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 4209535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 42110474Sandreas.hansson@arm.com currState->transState->finish( 42210474Sandreas.hansson@arm.com std::make_shared<UnimpFault>("Squashed Inst"), 42310474Sandreas.hansson@arm.com currState->req, currState->tc, currState->mode); 4249535Smrinmoy.ghosh@arm.com } else { 4259535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 42610621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 42710037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 42810037SARM gem5 Developers currState->transState, currState->mode); 42910037SARM gem5 Developers 4309535Smrinmoy.ghosh@arm.com } 4319258SAli.Saidi@ARM.com 4329258SAli.Saidi@ARM.com // delete the current request 4339258SAli.Saidi@ARM.com delete currState; 4349258SAli.Saidi@ARM.com 4359258SAli.Saidi@ARM.com // peak at the next one 4369535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 4379258SAli.Saidi@ARM.com currState = pendingQueue.front(); 43810037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 43910037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 44012735Sandreas.sandberg@arm.com false, currState->el); 4419535Smrinmoy.ghosh@arm.com } else { 4429535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 4439258SAli.Saidi@ARM.com currState = NULL; 4449535Smrinmoy.ghosh@arm.com } 4459258SAli.Saidi@ARM.com } 44610621SCurtis.Dunham@arm.com pendingChange(); 4479258SAli.Saidi@ARM.com 44810621SCurtis.Dunham@arm.com // if we still have pending translations, schedule more work 4499258SAli.Saidi@ARM.com nextWalk(tc); 4509258SAli.Saidi@ARM.com currState = NULL; 4517728SAli.Saidi@ARM.com} 4527728SAli.Saidi@ARM.com 4537728SAli.Saidi@ARM.comFault 4547728SAli.Saidi@ARM.comTableWalker::processWalk() 4557728SAli.Saidi@ARM.com{ 4567404SAli.Saidi@ARM.com Addr ttbr = 0; 4577404SAli.Saidi@ARM.com 4587404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 45910037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 4607404SAli.Saidi@ARM.com 46110037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 46210037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 46310037SARM gem5 Developers 32 - currState->ttbcr.n)); 4647406SAli.Saidi@ARM.com 46510621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 46610621SCurtis.Dunham@arm.com 46710037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 46810037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4697406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 47010037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 47110037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 47210037SARM gem5 Developers if (currState->isFetch) 47310474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 47410474Sandreas.hansson@arm.com currState->vaddr_tainted, 47510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 47610474Sandreas.hansson@arm.com isStage2, 47710474Sandreas.hansson@arm.com ArmFault::VmsaTran); 47810037SARM gem5 Developers else 47910474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 48010474Sandreas.hansson@arm.com currState->vaddr_tainted, 48110474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 48210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 48310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 48410037SARM gem5 Developers } 48512499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 48610037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4877404SAli.Saidi@ARM.com } else { 4887406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 48910037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 49010037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 49110037SARM gem5 Developers if (currState->isFetch) 49210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 49310474Sandreas.hansson@arm.com currState->vaddr_tainted, 49410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 49510474Sandreas.hansson@arm.com isStage2, 49610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49710037SARM gem5 Developers else 49810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 49910474Sandreas.hansson@arm.com currState->vaddr_tainted, 50010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 50110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 50210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 50310037SARM gem5 Developers } 50412499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 50510037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 50610037SARM gem5 Developers currState->ttbcr.n = 0; 5077404SAli.Saidi@ARM.com } 5087404SAli.Saidi@ARM.com 50910037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 51010037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 51110037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 51210037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 5137404SAli.Saidi@ARM.com 5147404SAli.Saidi@ARM.com // Trickbox address check 5157439Sdam.sunwoo@arm.com Fault f; 51611395Sandreas.sandberg@arm.com f = testWalk(l1desc_addr, sizeof(uint32_t), 51711395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, L1); 5187439Sdam.sunwoo@arm.com if (f) { 51910037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5207579Sminkyu.jeong@arm.com if (currState->timing) { 5217728SAli.Saidi@ARM.com pending = false; 5227728SAli.Saidi@ARM.com nextWalk(currState->tc); 5237579Sminkyu.jeong@arm.com currState = NULL; 5247579Sminkyu.jeong@arm.com } else { 5257579Sminkyu.jeong@arm.com currState->tc = NULL; 5267579Sminkyu.jeong@arm.com currState->req = NULL; 5277579Sminkyu.jeong@arm.com } 5287579Sminkyu.jeong@arm.com return f; 5297404SAli.Saidi@ARM.com } 5307404SAli.Saidi@ARM.com 53110836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 5327946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 53310836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 5347946SGiacomo.Gabrielli@arm.com } 5357946SGiacomo.Gabrielli@arm.com 53611181Snathananel.premillieu@arm.com if (currState->isSecure) { 53711181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 53811181Snathananel.premillieu@arm.com } 53911181Snathananel.premillieu@arm.com 54010037SARM gem5 Developers bool delayed; 54110037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 54210037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 54310037SARM gem5 Developers &TableWalker::doL1Descriptor); 54410037SARM gem5 Developers if (!delayed) { 54510037SARM gem5 Developers f = currState->fault; 54610037SARM gem5 Developers } 54710037SARM gem5 Developers 54810037SARM gem5 Developers return f; 54910037SARM gem5 Developers} 55010037SARM gem5 Developers 55110037SARM gem5 DevelopersFault 55210037SARM gem5 DevelopersTableWalker::processWalkLPAE() 55310037SARM gem5 Developers{ 55410037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 55510037SARM gem5 Developers int tsz, n; 55610037SARM gem5 Developers LookupLevel start_lookup_level = L1; 55710037SARM gem5 Developers 55810037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 55910037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 56010037SARM gem5 Developers 56110621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 56210621SCurtis.Dunham@arm.com 56310836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 56410037SARM gem5 Developers if (currState->isSecure) 56510037SARM gem5 Developers flag.set(Request::SECURE); 56610037SARM gem5 Developers 56710037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 56810037SARM gem5 Developers // use HTTBR 56910037SARM gem5 Developers if (isStage2) { 57010037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 57110037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 57210037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 57310037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 57410037SARM gem5 Developers } else if (currState->isHyp) { 57510037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 57610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 57710037SARM gem5 Developers tsz = currState->htcr.t0sz; 57810037SARM gem5 Developers } else { 57911517SCurtis.Dunham@arm.com assert(longDescFormatInUse(currState->tc)); 58010037SARM gem5 Developers 58110037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 58210037SARM gem5 Developers if (currState->ttbcr.t0sz) 58310037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 58410037SARM gem5 Developers else if (currState->ttbcr.t1sz) 58510037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 58610037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 58710037SARM gem5 Developers else 58810037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 58910037SARM gem5 Developers if (currState->ttbcr.t1sz) 59010037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 59110037SARM gem5 Developers else 59210037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 59310037SARM gem5 Developers 59410037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 59510037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 59610037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 59710037SARM gem5 Developers // ARM issue C B3.6.4) 59810037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 59910037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 60010037SARM gem5 Developers // Check if table walk is allowed 60110037SARM gem5 Developers if (currState->ttbcr.epd0) { 60210037SARM gem5 Developers if (currState->isFetch) 60310474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 60410474Sandreas.hansson@arm.com currState->vaddr_tainted, 60510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60610474Sandreas.hansson@arm.com isStage2, 60710474Sandreas.hansson@arm.com ArmFault::LpaeTran); 60810037SARM gem5 Developers else 60910474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 61010474Sandreas.hansson@arm.com currState->vaddr_tainted, 61110474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 61210474Sandreas.hansson@arm.com currState->isWrite, 61310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 61410474Sandreas.hansson@arm.com isStage2, 61510474Sandreas.hansson@arm.com ArmFault::LpaeTran); 61610037SARM gem5 Developers } 61712499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 61810037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 61910037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 62010037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 62110037SARM gem5 Developers start_lookup_level = L2; 62210037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 62310037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 62410037SARM gem5 Developers // Check if table walk is allowed 62510037SARM gem5 Developers if (currState->ttbcr.epd1) { 62610037SARM gem5 Developers if (currState->isFetch) 62710474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 62810474Sandreas.hansson@arm.com currState->vaddr_tainted, 62910474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63010474Sandreas.hansson@arm.com isStage2, 63110474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63210037SARM gem5 Developers else 63310474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 63410474Sandreas.hansson@arm.com currState->vaddr_tainted, 63510474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 63610474Sandreas.hansson@arm.com currState->isWrite, 63710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63810474Sandreas.hansson@arm.com isStage2, 63910474Sandreas.hansson@arm.com ArmFault::LpaeTran); 64010037SARM gem5 Developers } 64112499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 64210037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 64310037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 64410037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 64510037SARM gem5 Developers start_lookup_level = L2; 64610037SARM gem5 Developers } else { 64710037SARM gem5 Developers // Out of boundaries -> translation fault 64810037SARM gem5 Developers if (currState->isFetch) 64910474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 65010474Sandreas.hansson@arm.com currState->vaddr_tainted, 65110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 65210474Sandreas.hansson@arm.com isStage2, 65310474Sandreas.hansson@arm.com ArmFault::LpaeTran); 65410037SARM gem5 Developers else 65510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65610474Sandreas.hansson@arm.com currState->vaddr_tainted, 65710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 65810474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 65910474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 66010037SARM gem5 Developers } 66110037SARM gem5 Developers 66210037SARM gem5 Developers } 66310037SARM gem5 Developers 66410037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 66510037SARM gem5 Developers if (start_lookup_level == L1) { 66610037SARM gem5 Developers n = 5 - tsz; 66710037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 66810037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 66910037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67010037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67110037SARM gem5 Developers } else { 67210037SARM gem5 Developers // Skip first-level lookup 67310037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 67410037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 67510037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 67610037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67710037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67810037SARM gem5 Developers } 67910037SARM gem5 Developers 68010037SARM gem5 Developers // Trickbox address check 68111395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 68211395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 68310037SARM gem5 Developers if (f) { 68410037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 68510037SARM gem5 Developers if (currState->timing) { 68610037SARM gem5 Developers pending = false; 68710037SARM gem5 Developers nextWalk(currState->tc); 68810037SARM gem5 Developers currState = NULL; 68910037SARM gem5 Developers } else { 69010037SARM gem5 Developers currState->tc = NULL; 69110037SARM gem5 Developers currState->req = NULL; 69210037SARM gem5 Developers } 69310037SARM gem5 Developers return f; 69410037SARM gem5 Developers } 69510037SARM gem5 Developers 69610037SARM gem5 Developers if (currState->sctlr.c == 0) { 69710836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 69810037SARM gem5 Developers } 69910037SARM gem5 Developers 70010037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 70110037SARM gem5 Developers currState->longDesc.aarch64 = false; 70210324SCurtis.Dunham@arm.com currState->longDesc.grainSize = Grain4KB; 70310037SARM gem5 Developers 70410037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70510037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 70611588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], 70711588SCurtis.Dunham@arm.com &TableWalker::doLongDescriptor); 70810037SARM gem5 Developers if (!delayed) { 70910037SARM gem5 Developers f = currState->fault; 71010037SARM gem5 Developers } 71110037SARM gem5 Developers 71210037SARM gem5 Developers return f; 71310037SARM gem5 Developers} 71410037SARM gem5 Developers 71510037SARM gem5 Developersunsigned 71610037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 71710037SARM gem5 Developers{ 71810037SARM gem5 Developers if (tsz < 25) 71910037SARM gem5 Developers return 25; 72010037SARM gem5 Developers if (tsz > 48) 72110037SARM gem5 Developers return 48; 72210037SARM gem5 Developers return tsz; 72310037SARM gem5 Developers} 72410037SARM gem5 Developers 72510037SARM gem5 Developersbool 72610037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 72710037SARM gem5 Developers{ 72810037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 72910037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 73010037SARM gem5 Developers} 73110037SARM gem5 Developers 73210037SARM gem5 DevelopersFault 73310037SARM gem5 DevelopersTableWalker::processWalkAArch64() 73410037SARM gem5 Developers{ 73510037SARM gem5 Developers assert(currState->aarch64); 73610037SARM gem5 Developers 73710324SCurtis.Dunham@arm.com DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 73810324SCurtis.Dunham@arm.com currState->vaddr_tainted, currState->tcr); 73910324SCurtis.Dunham@arm.com 74012709Sgiacomo.travaglini@arm.com static const GrainSize GrainMap_tg0[] = 74110324SCurtis.Dunham@arm.com { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 74212709Sgiacomo.travaglini@arm.com static const GrainSize GrainMap_tg1[] = 74310324SCurtis.Dunham@arm.com { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 74410037SARM gem5 Developers 74510621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 74610621SCurtis.Dunham@arm.com 74710037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 74810037SARM gem5 Developers Addr ttbr = 0; 74910037SARM gem5 Developers int tsz = 0, ps = 0; 75010324SCurtis.Dunham@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 75110037SARM gem5 Developers bool fault = false; 75211575SDylan.Johnson@ARM.com 75311575SDylan.Johnson@ARM.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 75411575SDylan.Johnson@ARM.com 75510037SARM gem5 Developers switch (currState->el) { 75610037SARM gem5 Developers case EL0: 75710037SARM gem5 Developers case EL1: 75811575SDylan.Johnson@ARM.com if (isStage2) { 75911575SDylan.Johnson@ARM.com DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 76011575SDylan.Johnson@ARM.com ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 76111575SDylan.Johnson@ARM.com tsz = 64 - currState->vtcr.t0sz64; 76212709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->vtcr.tg0]; 76311575SDylan.Johnson@ARM.com // ARM DDI 0487A.f D7-2148 76411575SDylan.Johnson@ARM.com // The starting level of stage 2 translation depends on 76511575SDylan.Johnson@ARM.com // VTCR_EL2.SL0 and VTCR_EL2.TG0 76611575SDylan.Johnson@ARM.com LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 76711575SDylan.Johnson@ARM.com uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 76811575SDylan.Johnson@ARM.com static const LookupLevel SLL[] = { 76911575SDylan.Johnson@ARM.com L2, L3, L3, __, // sl0 == 0 77011575SDylan.Johnson@ARM.com L1, L2, L2, __, // sl0 == 1, etc. 77111575SDylan.Johnson@ARM.com L0, L1, L1, __, 77211575SDylan.Johnson@ARM.com __, __, __, __ 77311575SDylan.Johnson@ARM.com }; 77411575SDylan.Johnson@ARM.com start_lookup_level = SLL[sl_tg]; 77511575SDylan.Johnson@ARM.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 77611575SDylan.Johnson@ARM.com "Cannot discern lookup level from vtcr.{sl0,tg0}"); 77713019Sanouk.vanlaer@arm.com ps = currState->vtcr.ps; 77813019Sanouk.vanlaer@arm.com } else { 77913019Sanouk.vanlaer@arm.com switch (bits(currState->vaddr, 63,48)) { 78013019Sanouk.vanlaer@arm.com case 0: 78113019Sanouk.vanlaer@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 78213019Sanouk.vanlaer@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 78313019Sanouk.vanlaer@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 78413019Sanouk.vanlaer@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 78514095Sgiacomo.travaglini@arm.com currState->hpd = currState->tcr.hpd0; 78613019Sanouk.vanlaer@arm.com if (bits(currState->vaddr, 63, tsz) != 0x0 || 78713019Sanouk.vanlaer@arm.com currState->tcr.epd0) 78813019Sanouk.vanlaer@arm.com fault = true; 78913019Sanouk.vanlaer@arm.com break; 79013019Sanouk.vanlaer@arm.com case 0xffff: 79113019Sanouk.vanlaer@arm.com DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 79213019Sanouk.vanlaer@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 79313019Sanouk.vanlaer@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 79413019Sanouk.vanlaer@arm.com tg = GrainMap_tg1[currState->tcr.tg1]; 79514095Sgiacomo.travaglini@arm.com currState->hpd = currState->tcr.hpd1; 79613019Sanouk.vanlaer@arm.com if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 79713019Sanouk.vanlaer@arm.com currState->tcr.epd1) 79813019Sanouk.vanlaer@arm.com fault = true; 79913019Sanouk.vanlaer@arm.com break; 80013019Sanouk.vanlaer@arm.com default: 80113019Sanouk.vanlaer@arm.com // top two bytes must be all 0s or all 1s, else invalid addr 80213019Sanouk.vanlaer@arm.com fault = true; 80313019Sanouk.vanlaer@arm.com } 80413019Sanouk.vanlaer@arm.com ps = currState->tcr.ips; 80510037SARM gem5 Developers } 80610037SARM gem5 Developers break; 80710037SARM gem5 Developers case EL2: 80812709Sgiacomo.travaglini@arm.com switch(bits(currState->vaddr, 63,48)) { 80912709Sgiacomo.travaglini@arm.com case 0: 81012709Sgiacomo.travaglini@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 81112709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 81212709Sgiacomo.travaglini@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 81312709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 81414095Sgiacomo.travaglini@arm.com currState->hpd = currState->hcr.e2h ? 81514095Sgiacomo.travaglini@arm.com currState->tcr.hpd0 : currState->tcr.hpd; 81612709Sgiacomo.travaglini@arm.com break; 81712709Sgiacomo.travaglini@arm.com 81812709Sgiacomo.travaglini@arm.com case 0xffff: 81912709Sgiacomo.travaglini@arm.com DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 82012709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2); 82112709Sgiacomo.travaglini@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 82212709Sgiacomo.travaglini@arm.com tg = GrainMap_tg1[currState->tcr.tg1]; 82314095Sgiacomo.travaglini@arm.com currState->hpd = currState->tcr.hpd1; 82412709Sgiacomo.travaglini@arm.com if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 82512709Sgiacomo.travaglini@arm.com currState->tcr.epd1 || !currState->hcr.e2h) 82612709Sgiacomo.travaglini@arm.com fault = true; 82712709Sgiacomo.travaglini@arm.com break; 82812709Sgiacomo.travaglini@arm.com 82912709Sgiacomo.travaglini@arm.com default: 83012709Sgiacomo.travaglini@arm.com // invalid addr if top two bytes are not all 0s 83112709Sgiacomo.travaglini@arm.com fault = true; 83212709Sgiacomo.travaglini@arm.com } 83313018Sanouk.vanlaer@arm.com ps = currState->tcr.ps; 83412709Sgiacomo.travaglini@arm.com break; 83510037SARM gem5 Developers case EL3: 83610037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 83710037SARM gem5 Developers case 0: 83810324SCurtis.Dunham@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 83912709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 84010324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 84112709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 84214095Sgiacomo.travaglini@arm.com currState->hpd = currState->tcr.hpd; 84310037SARM gem5 Developers break; 84410037SARM gem5 Developers default: 84510037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 84610324SCurtis.Dunham@arm.com fault = true; 84710037SARM gem5 Developers } 84813018Sanouk.vanlaer@arm.com ps = currState->tcr.ps; 84910037SARM gem5 Developers break; 85010037SARM gem5 Developers } 85110037SARM gem5 Developers 85210037SARM gem5 Developers if (fault) { 85310037SARM gem5 Developers Fault f; 85410037SARM gem5 Developers if (currState->isFetch) 85510474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 85610474Sandreas.hansson@arm.com currState->vaddr_tainted, 85710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 85810474Sandreas.hansson@arm.com ArmFault::LpaeTran); 85910037SARM gem5 Developers else 86010474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 86110474Sandreas.hansson@arm.com currState->vaddr_tainted, 86210474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 86310474Sandreas.hansson@arm.com currState->isWrite, 86410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, 86510474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 86610037SARM gem5 Developers 86710037SARM gem5 Developers if (currState->timing) { 86810037SARM gem5 Developers pending = false; 86910037SARM gem5 Developers nextWalk(currState->tc); 87010037SARM gem5 Developers currState = NULL; 87110037SARM gem5 Developers } else { 87210037SARM gem5 Developers currState->tc = NULL; 87310037SARM gem5 Developers currState->req = NULL; 87410037SARM gem5 Developers } 87510037SARM gem5 Developers return f; 87610037SARM gem5 Developers 87710037SARM gem5 Developers } 87810037SARM gem5 Developers 87910324SCurtis.Dunham@arm.com if (tg == ReservedGrain) { 88010324SCurtis.Dunham@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 88110324SCurtis.Dunham@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 88210324SCurtis.Dunham@arm.com tg = Grain4KB; 88310324SCurtis.Dunham@arm.com } 88410324SCurtis.Dunham@arm.com 88510037SARM gem5 Developers // Determine starting lookup level 88610324SCurtis.Dunham@arm.com // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 88710324SCurtis.Dunham@arm.com // in ARM DDI 0487A. These table values correspond to the cascading tests 88810324SCurtis.Dunham@arm.com // to compute the lookup level and are of the form 88910324SCurtis.Dunham@arm.com // (grain_size + N*stride), for N = {1, 2, 3}. 89010324SCurtis.Dunham@arm.com // A value of 64 will never succeed and a value of 0 will always succeed. 89111575SDylan.Johnson@ARM.com if (start_lookup_level == MAX_LOOKUP_LEVELS) { 89210324SCurtis.Dunham@arm.com struct GrainMap { 89310324SCurtis.Dunham@arm.com GrainSize grain_size; 89410324SCurtis.Dunham@arm.com unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 89510324SCurtis.Dunham@arm.com }; 89610324SCurtis.Dunham@arm.com static const GrainMap GM[] = { 89710324SCurtis.Dunham@arm.com { Grain4KB, { 39, 30, 0, 0 } }, 89810324SCurtis.Dunham@arm.com { Grain16KB, { 47, 36, 25, 0 } }, 89910324SCurtis.Dunham@arm.com { Grain64KB, { 64, 42, 29, 0 } } 90010324SCurtis.Dunham@arm.com }; 90110324SCurtis.Dunham@arm.com 90210324SCurtis.Dunham@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 90310324SCurtis.Dunham@arm.com 90410324SCurtis.Dunham@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 90510324SCurtis.Dunham@arm.com if (tg == GM[i].grain_size) { 90610324SCurtis.Dunham@arm.com lookup = GM[i].lookup_level_cutoff; 90710324SCurtis.Dunham@arm.com break; 90810324SCurtis.Dunham@arm.com } 90910324SCurtis.Dunham@arm.com } 91010324SCurtis.Dunham@arm.com assert(lookup); 91110324SCurtis.Dunham@arm.com 91210324SCurtis.Dunham@arm.com for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 91310324SCurtis.Dunham@arm.com if (tsz > lookup[L]) { 91410324SCurtis.Dunham@arm.com start_lookup_level = (LookupLevel) L; 91510324SCurtis.Dunham@arm.com break; 91610324SCurtis.Dunham@arm.com } 91710324SCurtis.Dunham@arm.com } 91810324SCurtis.Dunham@arm.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 91910324SCurtis.Dunham@arm.com "Table walker couldn't find lookup level\n"); 92010037SARM gem5 Developers } 92110037SARM gem5 Developers 92211575SDylan.Johnson@ARM.com int stride = tg - 3; 92311575SDylan.Johnson@ARM.com 92410037SARM gem5 Developers // Determine table base address 92510324SCurtis.Dunham@arm.com int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 92610037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 92710037SARM gem5 Developers 92810037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 92910037SARM gem5 Developers // necessary 93010037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 93110037SARM gem5 Developers // Clamp to lower limit 93210037SARM gem5 Developers if (pa_range > physAddrRange) 93310037SARM gem5 Developers currState->physAddrRange = physAddrRange; 93410037SARM gem5 Developers else 93510037SARM gem5 Developers currState->physAddrRange = pa_range; 93610037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 93710037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 93810037SARM gem5 Developers Fault f; 93910037SARM gem5 Developers if (currState->isFetch) 94010474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 94110474Sandreas.hansson@arm.com currState->vaddr_tainted, 94210474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 94310474Sandreas.hansson@arm.com isStage2, 94410474Sandreas.hansson@arm.com ArmFault::LpaeTran); 94510037SARM gem5 Developers else 94610474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 94710474Sandreas.hansson@arm.com currState->vaddr_tainted, 94810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 94910474Sandreas.hansson@arm.com currState->isWrite, 95010474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 95110474Sandreas.hansson@arm.com isStage2, 95210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 95310037SARM gem5 Developers 95410037SARM gem5 Developers 95510037SARM gem5 Developers if (currState->timing) { 95610037SARM gem5 Developers pending = false; 95710037SARM gem5 Developers nextWalk(currState->tc); 95810037SARM gem5 Developers currState = NULL; 95910037SARM gem5 Developers } else { 96010037SARM gem5 Developers currState->tc = NULL; 96110037SARM gem5 Developers currState->req = NULL; 96210037SARM gem5 Developers } 96310037SARM gem5 Developers return f; 96410037SARM gem5 Developers 96510037SARM gem5 Developers } 96610037SARM gem5 Developers 96710037SARM gem5 Developers // Determine descriptor address 96810037SARM gem5 Developers Addr desc_addr = base_addr | 96910037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 97010324SCurtis.Dunham@arm.com stride * (3 - start_lookup_level) + tg) << 3); 97110037SARM gem5 Developers 97210037SARM gem5 Developers // Trickbox address check 97311395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 97411395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 97510037SARM gem5 Developers if (f) { 97610037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 97710037SARM gem5 Developers if (currState->timing) { 97810037SARM gem5 Developers pending = false; 97910037SARM gem5 Developers nextWalk(currState->tc); 98010037SARM gem5 Developers currState = NULL; 98110037SARM gem5 Developers } else { 98210037SARM gem5 Developers currState->tc = NULL; 98310037SARM gem5 Developers currState->req = NULL; 98410037SARM gem5 Developers } 98510037SARM gem5 Developers return f; 98610037SARM gem5 Developers } 98710037SARM gem5 Developers 98810836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 98910037SARM gem5 Developers if (currState->sctlr.c == 0) { 99010836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 99110037SARM gem5 Developers } 99210037SARM gem5 Developers 99311181Snathananel.premillieu@arm.com if (currState->isSecure) { 99411181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 99511181Snathananel.premillieu@arm.com } 99611181Snathananel.premillieu@arm.com 99710037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 99810037SARM gem5 Developers currState->longDesc.aarch64 = true; 99910324SCurtis.Dunham@arm.com currState->longDesc.grainSize = tg; 100010037SARM gem5 Developers 10017439Sdam.sunwoo@arm.com if (currState->timing) { 100211588SCurtis.Dunham@arm.com fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data, 100311588SCurtis.Dunham@arm.com sizeof(uint64_t), flag, start_lookup_level, 100411588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], NULL); 100511579SDylan.Johnson@ARM.com } else { 100611575SDylan.Johnson@ARM.com fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 100711575SDylan.Johnson@ARM.com sizeof(uint64_t), flag, -1, NULL, 100811575SDylan.Johnson@ARM.com &TableWalker::doLongDescriptor); 10097439Sdam.sunwoo@arm.com f = currState->fault; 10107404SAli.Saidi@ARM.com } 10117404SAli.Saidi@ARM.com 10127439Sdam.sunwoo@arm.com return f; 10137404SAli.Saidi@ARM.com} 10147404SAli.Saidi@ARM.com 10157404SAli.Saidi@ARM.comvoid 10167439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 10177439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 10187404SAli.Saidi@ARM.com{ 10197439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 10207439Sdam.sunwoo@arm.com // variables 10217436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 10227436Sdam.sunwoo@arm.com te.shareable = false; // default value 10237582SAli.Saidi@arm.com te.nonCacheable = false; 102410037SARM gem5 Developers te.outerShareable = false; 10257439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 10267404SAli.Saidi@ARM.com switch(texcb) { 10277436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 10287404SAli.Saidi@ARM.com te.nonCacheable = true; 102910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 10307436Sdam.sunwoo@arm.com te.shareable = true; 10317436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10337404SAli.Saidi@ARM.com break; 10347436Sdam.sunwoo@arm.com case 1: // Shareable Device 10357436Sdam.sunwoo@arm.com te.nonCacheable = true; 103610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10377436Sdam.sunwoo@arm.com te.shareable = true; 10387436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10397436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10407436Sdam.sunwoo@arm.com break; 10417436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 104210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10437436Sdam.sunwoo@arm.com te.shareable = s; 10447436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10457436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10467436Sdam.sunwoo@arm.com break; 10477436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 104810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10497436Sdam.sunwoo@arm.com te.shareable = s; 10507436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10517436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10527436Sdam.sunwoo@arm.com break; 10537436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 10547436Sdam.sunwoo@arm.com te.nonCacheable = true; 105510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10567436Sdam.sunwoo@arm.com te.shareable = s; 10577436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10587436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10597436Sdam.sunwoo@arm.com break; 10607436Sdam.sunwoo@arm.com case 5: // Reserved 10617439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10627436Sdam.sunwoo@arm.com break; 10637436Sdam.sunwoo@arm.com case 6: // Implementation Defined 10647439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 10657436Sdam.sunwoo@arm.com break; 10667436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 106710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10687436Sdam.sunwoo@arm.com te.shareable = s; 10697436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10707436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10717436Sdam.sunwoo@arm.com break; 10727436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 10737436Sdam.sunwoo@arm.com te.nonCacheable = true; 107410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10757436Sdam.sunwoo@arm.com te.shareable = false; 10767436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10777436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10787436Sdam.sunwoo@arm.com break; 10797436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 10807439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10817436Sdam.sunwoo@arm.com break; 10827436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 108310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10847436Sdam.sunwoo@arm.com te.shareable = s; 10857404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 10867404SAli.Saidi@ARM.com te.nonCacheable = true; 10877436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 10887436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 10897404SAli.Saidi@ARM.com break; 10907436Sdam.sunwoo@arm.com default: 10917436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 10927404SAli.Saidi@ARM.com } 10937404SAli.Saidi@ARM.com } else { 10947438SAli.Saidi@ARM.com assert(tc); 109512499Sgiacomo.travaglini@arm.com PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, 109610037SARM gem5 Developers currState->tc, !currState->isSecure)); 109712499Sgiacomo.travaglini@arm.com NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, 109810037SARM gem5 Developers currState->tc, !currState->isSecure)); 10997436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 11007582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 11017404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 11027404SAli.Saidi@ARM.com case 0: 11037436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 11047436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 11057436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 110610037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 11077404SAli.Saidi@ARM.com break; 11087404SAli.Saidi@ARM.com case 1: 11097436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 11107436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 11117436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 111210037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 11137404SAli.Saidi@ARM.com break; 11147404SAli.Saidi@ARM.com case 2: 11157436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 11167436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 11177436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 111810037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 11197404SAli.Saidi@ARM.com break; 11207404SAli.Saidi@ARM.com case 3: 11217436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 11227436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 11237436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 112410037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 11257404SAli.Saidi@ARM.com break; 11267404SAli.Saidi@ARM.com case 4: 11277436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 11287436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 11297436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 113010037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 11317404SAli.Saidi@ARM.com break; 11327404SAli.Saidi@ARM.com case 5: 11337436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 11347436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 11357436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 113610037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 11377404SAli.Saidi@ARM.com break; 11387404SAli.Saidi@ARM.com case 6: 11397404SAli.Saidi@ARM.com panic("Imp defined type\n"); 11407404SAli.Saidi@ARM.com case 7: 11417436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 11427436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 11437436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 114410037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 11457404SAli.Saidi@ARM.com break; 11467404SAli.Saidi@ARM.com } 11477436Sdam.sunwoo@arm.com 11487436Sdam.sunwoo@arm.com switch(curr_tr) { 11497436Sdam.sunwoo@arm.com case 0: 11507436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 115110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 11527436Sdam.sunwoo@arm.com te.nonCacheable = true; 11537436Sdam.sunwoo@arm.com te.innerAttrs = 1; 11547436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11557436Sdam.sunwoo@arm.com te.shareable = true; 11567436Sdam.sunwoo@arm.com break; 11577436Sdam.sunwoo@arm.com case 1: 11587436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 11597436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 116010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 11617436Sdam.sunwoo@arm.com te.nonCacheable = true; 11627436Sdam.sunwoo@arm.com te.innerAttrs = 3; 11637436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11647436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 11657436Sdam.sunwoo@arm.com te.shareable = true; 11667436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 11677436Sdam.sunwoo@arm.com te.shareable = true; 11687436Sdam.sunwoo@arm.com break; 11697436Sdam.sunwoo@arm.com case 2: 11707436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 11717436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 117210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 11737436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 11747436Sdam.sunwoo@arm.com te.shareable = true; 11757436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 11767436Sdam.sunwoo@arm.com te.shareable = true; 11777436Sdam.sunwoo@arm.com break; 11787436Sdam.sunwoo@arm.com case 3: 11797436Sdam.sunwoo@arm.com panic("Reserved type"); 11807436Sdam.sunwoo@arm.com } 11817436Sdam.sunwoo@arm.com 118210037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 11837436Sdam.sunwoo@arm.com switch(curr_ir) { 11847436Sdam.sunwoo@arm.com case 0: 11857436Sdam.sunwoo@arm.com te.nonCacheable = true; 11867436Sdam.sunwoo@arm.com te.innerAttrs = 0; 11877436Sdam.sunwoo@arm.com break; 11887436Sdam.sunwoo@arm.com case 1: 11897436Sdam.sunwoo@arm.com te.innerAttrs = 5; 11907436Sdam.sunwoo@arm.com break; 11917436Sdam.sunwoo@arm.com case 2: 11927436Sdam.sunwoo@arm.com te.innerAttrs = 6; 11937436Sdam.sunwoo@arm.com break; 11947436Sdam.sunwoo@arm.com case 3: 11957436Sdam.sunwoo@arm.com te.innerAttrs = 7; 11967436Sdam.sunwoo@arm.com break; 11977436Sdam.sunwoo@arm.com } 11987436Sdam.sunwoo@arm.com 11997436Sdam.sunwoo@arm.com switch(curr_or) { 12007436Sdam.sunwoo@arm.com case 0: 12017436Sdam.sunwoo@arm.com te.nonCacheable = true; 12027436Sdam.sunwoo@arm.com te.outerAttrs = 0; 12037436Sdam.sunwoo@arm.com break; 12047436Sdam.sunwoo@arm.com case 1: 12057436Sdam.sunwoo@arm.com te.outerAttrs = 1; 12067436Sdam.sunwoo@arm.com break; 12077436Sdam.sunwoo@arm.com case 2: 12087436Sdam.sunwoo@arm.com te.outerAttrs = 2; 12097436Sdam.sunwoo@arm.com break; 12107436Sdam.sunwoo@arm.com case 3: 12117436Sdam.sunwoo@arm.com te.outerAttrs = 3; 12127436Sdam.sunwoo@arm.com break; 12137436Sdam.sunwoo@arm.com } 12147436Sdam.sunwoo@arm.com } 12157404SAli.Saidi@ARM.com } 121610367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 121710367SAndrew.Bardsley@arm.com "outerAttrs: %d\n", 12187439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 121910037SARM gem5 Developers te.setAttributes(false); 122010037SARM gem5 Developers} 12217436Sdam.sunwoo@arm.com 122210037SARM gem5 Developersvoid 122310037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 122410037SARM gem5 Developers LongDescriptor &lDescriptor) 122510037SARM gem5 Developers{ 122610037SARM gem5 Developers assert(_haveLPAE); 12277436Sdam.sunwoo@arm.com 122810037SARM gem5 Developers uint8_t attr; 122910037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 123010037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 123110037SARM gem5 Developers // translation 123210037SARM gem5 Developers if (isStage2) { 123310037SARM gem5 Developers attr = lDescriptor.memAttr(); 123410037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 123510037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 12367436Sdam.sunwoo@arm.com 123710037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 123810037SARM gem5 Developers 123910037SARM gem5 Developers if (attr_3_2 == 0) { 124010037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 124110037SARM gem5 Developers : TlbEntry::MemoryType::Device; 124210037SARM gem5 Developers te.outerAttrs = 0; 124310037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 124410037SARM gem5 Developers te.nonCacheable = true; 124510037SARM gem5 Developers } else { 124610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 124710037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 124810037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 124910037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 125010037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 125110037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 125210037SARM gem5 Developers } 125310037SARM gem5 Developers } else { 125410037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 125510037SARM gem5 Developers 125610037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 125710037SARM gem5 Developers // value of SCTLR.TRE 125810421Sandreas.hansson@arm.com MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 125912499Sgiacomo.travaglini@arm.com int reg_as_int = snsBankedIndex(reg, currState->tc, 126012499Sgiacomo.travaglini@arm.com !currState->isSecure); 126110421Sandreas.hansson@arm.com uint32_t mair = currState->tc->readMiscReg(reg_as_int); 126210037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 126310037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 126410037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 126510037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 126610037SARM gem5 Developers 126710037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 126810037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 126910037SARM gem5 Developers // accordingly to provide the illusion of full support 127010037SARM gem5 Developers te.nonCacheable = false; 127110037SARM gem5 Developers 127210037SARM gem5 Developers switch (attr_7_4) { 127310037SARM gem5 Developers case 0x0: 127410037SARM gem5 Developers // Strongly-ordered or Device memory 127510037SARM gem5 Developers if (attr_3_0 == 0x0) 127610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 127710037SARM gem5 Developers else if (attr_3_0 == 0x4) 127810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 127910037SARM gem5 Developers else 128010037SARM gem5 Developers panic("Unpredictable behavior\n"); 128110037SARM gem5 Developers te.nonCacheable = true; 128210037SARM gem5 Developers te.outerAttrs = 0; 128310037SARM gem5 Developers break; 128410037SARM gem5 Developers case 0x4: 128510037SARM gem5 Developers // Normal memory, Outer Non-cacheable 128610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 128710037SARM gem5 Developers te.outerAttrs = 0; 128810037SARM gem5 Developers if (attr_3_0 == 0x4) 128910037SARM gem5 Developers // Inner Non-cacheable 129010037SARM gem5 Developers te.nonCacheable = true; 129110037SARM gem5 Developers else if (attr_3_0 < 0x8) 129210037SARM gem5 Developers panic("Unpredictable behavior\n"); 129310037SARM gem5 Developers break; 129410037SARM gem5 Developers case 0x8: 129510037SARM gem5 Developers case 0x9: 129610037SARM gem5 Developers case 0xa: 129710037SARM gem5 Developers case 0xb: 129810037SARM gem5 Developers case 0xc: 129910037SARM gem5 Developers case 0xd: 130010037SARM gem5 Developers case 0xe: 130110037SARM gem5 Developers case 0xf: 130210037SARM gem5 Developers if (attr_7_4 & 0x4) { 130310037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 130410037SARM gem5 Developers } else { 130510037SARM gem5 Developers te.outerAttrs = 0x2; 130610037SARM gem5 Developers } 130710037SARM gem5 Developers // Normal memory, Outer Cacheable 130810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 130910037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 131010037SARM gem5 Developers panic("Unpredictable behavior\n"); 131110037SARM gem5 Developers break; 131210037SARM gem5 Developers default: 131310037SARM gem5 Developers panic("Unpredictable behavior\n"); 131410037SARM gem5 Developers break; 131510037SARM gem5 Developers } 131610037SARM gem5 Developers 131710037SARM gem5 Developers switch (attr_3_0) { 131810037SARM gem5 Developers case 0x0: 131910037SARM gem5 Developers te.innerAttrs = 0x1; 132010037SARM gem5 Developers break; 132110037SARM gem5 Developers case 0x4: 132210037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 132310037SARM gem5 Developers break; 132410037SARM gem5 Developers case 0x8: 132510037SARM gem5 Developers case 0x9: 132610037SARM gem5 Developers case 0xA: 132710037SARM gem5 Developers case 0xB: 132810037SARM gem5 Developers te.innerAttrs = 6; 132910037SARM gem5 Developers break; 133010037SARM gem5 Developers case 0xC: 133110037SARM gem5 Developers case 0xD: 133210037SARM gem5 Developers case 0xE: 133310037SARM gem5 Developers case 0xF: 133410037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 133510037SARM gem5 Developers break; 133610037SARM gem5 Developers default: 133710037SARM gem5 Developers panic("Unpredictable behavior\n"); 133810037SARM gem5 Developers break; 133910037SARM gem5 Developers } 134010037SARM gem5 Developers } 134110037SARM gem5 Developers 134210037SARM gem5 Developers te.outerShareable = sh == 2; 134310037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 134410037SARM gem5 Developers te.setAttributes(true); 134510037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 134610037SARM gem5 Developers} 134710037SARM gem5 Developers 134810037SARM gem5 Developersvoid 134911583SDylan.Johnson@ARM.comTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, 135011583SDylan.Johnson@ARM.com LongDescriptor &lDescriptor) 135110037SARM gem5 Developers{ 135211583SDylan.Johnson@ARM.com uint8_t attr; 135311583SDylan.Johnson@ARM.com uint8_t attr_hi; 135411583SDylan.Johnson@ARM.com uint8_t attr_lo; 135511583SDylan.Johnson@ARM.com uint8_t sh = lDescriptor.sh(); 135610037SARM gem5 Developers 135711583SDylan.Johnson@ARM.com if (isStage2) { 135811583SDylan.Johnson@ARM.com attr = lDescriptor.memAttr(); 135911583SDylan.Johnson@ARM.com uint8_t attr_hi = (attr >> 2) & 0x3; 136011583SDylan.Johnson@ARM.com uint8_t attr_lo = attr & 0x3; 136111583SDylan.Johnson@ARM.com 136211583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh); 136311583SDylan.Johnson@ARM.com 136411583SDylan.Johnson@ARM.com if (attr_hi == 0) { 136511583SDylan.Johnson@ARM.com te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered 136611583SDylan.Johnson@ARM.com : TlbEntry::MemoryType::Device; 136711583SDylan.Johnson@ARM.com te.outerAttrs = 0; 136811583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 0 ? 1 : 3; 136911583SDylan.Johnson@ARM.com te.nonCacheable = true; 137011583SDylan.Johnson@ARM.com } else { 137111583SDylan.Johnson@ARM.com te.mtype = TlbEntry::MemoryType::Normal; 137211583SDylan.Johnson@ARM.com te.outerAttrs = attr_hi == 1 ? 0 : 137311583SDylan.Johnson@ARM.com attr_hi == 2 ? 2 : 1; 137411583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 1 ? 0 : 137511583SDylan.Johnson@ARM.com attr_lo == 2 ? 6 : 5; 137611938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 137711938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 137811938Snikos.nikoleris@arm.com te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) || 137911938Snikos.nikoleris@arm.com (attr_lo == 1) || (attr_lo == 2); 138011583SDylan.Johnson@ARM.com } 138111583SDylan.Johnson@ARM.com } else { 138211583SDylan.Johnson@ARM.com uint8_t attrIndx = lDescriptor.attrIndx(); 138311583SDylan.Johnson@ARM.com 138411583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 138511583SDylan.Johnson@ARM.com 138611583SDylan.Johnson@ARM.com // Select MAIR 138711583SDylan.Johnson@ARM.com uint64_t mair; 138811583SDylan.Johnson@ARM.com switch (currState->el) { 138911583SDylan.Johnson@ARM.com case EL0: 139011583SDylan.Johnson@ARM.com case EL1: 139111583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL1); 139211583SDylan.Johnson@ARM.com break; 139311583SDylan.Johnson@ARM.com case EL2: 139411583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL2); 139511583SDylan.Johnson@ARM.com break; 139611583SDylan.Johnson@ARM.com case EL3: 139711583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL3); 139811583SDylan.Johnson@ARM.com break; 139911583SDylan.Johnson@ARM.com default: 140011583SDylan.Johnson@ARM.com panic("Invalid exception level"); 140111583SDylan.Johnson@ARM.com break; 140211583SDylan.Johnson@ARM.com } 140311583SDylan.Johnson@ARM.com 140411583SDylan.Johnson@ARM.com // Select attributes 140511583SDylan.Johnson@ARM.com attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 140611583SDylan.Johnson@ARM.com attr_lo = bits(attr, 3, 0); 140711583SDylan.Johnson@ARM.com attr_hi = bits(attr, 7, 4); 140811583SDylan.Johnson@ARM.com 140911583SDylan.Johnson@ARM.com // Memory type 141011583SDylan.Johnson@ARM.com te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 141111583SDylan.Johnson@ARM.com 141211583SDylan.Johnson@ARM.com // Cacheability 141311583SDylan.Johnson@ARM.com te.nonCacheable = false; 141411938Snikos.nikoleris@arm.com if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory 141511938Snikos.nikoleris@arm.com te.nonCacheable = true; 141611938Snikos.nikoleris@arm.com } 141711938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 141811938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 141911938Snikos.nikoleris@arm.com switch (attr_hi) { 142011938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 142111938Snikos.nikoleris@arm.com case 0x4: // Normal memory, Outer Non-cacheable 142211938Snikos.nikoleris@arm.com case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 142311938Snikos.nikoleris@arm.com te.nonCacheable = true; 142411938Snikos.nikoleris@arm.com } 142511938Snikos.nikoleris@arm.com switch (attr_lo) { 142611938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 142711938Snikos.nikoleris@arm.com case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 142811938Snikos.nikoleris@arm.com warn_if(!attr_hi, "Unpredictable behavior"); 142912392Sjason@lowepower.com M5_FALLTHROUGH; 143011938Snikos.nikoleris@arm.com case 0x4: // Device-nGnRE memory or 143111938Snikos.nikoleris@arm.com // Normal memory, Inner Non-cacheable 143211938Snikos.nikoleris@arm.com case 0x8: // Device-nGRE memory or 143311938Snikos.nikoleris@arm.com // Normal memory, Inner Write-through non-transient 143411583SDylan.Johnson@ARM.com te.nonCacheable = true; 143511583SDylan.Johnson@ARM.com } 143611583SDylan.Johnson@ARM.com 143711583SDylan.Johnson@ARM.com te.shareable = sh == 2; 143811583SDylan.Johnson@ARM.com te.outerShareable = (sh & 0x2) ? true : false; 143911583SDylan.Johnson@ARM.com // Attributes formatted according to the 64-bit PAR 144011583SDylan.Johnson@ARM.com te.attributes = ((uint64_t) attr << 56) | 144111583SDylan.Johnson@ARM.com (1 << 11) | // LPAE bit 144211583SDylan.Johnson@ARM.com (te.ns << 9) | // NS bit 144311583SDylan.Johnson@ARM.com (sh << 7); 144410037SARM gem5 Developers } 14457404SAli.Saidi@ARM.com} 14467404SAli.Saidi@ARM.com 14477404SAli.Saidi@ARM.comvoid 14487404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 14497404SAli.Saidi@ARM.com{ 145010037SARM gem5 Developers if (currState->fault != NoFault) { 145110037SARM gem5 Developers return; 145210037SARM gem5 Developers } 145310037SARM gem5 Developers 145412526Schuan.zhu@arm.com currState->l1Desc.data = htog(currState->l1Desc.data, 145512526Schuan.zhu@arm.com byteOrder(currState->tc)); 145612526Schuan.zhu@arm.com 14577439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 145810037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 14597404SAli.Saidi@ARM.com TlbEntry te; 14607404SAli.Saidi@ARM.com 14617439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 14627404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 14637404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 14647946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 14657439Sdam.sunwoo@arm.com currState->tc = NULL; 14667439Sdam.sunwoo@arm.com currState->req = NULL; 14677437Sdam.sunwoo@arm.com } 14687406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 14697439Sdam.sunwoo@arm.com if (currState->isFetch) 14707439Sdam.sunwoo@arm.com currState->fault = 147110474Sandreas.hansson@arm.com std::make_shared<PrefetchAbort>( 147210474Sandreas.hansson@arm.com currState->vaddr_tainted, 147310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 147410474Sandreas.hansson@arm.com isStage2, 147510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14767406SAli.Saidi@ARM.com else 14777439Sdam.sunwoo@arm.com currState->fault = 147810474Sandreas.hansson@arm.com std::make_shared<DataAbort>( 147910474Sandreas.hansson@arm.com currState->vaddr_tainted, 148010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 148110474Sandreas.hansson@arm.com currState->isWrite, 148210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 148310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14847404SAli.Saidi@ARM.com return; 14857404SAli.Saidi@ARM.com case L1Descriptor::Section: 14867439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 14877436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 14887436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 14897436Sdam.sunwoo@arm.com * AccessFlag0 14907436Sdam.sunwoo@arm.com */ 14917436Sdam.sunwoo@arm.com 149210474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 149310474Sandreas.hansson@arm.com currState->vaddr_tainted, 149410474Sandreas.hansson@arm.com currState->l1Desc.domain(), 149510474Sandreas.hansson@arm.com currState->isWrite, 149610474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L1, 149710474Sandreas.hansson@arm.com isStage2, 149810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14997436Sdam.sunwoo@arm.com } 15007439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 15017404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 15027404SAli.Saidi@ARM.com } 150310037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 150410037SARM gem5 Developers return; 150510037SARM gem5 Developers case L1Descriptor::PageTable: 150610037SARM gem5 Developers { 150710037SARM gem5 Developers Addr l2desc_addr; 150810037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 150910037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 151010037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 151110037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 15127404SAli.Saidi@ARM.com 151310037SARM gem5 Developers // Trickbox address check 151411395Sandreas.sandberg@arm.com currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 151511395Sandreas.sandberg@arm.com currState->l1Desc.domain(), L2); 15167404SAli.Saidi@ARM.com 151710037SARM gem5 Developers if (currState->fault) { 151810037SARM gem5 Developers if (!currState->timing) { 151910037SARM gem5 Developers currState->tc = NULL; 152010037SARM gem5 Developers currState->req = NULL; 152110037SARM gem5 Developers } 152210037SARM gem5 Developers return; 152310037SARM gem5 Developers } 152410037SARM gem5 Developers 152510836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 152610037SARM gem5 Developers if (currState->isSecure) 152710037SARM gem5 Developers flag.set(Request::SECURE); 152810037SARM gem5 Developers 152910037SARM gem5 Developers bool delayed; 153010037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 153110037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 153210037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 153310037SARM gem5 Developers &TableWalker::doL2Descriptor); 153410037SARM gem5 Developers if (delayed) { 153510037SARM gem5 Developers currState->delayed = true; 153610037SARM gem5 Developers } 153710037SARM gem5 Developers 153810037SARM gem5 Developers return; 153910037SARM gem5 Developers } 154010037SARM gem5 Developers default: 154110037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 154210037SARM gem5 Developers } 154310037SARM gem5 Developers} 154410037SARM gem5 Developers 154514093Sgiacomo.travaglini@arm.comFault 154614093Sgiacomo.travaglini@arm.comTableWalker::generateLongDescFault(ArmFault::FaultSource src) 154714093Sgiacomo.travaglini@arm.com{ 154814093Sgiacomo.travaglini@arm.com if (currState->isFetch) { 154914093Sgiacomo.travaglini@arm.com return std::make_shared<PrefetchAbort>( 155014093Sgiacomo.travaglini@arm.com currState->vaddr_tainted, 155114093Sgiacomo.travaglini@arm.com src + currState->longDesc.lookupLevel, 155214093Sgiacomo.travaglini@arm.com isStage2, 155314093Sgiacomo.travaglini@arm.com ArmFault::LpaeTran); 155414093Sgiacomo.travaglini@arm.com } else { 155514093Sgiacomo.travaglini@arm.com return std::make_shared<DataAbort>( 155614093Sgiacomo.travaglini@arm.com currState->vaddr_tainted, 155714093Sgiacomo.travaglini@arm.com TlbEntry::DomainType::NoAccess, 155814093Sgiacomo.travaglini@arm.com currState->isWrite, 155914093Sgiacomo.travaglini@arm.com src + currState->longDesc.lookupLevel, 156014093Sgiacomo.travaglini@arm.com isStage2, 156114093Sgiacomo.travaglini@arm.com ArmFault::LpaeTran); 156214093Sgiacomo.travaglini@arm.com } 156314093Sgiacomo.travaglini@arm.com} 156414093Sgiacomo.travaglini@arm.com 156510037SARM gem5 Developersvoid 156610037SARM gem5 DevelopersTableWalker::doLongDescriptor() 156710037SARM gem5 Developers{ 156810037SARM gem5 Developers if (currState->fault != NoFault) { 156910037SARM gem5 Developers return; 157010037SARM gem5 Developers } 157110037SARM gem5 Developers 157212526Schuan.zhu@arm.com currState->longDesc.data = htog(currState->longDesc.data, 157312526Schuan.zhu@arm.com byteOrder(currState->tc)); 157412526Schuan.zhu@arm.com 157510037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 157610037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 157710037SARM gem5 Developers currState->longDesc.data, 157810037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 157910037SARM gem5 Developers 158010037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 158110037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 158210037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 158310037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 158410037SARM gem5 Developers currState->longDesc.lookupLevel, 158510037SARM gem5 Developers currState->longDesc.data, 158610037SARM gem5 Developers currState->longDesc.pxn(), 158710037SARM gem5 Developers currState->longDesc.xn(), 158810037SARM gem5 Developers currState->longDesc.ap(), 158910037SARM gem5 Developers currState->longDesc.af(), 159010037SARM gem5 Developers currState->longDesc.type()); 159110037SARM gem5 Developers } else { 159210037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 159310037SARM gem5 Developers currState->longDesc.lookupLevel, 159410037SARM gem5 Developers currState->longDesc.data, 159510037SARM gem5 Developers currState->longDesc.type()); 159610037SARM gem5 Developers } 159710037SARM gem5 Developers 159810037SARM gem5 Developers TlbEntry te; 159910037SARM gem5 Developers 160010037SARM gem5 Developers switch (currState->longDesc.type()) { 160110037SARM gem5 Developers case LongDescriptor::Invalid: 16027439Sdam.sunwoo@arm.com if (!currState->timing) { 16037439Sdam.sunwoo@arm.com currState->tc = NULL; 16047439Sdam.sunwoo@arm.com currState->req = NULL; 16057437Sdam.sunwoo@arm.com } 16067404SAli.Saidi@ARM.com 160710037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 160810037SARM gem5 Developers currState->longDesc.lookupLevel, 160910037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 161014093Sgiacomo.travaglini@arm.com 161114093Sgiacomo.travaglini@arm.com currState->fault = generateLongDescFault(ArmFault::TranslationLL); 16127404SAli.Saidi@ARM.com return; 161314093Sgiacomo.travaglini@arm.com 161410037SARM gem5 Developers case LongDescriptor::Block: 161510037SARM gem5 Developers case LongDescriptor::Page: 161610037SARM gem5 Developers { 161714093Sgiacomo.travaglini@arm.com auto fault_source = ArmFault::FaultSourceInvalid; 161810037SARM gem5 Developers // Check for address size fault 161910037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 162010037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 162110037SARM gem5 Developers currState->longDesc.offsetBits()), 162210037SARM gem5 Developers currState->physAddrRange)) { 162314093Sgiacomo.travaglini@arm.com 162410037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 162510037SARM gem5 Developers currState->longDesc.lookupLevel); 162614093Sgiacomo.travaglini@arm.com fault_source = ArmFault::AddressSizeLL; 162714093Sgiacomo.travaglini@arm.com 162810037SARM gem5 Developers // Check for access fault 162910037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 163014093Sgiacomo.travaglini@arm.com 163110037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 163210037SARM gem5 Developers currState->longDesc.lookupLevel); 163314093Sgiacomo.travaglini@arm.com fault_source = ArmFault::AccessFlagLL; 163410037SARM gem5 Developers } 163514093Sgiacomo.travaglini@arm.com 163614093Sgiacomo.travaglini@arm.com if (fault_source != ArmFault::FaultSourceInvalid) { 163714093Sgiacomo.travaglini@arm.com currState->fault = generateLongDescFault(fault_source); 163810037SARM gem5 Developers } else { 163910037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 164010037SARM gem5 Developers } 164110037SARM gem5 Developers } 164210037SARM gem5 Developers return; 164310037SARM gem5 Developers case LongDescriptor::Table: 164410037SARM gem5 Developers { 164510037SARM gem5 Developers // Set hierarchical permission flags 164610037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 164710037SARM gem5 Developers currState->longDesc.secureTable(); 164810037SARM gem5 Developers currState->rwTable = currState->rwTable && 164914095Sgiacomo.travaglini@arm.com (currState->longDesc.rwTable() || currState->hpd); 165010037SARM gem5 Developers currState->userTable = currState->userTable && 165114095Sgiacomo.travaglini@arm.com (currState->longDesc.userTable() || currState->hpd); 165210037SARM gem5 Developers currState->xnTable = currState->xnTable || 165314095Sgiacomo.travaglini@arm.com (currState->longDesc.xnTable() && !currState->hpd); 165410037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 165514095Sgiacomo.travaglini@arm.com (currState->longDesc.pxnTable() && !currState->hpd); 16567404SAli.Saidi@ARM.com 165710037SARM gem5 Developers // Set up next level lookup 165810037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 165910037SARM gem5 Developers currState->vaddr); 16607439Sdam.sunwoo@arm.com 166110037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 166210037SARM gem5 Developers currState->longDesc.lookupLevel, 166310037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 166410037SARM gem5 Developers next_desc_addr, 166510037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 166610037SARM gem5 Developers 166710037SARM gem5 Developers // Check for address size fault 166810037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 166910037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 167010037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 167110037SARM gem5 Developers currState->longDesc.lookupLevel); 167214093Sgiacomo.travaglini@arm.com 167314093Sgiacomo.travaglini@arm.com currState->fault = generateLongDescFault( 167414093Sgiacomo.travaglini@arm.com ArmFault::AddressSizeLL); 167510037SARM gem5 Developers return; 16767437Sdam.sunwoo@arm.com } 16777404SAli.Saidi@ARM.com 167810037SARM gem5 Developers // Trickbox address check 167911395Sandreas.sandberg@arm.com currState->fault = testWalk( 168011395Sandreas.sandberg@arm.com next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 168111395Sandreas.sandberg@arm.com toLookupLevel(currState->longDesc.lookupLevel +1)); 16827404SAli.Saidi@ARM.com 168310037SARM gem5 Developers if (currState->fault) { 168410037SARM gem5 Developers if (!currState->timing) { 168510037SARM gem5 Developers currState->tc = NULL; 168610037SARM gem5 Developers currState->req = NULL; 168710037SARM gem5 Developers } 168810037SARM gem5 Developers return; 168910037SARM gem5 Developers } 169010037SARM gem5 Developers 169110836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 169210037SARM gem5 Developers if (currState->secureLookup) 169310037SARM gem5 Developers flag.set(Request::SECURE); 169410037SARM gem5 Developers 169511588SCurtis.Dunham@arm.com LookupLevel L = currState->longDesc.lookupLevel = 169610037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 169710037SARM gem5 Developers Event *event = NULL; 169811588SCurtis.Dunham@arm.com switch (L) { 169910037SARM gem5 Developers case L1: 170010037SARM gem5 Developers assert(currState->aarch64); 170110037SARM gem5 Developers case L2: 170210037SARM gem5 Developers case L3: 170311588SCurtis.Dunham@arm.com event = LongDescEventByLevel[L]; 170410037SARM gem5 Developers break; 170510037SARM gem5 Developers default: 170610037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 170710037SARM gem5 Developers break; 170810037SARM gem5 Developers } 170910037SARM gem5 Developers 171010037SARM gem5 Developers bool delayed; 171110037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 171210037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 171310037SARM gem5 Developers &TableWalker::doLongDescriptor); 171410037SARM gem5 Developers if (delayed) { 171510037SARM gem5 Developers currState->delayed = true; 171610037SARM gem5 Developers } 17177404SAli.Saidi@ARM.com } 17187404SAli.Saidi@ARM.com return; 17197404SAli.Saidi@ARM.com default: 17207404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 17217404SAli.Saidi@ARM.com } 17227404SAli.Saidi@ARM.com} 17237404SAli.Saidi@ARM.com 17247404SAli.Saidi@ARM.comvoid 17257404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 17267404SAli.Saidi@ARM.com{ 172710037SARM gem5 Developers if (currState->fault != NoFault) { 172810037SARM gem5 Developers return; 172910037SARM gem5 Developers } 173010037SARM gem5 Developers 173112526Schuan.zhu@arm.com currState->l2Desc.data = htog(currState->l2Desc.data, 173212526Schuan.zhu@arm.com byteOrder(currState->tc)); 173312526Schuan.zhu@arm.com 17347439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 173510037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 17367404SAli.Saidi@ARM.com TlbEntry te; 17377404SAli.Saidi@ARM.com 17387439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 17397404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 17407946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 17417439Sdam.sunwoo@arm.com currState->tc = NULL; 17427439Sdam.sunwoo@arm.com currState->req = NULL; 17437437Sdam.sunwoo@arm.com } 17447439Sdam.sunwoo@arm.com if (currState->isFetch) 174510474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 174610474Sandreas.hansson@arm.com currState->vaddr_tainted, 174710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L2, 174810474Sandreas.hansson@arm.com isStage2, 174910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17507406SAli.Saidi@ARM.com else 175110474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 175210474Sandreas.hansson@arm.com currState->vaddr_tainted, currState->l1Desc.domain(), 175310474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L2, 175410474Sandreas.hansson@arm.com isStage2, 175510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17567404SAli.Saidi@ARM.com return; 17577404SAli.Saidi@ARM.com } 17587404SAli.Saidi@ARM.com 17597439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 17607436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 17617436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 17627436Sdam.sunwoo@arm.com */ 176310037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 176410037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 17657436Sdam.sunwoo@arm.com 176610474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 176710474Sandreas.hansson@arm.com currState->vaddr_tainted, 176810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 176910474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L2, isStage2, 177010474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17717436Sdam.sunwoo@arm.com } 17727436Sdam.sunwoo@arm.com 177310037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 17747437Sdam.sunwoo@arm.com} 17757437Sdam.sunwoo@arm.com 17767437Sdam.sunwoo@arm.comvoid 17777437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 17787437Sdam.sunwoo@arm.com{ 177910037SARM gem5 Developers currState = stateQueues[L1].front(); 17807439Sdam.sunwoo@arm.com currState->delayed = false; 178110037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 178210037SARM gem5 Developers if (currState->stage2Tran) { 178310037SARM gem5 Developers delete currState->stage2Tran; 178410037SARM gem5 Developers currState->stage2Tran = NULL; 178510037SARM gem5 Developers } 178610037SARM gem5 Developers 17877437Sdam.sunwoo@arm.com 17887578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 17897578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 17907578Sdam.sunwoo@arm.com 179110037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 17927437Sdam.sunwoo@arm.com doL1Descriptor(); 17937437Sdam.sunwoo@arm.com 179410037SARM gem5 Developers stateQueues[L1].pop_front(); 17957437Sdam.sunwoo@arm.com // Check if fault was generated 17967439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 17977439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 17987439Sdam.sunwoo@arm.com currState->tc, currState->mode); 179910621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 18007437Sdam.sunwoo@arm.com 18017728SAli.Saidi@ARM.com pending = false; 18027728SAli.Saidi@ARM.com nextWalk(currState->tc); 18037728SAli.Saidi@ARM.com 18047439Sdam.sunwoo@arm.com currState->req = NULL; 18057439Sdam.sunwoo@arm.com currState->tc = NULL; 18067439Sdam.sunwoo@arm.com currState->delayed = false; 18078510SAli.Saidi@ARM.com delete currState; 18087437Sdam.sunwoo@arm.com } 18097439Sdam.sunwoo@arm.com else if (!currState->delayed) { 18107653Sgene.wu@arm.com // delay is not set so there is no L2 to do 181110037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 181212738Sandreas.sandberg@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 181312738Sandreas.sandberg@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 181412738Sandreas.sandberg@arm.com tlb->translateTiming(currState->req, currState->tc, 181512738Sandreas.sandberg@arm.com currState->transState, currState->mode); 181612738Sandreas.sandberg@arm.com statWalksShortTerminatedAtLevel[0]++; 18177437Sdam.sunwoo@arm.com 18187728SAli.Saidi@ARM.com pending = false; 18197728SAli.Saidi@ARM.com nextWalk(currState->tc); 18207728SAli.Saidi@ARM.com 18217439Sdam.sunwoo@arm.com currState->req = NULL; 18227439Sdam.sunwoo@arm.com currState->tc = NULL; 18237439Sdam.sunwoo@arm.com currState->delayed = false; 18247653Sgene.wu@arm.com delete currState; 18257653Sgene.wu@arm.com } else { 18267653Sgene.wu@arm.com // need to do L2 descriptor 182710037SARM gem5 Developers stateQueues[L2].push_back(currState); 18287437Sdam.sunwoo@arm.com } 18297439Sdam.sunwoo@arm.com currState = NULL; 18307437Sdam.sunwoo@arm.com} 18317437Sdam.sunwoo@arm.com 18327437Sdam.sunwoo@arm.comvoid 18337437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 18347437Sdam.sunwoo@arm.com{ 183510037SARM gem5 Developers currState = stateQueues[L2].front(); 18367439Sdam.sunwoo@arm.com assert(currState->delayed); 183710037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 183810037SARM gem5 Developers if (currState->stage2Tran) { 183910037SARM gem5 Developers delete currState->stage2Tran; 184010037SARM gem5 Developers currState->stage2Tran = NULL; 184110037SARM gem5 Developers } 18427437Sdam.sunwoo@arm.com 18437439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 184410037SARM gem5 Developers currState->vaddr_tainted); 18457437Sdam.sunwoo@arm.com doL2Descriptor(); 18467437Sdam.sunwoo@arm.com 18477437Sdam.sunwoo@arm.com // Check if fault was generated 18487439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18497439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18507439Sdam.sunwoo@arm.com currState->tc, currState->mode); 185110621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 185212738Sandreas.sandberg@arm.com } else { 185312738Sandreas.sandberg@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 185412738Sandreas.sandberg@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 185512738Sandreas.sandberg@arm.com tlb->translateTiming(currState->req, currState->tc, 185612738Sandreas.sandberg@arm.com currState->transState, currState->mode); 185712738Sandreas.sandberg@arm.com statWalksShortTerminatedAtLevel[1]++; 18587437Sdam.sunwoo@arm.com } 18597437Sdam.sunwoo@arm.com 18607728SAli.Saidi@ARM.com 186110037SARM gem5 Developers stateQueues[L2].pop_front(); 18627728SAli.Saidi@ARM.com pending = false; 18637728SAli.Saidi@ARM.com nextWalk(currState->tc); 18647728SAli.Saidi@ARM.com 18657439Sdam.sunwoo@arm.com currState->req = NULL; 18667439Sdam.sunwoo@arm.com currState->tc = NULL; 18677439Sdam.sunwoo@arm.com currState->delayed = false; 18687439Sdam.sunwoo@arm.com 18697653Sgene.wu@arm.com delete currState; 18707439Sdam.sunwoo@arm.com currState = NULL; 18717404SAli.Saidi@ARM.com} 18727404SAli.Saidi@ARM.com 18737728SAli.Saidi@ARM.comvoid 187410037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 187510037SARM gem5 Developers{ 187610037SARM gem5 Developers doLongDescriptorWrapper(L0); 187710037SARM gem5 Developers} 187810037SARM gem5 Developers 187910037SARM gem5 Developersvoid 188010037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 188110037SARM gem5 Developers{ 188210037SARM gem5 Developers doLongDescriptorWrapper(L1); 188310037SARM gem5 Developers} 188410037SARM gem5 Developers 188510037SARM gem5 Developersvoid 188610037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 188710037SARM gem5 Developers{ 188810037SARM gem5 Developers doLongDescriptorWrapper(L2); 188910037SARM gem5 Developers} 189010037SARM gem5 Developers 189110037SARM gem5 Developersvoid 189210037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 189310037SARM gem5 Developers{ 189410037SARM gem5 Developers doLongDescriptorWrapper(L3); 189510037SARM gem5 Developers} 189610037SARM gem5 Developers 189710037SARM gem5 Developersvoid 189810037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 189910037SARM gem5 Developers{ 190010037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 190110037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 190210037SARM gem5 Developers currState->delayed = false; 190310037SARM gem5 Developers 190410037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 190510037SARM gem5 Developers if (currState->stage2Tran) { 190610037SARM gem5 Developers delete currState->stage2Tran; 190710037SARM gem5 Developers currState->stage2Tran = NULL; 190810037SARM gem5 Developers } 190910037SARM gem5 Developers 191010037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 191110037SARM gem5 Developers currState->vaddr_tainted); 191210037SARM gem5 Developers doLongDescriptor(); 191310037SARM gem5 Developers 191410037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 191510037SARM gem5 Developers 191610037SARM gem5 Developers if (currState->fault != NoFault) { 191710037SARM gem5 Developers // A fault was generated 191810037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 191910037SARM gem5 Developers currState->tc, currState->mode); 192010037SARM gem5 Developers 192110037SARM gem5 Developers pending = false; 192210037SARM gem5 Developers nextWalk(currState->tc); 192310037SARM gem5 Developers 192410037SARM gem5 Developers currState->req = NULL; 192510037SARM gem5 Developers currState->tc = NULL; 192610037SARM gem5 Developers currState->delayed = false; 192710037SARM gem5 Developers delete currState; 192810037SARM gem5 Developers } else if (!currState->delayed) { 192910037SARM gem5 Developers // No additional lookups required 193012738Sandreas.sandberg@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 193112738Sandreas.sandberg@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 193212738Sandreas.sandberg@arm.com tlb->translateTiming(currState->req, currState->tc, 193312738Sandreas.sandberg@arm.com currState->transState, currState->mode); 193412738Sandreas.sandberg@arm.com statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 193510037SARM gem5 Developers 193610037SARM gem5 Developers pending = false; 193710037SARM gem5 Developers nextWalk(currState->tc); 193810037SARM gem5 Developers 193910037SARM gem5 Developers currState->req = NULL; 194010037SARM gem5 Developers currState->tc = NULL; 194110037SARM gem5 Developers currState->delayed = false; 194210037SARM gem5 Developers delete currState; 194310037SARM gem5 Developers } else { 194410037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 194510037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 194610037SARM gem5 Developers // Need to perform additional lookups 194710037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 194810037SARM gem5 Developers } 194910037SARM gem5 Developers currState = NULL; 195010037SARM gem5 Developers} 195110037SARM gem5 Developers 195210037SARM gem5 Developers 195310037SARM gem5 Developersvoid 19547728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 19557728SAli.Saidi@ARM.com{ 19567728SAli.Saidi@ARM.com if (pendingQueue.size()) 19579309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 195810509SAli.Saidi@ARM.com else 195910509SAli.Saidi@ARM.com completeDrain(); 19607728SAli.Saidi@ARM.com} 19617728SAli.Saidi@ARM.com 196210037SARM gem5 Developersbool 196310037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 196410037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 196510037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 196610037SARM gem5 Developers{ 196710037SARM gem5 Developers bool isTiming = currState->timing; 19687728SAli.Saidi@ARM.com 196911575SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 197011575SDylan.Johnson@ARM.com descAddr, currState->stage2Req); 197111575SDylan.Johnson@ARM.com 197211575SDylan.Johnson@ARM.com // If this translation has a stage 2 then we know descAddr is an IPA and 197311575SDylan.Johnson@ARM.com // needs to be translated before we can access the page table. Do that 197411575SDylan.Johnson@ARM.com // check here. 197510037SARM gem5 Developers if (currState->stage2Req) { 197610037SARM gem5 Developers Fault fault; 197710037SARM gem5 Developers flags = flags | TLB::MustBeOne; 197810037SARM gem5 Developers 197910037SARM gem5 Developers if (isTiming) { 198010037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 198110037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 198210037SARM gem5 Developers currState->vaddr); 198310037SARM gem5 Developers currState->stage2Tran = tran; 198410037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 198510717Sandreas.hansson@arm.com flags); 198610037SARM gem5 Developers fault = tran->fault; 198710037SARM gem5 Developers } else { 198810037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 198910717Sandreas.hansson@arm.com currState->vaddr, descAddr, data, numBytes, flags, 199010037SARM gem5 Developers currState->functional); 199110037SARM gem5 Developers } 199210037SARM gem5 Developers 199310037SARM gem5 Developers if (fault != NoFault) { 199410037SARM gem5 Developers currState->fault = fault; 199510037SARM gem5 Developers } 199610037SARM gem5 Developers if (isTiming) { 199710037SARM gem5 Developers if (queueIndex >= 0) { 199810037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 199910037SARM gem5 Developers stateQueues[queueIndex].size()); 200010037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 200110037SARM gem5 Developers currState = NULL; 200210037SARM gem5 Developers } 200310037SARM gem5 Developers } else { 200410037SARM gem5 Developers (this->*doDescriptor)(); 200510037SARM gem5 Developers } 200610037SARM gem5 Developers } else { 200710037SARM gem5 Developers if (isTiming) { 200810717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 200910621SCurtis.Dunham@arm.com currState->tc->getCpuPtr()->clockPeriod(),flags); 201010037SARM gem5 Developers if (queueIndex >= 0) { 201110037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 201210037SARM gem5 Developers stateQueues[queueIndex].size()); 201310037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 201410037SARM gem5 Developers currState = NULL; 201510037SARM gem5 Developers } 201610037SARM gem5 Developers } else if (!currState->functional) { 201710717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 201810037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 201910037SARM gem5 Developers (this->*doDescriptor)(); 202010037SARM gem5 Developers } else { 202112749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 202212749Sgiacomo.travaglini@arm.com descAddr, numBytes, flags, masterId); 202312749Sgiacomo.travaglini@arm.com 202410037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 202510037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 202610037SARM gem5 Developers pkt->dataStatic(data); 202710717Sandreas.hansson@arm.com port->sendFunctional(pkt); 202810037SARM gem5 Developers (this->*doDescriptor)(); 202910037SARM gem5 Developers delete pkt; 203010037SARM gem5 Developers } 203110037SARM gem5 Developers } 203210037SARM gem5 Developers return (isTiming); 203310037SARM gem5 Developers} 203410037SARM gem5 Developers 203510037SARM gem5 Developersvoid 203610037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 203710037SARM gem5 Developers{ 203810037SARM gem5 Developers TlbEntry te; 203910037SARM gem5 Developers 204010037SARM gem5 Developers // Create and fill a new page table entry 204110037SARM gem5 Developers te.valid = true; 204210037SARM gem5 Developers te.longDescFormat = longDescriptor; 204310037SARM gem5 Developers te.isHyp = currState->isHyp; 204410037SARM gem5 Developers te.asid = currState->asid; 204510037SARM gem5 Developers te.vmid = currState->vmid; 204610037SARM gem5 Developers te.N = descriptor.offsetBits(); 204710037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 204810037SARM gem5 Developers te.size = (1<<te.N) - 1; 204910037SARM gem5 Developers te.pfn = descriptor.pfn(); 205010037SARM gem5 Developers te.domain = descriptor.domain(); 205110037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 205210037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 205310037SARM gem5 Developers te.nstid = !currState->isSecure; 205410037SARM gem5 Developers te.xn = descriptor.xn(); 205510037SARM gem5 Developers if (currState->aarch64) 205610037SARM gem5 Developers te.el = currState->el; 205710037SARM gem5 Developers else 205814088Sgiacomo.travaglini@arm.com te.el = EL1; 205910037SARM gem5 Developers 206010621SCurtis.Dunham@arm.com statPageSizes[pageSizeNtoStatBin(te.N)]++; 206110621SCurtis.Dunham@arm.com statRequestOrigin[COMPLETED][currState->isFetch]++; 206210621SCurtis.Dunham@arm.com 206310037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 206410037SARM gem5 Developers // as global 206510037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 206610037SARM gem5 Developers if (longDescriptor) { 206710037SARM gem5 Developers LongDescriptor lDescriptor = 206810037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 206910037SARM gem5 Developers 207010037SARM gem5 Developers te.xn |= currState->xnTable; 207110037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 207210037SARM gem5 Developers if (isStage2) { 207310037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 207410037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 207510037SARM gem5 Developers te.hap = lDescriptor.ap(); 207610037SARM gem5 Developers } else { 207710037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 207810037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 207910037SARM gem5 Developers } 208010037SARM gem5 Developers if (currState->aarch64) 208111583SDylan.Johnson@ARM.com memAttrsAArch64(currState->tc, te, lDescriptor); 208210037SARM gem5 Developers else 208310037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 208410037SARM gem5 Developers } else { 208510037SARM gem5 Developers te.ap = descriptor.ap(); 208610037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 208710037SARM gem5 Developers descriptor.shareable()); 208810037SARM gem5 Developers } 208910037SARM gem5 Developers 209010037SARM gem5 Developers // Debug output 209110037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 209210037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 209310037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 209410037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 209510037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 209610037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 209710037SARM gem5 Developers te.nonCacheable, te.ns); 209810037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 209910037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 210010037SARM gem5 Developers descriptor.getRawData()); 210110037SARM gem5 Developers 210210037SARM gem5 Developers // Insert the entry into the TLB 210310037SARM gem5 Developers tlb->insert(currState->vaddr, te); 210410037SARM gem5 Developers if (!currState->timing) { 210510037SARM gem5 Developers currState->tc = NULL; 210610037SARM gem5 Developers currState->req = NULL; 210710037SARM gem5 Developers } 210810037SARM gem5 Developers} 21097728SAli.Saidi@ARM.com 21107404SAli.Saidi@ARM.comArmISA::TableWalker * 21117404SAli.Saidi@ARM.comArmTableWalkerParams::create() 21127404SAli.Saidi@ARM.com{ 21137404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 21147404SAli.Saidi@ARM.com} 21157404SAli.Saidi@ARM.com 211610037SARM gem5 DevelopersLookupLevel 211710037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 211810037SARM gem5 Developers{ 211910037SARM gem5 Developers switch (lookup_level_as_int) { 212010037SARM gem5 Developers case L1: 212110037SARM gem5 Developers return L1; 212210037SARM gem5 Developers case L2: 212310037SARM gem5 Developers return L2; 212410037SARM gem5 Developers case L3: 212510037SARM gem5 Developers return L3; 212610037SARM gem5 Developers default: 212710037SARM gem5 Developers panic("Invalid lookup level conversion"); 212810037SARM gem5 Developers } 212910037SARM gem5 Developers} 213010621SCurtis.Dunham@arm.com 213110621SCurtis.Dunham@arm.com/* this method keeps track of the table walker queue's residency, so 213210621SCurtis.Dunham@arm.com * needs to be called whenever requests start and complete. */ 213310621SCurtis.Dunham@arm.comvoid 213410621SCurtis.Dunham@arm.comTableWalker::pendingChange() 213510621SCurtis.Dunham@arm.com{ 213610621SCurtis.Dunham@arm.com unsigned n = pendingQueue.size(); 213710621SCurtis.Dunham@arm.com if ((currState != NULL) && (currState != pendingQueue.front())) { 213810621SCurtis.Dunham@arm.com ++n; 213910621SCurtis.Dunham@arm.com } 214010621SCurtis.Dunham@arm.com 214110621SCurtis.Dunham@arm.com if (n != pendingReqs) { 214210621SCurtis.Dunham@arm.com Tick now = curTick(); 214310621SCurtis.Dunham@arm.com statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 214410621SCurtis.Dunham@arm.com pendingReqs = n; 214510621SCurtis.Dunham@arm.com pendingChangeTick = now; 214610621SCurtis.Dunham@arm.com } 214710621SCurtis.Dunham@arm.com} 214810621SCurtis.Dunham@arm.com 214911395Sandreas.sandberg@arm.comFault 215011395Sandreas.sandberg@arm.comTableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 215111395Sandreas.sandberg@arm.com LookupLevel lookup_level) 215211395Sandreas.sandberg@arm.com{ 215311395Sandreas.sandberg@arm.com return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 215411395Sandreas.sandberg@arm.com currState->mode, domain, lookup_level); 215511395Sandreas.sandberg@arm.com} 215611395Sandreas.sandberg@arm.com 215711395Sandreas.sandberg@arm.com 215810621SCurtis.Dunham@arm.comuint8_t 215910621SCurtis.Dunham@arm.comTableWalker::pageSizeNtoStatBin(uint8_t N) 216010621SCurtis.Dunham@arm.com{ 216110621SCurtis.Dunham@arm.com /* for statPageSizes */ 216210621SCurtis.Dunham@arm.com switch(N) { 216310621SCurtis.Dunham@arm.com case 12: return 0; // 4K 216410621SCurtis.Dunham@arm.com case 14: return 1; // 16K (using 16K granule in v8-64) 216510621SCurtis.Dunham@arm.com case 16: return 2; // 64K 216610621SCurtis.Dunham@arm.com case 20: return 3; // 1M 216710621SCurtis.Dunham@arm.com case 21: return 4; // 2M-LPAE 216810621SCurtis.Dunham@arm.com case 24: return 5; // 16M 216910621SCurtis.Dunham@arm.com case 25: return 6; // 32M (using 16K granule in v8-64) 217010621SCurtis.Dunham@arm.com case 29: return 7; // 512M (using 64K granule in v8-64) 217110621SCurtis.Dunham@arm.com case 30: return 8; // 1G-LPAE 217210621SCurtis.Dunham@arm.com default: 217310621SCurtis.Dunham@arm.com panic("unknown page size"); 217410621SCurtis.Dunham@arm.com return 255; 217510621SCurtis.Dunham@arm.com } 217610621SCurtis.Dunham@arm.com} 217710621SCurtis.Dunham@arm.com 217810621SCurtis.Dunham@arm.comvoid 217910621SCurtis.Dunham@arm.comTableWalker::regStats() 218010621SCurtis.Dunham@arm.com{ 218111522Sstephan.diestelhorst@arm.com ClockedObject::regStats(); 218211522Sstephan.diestelhorst@arm.com 218310621SCurtis.Dunham@arm.com statWalks 218410621SCurtis.Dunham@arm.com .name(name() + ".walks") 218510621SCurtis.Dunham@arm.com .desc("Table walker walks requested") 218610621SCurtis.Dunham@arm.com ; 218710621SCurtis.Dunham@arm.com 218810621SCurtis.Dunham@arm.com statWalksShortDescriptor 218910621SCurtis.Dunham@arm.com .name(name() + ".walksShort") 219010621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with short descriptors") 219110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 219210621SCurtis.Dunham@arm.com ; 219310621SCurtis.Dunham@arm.com 219410621SCurtis.Dunham@arm.com statWalksLongDescriptor 219510621SCurtis.Dunham@arm.com .name(name() + ".walksLong") 219610621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with long descriptors") 219710621SCurtis.Dunham@arm.com .flags(Stats::nozero) 219810621SCurtis.Dunham@arm.com ; 219910621SCurtis.Dunham@arm.com 220010621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel 220110621SCurtis.Dunham@arm.com .init(2) 220210621SCurtis.Dunham@arm.com .name(name() + ".walksShortTerminationLevel") 220310621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 220410621SCurtis.Dunham@arm.com "with short descriptors terminate") 220510621SCurtis.Dunham@arm.com .flags(Stats::nozero) 220610621SCurtis.Dunham@arm.com ; 220710621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(0, "Level1"); 220810621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(1, "Level2"); 220910621SCurtis.Dunham@arm.com 221010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel 221110621SCurtis.Dunham@arm.com .init(4) 221210621SCurtis.Dunham@arm.com .name(name() + ".walksLongTerminationLevel") 221310621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 221410621SCurtis.Dunham@arm.com "with long descriptors terminate") 221510621SCurtis.Dunham@arm.com .flags(Stats::nozero) 221610621SCurtis.Dunham@arm.com ; 221710621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(0, "Level0"); 221810621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(1, "Level1"); 221910621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(2, "Level2"); 222010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(3, "Level3"); 222110621SCurtis.Dunham@arm.com 222210621SCurtis.Dunham@arm.com statSquashedBefore 222310621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedBefore") 222410621SCurtis.Dunham@arm.com .desc("Table walks squashed before starting") 222510621SCurtis.Dunham@arm.com .flags(Stats::nozero) 222610621SCurtis.Dunham@arm.com ; 222710621SCurtis.Dunham@arm.com 222810621SCurtis.Dunham@arm.com statSquashedAfter 222910621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedAfter") 223010621SCurtis.Dunham@arm.com .desc("Table walks squashed after completion") 223110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 223210621SCurtis.Dunham@arm.com ; 223310621SCurtis.Dunham@arm.com 223410621SCurtis.Dunham@arm.com statWalkWaitTime 223510621SCurtis.Dunham@arm.com .init(16) 223610621SCurtis.Dunham@arm.com .name(name() + ".walkWaitTime") 223710621SCurtis.Dunham@arm.com .desc("Table walker wait (enqueue to first request) latency") 223810621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 223910621SCurtis.Dunham@arm.com ; 224010621SCurtis.Dunham@arm.com 224110621SCurtis.Dunham@arm.com statWalkServiceTime 224210621SCurtis.Dunham@arm.com .init(16) 224310621SCurtis.Dunham@arm.com .name(name() + ".walkCompletionTime") 224410621SCurtis.Dunham@arm.com .desc("Table walker service (enqueue to completion) latency") 224510621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 224610621SCurtis.Dunham@arm.com ; 224710621SCurtis.Dunham@arm.com 224810621SCurtis.Dunham@arm.com statPendingWalks 224910621SCurtis.Dunham@arm.com .init(16) 225010621SCurtis.Dunham@arm.com .name(name() + ".walksPending") 225110621SCurtis.Dunham@arm.com .desc("Table walker pending requests distribution") 225210621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 225310621SCurtis.Dunham@arm.com ; 225410621SCurtis.Dunham@arm.com 225510621SCurtis.Dunham@arm.com statPageSizes // see DDI 0487A D4-1661 225610621SCurtis.Dunham@arm.com .init(9) 225710621SCurtis.Dunham@arm.com .name(name() + ".walkPageSizes") 225810621SCurtis.Dunham@arm.com .desc("Table walker page sizes translated") 225910621SCurtis.Dunham@arm.com .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 226010621SCurtis.Dunham@arm.com ; 226110621SCurtis.Dunham@arm.com statPageSizes.subname(0, "4K"); 226210621SCurtis.Dunham@arm.com statPageSizes.subname(1, "16K"); 226310621SCurtis.Dunham@arm.com statPageSizes.subname(2, "64K"); 226410621SCurtis.Dunham@arm.com statPageSizes.subname(3, "1M"); 226510621SCurtis.Dunham@arm.com statPageSizes.subname(4, "2M"); 226610621SCurtis.Dunham@arm.com statPageSizes.subname(5, "16M"); 226710621SCurtis.Dunham@arm.com statPageSizes.subname(6, "32M"); 226810621SCurtis.Dunham@arm.com statPageSizes.subname(7, "512M"); 226910621SCurtis.Dunham@arm.com statPageSizes.subname(8, "1G"); 227010621SCurtis.Dunham@arm.com 227110621SCurtis.Dunham@arm.com statRequestOrigin 227210621SCurtis.Dunham@arm.com .init(2,2) // Instruction/Data, requests/completed 227310621SCurtis.Dunham@arm.com .name(name() + ".walkRequestOrigin") 227410621SCurtis.Dunham@arm.com .desc("Table walker requests started/completed, data/inst") 227510621SCurtis.Dunham@arm.com .flags(Stats::total) 227610621SCurtis.Dunham@arm.com ; 227710621SCurtis.Dunham@arm.com statRequestOrigin.subname(0,"Requested"); 227810621SCurtis.Dunham@arm.com statRequestOrigin.subname(1,"Completed"); 227910621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(0,"Data"); 228010621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(1,"Inst"); 228110621SCurtis.Dunham@arm.com} 2282