table_walker.cc revision 12749
17404SAli.Saidi@ARM.com/* 212709Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2018 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 4010873Sandreas.sandberg@arm.com#include "arch/arm/table_walker.hh" 417404SAli.Saidi@ARM.com 4210474Sandreas.hansson@arm.com#include <memory> 4310474Sandreas.hansson@arm.com 447404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4510037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4610037SARM gem5 Developers#include "arch/arm/system.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 487728SAli.Saidi@ARM.com#include "cpu/base.hh" 497404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 508245Snate@binkert.org#include "debug/Checkpoint.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528245Snate@binkert.org#include "debug/TLB.hh" 538245Snate@binkert.org#include "debug/TLBVerbose.hh" 5410873Sandreas.sandberg@arm.com#include "dev/dma_device.hh" 557748SAli.Saidi@ARM.com#include "sim/system.hh" 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comusing namespace ArmISA; 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 6010913Sandreas.sandberg@arm.com : MemObject(p), 6110717Sandreas.hansson@arm.com stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 6210717Sandreas.hansson@arm.com isStage2(p->is_stage2), tlb(NULL), 6310717Sandreas.hansson@arm.com currState(NULL), pending(false), 649258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6510621SCurtis.Dunham@arm.com pendingReqs(0), 6610621SCurtis.Dunham@arm.com pendingChangeTick(curTick()), 6712086Sspwilson2@wisc.edu doL1DescEvent([this]{ doL1DescriptorWrapper(); }, name()), 6812086Sspwilson2@wisc.edu doL2DescEvent([this]{ doL2DescriptorWrapper(); }, name()), 6912086Sspwilson2@wisc.edu doL0LongDescEvent([this]{ doL0LongDescriptorWrapper(); }, name()), 7012086Sspwilson2@wisc.edu doL1LongDescEvent([this]{ doL1LongDescriptorWrapper(); }, name()), 7112086Sspwilson2@wisc.edu doL2LongDescEvent([this]{ doL2LongDescriptorWrapper(); }, name()), 7212086Sspwilson2@wisc.edu doL3LongDescEvent([this]{ doL3LongDescriptorWrapper(); }, name()), 7311588SCurtis.Dunham@arm.com LongDescEventByLevel { &doL0LongDescEvent, &doL1LongDescEvent, 7411588SCurtis.Dunham@arm.com &doL2LongDescEvent, &doL3LongDescEvent }, 7512086Sspwilson2@wisc.edu doProcessEvent([this]{ processWalkWrapper(); }, name()) 767439Sdam.sunwoo@arm.com{ 777576SAli.Saidi@ARM.com sctlr = 0; 7810037SARM gem5 Developers 7910037SARM gem5 Developers // Cache system-level properties 8010037SARM gem5 Developers if (FullSystem) { 8110717Sandreas.hansson@arm.com ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 8210037SARM gem5 Developers assert(armSys); 8310037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 8410037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 8510037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 8610037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 8710037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 8810037SARM gem5 Developers } else { 8910037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 9010037SARM gem5 Developers _haveLargeAsid64 = false; 9110037SARM gem5 Developers physAddrRange = 32; 9210037SARM gem5 Developers } 9310037SARM gem5 Developers 947439Sdam.sunwoo@arm.com} 957404SAli.Saidi@ARM.com 967404SAli.Saidi@ARM.comTableWalker::~TableWalker() 977404SAli.Saidi@ARM.com{ 987404SAli.Saidi@ARM.com ; 997404SAli.Saidi@ARM.com} 1007404SAli.Saidi@ARM.com 10110717Sandreas.hansson@arm.comvoid 10210717Sandreas.hansson@arm.comTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 10310717Sandreas.hansson@arm.com{ 10410717Sandreas.hansson@arm.com stage2Mmu = m; 10510717Sandreas.hansson@arm.com port = &m->getPort(); 10610717Sandreas.hansson@arm.com masterId = master_id; 10710717Sandreas.hansson@arm.com} 10810717Sandreas.hansson@arm.com 10910717Sandreas.hansson@arm.comvoid 11010717Sandreas.hansson@arm.comTableWalker::init() 11110717Sandreas.hansson@arm.com{ 11210717Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 11310717Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 11410717Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 11510717Sandreas.hansson@arm.com} 11610717Sandreas.hansson@arm.com 11710717Sandreas.hansson@arm.comBaseMasterPort& 11810717Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 11910717Sandreas.hansson@arm.com{ 12010717Sandreas.hansson@arm.com if (if_name == "port") { 12110717Sandreas.hansson@arm.com if (!isStage2) { 12210717Sandreas.hansson@arm.com return *port; 12310717Sandreas.hansson@arm.com } else { 12410717Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 12510717Sandreas.hansson@arm.com } 12610717Sandreas.hansson@arm.com } 12710717Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 12810717Sandreas.hansson@arm.com} 12910717Sandreas.hansson@arm.com 13010537Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 13110537Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 13210537Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 13310537Sandreas.hansson@arm.com vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 13410537Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 13512738Sandreas.sandberg@arm.com pxnTable(false), stage2Req(false), 13610537Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 13710537Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 13810537Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 13910037SARM gem5 Developers{ 14010037SARM gem5 Developers} 14110037SARM gem5 Developers 1429152Satgutier@umich.eduvoid 1439152Satgutier@umich.eduTableWalker::completeDrain() 1449152Satgutier@umich.edu{ 14510913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 14611588SCurtis.Dunham@arm.com stateQueues[L0].empty() && stateQueues[L1].empty() && 14711588SCurtis.Dunham@arm.com stateQueues[L2].empty() && stateQueues[L3].empty() && 1489152Satgutier@umich.edu pendingQueue.empty()) { 14910913Sandreas.sandberg@arm.com 1509152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 15110913Sandreas.sandberg@arm.com signalDrainDone(); 1529152Satgutier@umich.edu } 1539152Satgutier@umich.edu} 1549152Satgutier@umich.edu 15510913Sandreas.sandberg@arm.comDrainState 15610913Sandreas.sandberg@arm.comTableWalker::drain() 1577404SAli.Saidi@ARM.com{ 15810037SARM gem5 Developers bool state_queues_not_empty = false; 1599152Satgutier@umich.edu 16010037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 16110037SARM gem5 Developers if (!stateQueues[i].empty()) { 16210037SARM gem5 Developers state_queues_not_empty = true; 16310037SARM gem5 Developers break; 16410037SARM gem5 Developers } 16510037SARM gem5 Developers } 16610037SARM gem5 Developers 16710037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1689152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 16910913Sandreas.sandberg@arm.com return DrainState::Draining; 17010037SARM gem5 Developers } else { 17110037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 17210913Sandreas.sandberg@arm.com return DrainState::Drained; 1737733SAli.Saidi@ARM.com } 1747404SAli.Saidi@ARM.com} 1757404SAli.Saidi@ARM.com 1767748SAli.Saidi@ARM.comvoid 1779342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1787748SAli.Saidi@ARM.com{ 1799524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1809152Satgutier@umich.edu delete currState; 1819152Satgutier@umich.edu currState = NULL; 18210621SCurtis.Dunham@arm.com pendingChange(); 1837748SAli.Saidi@ARM.com } 1847748SAli.Saidi@ARM.com} 1857748SAli.Saidi@ARM.com 1867404SAli.Saidi@ARM.comFault 18712749Sgiacomo.travaglini@arm.comTableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, 18810037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 18910037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 19011580SDylan.Johnson@ARM.com bool secure, TLB::ArmTranslationType tranType, 19111580SDylan.Johnson@ARM.com bool _stage2Req) 1927404SAli.Saidi@ARM.com{ 1938733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 19410621SCurtis.Dunham@arm.com ++statWalks; 19510621SCurtis.Dunham@arm.com 19610109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 19710037SARM gem5 Developers 19810109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 1997439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 2007439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 2017439Sdam.sunwoo@arm.com // TLB miss. 2027439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 2037404SAli.Saidi@ARM.com 2047439Sdam.sunwoo@arm.com currState = new WalkerState(); 2057439Sdam.sunwoo@arm.com currState->tableWalker = this; 20610109SGeoffrey.Blake@arm.com } else if (_functional) { 20710109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 20810109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 20910109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 21010109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 21110109SGeoffrey.Blake@arm.com savedCurrState = currState; 21210109SGeoffrey.Blake@arm.com currState = new WalkerState(); 21310109SGeoffrey.Blake@arm.com currState->tableWalker = this; 2148202SAli.Saidi@ARM.com } else if (_timing) { 2158202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 2168202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 2178202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 2188202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 2198202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 2208202SAli.Saidi@ARM.com // up everything. 22110037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 22210621SCurtis.Dunham@arm.com ++statSquashedBefore; 22310474Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 2248202SAli.Saidi@ARM.com } 2257439Sdam.sunwoo@arm.com } 22610621SCurtis.Dunham@arm.com pendingChange(); 2277439Sdam.sunwoo@arm.com 22810621SCurtis.Dunham@arm.com currState->startTime = curTick(); 2297439Sdam.sunwoo@arm.com currState->tc = _tc; 23011517SCurtis.Dunham@arm.com // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 23111517SCurtis.Dunham@arm.com // aarch32/translation/translation/AArch32.TranslateAddress dictates 23211517SCurtis.Dunham@arm.com // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 23312735Sandreas.sandberg@arm.com if (isStage2) { 23412735Sandreas.sandberg@arm.com currState->el = EL1; 23512735Sandreas.sandberg@arm.com currState->aarch64 = ELIs64(_tc, EL2); 23612735Sandreas.sandberg@arm.com } else { 23712735Sandreas.sandberg@arm.com currState->el = 23812735Sandreas.sandberg@arm.com TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType); 23912735Sandreas.sandberg@arm.com currState->aarch64 = 24012735Sandreas.sandberg@arm.com ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el); 24112735Sandreas.sandberg@arm.com } 2427439Sdam.sunwoo@arm.com currState->transState = _trans; 2437439Sdam.sunwoo@arm.com currState->req = _req; 2447439Sdam.sunwoo@arm.com currState->fault = NoFault; 24510037SARM gem5 Developers currState->asid = _asid; 24610037SARM gem5 Developers currState->vmid = _vmid; 24710037SARM gem5 Developers currState->isHyp = _isHyp; 2487439Sdam.sunwoo@arm.com currState->timing = _timing; 2498733Sgeoffrey.blake@arm.com currState->functional = _functional; 2507439Sdam.sunwoo@arm.com currState->mode = _mode; 25110037SARM gem5 Developers currState->tranType = tranType; 25210037SARM gem5 Developers currState->isSecure = secure; 25310037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2547404SAli.Saidi@ARM.com 2557436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2567436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 25710037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 25810037SARM gem5 Developers if (currState->aarch64) 25910037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 26010037SARM gem5 Developers currState->tc, currState->el); 26110037SARM gem5 Developers else 26210037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 26310037SARM gem5 Developers 26410037SARM gem5 Developers if (currState->aarch64) { 26511575SDylan.Johnson@ARM.com if (isStage2) { 26611575SDylan.Johnson@ARM.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 26711575SDylan.Johnson@ARM.com currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 26811575SDylan.Johnson@ARM.com } else switch (currState->el) { 26910037SARM gem5 Developers case EL0: 27010037SARM gem5 Developers case EL1: 27110037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 27210324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 27310037SARM gem5 Developers break; 27411574SCurtis.Dunham@arm.com case EL2: 27511574SCurtis.Dunham@arm.com assert(_haveVirtualization); 27611574SCurtis.Dunham@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 27711574SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 27811574SCurtis.Dunham@arm.com break; 27910037SARM gem5 Developers case EL3: 28010037SARM gem5 Developers assert(haveSecurity); 28110037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 28210324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 28310037SARM gem5 Developers break; 28410037SARM gem5 Developers default: 28510037SARM gem5 Developers panic("Invalid exception level"); 28610037SARM gem5 Developers break; 28710037SARM gem5 Developers } 28811575SDylan.Johnson@ARM.com currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 28910037SARM gem5 Developers } else { 29012499Sgiacomo.travaglini@arm.com currState->sctlr = currState->tc->readMiscReg(snsBankedIndex( 29110037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 29212499Sgiacomo.travaglini@arm.com currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex( 29310037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 29410037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 29510037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 29610037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 29710037SARM gem5 Developers } 2987439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 2997439Sdam.sunwoo@arm.com 3007439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 3017439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 3027439Sdam.sunwoo@arm.com 30310621SCurtis.Dunham@arm.com statRequestOrigin[REQUESTED][currState->isFetch]++; 30410621SCurtis.Dunham@arm.com 30511580SDylan.Johnson@ARM.com currState->stage2Req = _stage2Req && !isStage2; 3067728SAli.Saidi@ARM.com 30711517SCurtis.Dunham@arm.com bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 30811517SCurtis.Dunham@arm.com longDescFormatInUse(currState->tc); 30910037SARM gem5 Developers 31010037SARM gem5 Developers if (long_desc_format) { 31110037SARM gem5 Developers // Helper variables used for hierarchical permissions 31210037SARM gem5 Developers currState->secureLookup = currState->isSecure; 31310037SARM gem5 Developers currState->rwTable = true; 31410037SARM gem5 Developers currState->userTable = true; 31510037SARM gem5 Developers currState->xnTable = false; 31610037SARM gem5 Developers currState->pxnTable = false; 31710621SCurtis.Dunham@arm.com 31810621SCurtis.Dunham@arm.com ++statWalksLongDescriptor; 31910621SCurtis.Dunham@arm.com } else { 32010621SCurtis.Dunham@arm.com ++statWalksShortDescriptor; 32110037SARM gem5 Developers } 32210037SARM gem5 Developers 32310037SARM gem5 Developers if (!currState->timing) { 32410109SGeoffrey.Blake@arm.com Fault fault = NoFault; 32510037SARM gem5 Developers if (currState->aarch64) 32610109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 32710037SARM gem5 Developers else if (long_desc_format) 32810109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 32910037SARM gem5 Developers else 33010109SGeoffrey.Blake@arm.com fault = processWalk(); 33110109SGeoffrey.Blake@arm.com 33210109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 33310109SGeoffrey.Blake@arm.com // how we found it. 33410109SGeoffrey.Blake@arm.com if (currState->functional) { 33510109SGeoffrey.Blake@arm.com delete currState; 33610109SGeoffrey.Blake@arm.com currState = savedCurrState; 33710109SGeoffrey.Blake@arm.com } 33810109SGeoffrey.Blake@arm.com return fault; 33910037SARM gem5 Developers } 3407728SAli.Saidi@ARM.com 3418067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 3427728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 3437728SAli.Saidi@ARM.com currState = NULL; 34410621SCurtis.Dunham@arm.com pendingChange(); 3457728SAli.Saidi@ARM.com } else { 3467728SAli.Saidi@ARM.com pending = true; 34710621SCurtis.Dunham@arm.com pendingChange(); 34810037SARM gem5 Developers if (currState->aarch64) 34910037SARM gem5 Developers return processWalkAArch64(); 35010037SARM gem5 Developers else if (long_desc_format) 35110037SARM gem5 Developers return processWalkLPAE(); 35210037SARM gem5 Developers else 35310037SARM gem5 Developers return processWalk(); 3547728SAli.Saidi@ARM.com } 3557728SAli.Saidi@ARM.com 3567728SAli.Saidi@ARM.com return NoFault; 3577728SAli.Saidi@ARM.com} 3587728SAli.Saidi@ARM.com 3597728SAli.Saidi@ARM.comvoid 3607728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3617728SAli.Saidi@ARM.com{ 3627728SAli.Saidi@ARM.com assert(!currState); 3637728SAli.Saidi@ARM.com assert(pendingQueue.size()); 36410621SCurtis.Dunham@arm.com pendingChange(); 3657728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3669258SAli.Saidi@ARM.com 3679535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 36810037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 36910037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 37010037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 37112735Sandreas.sandberg@arm.com currState->el); 3729258SAli.Saidi@ARM.com 3739535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3749535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3759535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3769535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3779535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3789535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3799258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3809258SAli.Saidi@ARM.com pending = true; 3819258SAli.Saidi@ARM.com pendingQueue.pop_front(); 38210579SAndrew.Bardsley@arm.com // Keep currState in case one of the processWalk... calls NULLs it 38310579SAndrew.Bardsley@arm.com WalkerState *curr_state_copy = currState; 38410579SAndrew.Bardsley@arm.com Fault f; 38510037SARM gem5 Developers if (currState->aarch64) 38610579SAndrew.Bardsley@arm.com f = processWalkAArch64(); 38711517SCurtis.Dunham@arm.com else if (longDescFormatInUse(currState->tc) || 38811517SCurtis.Dunham@arm.com currState->isHyp || isStage2) 38910579SAndrew.Bardsley@arm.com f = processWalkLPAE(); 39010037SARM gem5 Developers else 39110579SAndrew.Bardsley@arm.com f = processWalk(); 39210579SAndrew.Bardsley@arm.com 39310579SAndrew.Bardsley@arm.com if (f != NoFault) { 39410579SAndrew.Bardsley@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 39510579SAndrew.Bardsley@arm.com curr_state_copy->tc, curr_state_copy->mode); 39610579SAndrew.Bardsley@arm.com 39710579SAndrew.Bardsley@arm.com delete curr_state_copy; 39810579SAndrew.Bardsley@arm.com } 3999258SAli.Saidi@ARM.com return; 4009258SAli.Saidi@ARM.com } 4019258SAli.Saidi@ARM.com 4029258SAli.Saidi@ARM.com 4039258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 4049258SAli.Saidi@ARM.com // squashed we shouldn't bother. 4059258SAli.Saidi@ARM.com unsigned num_squashed = 0; 4069258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 4079258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 4089535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 4099258SAli.Saidi@ARM.com pendingQueue.pop_front(); 4109258SAli.Saidi@ARM.com num_squashed++; 41110621SCurtis.Dunham@arm.com statSquashedBefore++; 4129258SAli.Saidi@ARM.com 41310037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 41410037SARM gem5 Developers currState->vaddr_tainted); 4159258SAli.Saidi@ARM.com 4169535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 4179535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 41810474Sandreas.hansson@arm.com currState->transState->finish( 41910474Sandreas.hansson@arm.com std::make_shared<UnimpFault>("Squashed Inst"), 42010474Sandreas.hansson@arm.com currState->req, currState->tc, currState->mode); 4219535Smrinmoy.ghosh@arm.com } else { 4229535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 42310621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 42410037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 42510037SARM gem5 Developers currState->transState, currState->mode); 42610037SARM gem5 Developers 4279535Smrinmoy.ghosh@arm.com } 4289258SAli.Saidi@ARM.com 4299258SAli.Saidi@ARM.com // delete the current request 4309258SAli.Saidi@ARM.com delete currState; 4319258SAli.Saidi@ARM.com 4329258SAli.Saidi@ARM.com // peak at the next one 4339535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 4349258SAli.Saidi@ARM.com currState = pendingQueue.front(); 43510037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 43610037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 43712735Sandreas.sandberg@arm.com false, currState->el); 4389535Smrinmoy.ghosh@arm.com } else { 4399535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 4409258SAli.Saidi@ARM.com currState = NULL; 4419535Smrinmoy.ghosh@arm.com } 4429258SAli.Saidi@ARM.com } 44310621SCurtis.Dunham@arm.com pendingChange(); 4449258SAli.Saidi@ARM.com 44510621SCurtis.Dunham@arm.com // if we still have pending translations, schedule more work 4469258SAli.Saidi@ARM.com nextWalk(tc); 4479258SAli.Saidi@ARM.com currState = NULL; 4487728SAli.Saidi@ARM.com} 4497728SAli.Saidi@ARM.com 4507728SAli.Saidi@ARM.comFault 4517728SAli.Saidi@ARM.comTableWalker::processWalk() 4527728SAli.Saidi@ARM.com{ 4537404SAli.Saidi@ARM.com Addr ttbr = 0; 4547404SAli.Saidi@ARM.com 4557404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 45610037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 4577404SAli.Saidi@ARM.com 45810037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 45910037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 46010037SARM gem5 Developers 32 - currState->ttbcr.n)); 4617406SAli.Saidi@ARM.com 46210621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 46310621SCurtis.Dunham@arm.com 46410037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 46510037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4667406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 46710037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 46810037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 46910037SARM gem5 Developers if (currState->isFetch) 47010474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 47110474Sandreas.hansson@arm.com currState->vaddr_tainted, 47210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 47310474Sandreas.hansson@arm.com isStage2, 47410474Sandreas.hansson@arm.com ArmFault::VmsaTran); 47510037SARM gem5 Developers else 47610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 47710474Sandreas.hansson@arm.com currState->vaddr_tainted, 47810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 47910474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 48010474Sandreas.hansson@arm.com ArmFault::VmsaTran); 48110037SARM gem5 Developers } 48212499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 48310037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4847404SAli.Saidi@ARM.com } else { 4857406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 48610037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 48710037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 48810037SARM gem5 Developers if (currState->isFetch) 48910474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 49010474Sandreas.hansson@arm.com currState->vaddr_tainted, 49110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 49210474Sandreas.hansson@arm.com isStage2, 49310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49410037SARM gem5 Developers else 49510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 49610474Sandreas.hansson@arm.com currState->vaddr_tainted, 49710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 49810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 49910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 50010037SARM gem5 Developers } 50112499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 50210037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 50310037SARM gem5 Developers currState->ttbcr.n = 0; 5047404SAli.Saidi@ARM.com } 5057404SAli.Saidi@ARM.com 50610037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 50710037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 50810037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 50910037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 5107404SAli.Saidi@ARM.com 5117404SAli.Saidi@ARM.com // Trickbox address check 5127439Sdam.sunwoo@arm.com Fault f; 51311395Sandreas.sandberg@arm.com f = testWalk(l1desc_addr, sizeof(uint32_t), 51411395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, L1); 5157439Sdam.sunwoo@arm.com if (f) { 51610037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5177579Sminkyu.jeong@arm.com if (currState->timing) { 5187728SAli.Saidi@ARM.com pending = false; 5197728SAli.Saidi@ARM.com nextWalk(currState->tc); 5207579Sminkyu.jeong@arm.com currState = NULL; 5217579Sminkyu.jeong@arm.com } else { 5227579Sminkyu.jeong@arm.com currState->tc = NULL; 5237579Sminkyu.jeong@arm.com currState->req = NULL; 5247579Sminkyu.jeong@arm.com } 5257579Sminkyu.jeong@arm.com return f; 5267404SAli.Saidi@ARM.com } 5277404SAli.Saidi@ARM.com 52810836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 5297946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 53010836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 5317946SGiacomo.Gabrielli@arm.com } 5327946SGiacomo.Gabrielli@arm.com 53311181Snathananel.premillieu@arm.com if (currState->isSecure) { 53411181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 53511181Snathananel.premillieu@arm.com } 53611181Snathananel.premillieu@arm.com 53710037SARM gem5 Developers bool delayed; 53810037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 53910037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 54010037SARM gem5 Developers &TableWalker::doL1Descriptor); 54110037SARM gem5 Developers if (!delayed) { 54210037SARM gem5 Developers f = currState->fault; 54310037SARM gem5 Developers } 54410037SARM gem5 Developers 54510037SARM gem5 Developers return f; 54610037SARM gem5 Developers} 54710037SARM gem5 Developers 54810037SARM gem5 DevelopersFault 54910037SARM gem5 DevelopersTableWalker::processWalkLPAE() 55010037SARM gem5 Developers{ 55110037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 55210037SARM gem5 Developers int tsz, n; 55310037SARM gem5 Developers LookupLevel start_lookup_level = L1; 55410037SARM gem5 Developers 55510037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 55610037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 55710037SARM gem5 Developers 55810621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 55910621SCurtis.Dunham@arm.com 56010836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 56110037SARM gem5 Developers if (currState->isSecure) 56210037SARM gem5 Developers flag.set(Request::SECURE); 56310037SARM gem5 Developers 56410037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 56510037SARM gem5 Developers // use HTTBR 56610037SARM gem5 Developers if (isStage2) { 56710037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 56810037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 56910037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 57010037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 57110037SARM gem5 Developers } else if (currState->isHyp) { 57210037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 57310037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 57410037SARM gem5 Developers tsz = currState->htcr.t0sz; 57510037SARM gem5 Developers } else { 57611517SCurtis.Dunham@arm.com assert(longDescFormatInUse(currState->tc)); 57710037SARM gem5 Developers 57810037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 57910037SARM gem5 Developers if (currState->ttbcr.t0sz) 58010037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 58110037SARM gem5 Developers else if (currState->ttbcr.t1sz) 58210037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 58310037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 58410037SARM gem5 Developers else 58510037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 58610037SARM gem5 Developers if (currState->ttbcr.t1sz) 58710037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 58810037SARM gem5 Developers else 58910037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 59010037SARM gem5 Developers 59110037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 59210037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 59310037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 59410037SARM gem5 Developers // ARM issue C B3.6.4) 59510037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 59610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 59710037SARM gem5 Developers // Check if table walk is allowed 59810037SARM gem5 Developers if (currState->ttbcr.epd0) { 59910037SARM gem5 Developers if (currState->isFetch) 60010474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 60110474Sandreas.hansson@arm.com currState->vaddr_tainted, 60210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60310474Sandreas.hansson@arm.com isStage2, 60410474Sandreas.hansson@arm.com ArmFault::LpaeTran); 60510037SARM gem5 Developers else 60610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 60710474Sandreas.hansson@arm.com currState->vaddr_tainted, 60810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 60910474Sandreas.hansson@arm.com currState->isWrite, 61010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 61110474Sandreas.hansson@arm.com isStage2, 61210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 61310037SARM gem5 Developers } 61412499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 61510037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 61610037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 61710037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 61810037SARM gem5 Developers start_lookup_level = L2; 61910037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 62010037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 62110037SARM gem5 Developers // Check if table walk is allowed 62210037SARM gem5 Developers if (currState->ttbcr.epd1) { 62310037SARM gem5 Developers if (currState->isFetch) 62410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 62510474Sandreas.hansson@arm.com currState->vaddr_tainted, 62610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 62710474Sandreas.hansson@arm.com isStage2, 62810474Sandreas.hansson@arm.com ArmFault::LpaeTran); 62910037SARM gem5 Developers else 63010474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 63110474Sandreas.hansson@arm.com currState->vaddr_tainted, 63210474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 63310474Sandreas.hansson@arm.com currState->isWrite, 63410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63510474Sandreas.hansson@arm.com isStage2, 63610474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63710037SARM gem5 Developers } 63812499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 63910037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 64010037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 64110037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 64210037SARM gem5 Developers start_lookup_level = L2; 64310037SARM gem5 Developers } else { 64410037SARM gem5 Developers // Out of boundaries -> translation fault 64510037SARM gem5 Developers if (currState->isFetch) 64610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64710474Sandreas.hansson@arm.com currState->vaddr_tainted, 64810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 64910474Sandreas.hansson@arm.com isStage2, 65010474Sandreas.hansson@arm.com ArmFault::LpaeTran); 65110037SARM gem5 Developers else 65210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65310474Sandreas.hansson@arm.com currState->vaddr_tainted, 65410474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 65510474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 65610474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 65710037SARM gem5 Developers } 65810037SARM gem5 Developers 65910037SARM gem5 Developers } 66010037SARM gem5 Developers 66110037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 66210037SARM gem5 Developers if (start_lookup_level == L1) { 66310037SARM gem5 Developers n = 5 - tsz; 66410037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 66510037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 66610037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 66710037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 66810037SARM gem5 Developers } else { 66910037SARM gem5 Developers // Skip first-level lookup 67010037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 67110037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 67210037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 67310037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67410037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67510037SARM gem5 Developers } 67610037SARM gem5 Developers 67710037SARM gem5 Developers // Trickbox address check 67811395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 67911395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 68010037SARM gem5 Developers if (f) { 68110037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 68210037SARM gem5 Developers if (currState->timing) { 68310037SARM gem5 Developers pending = false; 68410037SARM gem5 Developers nextWalk(currState->tc); 68510037SARM gem5 Developers currState = NULL; 68610037SARM gem5 Developers } else { 68710037SARM gem5 Developers currState->tc = NULL; 68810037SARM gem5 Developers currState->req = NULL; 68910037SARM gem5 Developers } 69010037SARM gem5 Developers return f; 69110037SARM gem5 Developers } 69210037SARM gem5 Developers 69310037SARM gem5 Developers if (currState->sctlr.c == 0) { 69410836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 69510037SARM gem5 Developers } 69610037SARM gem5 Developers 69710037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 69810037SARM gem5 Developers currState->longDesc.aarch64 = false; 69910324SCurtis.Dunham@arm.com currState->longDesc.grainSize = Grain4KB; 70010037SARM gem5 Developers 70110037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70210037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 70311588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], 70411588SCurtis.Dunham@arm.com &TableWalker::doLongDescriptor); 70510037SARM gem5 Developers if (!delayed) { 70610037SARM gem5 Developers f = currState->fault; 70710037SARM gem5 Developers } 70810037SARM gem5 Developers 70910037SARM gem5 Developers return f; 71010037SARM gem5 Developers} 71110037SARM gem5 Developers 71210037SARM gem5 Developersunsigned 71310037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 71410037SARM gem5 Developers{ 71510037SARM gem5 Developers if (tsz < 25) 71610037SARM gem5 Developers return 25; 71710037SARM gem5 Developers if (tsz > 48) 71810037SARM gem5 Developers return 48; 71910037SARM gem5 Developers return tsz; 72010037SARM gem5 Developers} 72110037SARM gem5 Developers 72210037SARM gem5 Developersbool 72310037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 72410037SARM gem5 Developers{ 72510037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 72610037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 72710037SARM gem5 Developers} 72810037SARM gem5 Developers 72910037SARM gem5 DevelopersFault 73010037SARM gem5 DevelopersTableWalker::processWalkAArch64() 73110037SARM gem5 Developers{ 73210037SARM gem5 Developers assert(currState->aarch64); 73310037SARM gem5 Developers 73410324SCurtis.Dunham@arm.com DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 73510324SCurtis.Dunham@arm.com currState->vaddr_tainted, currState->tcr); 73610324SCurtis.Dunham@arm.com 73712709Sgiacomo.travaglini@arm.com static const GrainSize GrainMap_tg0[] = 73810324SCurtis.Dunham@arm.com { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 73912709Sgiacomo.travaglini@arm.com static const GrainSize GrainMap_tg1[] = 74010324SCurtis.Dunham@arm.com { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 74110037SARM gem5 Developers 74210621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 74310621SCurtis.Dunham@arm.com 74410037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 74510037SARM gem5 Developers Addr ttbr = 0; 74610037SARM gem5 Developers int tsz = 0, ps = 0; 74710324SCurtis.Dunham@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 74810037SARM gem5 Developers bool fault = false; 74911575SDylan.Johnson@ARM.com 75011575SDylan.Johnson@ARM.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 75111575SDylan.Johnson@ARM.com 75210037SARM gem5 Developers switch (currState->el) { 75310037SARM gem5 Developers case EL0: 75410037SARM gem5 Developers case EL1: 75511575SDylan.Johnson@ARM.com if (isStage2) { 75611575SDylan.Johnson@ARM.com DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 75711575SDylan.Johnson@ARM.com ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 75811575SDylan.Johnson@ARM.com tsz = 64 - currState->vtcr.t0sz64; 75912709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->vtcr.tg0]; 76011575SDylan.Johnson@ARM.com // ARM DDI 0487A.f D7-2148 76111575SDylan.Johnson@ARM.com // The starting level of stage 2 translation depends on 76211575SDylan.Johnson@ARM.com // VTCR_EL2.SL0 and VTCR_EL2.TG0 76311575SDylan.Johnson@ARM.com LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 76411575SDylan.Johnson@ARM.com uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 76511575SDylan.Johnson@ARM.com static const LookupLevel SLL[] = { 76611575SDylan.Johnson@ARM.com L2, L3, L3, __, // sl0 == 0 76711575SDylan.Johnson@ARM.com L1, L2, L2, __, // sl0 == 1, etc. 76811575SDylan.Johnson@ARM.com L0, L1, L1, __, 76911575SDylan.Johnson@ARM.com __, __, __, __ 77011575SDylan.Johnson@ARM.com }; 77111575SDylan.Johnson@ARM.com start_lookup_level = SLL[sl_tg]; 77211575SDylan.Johnson@ARM.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 77311575SDylan.Johnson@ARM.com "Cannot discern lookup level from vtcr.{sl0,tg0}"); 77411575SDylan.Johnson@ARM.com } else switch (bits(currState->vaddr, 63,48)) { 77510037SARM gem5 Developers case 0: 77610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 77710037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 77810324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 77912709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 78010037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != 0x0 || 78110324SCurtis.Dunham@arm.com currState->tcr.epd0) 78210037SARM gem5 Developers fault = true; 78310037SARM gem5 Developers break; 78410037SARM gem5 Developers case 0xffff: 78510037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 78610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 78710324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 78812709Sgiacomo.travaglini@arm.com tg = GrainMap_tg1[currState->tcr.tg1]; 78910037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 79010324SCurtis.Dunham@arm.com currState->tcr.epd1) 79110037SARM gem5 Developers fault = true; 79210037SARM gem5 Developers break; 79310037SARM gem5 Developers default: 79410037SARM gem5 Developers // top two bytes must be all 0s or all 1s, else invalid addr 79510037SARM gem5 Developers fault = true; 79610037SARM gem5 Developers } 79710324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 79810037SARM gem5 Developers break; 79910037SARM gem5 Developers case EL2: 80012709Sgiacomo.travaglini@arm.com switch(bits(currState->vaddr, 63,48)) { 80112709Sgiacomo.travaglini@arm.com case 0: 80212709Sgiacomo.travaglini@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 80312709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 80412709Sgiacomo.travaglini@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 80512709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 80612709Sgiacomo.travaglini@arm.com break; 80712709Sgiacomo.travaglini@arm.com 80812709Sgiacomo.travaglini@arm.com case 0xffff: 80912709Sgiacomo.travaglini@arm.com DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 81012709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2); 81112709Sgiacomo.travaglini@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 81212709Sgiacomo.travaglini@arm.com tg = GrainMap_tg1[currState->tcr.tg1]; 81312709Sgiacomo.travaglini@arm.com if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 81412709Sgiacomo.travaglini@arm.com currState->tcr.epd1 || !currState->hcr.e2h) 81512709Sgiacomo.travaglini@arm.com fault = true; 81612709Sgiacomo.travaglini@arm.com break; 81712709Sgiacomo.travaglini@arm.com 81812709Sgiacomo.travaglini@arm.com default: 81912709Sgiacomo.travaglini@arm.com // invalid addr if top two bytes are not all 0s 82012709Sgiacomo.travaglini@arm.com fault = true; 82112709Sgiacomo.travaglini@arm.com } 82212709Sgiacomo.travaglini@arm.com ps = currState->tcr.ips; 82312709Sgiacomo.travaglini@arm.com break; 82410037SARM gem5 Developers case EL3: 82510037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 82610037SARM gem5 Developers case 0: 82710324SCurtis.Dunham@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 82812709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 82910324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 83012709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 83110037SARM gem5 Developers break; 83210037SARM gem5 Developers default: 83310037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 83410324SCurtis.Dunham@arm.com fault = true; 83510037SARM gem5 Developers } 83610324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 83710037SARM gem5 Developers break; 83810037SARM gem5 Developers } 83910037SARM gem5 Developers 84010037SARM gem5 Developers if (fault) { 84110037SARM gem5 Developers Fault f; 84210037SARM gem5 Developers if (currState->isFetch) 84310474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 84410474Sandreas.hansson@arm.com currState->vaddr_tainted, 84510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 84610474Sandreas.hansson@arm.com ArmFault::LpaeTran); 84710037SARM gem5 Developers else 84810474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 84910474Sandreas.hansson@arm.com currState->vaddr_tainted, 85010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 85110474Sandreas.hansson@arm.com currState->isWrite, 85210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, 85310474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 85410037SARM gem5 Developers 85510037SARM gem5 Developers if (currState->timing) { 85610037SARM gem5 Developers pending = false; 85710037SARM gem5 Developers nextWalk(currState->tc); 85810037SARM gem5 Developers currState = NULL; 85910037SARM gem5 Developers } else { 86010037SARM gem5 Developers currState->tc = NULL; 86110037SARM gem5 Developers currState->req = NULL; 86210037SARM gem5 Developers } 86310037SARM gem5 Developers return f; 86410037SARM gem5 Developers 86510037SARM gem5 Developers } 86610037SARM gem5 Developers 86710324SCurtis.Dunham@arm.com if (tg == ReservedGrain) { 86810324SCurtis.Dunham@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 86910324SCurtis.Dunham@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 87010324SCurtis.Dunham@arm.com tg = Grain4KB; 87110324SCurtis.Dunham@arm.com } 87210324SCurtis.Dunham@arm.com 87310037SARM gem5 Developers // Determine starting lookup level 87410324SCurtis.Dunham@arm.com // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 87510324SCurtis.Dunham@arm.com // in ARM DDI 0487A. These table values correspond to the cascading tests 87610324SCurtis.Dunham@arm.com // to compute the lookup level and are of the form 87710324SCurtis.Dunham@arm.com // (grain_size + N*stride), for N = {1, 2, 3}. 87810324SCurtis.Dunham@arm.com // A value of 64 will never succeed and a value of 0 will always succeed. 87911575SDylan.Johnson@ARM.com if (start_lookup_level == MAX_LOOKUP_LEVELS) { 88010324SCurtis.Dunham@arm.com struct GrainMap { 88110324SCurtis.Dunham@arm.com GrainSize grain_size; 88210324SCurtis.Dunham@arm.com unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 88310324SCurtis.Dunham@arm.com }; 88410324SCurtis.Dunham@arm.com static const GrainMap GM[] = { 88510324SCurtis.Dunham@arm.com { Grain4KB, { 39, 30, 0, 0 } }, 88610324SCurtis.Dunham@arm.com { Grain16KB, { 47, 36, 25, 0 } }, 88710324SCurtis.Dunham@arm.com { Grain64KB, { 64, 42, 29, 0 } } 88810324SCurtis.Dunham@arm.com }; 88910324SCurtis.Dunham@arm.com 89010324SCurtis.Dunham@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 89110324SCurtis.Dunham@arm.com 89210324SCurtis.Dunham@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 89310324SCurtis.Dunham@arm.com if (tg == GM[i].grain_size) { 89410324SCurtis.Dunham@arm.com lookup = GM[i].lookup_level_cutoff; 89510324SCurtis.Dunham@arm.com break; 89610324SCurtis.Dunham@arm.com } 89710324SCurtis.Dunham@arm.com } 89810324SCurtis.Dunham@arm.com assert(lookup); 89910324SCurtis.Dunham@arm.com 90010324SCurtis.Dunham@arm.com for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 90110324SCurtis.Dunham@arm.com if (tsz > lookup[L]) { 90210324SCurtis.Dunham@arm.com start_lookup_level = (LookupLevel) L; 90310324SCurtis.Dunham@arm.com break; 90410324SCurtis.Dunham@arm.com } 90510324SCurtis.Dunham@arm.com } 90610324SCurtis.Dunham@arm.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 90710324SCurtis.Dunham@arm.com "Table walker couldn't find lookup level\n"); 90810037SARM gem5 Developers } 90910037SARM gem5 Developers 91011575SDylan.Johnson@ARM.com int stride = tg - 3; 91111575SDylan.Johnson@ARM.com 91210037SARM gem5 Developers // Determine table base address 91310324SCurtis.Dunham@arm.com int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 91410037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 91510037SARM gem5 Developers 91610037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 91710037SARM gem5 Developers // necessary 91810037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 91910037SARM gem5 Developers // Clamp to lower limit 92010037SARM gem5 Developers if (pa_range > physAddrRange) 92110037SARM gem5 Developers currState->physAddrRange = physAddrRange; 92210037SARM gem5 Developers else 92310037SARM gem5 Developers currState->physAddrRange = pa_range; 92410037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 92510037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 92610037SARM gem5 Developers Fault f; 92710037SARM gem5 Developers if (currState->isFetch) 92810474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 92910474Sandreas.hansson@arm.com currState->vaddr_tainted, 93010474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 93110474Sandreas.hansson@arm.com isStage2, 93210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 93310037SARM gem5 Developers else 93410474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 93510474Sandreas.hansson@arm.com currState->vaddr_tainted, 93610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 93710474Sandreas.hansson@arm.com currState->isWrite, 93810474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 93910474Sandreas.hansson@arm.com isStage2, 94010474Sandreas.hansson@arm.com ArmFault::LpaeTran); 94110037SARM gem5 Developers 94210037SARM gem5 Developers 94310037SARM gem5 Developers if (currState->timing) { 94410037SARM gem5 Developers pending = false; 94510037SARM gem5 Developers nextWalk(currState->tc); 94610037SARM gem5 Developers currState = NULL; 94710037SARM gem5 Developers } else { 94810037SARM gem5 Developers currState->tc = NULL; 94910037SARM gem5 Developers currState->req = NULL; 95010037SARM gem5 Developers } 95110037SARM gem5 Developers return f; 95210037SARM gem5 Developers 95310037SARM gem5 Developers } 95410037SARM gem5 Developers 95510037SARM gem5 Developers // Determine descriptor address 95610037SARM gem5 Developers Addr desc_addr = base_addr | 95710037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 95810324SCurtis.Dunham@arm.com stride * (3 - start_lookup_level) + tg) << 3); 95910037SARM gem5 Developers 96010037SARM gem5 Developers // Trickbox address check 96111395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 96211395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 96310037SARM gem5 Developers if (f) { 96410037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 96510037SARM gem5 Developers if (currState->timing) { 96610037SARM gem5 Developers pending = false; 96710037SARM gem5 Developers nextWalk(currState->tc); 96810037SARM gem5 Developers currState = NULL; 96910037SARM gem5 Developers } else { 97010037SARM gem5 Developers currState->tc = NULL; 97110037SARM gem5 Developers currState->req = NULL; 97210037SARM gem5 Developers } 97310037SARM gem5 Developers return f; 97410037SARM gem5 Developers } 97510037SARM gem5 Developers 97610836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 97710037SARM gem5 Developers if (currState->sctlr.c == 0) { 97810836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 97910037SARM gem5 Developers } 98010037SARM gem5 Developers 98111181Snathananel.premillieu@arm.com if (currState->isSecure) { 98211181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 98311181Snathananel.premillieu@arm.com } 98411181Snathananel.premillieu@arm.com 98510037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 98610037SARM gem5 Developers currState->longDesc.aarch64 = true; 98710324SCurtis.Dunham@arm.com currState->longDesc.grainSize = tg; 98810037SARM gem5 Developers 9897439Sdam.sunwoo@arm.com if (currState->timing) { 99011588SCurtis.Dunham@arm.com fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data, 99111588SCurtis.Dunham@arm.com sizeof(uint64_t), flag, start_lookup_level, 99211588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], NULL); 99311579SDylan.Johnson@ARM.com } else { 99411575SDylan.Johnson@ARM.com fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 99511575SDylan.Johnson@ARM.com sizeof(uint64_t), flag, -1, NULL, 99611575SDylan.Johnson@ARM.com &TableWalker::doLongDescriptor); 9977439Sdam.sunwoo@arm.com f = currState->fault; 9987404SAli.Saidi@ARM.com } 9997404SAli.Saidi@ARM.com 10007439Sdam.sunwoo@arm.com return f; 10017404SAli.Saidi@ARM.com} 10027404SAli.Saidi@ARM.com 10037404SAli.Saidi@ARM.comvoid 10047439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 10057439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 10067404SAli.Saidi@ARM.com{ 10077439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 10087439Sdam.sunwoo@arm.com // variables 10097436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 10107436Sdam.sunwoo@arm.com te.shareable = false; // default value 10117582SAli.Saidi@arm.com te.nonCacheable = false; 101210037SARM gem5 Developers te.outerShareable = false; 10137439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 10147404SAli.Saidi@ARM.com switch(texcb) { 10157436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 10167404SAli.Saidi@ARM.com te.nonCacheable = true; 101710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 10187436Sdam.sunwoo@arm.com te.shareable = true; 10197436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10207436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10217404SAli.Saidi@ARM.com break; 10227436Sdam.sunwoo@arm.com case 1: // Shareable Device 10237436Sdam.sunwoo@arm.com te.nonCacheable = true; 102410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10257436Sdam.sunwoo@arm.com te.shareable = true; 10267436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10277436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10287436Sdam.sunwoo@arm.com break; 10297436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 103010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10317436Sdam.sunwoo@arm.com te.shareable = s; 10327436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10337436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10347436Sdam.sunwoo@arm.com break; 10357436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 103610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10377436Sdam.sunwoo@arm.com te.shareable = s; 10387436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10397436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10407436Sdam.sunwoo@arm.com break; 10417436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 10427436Sdam.sunwoo@arm.com te.nonCacheable = true; 104310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10447436Sdam.sunwoo@arm.com te.shareable = s; 10457436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10467436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10477436Sdam.sunwoo@arm.com break; 10487436Sdam.sunwoo@arm.com case 5: // Reserved 10497439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10507436Sdam.sunwoo@arm.com break; 10517436Sdam.sunwoo@arm.com case 6: // Implementation Defined 10527439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 10537436Sdam.sunwoo@arm.com break; 10547436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 105510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10567436Sdam.sunwoo@arm.com te.shareable = s; 10577436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10587436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10597436Sdam.sunwoo@arm.com break; 10607436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 10617436Sdam.sunwoo@arm.com te.nonCacheable = true; 106210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10637436Sdam.sunwoo@arm.com te.shareable = false; 10647436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10657436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10667436Sdam.sunwoo@arm.com break; 10677436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 10687439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10697436Sdam.sunwoo@arm.com break; 10707436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 107110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10727436Sdam.sunwoo@arm.com te.shareable = s; 10737404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 10747404SAli.Saidi@ARM.com te.nonCacheable = true; 10757436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 10767436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 10777404SAli.Saidi@ARM.com break; 10787436Sdam.sunwoo@arm.com default: 10797436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 10807404SAli.Saidi@ARM.com } 10817404SAli.Saidi@ARM.com } else { 10827438SAli.Saidi@ARM.com assert(tc); 108312499Sgiacomo.travaglini@arm.com PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, 108410037SARM gem5 Developers currState->tc, !currState->isSecure)); 108512499Sgiacomo.travaglini@arm.com NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, 108610037SARM gem5 Developers currState->tc, !currState->isSecure)); 10877436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 10887582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 10897404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 10907404SAli.Saidi@ARM.com case 0: 10917436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 10927436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 10937436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 109410037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 10957404SAli.Saidi@ARM.com break; 10967404SAli.Saidi@ARM.com case 1: 10977436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 10987436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 10997436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 110010037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 11017404SAli.Saidi@ARM.com break; 11027404SAli.Saidi@ARM.com case 2: 11037436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 11047436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 11057436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 110610037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 11077404SAli.Saidi@ARM.com break; 11087404SAli.Saidi@ARM.com case 3: 11097436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 11107436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 11117436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 111210037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 11137404SAli.Saidi@ARM.com break; 11147404SAli.Saidi@ARM.com case 4: 11157436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 11167436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 11177436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 111810037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 11197404SAli.Saidi@ARM.com break; 11207404SAli.Saidi@ARM.com case 5: 11217436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 11227436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 11237436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 112410037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 11257404SAli.Saidi@ARM.com break; 11267404SAli.Saidi@ARM.com case 6: 11277404SAli.Saidi@ARM.com panic("Imp defined type\n"); 11287404SAli.Saidi@ARM.com case 7: 11297436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 11307436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 11317436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 113210037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 11337404SAli.Saidi@ARM.com break; 11347404SAli.Saidi@ARM.com } 11357436Sdam.sunwoo@arm.com 11367436Sdam.sunwoo@arm.com switch(curr_tr) { 11377436Sdam.sunwoo@arm.com case 0: 11387436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 113910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 11407436Sdam.sunwoo@arm.com te.nonCacheable = true; 11417436Sdam.sunwoo@arm.com te.innerAttrs = 1; 11427436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11437436Sdam.sunwoo@arm.com te.shareable = true; 11447436Sdam.sunwoo@arm.com break; 11457436Sdam.sunwoo@arm.com case 1: 11467436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 11477436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 114810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 11497436Sdam.sunwoo@arm.com te.nonCacheable = true; 11507436Sdam.sunwoo@arm.com te.innerAttrs = 3; 11517436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11527436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 11537436Sdam.sunwoo@arm.com te.shareable = true; 11547436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 11557436Sdam.sunwoo@arm.com te.shareable = true; 11567436Sdam.sunwoo@arm.com break; 11577436Sdam.sunwoo@arm.com case 2: 11587436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 11597436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 116010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 11617436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 11627436Sdam.sunwoo@arm.com te.shareable = true; 11637436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 11647436Sdam.sunwoo@arm.com te.shareable = true; 11657436Sdam.sunwoo@arm.com break; 11667436Sdam.sunwoo@arm.com case 3: 11677436Sdam.sunwoo@arm.com panic("Reserved type"); 11687436Sdam.sunwoo@arm.com } 11697436Sdam.sunwoo@arm.com 117010037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 11717436Sdam.sunwoo@arm.com switch(curr_ir) { 11727436Sdam.sunwoo@arm.com case 0: 11737436Sdam.sunwoo@arm.com te.nonCacheable = true; 11747436Sdam.sunwoo@arm.com te.innerAttrs = 0; 11757436Sdam.sunwoo@arm.com break; 11767436Sdam.sunwoo@arm.com case 1: 11777436Sdam.sunwoo@arm.com te.innerAttrs = 5; 11787436Sdam.sunwoo@arm.com break; 11797436Sdam.sunwoo@arm.com case 2: 11807436Sdam.sunwoo@arm.com te.innerAttrs = 6; 11817436Sdam.sunwoo@arm.com break; 11827436Sdam.sunwoo@arm.com case 3: 11837436Sdam.sunwoo@arm.com te.innerAttrs = 7; 11847436Sdam.sunwoo@arm.com break; 11857436Sdam.sunwoo@arm.com } 11867436Sdam.sunwoo@arm.com 11877436Sdam.sunwoo@arm.com switch(curr_or) { 11887436Sdam.sunwoo@arm.com case 0: 11897436Sdam.sunwoo@arm.com te.nonCacheable = true; 11907436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11917436Sdam.sunwoo@arm.com break; 11927436Sdam.sunwoo@arm.com case 1: 11937436Sdam.sunwoo@arm.com te.outerAttrs = 1; 11947436Sdam.sunwoo@arm.com break; 11957436Sdam.sunwoo@arm.com case 2: 11967436Sdam.sunwoo@arm.com te.outerAttrs = 2; 11977436Sdam.sunwoo@arm.com break; 11987436Sdam.sunwoo@arm.com case 3: 11997436Sdam.sunwoo@arm.com te.outerAttrs = 3; 12007436Sdam.sunwoo@arm.com break; 12017436Sdam.sunwoo@arm.com } 12027436Sdam.sunwoo@arm.com } 12037404SAli.Saidi@ARM.com } 120410367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 120510367SAndrew.Bardsley@arm.com "outerAttrs: %d\n", 12067439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 120710037SARM gem5 Developers te.setAttributes(false); 120810037SARM gem5 Developers} 12097436Sdam.sunwoo@arm.com 121010037SARM gem5 Developersvoid 121110037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 121210037SARM gem5 Developers LongDescriptor &lDescriptor) 121310037SARM gem5 Developers{ 121410037SARM gem5 Developers assert(_haveLPAE); 12157436Sdam.sunwoo@arm.com 121610037SARM gem5 Developers uint8_t attr; 121710037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 121810037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 121910037SARM gem5 Developers // translation 122010037SARM gem5 Developers if (isStage2) { 122110037SARM gem5 Developers attr = lDescriptor.memAttr(); 122210037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 122310037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 12247436Sdam.sunwoo@arm.com 122510037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 122610037SARM gem5 Developers 122710037SARM gem5 Developers if (attr_3_2 == 0) { 122810037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 122910037SARM gem5 Developers : TlbEntry::MemoryType::Device; 123010037SARM gem5 Developers te.outerAttrs = 0; 123110037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 123210037SARM gem5 Developers te.nonCacheable = true; 123310037SARM gem5 Developers } else { 123410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 123510037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 123610037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 123710037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 123810037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 123910037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 124010037SARM gem5 Developers } 124110037SARM gem5 Developers } else { 124210037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 124310037SARM gem5 Developers 124410037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 124510037SARM gem5 Developers // value of SCTLR.TRE 124610421Sandreas.hansson@arm.com MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 124712499Sgiacomo.travaglini@arm.com int reg_as_int = snsBankedIndex(reg, currState->tc, 124812499Sgiacomo.travaglini@arm.com !currState->isSecure); 124910421Sandreas.hansson@arm.com uint32_t mair = currState->tc->readMiscReg(reg_as_int); 125010037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 125110037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 125210037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 125310037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 125410037SARM gem5 Developers 125510037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 125610037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 125710037SARM gem5 Developers // accordingly to provide the illusion of full support 125810037SARM gem5 Developers te.nonCacheable = false; 125910037SARM gem5 Developers 126010037SARM gem5 Developers switch (attr_7_4) { 126110037SARM gem5 Developers case 0x0: 126210037SARM gem5 Developers // Strongly-ordered or Device memory 126310037SARM gem5 Developers if (attr_3_0 == 0x0) 126410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 126510037SARM gem5 Developers else if (attr_3_0 == 0x4) 126610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 126710037SARM gem5 Developers else 126810037SARM gem5 Developers panic("Unpredictable behavior\n"); 126910037SARM gem5 Developers te.nonCacheable = true; 127010037SARM gem5 Developers te.outerAttrs = 0; 127110037SARM gem5 Developers break; 127210037SARM gem5 Developers case 0x4: 127310037SARM gem5 Developers // Normal memory, Outer Non-cacheable 127410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 127510037SARM gem5 Developers te.outerAttrs = 0; 127610037SARM gem5 Developers if (attr_3_0 == 0x4) 127710037SARM gem5 Developers // Inner Non-cacheable 127810037SARM gem5 Developers te.nonCacheable = true; 127910037SARM gem5 Developers else if (attr_3_0 < 0x8) 128010037SARM gem5 Developers panic("Unpredictable behavior\n"); 128110037SARM gem5 Developers break; 128210037SARM gem5 Developers case 0x8: 128310037SARM gem5 Developers case 0x9: 128410037SARM gem5 Developers case 0xa: 128510037SARM gem5 Developers case 0xb: 128610037SARM gem5 Developers case 0xc: 128710037SARM gem5 Developers case 0xd: 128810037SARM gem5 Developers case 0xe: 128910037SARM gem5 Developers case 0xf: 129010037SARM gem5 Developers if (attr_7_4 & 0x4) { 129110037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 129210037SARM gem5 Developers } else { 129310037SARM gem5 Developers te.outerAttrs = 0x2; 129410037SARM gem5 Developers } 129510037SARM gem5 Developers // Normal memory, Outer Cacheable 129610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 129710037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 129810037SARM gem5 Developers panic("Unpredictable behavior\n"); 129910037SARM gem5 Developers break; 130010037SARM gem5 Developers default: 130110037SARM gem5 Developers panic("Unpredictable behavior\n"); 130210037SARM gem5 Developers break; 130310037SARM gem5 Developers } 130410037SARM gem5 Developers 130510037SARM gem5 Developers switch (attr_3_0) { 130610037SARM gem5 Developers case 0x0: 130710037SARM gem5 Developers te.innerAttrs = 0x1; 130810037SARM gem5 Developers break; 130910037SARM gem5 Developers case 0x4: 131010037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 131110037SARM gem5 Developers break; 131210037SARM gem5 Developers case 0x8: 131310037SARM gem5 Developers case 0x9: 131410037SARM gem5 Developers case 0xA: 131510037SARM gem5 Developers case 0xB: 131610037SARM gem5 Developers te.innerAttrs = 6; 131710037SARM gem5 Developers break; 131810037SARM gem5 Developers case 0xC: 131910037SARM gem5 Developers case 0xD: 132010037SARM gem5 Developers case 0xE: 132110037SARM gem5 Developers case 0xF: 132210037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 132310037SARM gem5 Developers break; 132410037SARM gem5 Developers default: 132510037SARM gem5 Developers panic("Unpredictable behavior\n"); 132610037SARM gem5 Developers break; 132710037SARM gem5 Developers } 132810037SARM gem5 Developers } 132910037SARM gem5 Developers 133010037SARM gem5 Developers te.outerShareable = sh == 2; 133110037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 133210037SARM gem5 Developers te.setAttributes(true); 133310037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 133410037SARM gem5 Developers} 133510037SARM gem5 Developers 133610037SARM gem5 Developersvoid 133711583SDylan.Johnson@ARM.comTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, 133811583SDylan.Johnson@ARM.com LongDescriptor &lDescriptor) 133910037SARM gem5 Developers{ 134011583SDylan.Johnson@ARM.com uint8_t attr; 134111583SDylan.Johnson@ARM.com uint8_t attr_hi; 134211583SDylan.Johnson@ARM.com uint8_t attr_lo; 134311583SDylan.Johnson@ARM.com uint8_t sh = lDescriptor.sh(); 134410037SARM gem5 Developers 134511583SDylan.Johnson@ARM.com if (isStage2) { 134611583SDylan.Johnson@ARM.com attr = lDescriptor.memAttr(); 134711583SDylan.Johnson@ARM.com uint8_t attr_hi = (attr >> 2) & 0x3; 134811583SDylan.Johnson@ARM.com uint8_t attr_lo = attr & 0x3; 134911583SDylan.Johnson@ARM.com 135011583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh); 135111583SDylan.Johnson@ARM.com 135211583SDylan.Johnson@ARM.com if (attr_hi == 0) { 135311583SDylan.Johnson@ARM.com te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered 135411583SDylan.Johnson@ARM.com : TlbEntry::MemoryType::Device; 135511583SDylan.Johnson@ARM.com te.outerAttrs = 0; 135611583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 0 ? 1 : 3; 135711583SDylan.Johnson@ARM.com te.nonCacheable = true; 135811583SDylan.Johnson@ARM.com } else { 135911583SDylan.Johnson@ARM.com te.mtype = TlbEntry::MemoryType::Normal; 136011583SDylan.Johnson@ARM.com te.outerAttrs = attr_hi == 1 ? 0 : 136111583SDylan.Johnson@ARM.com attr_hi == 2 ? 2 : 1; 136211583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 1 ? 0 : 136311583SDylan.Johnson@ARM.com attr_lo == 2 ? 6 : 5; 136411938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 136511938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 136611938Snikos.nikoleris@arm.com te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) || 136711938Snikos.nikoleris@arm.com (attr_lo == 1) || (attr_lo == 2); 136811583SDylan.Johnson@ARM.com } 136911583SDylan.Johnson@ARM.com } else { 137011583SDylan.Johnson@ARM.com uint8_t attrIndx = lDescriptor.attrIndx(); 137111583SDylan.Johnson@ARM.com 137211583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 137311583SDylan.Johnson@ARM.com 137411583SDylan.Johnson@ARM.com // Select MAIR 137511583SDylan.Johnson@ARM.com uint64_t mair; 137611583SDylan.Johnson@ARM.com switch (currState->el) { 137711583SDylan.Johnson@ARM.com case EL0: 137811583SDylan.Johnson@ARM.com case EL1: 137911583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL1); 138011583SDylan.Johnson@ARM.com break; 138111583SDylan.Johnson@ARM.com case EL2: 138211583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL2); 138311583SDylan.Johnson@ARM.com break; 138411583SDylan.Johnson@ARM.com case EL3: 138511583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL3); 138611583SDylan.Johnson@ARM.com break; 138711583SDylan.Johnson@ARM.com default: 138811583SDylan.Johnson@ARM.com panic("Invalid exception level"); 138911583SDylan.Johnson@ARM.com break; 139011583SDylan.Johnson@ARM.com } 139111583SDylan.Johnson@ARM.com 139211583SDylan.Johnson@ARM.com // Select attributes 139311583SDylan.Johnson@ARM.com attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 139411583SDylan.Johnson@ARM.com attr_lo = bits(attr, 3, 0); 139511583SDylan.Johnson@ARM.com attr_hi = bits(attr, 7, 4); 139611583SDylan.Johnson@ARM.com 139711583SDylan.Johnson@ARM.com // Memory type 139811583SDylan.Johnson@ARM.com te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 139911583SDylan.Johnson@ARM.com 140011583SDylan.Johnson@ARM.com // Cacheability 140111583SDylan.Johnson@ARM.com te.nonCacheable = false; 140211938Snikos.nikoleris@arm.com if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory 140311938Snikos.nikoleris@arm.com te.nonCacheable = true; 140411938Snikos.nikoleris@arm.com } 140511938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 140611938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 140711938Snikos.nikoleris@arm.com switch (attr_hi) { 140811938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 140911938Snikos.nikoleris@arm.com case 0x4: // Normal memory, Outer Non-cacheable 141011938Snikos.nikoleris@arm.com case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 141111938Snikos.nikoleris@arm.com te.nonCacheable = true; 141211938Snikos.nikoleris@arm.com } 141311938Snikos.nikoleris@arm.com switch (attr_lo) { 141411938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 141511938Snikos.nikoleris@arm.com case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 141611938Snikos.nikoleris@arm.com warn_if(!attr_hi, "Unpredictable behavior"); 141712392Sjason@lowepower.com M5_FALLTHROUGH; 141811938Snikos.nikoleris@arm.com case 0x4: // Device-nGnRE memory or 141911938Snikos.nikoleris@arm.com // Normal memory, Inner Non-cacheable 142011938Snikos.nikoleris@arm.com case 0x8: // Device-nGRE memory or 142111938Snikos.nikoleris@arm.com // Normal memory, Inner Write-through non-transient 142211583SDylan.Johnson@ARM.com te.nonCacheable = true; 142311583SDylan.Johnson@ARM.com } 142411583SDylan.Johnson@ARM.com 142511583SDylan.Johnson@ARM.com te.shareable = sh == 2; 142611583SDylan.Johnson@ARM.com te.outerShareable = (sh & 0x2) ? true : false; 142711583SDylan.Johnson@ARM.com // Attributes formatted according to the 64-bit PAR 142811583SDylan.Johnson@ARM.com te.attributes = ((uint64_t) attr << 56) | 142911583SDylan.Johnson@ARM.com (1 << 11) | // LPAE bit 143011583SDylan.Johnson@ARM.com (te.ns << 9) | // NS bit 143111583SDylan.Johnson@ARM.com (sh << 7); 143210037SARM gem5 Developers } 14337404SAli.Saidi@ARM.com} 14347404SAli.Saidi@ARM.com 14357404SAli.Saidi@ARM.comvoid 14367404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 14377404SAli.Saidi@ARM.com{ 143810037SARM gem5 Developers if (currState->fault != NoFault) { 143910037SARM gem5 Developers return; 144010037SARM gem5 Developers } 144110037SARM gem5 Developers 144212526Schuan.zhu@arm.com currState->l1Desc.data = htog(currState->l1Desc.data, 144312526Schuan.zhu@arm.com byteOrder(currState->tc)); 144412526Schuan.zhu@arm.com 14457439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 144610037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 14477404SAli.Saidi@ARM.com TlbEntry te; 14487404SAli.Saidi@ARM.com 14497439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 14507404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 14517404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 14527946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 14537439Sdam.sunwoo@arm.com currState->tc = NULL; 14547439Sdam.sunwoo@arm.com currState->req = NULL; 14557437Sdam.sunwoo@arm.com } 14567406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 14577439Sdam.sunwoo@arm.com if (currState->isFetch) 14587439Sdam.sunwoo@arm.com currState->fault = 145910474Sandreas.hansson@arm.com std::make_shared<PrefetchAbort>( 146010474Sandreas.hansson@arm.com currState->vaddr_tainted, 146110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 146210474Sandreas.hansson@arm.com isStage2, 146310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14647406SAli.Saidi@ARM.com else 14657439Sdam.sunwoo@arm.com currState->fault = 146610474Sandreas.hansson@arm.com std::make_shared<DataAbort>( 146710474Sandreas.hansson@arm.com currState->vaddr_tainted, 146810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 146910474Sandreas.hansson@arm.com currState->isWrite, 147010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 147110474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14727404SAli.Saidi@ARM.com return; 14737404SAli.Saidi@ARM.com case L1Descriptor::Section: 14747439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 14757436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 14767436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 14777436Sdam.sunwoo@arm.com * AccessFlag0 14787436Sdam.sunwoo@arm.com */ 14797436Sdam.sunwoo@arm.com 148010474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 148110474Sandreas.hansson@arm.com currState->vaddr_tainted, 148210474Sandreas.hansson@arm.com currState->l1Desc.domain(), 148310474Sandreas.hansson@arm.com currState->isWrite, 148410474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L1, 148510474Sandreas.hansson@arm.com isStage2, 148610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14877436Sdam.sunwoo@arm.com } 14887439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 14897404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 14907404SAli.Saidi@ARM.com } 149110037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 149210037SARM gem5 Developers return; 149310037SARM gem5 Developers case L1Descriptor::PageTable: 149410037SARM gem5 Developers { 149510037SARM gem5 Developers Addr l2desc_addr; 149610037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 149710037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 149810037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 149910037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 15007404SAli.Saidi@ARM.com 150110037SARM gem5 Developers // Trickbox address check 150211395Sandreas.sandberg@arm.com currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 150311395Sandreas.sandberg@arm.com currState->l1Desc.domain(), L2); 15047404SAli.Saidi@ARM.com 150510037SARM gem5 Developers if (currState->fault) { 150610037SARM gem5 Developers if (!currState->timing) { 150710037SARM gem5 Developers currState->tc = NULL; 150810037SARM gem5 Developers currState->req = NULL; 150910037SARM gem5 Developers } 151010037SARM gem5 Developers return; 151110037SARM gem5 Developers } 151210037SARM gem5 Developers 151310836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 151410037SARM gem5 Developers if (currState->isSecure) 151510037SARM gem5 Developers flag.set(Request::SECURE); 151610037SARM gem5 Developers 151710037SARM gem5 Developers bool delayed; 151810037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 151910037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 152010037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 152110037SARM gem5 Developers &TableWalker::doL2Descriptor); 152210037SARM gem5 Developers if (delayed) { 152310037SARM gem5 Developers currState->delayed = true; 152410037SARM gem5 Developers } 152510037SARM gem5 Developers 152610037SARM gem5 Developers return; 152710037SARM gem5 Developers } 152810037SARM gem5 Developers default: 152910037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 153010037SARM gem5 Developers } 153110037SARM gem5 Developers} 153210037SARM gem5 Developers 153310037SARM gem5 Developersvoid 153410037SARM gem5 DevelopersTableWalker::doLongDescriptor() 153510037SARM gem5 Developers{ 153610037SARM gem5 Developers if (currState->fault != NoFault) { 153710037SARM gem5 Developers return; 153810037SARM gem5 Developers } 153910037SARM gem5 Developers 154012526Schuan.zhu@arm.com currState->longDesc.data = htog(currState->longDesc.data, 154112526Schuan.zhu@arm.com byteOrder(currState->tc)); 154212526Schuan.zhu@arm.com 154310037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 154410037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 154510037SARM gem5 Developers currState->longDesc.data, 154610037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 154710037SARM gem5 Developers 154810037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 154910037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 155010037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 155110037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 155210037SARM gem5 Developers currState->longDesc.lookupLevel, 155310037SARM gem5 Developers currState->longDesc.data, 155410037SARM gem5 Developers currState->longDesc.pxn(), 155510037SARM gem5 Developers currState->longDesc.xn(), 155610037SARM gem5 Developers currState->longDesc.ap(), 155710037SARM gem5 Developers currState->longDesc.af(), 155810037SARM gem5 Developers currState->longDesc.type()); 155910037SARM gem5 Developers } else { 156010037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 156110037SARM gem5 Developers currState->longDesc.lookupLevel, 156210037SARM gem5 Developers currState->longDesc.data, 156310037SARM gem5 Developers currState->longDesc.type()); 156410037SARM gem5 Developers } 156510037SARM gem5 Developers 156610037SARM gem5 Developers TlbEntry te; 156710037SARM gem5 Developers 156810037SARM gem5 Developers switch (currState->longDesc.type()) { 156910037SARM gem5 Developers case LongDescriptor::Invalid: 15707439Sdam.sunwoo@arm.com if (!currState->timing) { 15717439Sdam.sunwoo@arm.com currState->tc = NULL; 15727439Sdam.sunwoo@arm.com currState->req = NULL; 15737437Sdam.sunwoo@arm.com } 15747404SAli.Saidi@ARM.com 157510037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 157610037SARM gem5 Developers currState->longDesc.lookupLevel, 157710037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 157810037SARM gem5 Developers if (currState->isFetch) 157910474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 158010037SARM gem5 Developers currState->vaddr_tainted, 158110037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 158210037SARM gem5 Developers isStage2, 158310037SARM gem5 Developers ArmFault::LpaeTran); 158410037SARM gem5 Developers else 158510474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 158610037SARM gem5 Developers currState->vaddr_tainted, 158710037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 158810037SARM gem5 Developers currState->isWrite, 158910037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 159010037SARM gem5 Developers isStage2, 159110037SARM gem5 Developers ArmFault::LpaeTran); 15927404SAli.Saidi@ARM.com return; 159310037SARM gem5 Developers case LongDescriptor::Block: 159410037SARM gem5 Developers case LongDescriptor::Page: 159510037SARM gem5 Developers { 159610037SARM gem5 Developers bool fault = false; 159710037SARM gem5 Developers bool aff = false; 159810037SARM gem5 Developers // Check for address size fault 159910037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 160010037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 160110037SARM gem5 Developers currState->longDesc.offsetBits()), 160210037SARM gem5 Developers currState->physAddrRange)) { 160310037SARM gem5 Developers fault = true; 160410037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 160510037SARM gem5 Developers currState->longDesc.lookupLevel); 160610037SARM gem5 Developers // Check for access fault 160710037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 160810037SARM gem5 Developers fault = true; 160910037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 161010037SARM gem5 Developers currState->longDesc.lookupLevel); 161110037SARM gem5 Developers aff = true; 161210037SARM gem5 Developers } 161310037SARM gem5 Developers if (fault) { 161410037SARM gem5 Developers if (currState->isFetch) 161510474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 161610037SARM gem5 Developers currState->vaddr_tainted, 161710037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 161810037SARM gem5 Developers currState->longDesc.lookupLevel, 161910037SARM gem5 Developers isStage2, 162010037SARM gem5 Developers ArmFault::LpaeTran); 162110037SARM gem5 Developers else 162210474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 162310037SARM gem5 Developers currState->vaddr_tainted, 162410037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 162510037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 162610037SARM gem5 Developers currState->longDesc.lookupLevel, 162710037SARM gem5 Developers isStage2, 162810037SARM gem5 Developers ArmFault::LpaeTran); 162910037SARM gem5 Developers } else { 163010037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 163110037SARM gem5 Developers } 163210037SARM gem5 Developers } 163310037SARM gem5 Developers return; 163410037SARM gem5 Developers case LongDescriptor::Table: 163510037SARM gem5 Developers { 163610037SARM gem5 Developers // Set hierarchical permission flags 163710037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 163810037SARM gem5 Developers currState->longDesc.secureTable(); 163910037SARM gem5 Developers currState->rwTable = currState->rwTable && 164010037SARM gem5 Developers currState->longDesc.rwTable(); 164110037SARM gem5 Developers currState->userTable = currState->userTable && 164210037SARM gem5 Developers currState->longDesc.userTable(); 164310037SARM gem5 Developers currState->xnTable = currState->xnTable || 164410037SARM gem5 Developers currState->longDesc.xnTable(); 164510037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 164610037SARM gem5 Developers currState->longDesc.pxnTable(); 16477404SAli.Saidi@ARM.com 164810037SARM gem5 Developers // Set up next level lookup 164910037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 165010037SARM gem5 Developers currState->vaddr); 16517439Sdam.sunwoo@arm.com 165210037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 165310037SARM gem5 Developers currState->longDesc.lookupLevel, 165410037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 165510037SARM gem5 Developers next_desc_addr, 165610037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 165710037SARM gem5 Developers 165810037SARM gem5 Developers // Check for address size fault 165910037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 166010037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 166110037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 166210037SARM gem5 Developers currState->longDesc.lookupLevel); 166310037SARM gem5 Developers if (currState->isFetch) 166410474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 166510037SARM gem5 Developers currState->vaddr_tainted, 166610037SARM gem5 Developers ArmFault::AddressSizeLL 166710037SARM gem5 Developers + currState->longDesc.lookupLevel, 166810037SARM gem5 Developers isStage2, 166910037SARM gem5 Developers ArmFault::LpaeTran); 167010037SARM gem5 Developers else 167110474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 167210037SARM gem5 Developers currState->vaddr_tainted, 167310037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 167410037SARM gem5 Developers ArmFault::AddressSizeLL 167510037SARM gem5 Developers + currState->longDesc.lookupLevel, 167610037SARM gem5 Developers isStage2, 167710037SARM gem5 Developers ArmFault::LpaeTran); 167810037SARM gem5 Developers return; 16797437Sdam.sunwoo@arm.com } 16807404SAli.Saidi@ARM.com 168110037SARM gem5 Developers // Trickbox address check 168211395Sandreas.sandberg@arm.com currState->fault = testWalk( 168311395Sandreas.sandberg@arm.com next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 168411395Sandreas.sandberg@arm.com toLookupLevel(currState->longDesc.lookupLevel +1)); 16857404SAli.Saidi@ARM.com 168610037SARM gem5 Developers if (currState->fault) { 168710037SARM gem5 Developers if (!currState->timing) { 168810037SARM gem5 Developers currState->tc = NULL; 168910037SARM gem5 Developers currState->req = NULL; 169010037SARM gem5 Developers } 169110037SARM gem5 Developers return; 169210037SARM gem5 Developers } 169310037SARM gem5 Developers 169410836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 169510037SARM gem5 Developers if (currState->secureLookup) 169610037SARM gem5 Developers flag.set(Request::SECURE); 169710037SARM gem5 Developers 169811588SCurtis.Dunham@arm.com LookupLevel L = currState->longDesc.lookupLevel = 169910037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 170010037SARM gem5 Developers Event *event = NULL; 170111588SCurtis.Dunham@arm.com switch (L) { 170210037SARM gem5 Developers case L1: 170310037SARM gem5 Developers assert(currState->aarch64); 170410037SARM gem5 Developers case L2: 170510037SARM gem5 Developers case L3: 170611588SCurtis.Dunham@arm.com event = LongDescEventByLevel[L]; 170710037SARM gem5 Developers break; 170810037SARM gem5 Developers default: 170910037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 171010037SARM gem5 Developers break; 171110037SARM gem5 Developers } 171210037SARM gem5 Developers 171310037SARM gem5 Developers bool delayed; 171410037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 171510037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 171610037SARM gem5 Developers &TableWalker::doLongDescriptor); 171710037SARM gem5 Developers if (delayed) { 171810037SARM gem5 Developers currState->delayed = true; 171910037SARM gem5 Developers } 17207404SAli.Saidi@ARM.com } 17217404SAli.Saidi@ARM.com return; 17227404SAli.Saidi@ARM.com default: 17237404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 17247404SAli.Saidi@ARM.com } 17257404SAli.Saidi@ARM.com} 17267404SAli.Saidi@ARM.com 17277404SAli.Saidi@ARM.comvoid 17287404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 17297404SAli.Saidi@ARM.com{ 173010037SARM gem5 Developers if (currState->fault != NoFault) { 173110037SARM gem5 Developers return; 173210037SARM gem5 Developers } 173310037SARM gem5 Developers 173412526Schuan.zhu@arm.com currState->l2Desc.data = htog(currState->l2Desc.data, 173512526Schuan.zhu@arm.com byteOrder(currState->tc)); 173612526Schuan.zhu@arm.com 17377439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 173810037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 17397404SAli.Saidi@ARM.com TlbEntry te; 17407404SAli.Saidi@ARM.com 17417439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 17427404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 17437946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 17447439Sdam.sunwoo@arm.com currState->tc = NULL; 17457439Sdam.sunwoo@arm.com currState->req = NULL; 17467437Sdam.sunwoo@arm.com } 17477439Sdam.sunwoo@arm.com if (currState->isFetch) 174810474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 174910474Sandreas.hansson@arm.com currState->vaddr_tainted, 175010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L2, 175110474Sandreas.hansson@arm.com isStage2, 175210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17537406SAli.Saidi@ARM.com else 175410474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 175510474Sandreas.hansson@arm.com currState->vaddr_tainted, currState->l1Desc.domain(), 175610474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L2, 175710474Sandreas.hansson@arm.com isStage2, 175810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17597404SAli.Saidi@ARM.com return; 17607404SAli.Saidi@ARM.com } 17617404SAli.Saidi@ARM.com 17627439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 17637436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 17647436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 17657436Sdam.sunwoo@arm.com */ 176610037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 176710037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 17687436Sdam.sunwoo@arm.com 176910474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 177010474Sandreas.hansson@arm.com currState->vaddr_tainted, 177110474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 177210474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L2, isStage2, 177310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17747436Sdam.sunwoo@arm.com } 17757436Sdam.sunwoo@arm.com 177610037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 17777437Sdam.sunwoo@arm.com} 17787437Sdam.sunwoo@arm.com 17797437Sdam.sunwoo@arm.comvoid 17807437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 17817437Sdam.sunwoo@arm.com{ 178210037SARM gem5 Developers currState = stateQueues[L1].front(); 17837439Sdam.sunwoo@arm.com currState->delayed = false; 178410037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 178510037SARM gem5 Developers if (currState->stage2Tran) { 178610037SARM gem5 Developers delete currState->stage2Tran; 178710037SARM gem5 Developers currState->stage2Tran = NULL; 178810037SARM gem5 Developers } 178910037SARM gem5 Developers 17907437Sdam.sunwoo@arm.com 17917578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 17927578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 17937578Sdam.sunwoo@arm.com 179410037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 17957437Sdam.sunwoo@arm.com doL1Descriptor(); 17967437Sdam.sunwoo@arm.com 179710037SARM gem5 Developers stateQueues[L1].pop_front(); 17987437Sdam.sunwoo@arm.com // Check if fault was generated 17997439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18007439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18017439Sdam.sunwoo@arm.com currState->tc, currState->mode); 180210621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 18037437Sdam.sunwoo@arm.com 18047728SAli.Saidi@ARM.com pending = false; 18057728SAli.Saidi@ARM.com nextWalk(currState->tc); 18067728SAli.Saidi@ARM.com 18077439Sdam.sunwoo@arm.com currState->req = NULL; 18087439Sdam.sunwoo@arm.com currState->tc = NULL; 18097439Sdam.sunwoo@arm.com currState->delayed = false; 18108510SAli.Saidi@ARM.com delete currState; 18117437Sdam.sunwoo@arm.com } 18127439Sdam.sunwoo@arm.com else if (!currState->delayed) { 18137653Sgene.wu@arm.com // delay is not set so there is no L2 to do 181410037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 181512738Sandreas.sandberg@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 181612738Sandreas.sandberg@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 181712738Sandreas.sandberg@arm.com tlb->translateTiming(currState->req, currState->tc, 181812738Sandreas.sandberg@arm.com currState->transState, currState->mode); 181912738Sandreas.sandberg@arm.com statWalksShortTerminatedAtLevel[0]++; 18207437Sdam.sunwoo@arm.com 18217728SAli.Saidi@ARM.com pending = false; 18227728SAli.Saidi@ARM.com nextWalk(currState->tc); 18237728SAli.Saidi@ARM.com 18247439Sdam.sunwoo@arm.com currState->req = NULL; 18257439Sdam.sunwoo@arm.com currState->tc = NULL; 18267439Sdam.sunwoo@arm.com currState->delayed = false; 18277653Sgene.wu@arm.com delete currState; 18287653Sgene.wu@arm.com } else { 18297653Sgene.wu@arm.com // need to do L2 descriptor 183010037SARM gem5 Developers stateQueues[L2].push_back(currState); 18317437Sdam.sunwoo@arm.com } 18327439Sdam.sunwoo@arm.com currState = NULL; 18337437Sdam.sunwoo@arm.com} 18347437Sdam.sunwoo@arm.com 18357437Sdam.sunwoo@arm.comvoid 18367437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 18377437Sdam.sunwoo@arm.com{ 183810037SARM gem5 Developers currState = stateQueues[L2].front(); 18397439Sdam.sunwoo@arm.com assert(currState->delayed); 184010037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 184110037SARM gem5 Developers if (currState->stage2Tran) { 184210037SARM gem5 Developers delete currState->stage2Tran; 184310037SARM gem5 Developers currState->stage2Tran = NULL; 184410037SARM gem5 Developers } 18457437Sdam.sunwoo@arm.com 18467439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 184710037SARM gem5 Developers currState->vaddr_tainted); 18487437Sdam.sunwoo@arm.com doL2Descriptor(); 18497437Sdam.sunwoo@arm.com 18507437Sdam.sunwoo@arm.com // Check if fault was generated 18517439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18527439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18537439Sdam.sunwoo@arm.com currState->tc, currState->mode); 185410621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 185512738Sandreas.sandberg@arm.com } else { 185612738Sandreas.sandberg@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 185712738Sandreas.sandberg@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 185812738Sandreas.sandberg@arm.com tlb->translateTiming(currState->req, currState->tc, 185912738Sandreas.sandberg@arm.com currState->transState, currState->mode); 186012738Sandreas.sandberg@arm.com statWalksShortTerminatedAtLevel[1]++; 18617437Sdam.sunwoo@arm.com } 18627437Sdam.sunwoo@arm.com 18637728SAli.Saidi@ARM.com 186410037SARM gem5 Developers stateQueues[L2].pop_front(); 18657728SAli.Saidi@ARM.com pending = false; 18667728SAli.Saidi@ARM.com nextWalk(currState->tc); 18677728SAli.Saidi@ARM.com 18687439Sdam.sunwoo@arm.com currState->req = NULL; 18697439Sdam.sunwoo@arm.com currState->tc = NULL; 18707439Sdam.sunwoo@arm.com currState->delayed = false; 18717439Sdam.sunwoo@arm.com 18727653Sgene.wu@arm.com delete currState; 18737439Sdam.sunwoo@arm.com currState = NULL; 18747404SAli.Saidi@ARM.com} 18757404SAli.Saidi@ARM.com 18767728SAli.Saidi@ARM.comvoid 187710037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 187810037SARM gem5 Developers{ 187910037SARM gem5 Developers doLongDescriptorWrapper(L0); 188010037SARM gem5 Developers} 188110037SARM gem5 Developers 188210037SARM gem5 Developersvoid 188310037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 188410037SARM gem5 Developers{ 188510037SARM gem5 Developers doLongDescriptorWrapper(L1); 188610037SARM gem5 Developers} 188710037SARM gem5 Developers 188810037SARM gem5 Developersvoid 188910037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 189010037SARM gem5 Developers{ 189110037SARM gem5 Developers doLongDescriptorWrapper(L2); 189210037SARM gem5 Developers} 189310037SARM gem5 Developers 189410037SARM gem5 Developersvoid 189510037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 189610037SARM gem5 Developers{ 189710037SARM gem5 Developers doLongDescriptorWrapper(L3); 189810037SARM gem5 Developers} 189910037SARM gem5 Developers 190010037SARM gem5 Developersvoid 190110037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 190210037SARM gem5 Developers{ 190310037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 190410037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 190510037SARM gem5 Developers currState->delayed = false; 190610037SARM gem5 Developers 190710037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 190810037SARM gem5 Developers if (currState->stage2Tran) { 190910037SARM gem5 Developers delete currState->stage2Tran; 191010037SARM gem5 Developers currState->stage2Tran = NULL; 191110037SARM gem5 Developers } 191210037SARM gem5 Developers 191310037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 191410037SARM gem5 Developers currState->vaddr_tainted); 191510037SARM gem5 Developers doLongDescriptor(); 191610037SARM gem5 Developers 191710037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 191810037SARM gem5 Developers 191910037SARM gem5 Developers if (currState->fault != NoFault) { 192010037SARM gem5 Developers // A fault was generated 192110037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 192210037SARM gem5 Developers currState->tc, currState->mode); 192310037SARM gem5 Developers 192410037SARM gem5 Developers pending = false; 192510037SARM gem5 Developers nextWalk(currState->tc); 192610037SARM gem5 Developers 192710037SARM gem5 Developers currState->req = NULL; 192810037SARM gem5 Developers currState->tc = NULL; 192910037SARM gem5 Developers currState->delayed = false; 193010037SARM gem5 Developers delete currState; 193110037SARM gem5 Developers } else if (!currState->delayed) { 193210037SARM gem5 Developers // No additional lookups required 193312738Sandreas.sandberg@arm.com DPRINTF(TLBVerbose, "calling translateTiming again\n"); 193412738Sandreas.sandberg@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 193512738Sandreas.sandberg@arm.com tlb->translateTiming(currState->req, currState->tc, 193612738Sandreas.sandberg@arm.com currState->transState, currState->mode); 193712738Sandreas.sandberg@arm.com statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 193810037SARM gem5 Developers 193910037SARM gem5 Developers pending = false; 194010037SARM gem5 Developers nextWalk(currState->tc); 194110037SARM gem5 Developers 194210037SARM gem5 Developers currState->req = NULL; 194310037SARM gem5 Developers currState->tc = NULL; 194410037SARM gem5 Developers currState->delayed = false; 194510037SARM gem5 Developers delete currState; 194610037SARM gem5 Developers } else { 194710037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 194810037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 194910037SARM gem5 Developers // Need to perform additional lookups 195010037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 195110037SARM gem5 Developers } 195210037SARM gem5 Developers currState = NULL; 195310037SARM gem5 Developers} 195410037SARM gem5 Developers 195510037SARM gem5 Developers 195610037SARM gem5 Developersvoid 19577728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 19587728SAli.Saidi@ARM.com{ 19597728SAli.Saidi@ARM.com if (pendingQueue.size()) 19609309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 196110509SAli.Saidi@ARM.com else 196210509SAli.Saidi@ARM.com completeDrain(); 19637728SAli.Saidi@ARM.com} 19647728SAli.Saidi@ARM.com 196510037SARM gem5 Developersbool 196610037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 196710037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 196810037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 196910037SARM gem5 Developers{ 197010037SARM gem5 Developers bool isTiming = currState->timing; 19717728SAli.Saidi@ARM.com 197211575SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 197311575SDylan.Johnson@ARM.com descAddr, currState->stage2Req); 197411575SDylan.Johnson@ARM.com 197511575SDylan.Johnson@ARM.com // If this translation has a stage 2 then we know descAddr is an IPA and 197611575SDylan.Johnson@ARM.com // needs to be translated before we can access the page table. Do that 197711575SDylan.Johnson@ARM.com // check here. 197810037SARM gem5 Developers if (currState->stage2Req) { 197910037SARM gem5 Developers Fault fault; 198010037SARM gem5 Developers flags = flags | TLB::MustBeOne; 198110037SARM gem5 Developers 198210037SARM gem5 Developers if (isTiming) { 198310037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 198410037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 198510037SARM gem5 Developers currState->vaddr); 198610037SARM gem5 Developers currState->stage2Tran = tran; 198710037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 198810717Sandreas.hansson@arm.com flags); 198910037SARM gem5 Developers fault = tran->fault; 199010037SARM gem5 Developers } else { 199110037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 199210717Sandreas.hansson@arm.com currState->vaddr, descAddr, data, numBytes, flags, 199310037SARM gem5 Developers currState->functional); 199410037SARM gem5 Developers } 199510037SARM gem5 Developers 199610037SARM gem5 Developers if (fault != NoFault) { 199710037SARM gem5 Developers currState->fault = fault; 199810037SARM gem5 Developers } 199910037SARM gem5 Developers if (isTiming) { 200010037SARM gem5 Developers if (queueIndex >= 0) { 200110037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 200210037SARM gem5 Developers stateQueues[queueIndex].size()); 200310037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 200410037SARM gem5 Developers currState = NULL; 200510037SARM gem5 Developers } 200610037SARM gem5 Developers } else { 200710037SARM gem5 Developers (this->*doDescriptor)(); 200810037SARM gem5 Developers } 200910037SARM gem5 Developers } else { 201010037SARM gem5 Developers if (isTiming) { 201110717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 201210621SCurtis.Dunham@arm.com currState->tc->getCpuPtr()->clockPeriod(),flags); 201310037SARM gem5 Developers if (queueIndex >= 0) { 201410037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 201510037SARM gem5 Developers stateQueues[queueIndex].size()); 201610037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 201710037SARM gem5 Developers currState = NULL; 201810037SARM gem5 Developers } 201910037SARM gem5 Developers } else if (!currState->functional) { 202010717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 202110037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 202210037SARM gem5 Developers (this->*doDescriptor)(); 202310037SARM gem5 Developers } else { 202412749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 202512749Sgiacomo.travaglini@arm.com descAddr, numBytes, flags, masterId); 202612749Sgiacomo.travaglini@arm.com 202710037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 202810037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 202910037SARM gem5 Developers pkt->dataStatic(data); 203010717Sandreas.hansson@arm.com port->sendFunctional(pkt); 203110037SARM gem5 Developers (this->*doDescriptor)(); 203210037SARM gem5 Developers delete pkt; 203310037SARM gem5 Developers } 203410037SARM gem5 Developers } 203510037SARM gem5 Developers return (isTiming); 203610037SARM gem5 Developers} 203710037SARM gem5 Developers 203810037SARM gem5 Developersvoid 203910037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 204010037SARM gem5 Developers{ 204110037SARM gem5 Developers TlbEntry te; 204210037SARM gem5 Developers 204310037SARM gem5 Developers // Create and fill a new page table entry 204410037SARM gem5 Developers te.valid = true; 204510037SARM gem5 Developers te.longDescFormat = longDescriptor; 204610037SARM gem5 Developers te.isHyp = currState->isHyp; 204710037SARM gem5 Developers te.asid = currState->asid; 204810037SARM gem5 Developers te.vmid = currState->vmid; 204910037SARM gem5 Developers te.N = descriptor.offsetBits(); 205010037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 205110037SARM gem5 Developers te.size = (1<<te.N) - 1; 205210037SARM gem5 Developers te.pfn = descriptor.pfn(); 205310037SARM gem5 Developers te.domain = descriptor.domain(); 205410037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 205510037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 205610037SARM gem5 Developers te.nstid = !currState->isSecure; 205710037SARM gem5 Developers te.xn = descriptor.xn(); 205810037SARM gem5 Developers if (currState->aarch64) 205910037SARM gem5 Developers te.el = currState->el; 206010037SARM gem5 Developers else 206110037SARM gem5 Developers te.el = 1; 206210037SARM gem5 Developers 206310621SCurtis.Dunham@arm.com statPageSizes[pageSizeNtoStatBin(te.N)]++; 206410621SCurtis.Dunham@arm.com statRequestOrigin[COMPLETED][currState->isFetch]++; 206510621SCurtis.Dunham@arm.com 206610037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 206710037SARM gem5 Developers // as global 206810037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 206910037SARM gem5 Developers if (longDescriptor) { 207010037SARM gem5 Developers LongDescriptor lDescriptor = 207110037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 207210037SARM gem5 Developers 207310037SARM gem5 Developers te.xn |= currState->xnTable; 207410037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 207510037SARM gem5 Developers if (isStage2) { 207610037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 207710037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 207810037SARM gem5 Developers te.hap = lDescriptor.ap(); 207910037SARM gem5 Developers } else { 208010037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 208110037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 208210037SARM gem5 Developers } 208310037SARM gem5 Developers if (currState->aarch64) 208411583SDylan.Johnson@ARM.com memAttrsAArch64(currState->tc, te, lDescriptor); 208510037SARM gem5 Developers else 208610037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 208710037SARM gem5 Developers } else { 208810037SARM gem5 Developers te.ap = descriptor.ap(); 208910037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 209010037SARM gem5 Developers descriptor.shareable()); 209110037SARM gem5 Developers } 209210037SARM gem5 Developers 209310037SARM gem5 Developers // Debug output 209410037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 209510037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 209610037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 209710037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 209810037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 209910037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 210010037SARM gem5 Developers te.nonCacheable, te.ns); 210110037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 210210037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 210310037SARM gem5 Developers descriptor.getRawData()); 210410037SARM gem5 Developers 210510037SARM gem5 Developers // Insert the entry into the TLB 210610037SARM gem5 Developers tlb->insert(currState->vaddr, te); 210710037SARM gem5 Developers if (!currState->timing) { 210810037SARM gem5 Developers currState->tc = NULL; 210910037SARM gem5 Developers currState->req = NULL; 211010037SARM gem5 Developers } 211110037SARM gem5 Developers} 21127728SAli.Saidi@ARM.com 21137404SAli.Saidi@ARM.comArmISA::TableWalker * 21147404SAli.Saidi@ARM.comArmTableWalkerParams::create() 21157404SAli.Saidi@ARM.com{ 21167404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 21177404SAli.Saidi@ARM.com} 21187404SAli.Saidi@ARM.com 211910037SARM gem5 DevelopersLookupLevel 212010037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 212110037SARM gem5 Developers{ 212210037SARM gem5 Developers switch (lookup_level_as_int) { 212310037SARM gem5 Developers case L1: 212410037SARM gem5 Developers return L1; 212510037SARM gem5 Developers case L2: 212610037SARM gem5 Developers return L2; 212710037SARM gem5 Developers case L3: 212810037SARM gem5 Developers return L3; 212910037SARM gem5 Developers default: 213010037SARM gem5 Developers panic("Invalid lookup level conversion"); 213110037SARM gem5 Developers } 213210037SARM gem5 Developers} 213310621SCurtis.Dunham@arm.com 213410621SCurtis.Dunham@arm.com/* this method keeps track of the table walker queue's residency, so 213510621SCurtis.Dunham@arm.com * needs to be called whenever requests start and complete. */ 213610621SCurtis.Dunham@arm.comvoid 213710621SCurtis.Dunham@arm.comTableWalker::pendingChange() 213810621SCurtis.Dunham@arm.com{ 213910621SCurtis.Dunham@arm.com unsigned n = pendingQueue.size(); 214010621SCurtis.Dunham@arm.com if ((currState != NULL) && (currState != pendingQueue.front())) { 214110621SCurtis.Dunham@arm.com ++n; 214210621SCurtis.Dunham@arm.com } 214310621SCurtis.Dunham@arm.com 214410621SCurtis.Dunham@arm.com if (n != pendingReqs) { 214510621SCurtis.Dunham@arm.com Tick now = curTick(); 214610621SCurtis.Dunham@arm.com statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 214710621SCurtis.Dunham@arm.com pendingReqs = n; 214810621SCurtis.Dunham@arm.com pendingChangeTick = now; 214910621SCurtis.Dunham@arm.com } 215010621SCurtis.Dunham@arm.com} 215110621SCurtis.Dunham@arm.com 215211395Sandreas.sandberg@arm.comFault 215311395Sandreas.sandberg@arm.comTableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 215411395Sandreas.sandberg@arm.com LookupLevel lookup_level) 215511395Sandreas.sandberg@arm.com{ 215611395Sandreas.sandberg@arm.com return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 215711395Sandreas.sandberg@arm.com currState->mode, domain, lookup_level); 215811395Sandreas.sandberg@arm.com} 215911395Sandreas.sandberg@arm.com 216011395Sandreas.sandberg@arm.com 216110621SCurtis.Dunham@arm.comuint8_t 216210621SCurtis.Dunham@arm.comTableWalker::pageSizeNtoStatBin(uint8_t N) 216310621SCurtis.Dunham@arm.com{ 216410621SCurtis.Dunham@arm.com /* for statPageSizes */ 216510621SCurtis.Dunham@arm.com switch(N) { 216610621SCurtis.Dunham@arm.com case 12: return 0; // 4K 216710621SCurtis.Dunham@arm.com case 14: return 1; // 16K (using 16K granule in v8-64) 216810621SCurtis.Dunham@arm.com case 16: return 2; // 64K 216910621SCurtis.Dunham@arm.com case 20: return 3; // 1M 217010621SCurtis.Dunham@arm.com case 21: return 4; // 2M-LPAE 217110621SCurtis.Dunham@arm.com case 24: return 5; // 16M 217210621SCurtis.Dunham@arm.com case 25: return 6; // 32M (using 16K granule in v8-64) 217310621SCurtis.Dunham@arm.com case 29: return 7; // 512M (using 64K granule in v8-64) 217410621SCurtis.Dunham@arm.com case 30: return 8; // 1G-LPAE 217510621SCurtis.Dunham@arm.com default: 217610621SCurtis.Dunham@arm.com panic("unknown page size"); 217710621SCurtis.Dunham@arm.com return 255; 217810621SCurtis.Dunham@arm.com } 217910621SCurtis.Dunham@arm.com} 218010621SCurtis.Dunham@arm.com 218110621SCurtis.Dunham@arm.comvoid 218210621SCurtis.Dunham@arm.comTableWalker::regStats() 218310621SCurtis.Dunham@arm.com{ 218411522Sstephan.diestelhorst@arm.com ClockedObject::regStats(); 218511522Sstephan.diestelhorst@arm.com 218610621SCurtis.Dunham@arm.com statWalks 218710621SCurtis.Dunham@arm.com .name(name() + ".walks") 218810621SCurtis.Dunham@arm.com .desc("Table walker walks requested") 218910621SCurtis.Dunham@arm.com ; 219010621SCurtis.Dunham@arm.com 219110621SCurtis.Dunham@arm.com statWalksShortDescriptor 219210621SCurtis.Dunham@arm.com .name(name() + ".walksShort") 219310621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with short descriptors") 219410621SCurtis.Dunham@arm.com .flags(Stats::nozero) 219510621SCurtis.Dunham@arm.com ; 219610621SCurtis.Dunham@arm.com 219710621SCurtis.Dunham@arm.com statWalksLongDescriptor 219810621SCurtis.Dunham@arm.com .name(name() + ".walksLong") 219910621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with long descriptors") 220010621SCurtis.Dunham@arm.com .flags(Stats::nozero) 220110621SCurtis.Dunham@arm.com ; 220210621SCurtis.Dunham@arm.com 220310621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel 220410621SCurtis.Dunham@arm.com .init(2) 220510621SCurtis.Dunham@arm.com .name(name() + ".walksShortTerminationLevel") 220610621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 220710621SCurtis.Dunham@arm.com "with short descriptors terminate") 220810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 220910621SCurtis.Dunham@arm.com ; 221010621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(0, "Level1"); 221110621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(1, "Level2"); 221210621SCurtis.Dunham@arm.com 221310621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel 221410621SCurtis.Dunham@arm.com .init(4) 221510621SCurtis.Dunham@arm.com .name(name() + ".walksLongTerminationLevel") 221610621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 221710621SCurtis.Dunham@arm.com "with long descriptors terminate") 221810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 221910621SCurtis.Dunham@arm.com ; 222010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(0, "Level0"); 222110621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(1, "Level1"); 222210621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(2, "Level2"); 222310621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(3, "Level3"); 222410621SCurtis.Dunham@arm.com 222510621SCurtis.Dunham@arm.com statSquashedBefore 222610621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedBefore") 222710621SCurtis.Dunham@arm.com .desc("Table walks squashed before starting") 222810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 222910621SCurtis.Dunham@arm.com ; 223010621SCurtis.Dunham@arm.com 223110621SCurtis.Dunham@arm.com statSquashedAfter 223210621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedAfter") 223310621SCurtis.Dunham@arm.com .desc("Table walks squashed after completion") 223410621SCurtis.Dunham@arm.com .flags(Stats::nozero) 223510621SCurtis.Dunham@arm.com ; 223610621SCurtis.Dunham@arm.com 223710621SCurtis.Dunham@arm.com statWalkWaitTime 223810621SCurtis.Dunham@arm.com .init(16) 223910621SCurtis.Dunham@arm.com .name(name() + ".walkWaitTime") 224010621SCurtis.Dunham@arm.com .desc("Table walker wait (enqueue to first request) latency") 224110621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 224210621SCurtis.Dunham@arm.com ; 224310621SCurtis.Dunham@arm.com 224410621SCurtis.Dunham@arm.com statWalkServiceTime 224510621SCurtis.Dunham@arm.com .init(16) 224610621SCurtis.Dunham@arm.com .name(name() + ".walkCompletionTime") 224710621SCurtis.Dunham@arm.com .desc("Table walker service (enqueue to completion) latency") 224810621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 224910621SCurtis.Dunham@arm.com ; 225010621SCurtis.Dunham@arm.com 225110621SCurtis.Dunham@arm.com statPendingWalks 225210621SCurtis.Dunham@arm.com .init(16) 225310621SCurtis.Dunham@arm.com .name(name() + ".walksPending") 225410621SCurtis.Dunham@arm.com .desc("Table walker pending requests distribution") 225510621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 225610621SCurtis.Dunham@arm.com ; 225710621SCurtis.Dunham@arm.com 225810621SCurtis.Dunham@arm.com statPageSizes // see DDI 0487A D4-1661 225910621SCurtis.Dunham@arm.com .init(9) 226010621SCurtis.Dunham@arm.com .name(name() + ".walkPageSizes") 226110621SCurtis.Dunham@arm.com .desc("Table walker page sizes translated") 226210621SCurtis.Dunham@arm.com .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 226310621SCurtis.Dunham@arm.com ; 226410621SCurtis.Dunham@arm.com statPageSizes.subname(0, "4K"); 226510621SCurtis.Dunham@arm.com statPageSizes.subname(1, "16K"); 226610621SCurtis.Dunham@arm.com statPageSizes.subname(2, "64K"); 226710621SCurtis.Dunham@arm.com statPageSizes.subname(3, "1M"); 226810621SCurtis.Dunham@arm.com statPageSizes.subname(4, "2M"); 226910621SCurtis.Dunham@arm.com statPageSizes.subname(5, "16M"); 227010621SCurtis.Dunham@arm.com statPageSizes.subname(6, "32M"); 227110621SCurtis.Dunham@arm.com statPageSizes.subname(7, "512M"); 227210621SCurtis.Dunham@arm.com statPageSizes.subname(8, "1G"); 227310621SCurtis.Dunham@arm.com 227410621SCurtis.Dunham@arm.com statRequestOrigin 227510621SCurtis.Dunham@arm.com .init(2,2) // Instruction/Data, requests/completed 227610621SCurtis.Dunham@arm.com .name(name() + ".walkRequestOrigin") 227710621SCurtis.Dunham@arm.com .desc("Table walker requests started/completed, data/inst") 227810621SCurtis.Dunham@arm.com .flags(Stats::total) 227910621SCurtis.Dunham@arm.com ; 228010621SCurtis.Dunham@arm.com statRequestOrigin.subname(0,"Requested"); 228110621SCurtis.Dunham@arm.com statRequestOrigin.subname(1,"Completed"); 228210621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(0,"Data"); 228310621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(1,"Inst"); 228410621SCurtis.Dunham@arm.com} 2285