table_walker.cc revision 12735
17404SAli.Saidi@ARM.com/* 212709Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2018 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 4010873Sandreas.sandberg@arm.com#include "arch/arm/table_walker.hh" 417404SAli.Saidi@ARM.com 4210474Sandreas.hansson@arm.com#include <memory> 4310474Sandreas.hansson@arm.com 447404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4510037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4610037SARM gem5 Developers#include "arch/arm/system.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 487728SAli.Saidi@ARM.com#include "cpu/base.hh" 497404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 508245Snate@binkert.org#include "debug/Checkpoint.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528245Snate@binkert.org#include "debug/TLB.hh" 538245Snate@binkert.org#include "debug/TLBVerbose.hh" 5410873Sandreas.sandberg@arm.com#include "dev/dma_device.hh" 557748SAli.Saidi@ARM.com#include "sim/system.hh" 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comusing namespace ArmISA; 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 6010913Sandreas.sandberg@arm.com : MemObject(p), 6110717Sandreas.hansson@arm.com stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 6210717Sandreas.hansson@arm.com isStage2(p->is_stage2), tlb(NULL), 6310717Sandreas.hansson@arm.com currState(NULL), pending(false), 649258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6510621SCurtis.Dunham@arm.com pendingReqs(0), 6610621SCurtis.Dunham@arm.com pendingChangeTick(curTick()), 6712086Sspwilson2@wisc.edu doL1DescEvent([this]{ doL1DescriptorWrapper(); }, name()), 6812086Sspwilson2@wisc.edu doL2DescEvent([this]{ doL2DescriptorWrapper(); }, name()), 6912086Sspwilson2@wisc.edu doL0LongDescEvent([this]{ doL0LongDescriptorWrapper(); }, name()), 7012086Sspwilson2@wisc.edu doL1LongDescEvent([this]{ doL1LongDescriptorWrapper(); }, name()), 7112086Sspwilson2@wisc.edu doL2LongDescEvent([this]{ doL2LongDescriptorWrapper(); }, name()), 7212086Sspwilson2@wisc.edu doL3LongDescEvent([this]{ doL3LongDescriptorWrapper(); }, name()), 7311588SCurtis.Dunham@arm.com LongDescEventByLevel { &doL0LongDescEvent, &doL1LongDescEvent, 7411588SCurtis.Dunham@arm.com &doL2LongDescEvent, &doL3LongDescEvent }, 7512086Sspwilson2@wisc.edu doProcessEvent([this]{ processWalkWrapper(); }, name()) 767439Sdam.sunwoo@arm.com{ 777576SAli.Saidi@ARM.com sctlr = 0; 7810037SARM gem5 Developers 7910037SARM gem5 Developers // Cache system-level properties 8010037SARM gem5 Developers if (FullSystem) { 8110717Sandreas.hansson@arm.com ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 8210037SARM gem5 Developers assert(armSys); 8310037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 8410037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 8510037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 8610037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 8710037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 8810037SARM gem5 Developers } else { 8910037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 9010037SARM gem5 Developers _haveLargeAsid64 = false; 9110037SARM gem5 Developers physAddrRange = 32; 9210037SARM gem5 Developers } 9310037SARM gem5 Developers 947439Sdam.sunwoo@arm.com} 957404SAli.Saidi@ARM.com 967404SAli.Saidi@ARM.comTableWalker::~TableWalker() 977404SAli.Saidi@ARM.com{ 987404SAli.Saidi@ARM.com ; 997404SAli.Saidi@ARM.com} 1007404SAli.Saidi@ARM.com 10110717Sandreas.hansson@arm.comvoid 10210717Sandreas.hansson@arm.comTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 10310717Sandreas.hansson@arm.com{ 10410717Sandreas.hansson@arm.com stage2Mmu = m; 10510717Sandreas.hansson@arm.com port = &m->getPort(); 10610717Sandreas.hansson@arm.com masterId = master_id; 10710717Sandreas.hansson@arm.com} 10810717Sandreas.hansson@arm.com 10910717Sandreas.hansson@arm.comvoid 11010717Sandreas.hansson@arm.comTableWalker::init() 11110717Sandreas.hansson@arm.com{ 11210717Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 11310717Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 11410717Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 11510717Sandreas.hansson@arm.com} 11610717Sandreas.hansson@arm.com 11710717Sandreas.hansson@arm.comBaseMasterPort& 11810717Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 11910717Sandreas.hansson@arm.com{ 12010717Sandreas.hansson@arm.com if (if_name == "port") { 12110717Sandreas.hansson@arm.com if (!isStage2) { 12210717Sandreas.hansson@arm.com return *port; 12310717Sandreas.hansson@arm.com } else { 12410717Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 12510717Sandreas.hansson@arm.com } 12610717Sandreas.hansson@arm.com } 12710717Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 12810717Sandreas.hansson@arm.com} 12910717Sandreas.hansson@arm.com 13010537Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 13110537Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 13210537Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 13310537Sandreas.hansson@arm.com vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 13410537Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 13510537Sandreas.hansson@arm.com pxnTable(false), stage2Req(false), doingStage2(false), 13610537Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 13710537Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 13810537Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 13910037SARM gem5 Developers{ 14010037SARM gem5 Developers} 14110037SARM gem5 Developers 1429152Satgutier@umich.eduvoid 1439152Satgutier@umich.eduTableWalker::completeDrain() 1449152Satgutier@umich.edu{ 14510913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 14611588SCurtis.Dunham@arm.com stateQueues[L0].empty() && stateQueues[L1].empty() && 14711588SCurtis.Dunham@arm.com stateQueues[L2].empty() && stateQueues[L3].empty() && 1489152Satgutier@umich.edu pendingQueue.empty()) { 14910913Sandreas.sandberg@arm.com 1509152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 15110913Sandreas.sandberg@arm.com signalDrainDone(); 1529152Satgutier@umich.edu } 1539152Satgutier@umich.edu} 1549152Satgutier@umich.edu 15510913Sandreas.sandberg@arm.comDrainState 15610913Sandreas.sandberg@arm.comTableWalker::drain() 1577404SAli.Saidi@ARM.com{ 15810037SARM gem5 Developers bool state_queues_not_empty = false; 1599152Satgutier@umich.edu 16010037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 16110037SARM gem5 Developers if (!stateQueues[i].empty()) { 16210037SARM gem5 Developers state_queues_not_empty = true; 16310037SARM gem5 Developers break; 16410037SARM gem5 Developers } 16510037SARM gem5 Developers } 16610037SARM gem5 Developers 16710037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1689152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 16910913Sandreas.sandberg@arm.com return DrainState::Draining; 17010037SARM gem5 Developers } else { 17110037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 17210913Sandreas.sandberg@arm.com return DrainState::Drained; 1737733SAli.Saidi@ARM.com } 1747404SAli.Saidi@ARM.com} 1757404SAli.Saidi@ARM.com 1767748SAli.Saidi@ARM.comvoid 1779342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1787748SAli.Saidi@ARM.com{ 1799524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1809152Satgutier@umich.edu delete currState; 1819152Satgutier@umich.edu currState = NULL; 18210621SCurtis.Dunham@arm.com pendingChange(); 1837748SAli.Saidi@ARM.com } 1847748SAli.Saidi@ARM.com} 1857748SAli.Saidi@ARM.com 1867404SAli.Saidi@ARM.comFault 18710037SARM gem5 DevelopersTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 18810037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 18910037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 19011580SDylan.Johnson@ARM.com bool secure, TLB::ArmTranslationType tranType, 19111580SDylan.Johnson@ARM.com bool _stage2Req) 1927404SAli.Saidi@ARM.com{ 1938733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 19410621SCurtis.Dunham@arm.com ++statWalks; 19510621SCurtis.Dunham@arm.com 19610109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 19710037SARM gem5 Developers 19810109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 1997439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 2007439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 2017439Sdam.sunwoo@arm.com // TLB miss. 2027439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 2037404SAli.Saidi@ARM.com 2047439Sdam.sunwoo@arm.com currState = new WalkerState(); 2057439Sdam.sunwoo@arm.com currState->tableWalker = this; 20610109SGeoffrey.Blake@arm.com } else if (_functional) { 20710109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 20810109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 20910109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 21010109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 21110109SGeoffrey.Blake@arm.com savedCurrState = currState; 21210109SGeoffrey.Blake@arm.com currState = new WalkerState(); 21310109SGeoffrey.Blake@arm.com currState->tableWalker = this; 2148202SAli.Saidi@ARM.com } else if (_timing) { 2158202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 2168202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 2178202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 2188202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 2198202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 2208202SAli.Saidi@ARM.com // up everything. 22110037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 22210621SCurtis.Dunham@arm.com ++statSquashedBefore; 22310474Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 2248202SAli.Saidi@ARM.com } 2257439Sdam.sunwoo@arm.com } 22610621SCurtis.Dunham@arm.com pendingChange(); 2277439Sdam.sunwoo@arm.com 22810621SCurtis.Dunham@arm.com currState->startTime = curTick(); 2297439Sdam.sunwoo@arm.com currState->tc = _tc; 23011517SCurtis.Dunham@arm.com // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 23111517SCurtis.Dunham@arm.com // aarch32/translation/translation/AArch32.TranslateAddress dictates 23211517SCurtis.Dunham@arm.com // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 23312735Sandreas.sandberg@arm.com if (isStage2) { 23412735Sandreas.sandberg@arm.com currState->el = EL1; 23512735Sandreas.sandberg@arm.com currState->aarch64 = ELIs64(_tc, EL2); 23612735Sandreas.sandberg@arm.com } else { 23712735Sandreas.sandberg@arm.com currState->el = 23812735Sandreas.sandberg@arm.com TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType); 23912735Sandreas.sandberg@arm.com currState->aarch64 = 24012735Sandreas.sandberg@arm.com ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el); 24112735Sandreas.sandberg@arm.com } 2427439Sdam.sunwoo@arm.com currState->transState = _trans; 2437439Sdam.sunwoo@arm.com currState->req = _req; 2447439Sdam.sunwoo@arm.com currState->fault = NoFault; 24510037SARM gem5 Developers currState->asid = _asid; 24610037SARM gem5 Developers currState->vmid = _vmid; 24710037SARM gem5 Developers currState->isHyp = _isHyp; 2487439Sdam.sunwoo@arm.com currState->timing = _timing; 2498733Sgeoffrey.blake@arm.com currState->functional = _functional; 2507439Sdam.sunwoo@arm.com currState->mode = _mode; 25110037SARM gem5 Developers currState->tranType = tranType; 25210037SARM gem5 Developers currState->isSecure = secure; 25310037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2547404SAli.Saidi@ARM.com 2557436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2567436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 25710037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 25810037SARM gem5 Developers if (currState->aarch64) 25910037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 26010037SARM gem5 Developers currState->tc, currState->el); 26110037SARM gem5 Developers else 26210037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 26310037SARM gem5 Developers 26410037SARM gem5 Developers if (currState->aarch64) { 26511575SDylan.Johnson@ARM.com if (isStage2) { 26611575SDylan.Johnson@ARM.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 26711575SDylan.Johnson@ARM.com currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 26811575SDylan.Johnson@ARM.com } else switch (currState->el) { 26910037SARM gem5 Developers case EL0: 27010037SARM gem5 Developers case EL1: 27110037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 27210324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 27310037SARM gem5 Developers break; 27411574SCurtis.Dunham@arm.com case EL2: 27511574SCurtis.Dunham@arm.com assert(_haveVirtualization); 27611574SCurtis.Dunham@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 27711574SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 27811574SCurtis.Dunham@arm.com break; 27910037SARM gem5 Developers case EL3: 28010037SARM gem5 Developers assert(haveSecurity); 28110037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 28210324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 28310037SARM gem5 Developers break; 28410037SARM gem5 Developers default: 28510037SARM gem5 Developers panic("Invalid exception level"); 28610037SARM gem5 Developers break; 28710037SARM gem5 Developers } 28811575SDylan.Johnson@ARM.com currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 28910037SARM gem5 Developers } else { 29012499Sgiacomo.travaglini@arm.com currState->sctlr = currState->tc->readMiscReg(snsBankedIndex( 29110037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 29212499Sgiacomo.travaglini@arm.com currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex( 29310037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 29410037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 29510037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 29610037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 29710037SARM gem5 Developers } 2987439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 2997439Sdam.sunwoo@arm.com 3007439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 3017439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 3027439Sdam.sunwoo@arm.com 30310621SCurtis.Dunham@arm.com statRequestOrigin[REQUESTED][currState->isFetch]++; 30410621SCurtis.Dunham@arm.com 30510037SARM gem5 Developers // We only do a second stage of translation if we're not secure, or in 30610037SARM gem5 Developers // hyp mode, the second stage MMU is enabled, and this table walker 30710037SARM gem5 Developers // instance is the first stage. 30811580SDylan.Johnson@ARM.com // TODO: fix setting of doingStage2 for timing mode 30910037SARM gem5 Developers currState->doingStage2 = false; 31011580SDylan.Johnson@ARM.com currState->stage2Req = _stage2Req && !isStage2; 3117728SAli.Saidi@ARM.com 31211517SCurtis.Dunham@arm.com bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 31311517SCurtis.Dunham@arm.com longDescFormatInUse(currState->tc); 31410037SARM gem5 Developers 31510037SARM gem5 Developers if (long_desc_format) { 31610037SARM gem5 Developers // Helper variables used for hierarchical permissions 31710037SARM gem5 Developers currState->secureLookup = currState->isSecure; 31810037SARM gem5 Developers currState->rwTable = true; 31910037SARM gem5 Developers currState->userTable = true; 32010037SARM gem5 Developers currState->xnTable = false; 32110037SARM gem5 Developers currState->pxnTable = false; 32210621SCurtis.Dunham@arm.com 32310621SCurtis.Dunham@arm.com ++statWalksLongDescriptor; 32410621SCurtis.Dunham@arm.com } else { 32510621SCurtis.Dunham@arm.com ++statWalksShortDescriptor; 32610037SARM gem5 Developers } 32710037SARM gem5 Developers 32810037SARM gem5 Developers if (!currState->timing) { 32910109SGeoffrey.Blake@arm.com Fault fault = NoFault; 33010037SARM gem5 Developers if (currState->aarch64) 33110109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 33210037SARM gem5 Developers else if (long_desc_format) 33310109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 33410037SARM gem5 Developers else 33510109SGeoffrey.Blake@arm.com fault = processWalk(); 33610109SGeoffrey.Blake@arm.com 33710109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 33810109SGeoffrey.Blake@arm.com // how we found it. 33910109SGeoffrey.Blake@arm.com if (currState->functional) { 34010109SGeoffrey.Blake@arm.com delete currState; 34110109SGeoffrey.Blake@arm.com currState = savedCurrState; 34210109SGeoffrey.Blake@arm.com } 34310109SGeoffrey.Blake@arm.com return fault; 34410037SARM gem5 Developers } 3457728SAli.Saidi@ARM.com 3468067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 3477728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 3487728SAli.Saidi@ARM.com currState = NULL; 34910621SCurtis.Dunham@arm.com pendingChange(); 3507728SAli.Saidi@ARM.com } else { 3517728SAli.Saidi@ARM.com pending = true; 35210621SCurtis.Dunham@arm.com pendingChange(); 35310037SARM gem5 Developers if (currState->aarch64) 35410037SARM gem5 Developers return processWalkAArch64(); 35510037SARM gem5 Developers else if (long_desc_format) 35610037SARM gem5 Developers return processWalkLPAE(); 35710037SARM gem5 Developers else 35810037SARM gem5 Developers return processWalk(); 3597728SAli.Saidi@ARM.com } 3607728SAli.Saidi@ARM.com 3617728SAli.Saidi@ARM.com return NoFault; 3627728SAli.Saidi@ARM.com} 3637728SAli.Saidi@ARM.com 3647728SAli.Saidi@ARM.comvoid 3657728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3667728SAli.Saidi@ARM.com{ 3677728SAli.Saidi@ARM.com assert(!currState); 3687728SAli.Saidi@ARM.com assert(pendingQueue.size()); 36910621SCurtis.Dunham@arm.com pendingChange(); 3707728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3719258SAli.Saidi@ARM.com 3729535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 37310037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 37410037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 37510037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 37612735Sandreas.sandberg@arm.com currState->el); 3779258SAli.Saidi@ARM.com 3789535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3799535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3809535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3819535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3829535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3839535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3849258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3859258SAli.Saidi@ARM.com pending = true; 3869258SAli.Saidi@ARM.com pendingQueue.pop_front(); 38710579SAndrew.Bardsley@arm.com // Keep currState in case one of the processWalk... calls NULLs it 38810579SAndrew.Bardsley@arm.com WalkerState *curr_state_copy = currState; 38910579SAndrew.Bardsley@arm.com Fault f; 39010037SARM gem5 Developers if (currState->aarch64) 39110579SAndrew.Bardsley@arm.com f = processWalkAArch64(); 39211517SCurtis.Dunham@arm.com else if (longDescFormatInUse(currState->tc) || 39311517SCurtis.Dunham@arm.com currState->isHyp || isStage2) 39410579SAndrew.Bardsley@arm.com f = processWalkLPAE(); 39510037SARM gem5 Developers else 39610579SAndrew.Bardsley@arm.com f = processWalk(); 39710579SAndrew.Bardsley@arm.com 39810579SAndrew.Bardsley@arm.com if (f != NoFault) { 39910579SAndrew.Bardsley@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 40010579SAndrew.Bardsley@arm.com curr_state_copy->tc, curr_state_copy->mode); 40110579SAndrew.Bardsley@arm.com 40210579SAndrew.Bardsley@arm.com delete curr_state_copy; 40310579SAndrew.Bardsley@arm.com } 4049258SAli.Saidi@ARM.com return; 4059258SAli.Saidi@ARM.com } 4069258SAli.Saidi@ARM.com 4079258SAli.Saidi@ARM.com 4089258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 4099258SAli.Saidi@ARM.com // squashed we shouldn't bother. 4109258SAli.Saidi@ARM.com unsigned num_squashed = 0; 4119258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 4129258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 4139535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 4149258SAli.Saidi@ARM.com pendingQueue.pop_front(); 4159258SAli.Saidi@ARM.com num_squashed++; 41610621SCurtis.Dunham@arm.com statSquashedBefore++; 4179258SAli.Saidi@ARM.com 41810037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 41910037SARM gem5 Developers currState->vaddr_tainted); 4209258SAli.Saidi@ARM.com 4219535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 4229535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 42310474Sandreas.hansson@arm.com currState->transState->finish( 42410474Sandreas.hansson@arm.com std::make_shared<UnimpFault>("Squashed Inst"), 42510474Sandreas.hansson@arm.com currState->req, currState->tc, currState->mode); 4269535Smrinmoy.ghosh@arm.com } else { 4279535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 42810621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 42910037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 43010037SARM gem5 Developers currState->transState, currState->mode); 43110037SARM gem5 Developers 4329535Smrinmoy.ghosh@arm.com } 4339258SAli.Saidi@ARM.com 4349258SAli.Saidi@ARM.com // delete the current request 4359258SAli.Saidi@ARM.com delete currState; 4369258SAli.Saidi@ARM.com 4379258SAli.Saidi@ARM.com // peak at the next one 4389535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 4399258SAli.Saidi@ARM.com currState = pendingQueue.front(); 44010037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 44110037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 44212735Sandreas.sandberg@arm.com false, currState->el); 4439535Smrinmoy.ghosh@arm.com } else { 4449535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 4459258SAli.Saidi@ARM.com currState = NULL; 4469535Smrinmoy.ghosh@arm.com } 4479258SAli.Saidi@ARM.com } 44810621SCurtis.Dunham@arm.com pendingChange(); 4499258SAli.Saidi@ARM.com 45010621SCurtis.Dunham@arm.com // if we still have pending translations, schedule more work 4519258SAli.Saidi@ARM.com nextWalk(tc); 4529258SAli.Saidi@ARM.com currState = NULL; 4537728SAli.Saidi@ARM.com} 4547728SAli.Saidi@ARM.com 4557728SAli.Saidi@ARM.comFault 4567728SAli.Saidi@ARM.comTableWalker::processWalk() 4577728SAli.Saidi@ARM.com{ 4587404SAli.Saidi@ARM.com Addr ttbr = 0; 4597404SAli.Saidi@ARM.com 4607404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 46110037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 4627404SAli.Saidi@ARM.com 46310037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 46410037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 46510037SARM gem5 Developers 32 - currState->ttbcr.n)); 4667406SAli.Saidi@ARM.com 46710621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 46810621SCurtis.Dunham@arm.com 46910037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 47010037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4717406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 47210037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 47310037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 47410037SARM gem5 Developers if (currState->isFetch) 47510474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 47610474Sandreas.hansson@arm.com currState->vaddr_tainted, 47710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 47810474Sandreas.hansson@arm.com isStage2, 47910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 48010037SARM gem5 Developers else 48110474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 48210474Sandreas.hansson@arm.com currState->vaddr_tainted, 48310474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 48410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 48510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 48610037SARM gem5 Developers } 48712499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 48810037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4897404SAli.Saidi@ARM.com } else { 4907406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 49110037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 49210037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 49310037SARM gem5 Developers if (currState->isFetch) 49410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 49510474Sandreas.hansson@arm.com currState->vaddr_tainted, 49610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 49710474Sandreas.hansson@arm.com isStage2, 49810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49910037SARM gem5 Developers else 50010474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 50110474Sandreas.hansson@arm.com currState->vaddr_tainted, 50210474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 50310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 50410474Sandreas.hansson@arm.com ArmFault::VmsaTran); 50510037SARM gem5 Developers } 50612499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 50710037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 50810037SARM gem5 Developers currState->ttbcr.n = 0; 5097404SAli.Saidi@ARM.com } 5107404SAli.Saidi@ARM.com 51110037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 51210037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 51310037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 51410037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 5157404SAli.Saidi@ARM.com 5167404SAli.Saidi@ARM.com // Trickbox address check 5177439Sdam.sunwoo@arm.com Fault f; 51811395Sandreas.sandberg@arm.com f = testWalk(l1desc_addr, sizeof(uint32_t), 51911395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, L1); 5207439Sdam.sunwoo@arm.com if (f) { 52110037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5227579Sminkyu.jeong@arm.com if (currState->timing) { 5237728SAli.Saidi@ARM.com pending = false; 5247728SAli.Saidi@ARM.com nextWalk(currState->tc); 5257579Sminkyu.jeong@arm.com currState = NULL; 5267579Sminkyu.jeong@arm.com } else { 5277579Sminkyu.jeong@arm.com currState->tc = NULL; 5287579Sminkyu.jeong@arm.com currState->req = NULL; 5297579Sminkyu.jeong@arm.com } 5307579Sminkyu.jeong@arm.com return f; 5317404SAli.Saidi@ARM.com } 5327404SAli.Saidi@ARM.com 53310836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 5347946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 53510836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 5367946SGiacomo.Gabrielli@arm.com } 5377946SGiacomo.Gabrielli@arm.com 53811181Snathananel.premillieu@arm.com if (currState->isSecure) { 53911181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 54011181Snathananel.premillieu@arm.com } 54111181Snathananel.premillieu@arm.com 54210037SARM gem5 Developers bool delayed; 54310037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 54410037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 54510037SARM gem5 Developers &TableWalker::doL1Descriptor); 54610037SARM gem5 Developers if (!delayed) { 54710037SARM gem5 Developers f = currState->fault; 54810037SARM gem5 Developers } 54910037SARM gem5 Developers 55010037SARM gem5 Developers return f; 55110037SARM gem5 Developers} 55210037SARM gem5 Developers 55310037SARM gem5 DevelopersFault 55410037SARM gem5 DevelopersTableWalker::processWalkLPAE() 55510037SARM gem5 Developers{ 55610037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 55710037SARM gem5 Developers int tsz, n; 55810037SARM gem5 Developers LookupLevel start_lookup_level = L1; 55910037SARM gem5 Developers 56010037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 56110037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 56210037SARM gem5 Developers 56310621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 56410621SCurtis.Dunham@arm.com 56510836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 56610037SARM gem5 Developers if (currState->isSecure) 56710037SARM gem5 Developers flag.set(Request::SECURE); 56810037SARM gem5 Developers 56910037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 57010037SARM gem5 Developers // use HTTBR 57110037SARM gem5 Developers if (isStage2) { 57210037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 57310037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 57410037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 57510037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 57610037SARM gem5 Developers } else if (currState->isHyp) { 57710037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 57810037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 57910037SARM gem5 Developers tsz = currState->htcr.t0sz; 58010037SARM gem5 Developers } else { 58111517SCurtis.Dunham@arm.com assert(longDescFormatInUse(currState->tc)); 58210037SARM gem5 Developers 58310037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 58410037SARM gem5 Developers if (currState->ttbcr.t0sz) 58510037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 58610037SARM gem5 Developers else if (currState->ttbcr.t1sz) 58710037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 58810037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 58910037SARM gem5 Developers else 59010037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 59110037SARM gem5 Developers if (currState->ttbcr.t1sz) 59210037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 59310037SARM gem5 Developers else 59410037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 59510037SARM gem5 Developers 59610037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 59710037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 59810037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 59910037SARM gem5 Developers // ARM issue C B3.6.4) 60010037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 60110037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 60210037SARM gem5 Developers // Check if table walk is allowed 60310037SARM gem5 Developers if (currState->ttbcr.epd0) { 60410037SARM gem5 Developers if (currState->isFetch) 60510474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 60610474Sandreas.hansson@arm.com currState->vaddr_tainted, 60710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60810474Sandreas.hansson@arm.com isStage2, 60910474Sandreas.hansson@arm.com ArmFault::LpaeTran); 61010037SARM gem5 Developers else 61110474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 61210474Sandreas.hansson@arm.com currState->vaddr_tainted, 61310474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 61410474Sandreas.hansson@arm.com currState->isWrite, 61510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 61610474Sandreas.hansson@arm.com isStage2, 61710474Sandreas.hansson@arm.com ArmFault::LpaeTran); 61810037SARM gem5 Developers } 61912499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 62010037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 62110037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 62210037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 62310037SARM gem5 Developers start_lookup_level = L2; 62410037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 62510037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 62610037SARM gem5 Developers // Check if table walk is allowed 62710037SARM gem5 Developers if (currState->ttbcr.epd1) { 62810037SARM gem5 Developers if (currState->isFetch) 62910474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 63010474Sandreas.hansson@arm.com currState->vaddr_tainted, 63110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63210474Sandreas.hansson@arm.com isStage2, 63310474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63410037SARM gem5 Developers else 63510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 63610474Sandreas.hansson@arm.com currState->vaddr_tainted, 63710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 63810474Sandreas.hansson@arm.com currState->isWrite, 63910474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 64010474Sandreas.hansson@arm.com isStage2, 64110474Sandreas.hansson@arm.com ArmFault::LpaeTran); 64210037SARM gem5 Developers } 64312499Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(snsBankedIndex( 64410037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 64510037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 64610037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 64710037SARM gem5 Developers start_lookup_level = L2; 64810037SARM gem5 Developers } else { 64910037SARM gem5 Developers // Out of boundaries -> translation fault 65010037SARM gem5 Developers if (currState->isFetch) 65110474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 65210474Sandreas.hansson@arm.com currState->vaddr_tainted, 65310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 65410474Sandreas.hansson@arm.com isStage2, 65510474Sandreas.hansson@arm.com ArmFault::LpaeTran); 65610037SARM gem5 Developers else 65710474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65810474Sandreas.hansson@arm.com currState->vaddr_tainted, 65910474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 66010474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 66110474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 66210037SARM gem5 Developers } 66310037SARM gem5 Developers 66410037SARM gem5 Developers } 66510037SARM gem5 Developers 66610037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 66710037SARM gem5 Developers if (start_lookup_level == L1) { 66810037SARM gem5 Developers n = 5 - tsz; 66910037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 67010037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 67110037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67210037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67310037SARM gem5 Developers } else { 67410037SARM gem5 Developers // Skip first-level lookup 67510037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 67610037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 67710037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 67810037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67910037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 68010037SARM gem5 Developers } 68110037SARM gem5 Developers 68210037SARM gem5 Developers // Trickbox address check 68311395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 68411395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 68510037SARM gem5 Developers if (f) { 68610037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 68710037SARM gem5 Developers if (currState->timing) { 68810037SARM gem5 Developers pending = false; 68910037SARM gem5 Developers nextWalk(currState->tc); 69010037SARM gem5 Developers currState = NULL; 69110037SARM gem5 Developers } else { 69210037SARM gem5 Developers currState->tc = NULL; 69310037SARM gem5 Developers currState->req = NULL; 69410037SARM gem5 Developers } 69510037SARM gem5 Developers return f; 69610037SARM gem5 Developers } 69710037SARM gem5 Developers 69810037SARM gem5 Developers if (currState->sctlr.c == 0) { 69910836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 70010037SARM gem5 Developers } 70110037SARM gem5 Developers 70210037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 70310037SARM gem5 Developers currState->longDesc.aarch64 = false; 70410324SCurtis.Dunham@arm.com currState->longDesc.grainSize = Grain4KB; 70510037SARM gem5 Developers 70610037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70710037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 70811588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], 70911588SCurtis.Dunham@arm.com &TableWalker::doLongDescriptor); 71010037SARM gem5 Developers if (!delayed) { 71110037SARM gem5 Developers f = currState->fault; 71210037SARM gem5 Developers } 71310037SARM gem5 Developers 71410037SARM gem5 Developers return f; 71510037SARM gem5 Developers} 71610037SARM gem5 Developers 71710037SARM gem5 Developersunsigned 71810037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 71910037SARM gem5 Developers{ 72010037SARM gem5 Developers if (tsz < 25) 72110037SARM gem5 Developers return 25; 72210037SARM gem5 Developers if (tsz > 48) 72310037SARM gem5 Developers return 48; 72410037SARM gem5 Developers return tsz; 72510037SARM gem5 Developers} 72610037SARM gem5 Developers 72710037SARM gem5 Developersbool 72810037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 72910037SARM gem5 Developers{ 73010037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 73110037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 73210037SARM gem5 Developers} 73310037SARM gem5 Developers 73410037SARM gem5 DevelopersFault 73510037SARM gem5 DevelopersTableWalker::processWalkAArch64() 73610037SARM gem5 Developers{ 73710037SARM gem5 Developers assert(currState->aarch64); 73810037SARM gem5 Developers 73910324SCurtis.Dunham@arm.com DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 74010324SCurtis.Dunham@arm.com currState->vaddr_tainted, currState->tcr); 74110324SCurtis.Dunham@arm.com 74212709Sgiacomo.travaglini@arm.com static const GrainSize GrainMap_tg0[] = 74310324SCurtis.Dunham@arm.com { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 74412709Sgiacomo.travaglini@arm.com static const GrainSize GrainMap_tg1[] = 74510324SCurtis.Dunham@arm.com { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 74610037SARM gem5 Developers 74710621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 74810621SCurtis.Dunham@arm.com 74910037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 75010037SARM gem5 Developers Addr ttbr = 0; 75110037SARM gem5 Developers int tsz = 0, ps = 0; 75210324SCurtis.Dunham@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 75310037SARM gem5 Developers bool fault = false; 75411575SDylan.Johnson@ARM.com 75511575SDylan.Johnson@ARM.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 75611575SDylan.Johnson@ARM.com 75710037SARM gem5 Developers switch (currState->el) { 75810037SARM gem5 Developers case EL0: 75910037SARM gem5 Developers case EL1: 76011575SDylan.Johnson@ARM.com if (isStage2) { 76111575SDylan.Johnson@ARM.com DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 76211575SDylan.Johnson@ARM.com ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 76311575SDylan.Johnson@ARM.com tsz = 64 - currState->vtcr.t0sz64; 76412709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->vtcr.tg0]; 76511575SDylan.Johnson@ARM.com // ARM DDI 0487A.f D7-2148 76611575SDylan.Johnson@ARM.com // The starting level of stage 2 translation depends on 76711575SDylan.Johnson@ARM.com // VTCR_EL2.SL0 and VTCR_EL2.TG0 76811575SDylan.Johnson@ARM.com LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 76911575SDylan.Johnson@ARM.com uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 77011575SDylan.Johnson@ARM.com static const LookupLevel SLL[] = { 77111575SDylan.Johnson@ARM.com L2, L3, L3, __, // sl0 == 0 77211575SDylan.Johnson@ARM.com L1, L2, L2, __, // sl0 == 1, etc. 77311575SDylan.Johnson@ARM.com L0, L1, L1, __, 77411575SDylan.Johnson@ARM.com __, __, __, __ 77511575SDylan.Johnson@ARM.com }; 77611575SDylan.Johnson@ARM.com start_lookup_level = SLL[sl_tg]; 77711575SDylan.Johnson@ARM.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 77811575SDylan.Johnson@ARM.com "Cannot discern lookup level from vtcr.{sl0,tg0}"); 77911575SDylan.Johnson@ARM.com } else switch (bits(currState->vaddr, 63,48)) { 78010037SARM gem5 Developers case 0: 78110037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 78210037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 78310324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 78412709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 78510037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != 0x0 || 78610324SCurtis.Dunham@arm.com currState->tcr.epd0) 78710037SARM gem5 Developers fault = true; 78810037SARM gem5 Developers break; 78910037SARM gem5 Developers case 0xffff: 79010037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 79110037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 79210324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 79312709Sgiacomo.travaglini@arm.com tg = GrainMap_tg1[currState->tcr.tg1]; 79410037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 79510324SCurtis.Dunham@arm.com currState->tcr.epd1) 79610037SARM gem5 Developers fault = true; 79710037SARM gem5 Developers break; 79810037SARM gem5 Developers default: 79910037SARM gem5 Developers // top two bytes must be all 0s or all 1s, else invalid addr 80010037SARM gem5 Developers fault = true; 80110037SARM gem5 Developers } 80210324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 80310037SARM gem5 Developers break; 80410037SARM gem5 Developers case EL2: 80512709Sgiacomo.travaglini@arm.com switch(bits(currState->vaddr, 63,48)) { 80612709Sgiacomo.travaglini@arm.com case 0: 80712709Sgiacomo.travaglini@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 80812709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 80912709Sgiacomo.travaglini@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 81012709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 81112709Sgiacomo.travaglini@arm.com break; 81212709Sgiacomo.travaglini@arm.com 81312709Sgiacomo.travaglini@arm.com case 0xffff: 81412709Sgiacomo.travaglini@arm.com DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 81512709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2); 81612709Sgiacomo.travaglini@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 81712709Sgiacomo.travaglini@arm.com tg = GrainMap_tg1[currState->tcr.tg1]; 81812709Sgiacomo.travaglini@arm.com if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 81912709Sgiacomo.travaglini@arm.com currState->tcr.epd1 || !currState->hcr.e2h) 82012709Sgiacomo.travaglini@arm.com fault = true; 82112709Sgiacomo.travaglini@arm.com break; 82212709Sgiacomo.travaglini@arm.com 82312709Sgiacomo.travaglini@arm.com default: 82412709Sgiacomo.travaglini@arm.com // invalid addr if top two bytes are not all 0s 82512709Sgiacomo.travaglini@arm.com fault = true; 82612709Sgiacomo.travaglini@arm.com } 82712709Sgiacomo.travaglini@arm.com ps = currState->tcr.ips; 82812709Sgiacomo.travaglini@arm.com break; 82910037SARM gem5 Developers case EL3: 83010037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 83110037SARM gem5 Developers case 0: 83210324SCurtis.Dunham@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 83312709Sgiacomo.travaglini@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 83410324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 83512709Sgiacomo.travaglini@arm.com tg = GrainMap_tg0[currState->tcr.tg0]; 83610037SARM gem5 Developers break; 83710037SARM gem5 Developers default: 83810037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 83910324SCurtis.Dunham@arm.com fault = true; 84010037SARM gem5 Developers } 84110324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 84210037SARM gem5 Developers break; 84310037SARM gem5 Developers } 84410037SARM gem5 Developers 84510037SARM gem5 Developers if (fault) { 84610037SARM gem5 Developers Fault f; 84710037SARM gem5 Developers if (currState->isFetch) 84810474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 84910474Sandreas.hansson@arm.com currState->vaddr_tainted, 85010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 85110474Sandreas.hansson@arm.com ArmFault::LpaeTran); 85210037SARM gem5 Developers else 85310474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 85410474Sandreas.hansson@arm.com currState->vaddr_tainted, 85510474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 85610474Sandreas.hansson@arm.com currState->isWrite, 85710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, 85810474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 85910037SARM gem5 Developers 86010037SARM gem5 Developers if (currState->timing) { 86110037SARM gem5 Developers pending = false; 86210037SARM gem5 Developers nextWalk(currState->tc); 86310037SARM gem5 Developers currState = NULL; 86410037SARM gem5 Developers } else { 86510037SARM gem5 Developers currState->tc = NULL; 86610037SARM gem5 Developers currState->req = NULL; 86710037SARM gem5 Developers } 86810037SARM gem5 Developers return f; 86910037SARM gem5 Developers 87010037SARM gem5 Developers } 87110037SARM gem5 Developers 87210324SCurtis.Dunham@arm.com if (tg == ReservedGrain) { 87310324SCurtis.Dunham@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 87410324SCurtis.Dunham@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 87510324SCurtis.Dunham@arm.com tg = Grain4KB; 87610324SCurtis.Dunham@arm.com } 87710324SCurtis.Dunham@arm.com 87810037SARM gem5 Developers // Determine starting lookup level 87910324SCurtis.Dunham@arm.com // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 88010324SCurtis.Dunham@arm.com // in ARM DDI 0487A. These table values correspond to the cascading tests 88110324SCurtis.Dunham@arm.com // to compute the lookup level and are of the form 88210324SCurtis.Dunham@arm.com // (grain_size + N*stride), for N = {1, 2, 3}. 88310324SCurtis.Dunham@arm.com // A value of 64 will never succeed and a value of 0 will always succeed. 88411575SDylan.Johnson@ARM.com if (start_lookup_level == MAX_LOOKUP_LEVELS) { 88510324SCurtis.Dunham@arm.com struct GrainMap { 88610324SCurtis.Dunham@arm.com GrainSize grain_size; 88710324SCurtis.Dunham@arm.com unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 88810324SCurtis.Dunham@arm.com }; 88910324SCurtis.Dunham@arm.com static const GrainMap GM[] = { 89010324SCurtis.Dunham@arm.com { Grain4KB, { 39, 30, 0, 0 } }, 89110324SCurtis.Dunham@arm.com { Grain16KB, { 47, 36, 25, 0 } }, 89210324SCurtis.Dunham@arm.com { Grain64KB, { 64, 42, 29, 0 } } 89310324SCurtis.Dunham@arm.com }; 89410324SCurtis.Dunham@arm.com 89510324SCurtis.Dunham@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 89610324SCurtis.Dunham@arm.com 89710324SCurtis.Dunham@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 89810324SCurtis.Dunham@arm.com if (tg == GM[i].grain_size) { 89910324SCurtis.Dunham@arm.com lookup = GM[i].lookup_level_cutoff; 90010324SCurtis.Dunham@arm.com break; 90110324SCurtis.Dunham@arm.com } 90210324SCurtis.Dunham@arm.com } 90310324SCurtis.Dunham@arm.com assert(lookup); 90410324SCurtis.Dunham@arm.com 90510324SCurtis.Dunham@arm.com for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 90610324SCurtis.Dunham@arm.com if (tsz > lookup[L]) { 90710324SCurtis.Dunham@arm.com start_lookup_level = (LookupLevel) L; 90810324SCurtis.Dunham@arm.com break; 90910324SCurtis.Dunham@arm.com } 91010324SCurtis.Dunham@arm.com } 91110324SCurtis.Dunham@arm.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 91210324SCurtis.Dunham@arm.com "Table walker couldn't find lookup level\n"); 91310037SARM gem5 Developers } 91410037SARM gem5 Developers 91511575SDylan.Johnson@ARM.com int stride = tg - 3; 91611575SDylan.Johnson@ARM.com 91710037SARM gem5 Developers // Determine table base address 91810324SCurtis.Dunham@arm.com int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 91910037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 92010037SARM gem5 Developers 92110037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 92210037SARM gem5 Developers // necessary 92310037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 92410037SARM gem5 Developers // Clamp to lower limit 92510037SARM gem5 Developers if (pa_range > physAddrRange) 92610037SARM gem5 Developers currState->physAddrRange = physAddrRange; 92710037SARM gem5 Developers else 92810037SARM gem5 Developers currState->physAddrRange = pa_range; 92910037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 93010037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 93110037SARM gem5 Developers Fault f; 93210037SARM gem5 Developers if (currState->isFetch) 93310474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 93410474Sandreas.hansson@arm.com currState->vaddr_tainted, 93510474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 93610474Sandreas.hansson@arm.com isStage2, 93710474Sandreas.hansson@arm.com ArmFault::LpaeTran); 93810037SARM gem5 Developers else 93910474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 94010474Sandreas.hansson@arm.com currState->vaddr_tainted, 94110474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 94210474Sandreas.hansson@arm.com currState->isWrite, 94310474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 94410474Sandreas.hansson@arm.com isStage2, 94510474Sandreas.hansson@arm.com ArmFault::LpaeTran); 94610037SARM gem5 Developers 94710037SARM gem5 Developers 94810037SARM gem5 Developers if (currState->timing) { 94910037SARM gem5 Developers pending = false; 95010037SARM gem5 Developers nextWalk(currState->tc); 95110037SARM gem5 Developers currState = NULL; 95210037SARM gem5 Developers } else { 95310037SARM gem5 Developers currState->tc = NULL; 95410037SARM gem5 Developers currState->req = NULL; 95510037SARM gem5 Developers } 95610037SARM gem5 Developers return f; 95710037SARM gem5 Developers 95810037SARM gem5 Developers } 95910037SARM gem5 Developers 96010037SARM gem5 Developers // Determine descriptor address 96110037SARM gem5 Developers Addr desc_addr = base_addr | 96210037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 96310324SCurtis.Dunham@arm.com stride * (3 - start_lookup_level) + tg) << 3); 96410037SARM gem5 Developers 96510037SARM gem5 Developers // Trickbox address check 96611395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 96711395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 96810037SARM gem5 Developers if (f) { 96910037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 97010037SARM gem5 Developers if (currState->timing) { 97110037SARM gem5 Developers pending = false; 97210037SARM gem5 Developers nextWalk(currState->tc); 97310037SARM gem5 Developers currState = NULL; 97410037SARM gem5 Developers } else { 97510037SARM gem5 Developers currState->tc = NULL; 97610037SARM gem5 Developers currState->req = NULL; 97710037SARM gem5 Developers } 97810037SARM gem5 Developers return f; 97910037SARM gem5 Developers } 98010037SARM gem5 Developers 98110836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 98210037SARM gem5 Developers if (currState->sctlr.c == 0) { 98310836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 98410037SARM gem5 Developers } 98510037SARM gem5 Developers 98611181Snathananel.premillieu@arm.com if (currState->isSecure) { 98711181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 98811181Snathananel.premillieu@arm.com } 98911181Snathananel.premillieu@arm.com 99010037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 99110037SARM gem5 Developers currState->longDesc.aarch64 = true; 99210324SCurtis.Dunham@arm.com currState->longDesc.grainSize = tg; 99310037SARM gem5 Developers 9947439Sdam.sunwoo@arm.com if (currState->timing) { 99511588SCurtis.Dunham@arm.com fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data, 99611588SCurtis.Dunham@arm.com sizeof(uint64_t), flag, start_lookup_level, 99711588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], NULL); 99811579SDylan.Johnson@ARM.com } else { 99911575SDylan.Johnson@ARM.com fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 100011575SDylan.Johnson@ARM.com sizeof(uint64_t), flag, -1, NULL, 100111575SDylan.Johnson@ARM.com &TableWalker::doLongDescriptor); 10027439Sdam.sunwoo@arm.com f = currState->fault; 10037404SAli.Saidi@ARM.com } 10047404SAli.Saidi@ARM.com 10057439Sdam.sunwoo@arm.com return f; 10067404SAli.Saidi@ARM.com} 10077404SAli.Saidi@ARM.com 10087404SAli.Saidi@ARM.comvoid 10097439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 10107439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 10117404SAli.Saidi@ARM.com{ 10127439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 10137439Sdam.sunwoo@arm.com // variables 10147436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 10157436Sdam.sunwoo@arm.com te.shareable = false; // default value 10167582SAli.Saidi@arm.com te.nonCacheable = false; 101710037SARM gem5 Developers te.outerShareable = false; 10187439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 10197404SAli.Saidi@ARM.com switch(texcb) { 10207436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 10217404SAli.Saidi@ARM.com te.nonCacheable = true; 102210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 10237436Sdam.sunwoo@arm.com te.shareable = true; 10247436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10257436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10267404SAli.Saidi@ARM.com break; 10277436Sdam.sunwoo@arm.com case 1: // Shareable Device 10287436Sdam.sunwoo@arm.com te.nonCacheable = true; 102910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10307436Sdam.sunwoo@arm.com te.shareable = true; 10317436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10337436Sdam.sunwoo@arm.com break; 10347436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 103510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10367436Sdam.sunwoo@arm.com te.shareable = s; 10377436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10387436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10397436Sdam.sunwoo@arm.com break; 10407436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 104110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10427436Sdam.sunwoo@arm.com te.shareable = s; 10437436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10447436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10457436Sdam.sunwoo@arm.com break; 10467436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 10477436Sdam.sunwoo@arm.com te.nonCacheable = true; 104810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10497436Sdam.sunwoo@arm.com te.shareable = s; 10507436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10517436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10527436Sdam.sunwoo@arm.com break; 10537436Sdam.sunwoo@arm.com case 5: // Reserved 10547439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10557436Sdam.sunwoo@arm.com break; 10567436Sdam.sunwoo@arm.com case 6: // Implementation Defined 10577439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 10587436Sdam.sunwoo@arm.com break; 10597436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 106010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10617436Sdam.sunwoo@arm.com te.shareable = s; 10627436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10637436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10647436Sdam.sunwoo@arm.com break; 10657436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 10667436Sdam.sunwoo@arm.com te.nonCacheable = true; 106710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10687436Sdam.sunwoo@arm.com te.shareable = false; 10697436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10707436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10717436Sdam.sunwoo@arm.com break; 10727436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 10737439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10747436Sdam.sunwoo@arm.com break; 10757436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 107610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10777436Sdam.sunwoo@arm.com te.shareable = s; 10787404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 10797404SAli.Saidi@ARM.com te.nonCacheable = true; 10807436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 10817436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 10827404SAli.Saidi@ARM.com break; 10837436Sdam.sunwoo@arm.com default: 10847436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 10857404SAli.Saidi@ARM.com } 10867404SAli.Saidi@ARM.com } else { 10877438SAli.Saidi@ARM.com assert(tc); 108812499Sgiacomo.travaglini@arm.com PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, 108910037SARM gem5 Developers currState->tc, !currState->isSecure)); 109012499Sgiacomo.travaglini@arm.com NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, 109110037SARM gem5 Developers currState->tc, !currState->isSecure)); 10927436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 10937582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 10947404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 10957404SAli.Saidi@ARM.com case 0: 10967436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 10977436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 10987436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 109910037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 11007404SAli.Saidi@ARM.com break; 11017404SAli.Saidi@ARM.com case 1: 11027436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 11037436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 11047436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 110510037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 11067404SAli.Saidi@ARM.com break; 11077404SAli.Saidi@ARM.com case 2: 11087436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 11097436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 11107436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 111110037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 11127404SAli.Saidi@ARM.com break; 11137404SAli.Saidi@ARM.com case 3: 11147436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 11157436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 11167436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 111710037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 11187404SAli.Saidi@ARM.com break; 11197404SAli.Saidi@ARM.com case 4: 11207436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 11217436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 11227436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 112310037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 11247404SAli.Saidi@ARM.com break; 11257404SAli.Saidi@ARM.com case 5: 11267436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 11277436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 11287436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 112910037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 11307404SAli.Saidi@ARM.com break; 11317404SAli.Saidi@ARM.com case 6: 11327404SAli.Saidi@ARM.com panic("Imp defined type\n"); 11337404SAli.Saidi@ARM.com case 7: 11347436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 11357436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 11367436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 113710037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 11387404SAli.Saidi@ARM.com break; 11397404SAli.Saidi@ARM.com } 11407436Sdam.sunwoo@arm.com 11417436Sdam.sunwoo@arm.com switch(curr_tr) { 11427436Sdam.sunwoo@arm.com case 0: 11437436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 114410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 11457436Sdam.sunwoo@arm.com te.nonCacheable = true; 11467436Sdam.sunwoo@arm.com te.innerAttrs = 1; 11477436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11487436Sdam.sunwoo@arm.com te.shareable = true; 11497436Sdam.sunwoo@arm.com break; 11507436Sdam.sunwoo@arm.com case 1: 11517436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 11527436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 115310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 11547436Sdam.sunwoo@arm.com te.nonCacheable = true; 11557436Sdam.sunwoo@arm.com te.innerAttrs = 3; 11567436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11577436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 11587436Sdam.sunwoo@arm.com te.shareable = true; 11597436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 11607436Sdam.sunwoo@arm.com te.shareable = true; 11617436Sdam.sunwoo@arm.com break; 11627436Sdam.sunwoo@arm.com case 2: 11637436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 11647436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 116510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 11667436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 11677436Sdam.sunwoo@arm.com te.shareable = true; 11687436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 11697436Sdam.sunwoo@arm.com te.shareable = true; 11707436Sdam.sunwoo@arm.com break; 11717436Sdam.sunwoo@arm.com case 3: 11727436Sdam.sunwoo@arm.com panic("Reserved type"); 11737436Sdam.sunwoo@arm.com } 11747436Sdam.sunwoo@arm.com 117510037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 11767436Sdam.sunwoo@arm.com switch(curr_ir) { 11777436Sdam.sunwoo@arm.com case 0: 11787436Sdam.sunwoo@arm.com te.nonCacheable = true; 11797436Sdam.sunwoo@arm.com te.innerAttrs = 0; 11807436Sdam.sunwoo@arm.com break; 11817436Sdam.sunwoo@arm.com case 1: 11827436Sdam.sunwoo@arm.com te.innerAttrs = 5; 11837436Sdam.sunwoo@arm.com break; 11847436Sdam.sunwoo@arm.com case 2: 11857436Sdam.sunwoo@arm.com te.innerAttrs = 6; 11867436Sdam.sunwoo@arm.com break; 11877436Sdam.sunwoo@arm.com case 3: 11887436Sdam.sunwoo@arm.com te.innerAttrs = 7; 11897436Sdam.sunwoo@arm.com break; 11907436Sdam.sunwoo@arm.com } 11917436Sdam.sunwoo@arm.com 11927436Sdam.sunwoo@arm.com switch(curr_or) { 11937436Sdam.sunwoo@arm.com case 0: 11947436Sdam.sunwoo@arm.com te.nonCacheable = true; 11957436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11967436Sdam.sunwoo@arm.com break; 11977436Sdam.sunwoo@arm.com case 1: 11987436Sdam.sunwoo@arm.com te.outerAttrs = 1; 11997436Sdam.sunwoo@arm.com break; 12007436Sdam.sunwoo@arm.com case 2: 12017436Sdam.sunwoo@arm.com te.outerAttrs = 2; 12027436Sdam.sunwoo@arm.com break; 12037436Sdam.sunwoo@arm.com case 3: 12047436Sdam.sunwoo@arm.com te.outerAttrs = 3; 12057436Sdam.sunwoo@arm.com break; 12067436Sdam.sunwoo@arm.com } 12077436Sdam.sunwoo@arm.com } 12087404SAli.Saidi@ARM.com } 120910367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 121010367SAndrew.Bardsley@arm.com "outerAttrs: %d\n", 12117439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 121210037SARM gem5 Developers te.setAttributes(false); 121310037SARM gem5 Developers} 12147436Sdam.sunwoo@arm.com 121510037SARM gem5 Developersvoid 121610037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 121710037SARM gem5 Developers LongDescriptor &lDescriptor) 121810037SARM gem5 Developers{ 121910037SARM gem5 Developers assert(_haveLPAE); 12207436Sdam.sunwoo@arm.com 122110037SARM gem5 Developers uint8_t attr; 122210037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 122310037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 122410037SARM gem5 Developers // translation 122510037SARM gem5 Developers if (isStage2) { 122610037SARM gem5 Developers attr = lDescriptor.memAttr(); 122710037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 122810037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 12297436Sdam.sunwoo@arm.com 123010037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 123110037SARM gem5 Developers 123210037SARM gem5 Developers if (attr_3_2 == 0) { 123310037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 123410037SARM gem5 Developers : TlbEntry::MemoryType::Device; 123510037SARM gem5 Developers te.outerAttrs = 0; 123610037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 123710037SARM gem5 Developers te.nonCacheable = true; 123810037SARM gem5 Developers } else { 123910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 124010037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 124110037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 124210037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 124310037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 124410037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 124510037SARM gem5 Developers } 124610037SARM gem5 Developers } else { 124710037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 124810037SARM gem5 Developers 124910037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 125010037SARM gem5 Developers // value of SCTLR.TRE 125110421Sandreas.hansson@arm.com MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 125212499Sgiacomo.travaglini@arm.com int reg_as_int = snsBankedIndex(reg, currState->tc, 125312499Sgiacomo.travaglini@arm.com !currState->isSecure); 125410421Sandreas.hansson@arm.com uint32_t mair = currState->tc->readMiscReg(reg_as_int); 125510037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 125610037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 125710037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 125810037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 125910037SARM gem5 Developers 126010037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 126110037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 126210037SARM gem5 Developers // accordingly to provide the illusion of full support 126310037SARM gem5 Developers te.nonCacheable = false; 126410037SARM gem5 Developers 126510037SARM gem5 Developers switch (attr_7_4) { 126610037SARM gem5 Developers case 0x0: 126710037SARM gem5 Developers // Strongly-ordered or Device memory 126810037SARM gem5 Developers if (attr_3_0 == 0x0) 126910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 127010037SARM gem5 Developers else if (attr_3_0 == 0x4) 127110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 127210037SARM gem5 Developers else 127310037SARM gem5 Developers panic("Unpredictable behavior\n"); 127410037SARM gem5 Developers te.nonCacheable = true; 127510037SARM gem5 Developers te.outerAttrs = 0; 127610037SARM gem5 Developers break; 127710037SARM gem5 Developers case 0x4: 127810037SARM gem5 Developers // Normal memory, Outer Non-cacheable 127910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 128010037SARM gem5 Developers te.outerAttrs = 0; 128110037SARM gem5 Developers if (attr_3_0 == 0x4) 128210037SARM gem5 Developers // Inner Non-cacheable 128310037SARM gem5 Developers te.nonCacheable = true; 128410037SARM gem5 Developers else if (attr_3_0 < 0x8) 128510037SARM gem5 Developers panic("Unpredictable behavior\n"); 128610037SARM gem5 Developers break; 128710037SARM gem5 Developers case 0x8: 128810037SARM gem5 Developers case 0x9: 128910037SARM gem5 Developers case 0xa: 129010037SARM gem5 Developers case 0xb: 129110037SARM gem5 Developers case 0xc: 129210037SARM gem5 Developers case 0xd: 129310037SARM gem5 Developers case 0xe: 129410037SARM gem5 Developers case 0xf: 129510037SARM gem5 Developers if (attr_7_4 & 0x4) { 129610037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 129710037SARM gem5 Developers } else { 129810037SARM gem5 Developers te.outerAttrs = 0x2; 129910037SARM gem5 Developers } 130010037SARM gem5 Developers // Normal memory, Outer Cacheable 130110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 130210037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 130310037SARM gem5 Developers panic("Unpredictable behavior\n"); 130410037SARM gem5 Developers break; 130510037SARM gem5 Developers default: 130610037SARM gem5 Developers panic("Unpredictable behavior\n"); 130710037SARM gem5 Developers break; 130810037SARM gem5 Developers } 130910037SARM gem5 Developers 131010037SARM gem5 Developers switch (attr_3_0) { 131110037SARM gem5 Developers case 0x0: 131210037SARM gem5 Developers te.innerAttrs = 0x1; 131310037SARM gem5 Developers break; 131410037SARM gem5 Developers case 0x4: 131510037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 131610037SARM gem5 Developers break; 131710037SARM gem5 Developers case 0x8: 131810037SARM gem5 Developers case 0x9: 131910037SARM gem5 Developers case 0xA: 132010037SARM gem5 Developers case 0xB: 132110037SARM gem5 Developers te.innerAttrs = 6; 132210037SARM gem5 Developers break; 132310037SARM gem5 Developers case 0xC: 132410037SARM gem5 Developers case 0xD: 132510037SARM gem5 Developers case 0xE: 132610037SARM gem5 Developers case 0xF: 132710037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 132810037SARM gem5 Developers break; 132910037SARM gem5 Developers default: 133010037SARM gem5 Developers panic("Unpredictable behavior\n"); 133110037SARM gem5 Developers break; 133210037SARM gem5 Developers } 133310037SARM gem5 Developers } 133410037SARM gem5 Developers 133510037SARM gem5 Developers te.outerShareable = sh == 2; 133610037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 133710037SARM gem5 Developers te.setAttributes(true); 133810037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 133910037SARM gem5 Developers} 134010037SARM gem5 Developers 134110037SARM gem5 Developersvoid 134211583SDylan.Johnson@ARM.comTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, 134311583SDylan.Johnson@ARM.com LongDescriptor &lDescriptor) 134410037SARM gem5 Developers{ 134511583SDylan.Johnson@ARM.com uint8_t attr; 134611583SDylan.Johnson@ARM.com uint8_t attr_hi; 134711583SDylan.Johnson@ARM.com uint8_t attr_lo; 134811583SDylan.Johnson@ARM.com uint8_t sh = lDescriptor.sh(); 134910037SARM gem5 Developers 135011583SDylan.Johnson@ARM.com if (isStage2) { 135111583SDylan.Johnson@ARM.com attr = lDescriptor.memAttr(); 135211583SDylan.Johnson@ARM.com uint8_t attr_hi = (attr >> 2) & 0x3; 135311583SDylan.Johnson@ARM.com uint8_t attr_lo = attr & 0x3; 135411583SDylan.Johnson@ARM.com 135511583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh); 135611583SDylan.Johnson@ARM.com 135711583SDylan.Johnson@ARM.com if (attr_hi == 0) { 135811583SDylan.Johnson@ARM.com te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered 135911583SDylan.Johnson@ARM.com : TlbEntry::MemoryType::Device; 136011583SDylan.Johnson@ARM.com te.outerAttrs = 0; 136111583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 0 ? 1 : 3; 136211583SDylan.Johnson@ARM.com te.nonCacheable = true; 136311583SDylan.Johnson@ARM.com } else { 136411583SDylan.Johnson@ARM.com te.mtype = TlbEntry::MemoryType::Normal; 136511583SDylan.Johnson@ARM.com te.outerAttrs = attr_hi == 1 ? 0 : 136611583SDylan.Johnson@ARM.com attr_hi == 2 ? 2 : 1; 136711583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 1 ? 0 : 136811583SDylan.Johnson@ARM.com attr_lo == 2 ? 6 : 5; 136911938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 137011938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 137111938Snikos.nikoleris@arm.com te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) || 137211938Snikos.nikoleris@arm.com (attr_lo == 1) || (attr_lo == 2); 137311583SDylan.Johnson@ARM.com } 137411583SDylan.Johnson@ARM.com } else { 137511583SDylan.Johnson@ARM.com uint8_t attrIndx = lDescriptor.attrIndx(); 137611583SDylan.Johnson@ARM.com 137711583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 137811583SDylan.Johnson@ARM.com 137911583SDylan.Johnson@ARM.com // Select MAIR 138011583SDylan.Johnson@ARM.com uint64_t mair; 138111583SDylan.Johnson@ARM.com switch (currState->el) { 138211583SDylan.Johnson@ARM.com case EL0: 138311583SDylan.Johnson@ARM.com case EL1: 138411583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL1); 138511583SDylan.Johnson@ARM.com break; 138611583SDylan.Johnson@ARM.com case EL2: 138711583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL2); 138811583SDylan.Johnson@ARM.com break; 138911583SDylan.Johnson@ARM.com case EL3: 139011583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL3); 139111583SDylan.Johnson@ARM.com break; 139211583SDylan.Johnson@ARM.com default: 139311583SDylan.Johnson@ARM.com panic("Invalid exception level"); 139411583SDylan.Johnson@ARM.com break; 139511583SDylan.Johnson@ARM.com } 139611583SDylan.Johnson@ARM.com 139711583SDylan.Johnson@ARM.com // Select attributes 139811583SDylan.Johnson@ARM.com attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 139911583SDylan.Johnson@ARM.com attr_lo = bits(attr, 3, 0); 140011583SDylan.Johnson@ARM.com attr_hi = bits(attr, 7, 4); 140111583SDylan.Johnson@ARM.com 140211583SDylan.Johnson@ARM.com // Memory type 140311583SDylan.Johnson@ARM.com te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 140411583SDylan.Johnson@ARM.com 140511583SDylan.Johnson@ARM.com // Cacheability 140611583SDylan.Johnson@ARM.com te.nonCacheable = false; 140711938Snikos.nikoleris@arm.com if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory 140811938Snikos.nikoleris@arm.com te.nonCacheable = true; 140911938Snikos.nikoleris@arm.com } 141011938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 141111938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 141211938Snikos.nikoleris@arm.com switch (attr_hi) { 141311938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 141411938Snikos.nikoleris@arm.com case 0x4: // Normal memory, Outer Non-cacheable 141511938Snikos.nikoleris@arm.com case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 141611938Snikos.nikoleris@arm.com te.nonCacheable = true; 141711938Snikos.nikoleris@arm.com } 141811938Snikos.nikoleris@arm.com switch (attr_lo) { 141911938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 142011938Snikos.nikoleris@arm.com case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 142111938Snikos.nikoleris@arm.com warn_if(!attr_hi, "Unpredictable behavior"); 142212392Sjason@lowepower.com M5_FALLTHROUGH; 142311938Snikos.nikoleris@arm.com case 0x4: // Device-nGnRE memory or 142411938Snikos.nikoleris@arm.com // Normal memory, Inner Non-cacheable 142511938Snikos.nikoleris@arm.com case 0x8: // Device-nGRE memory or 142611938Snikos.nikoleris@arm.com // Normal memory, Inner Write-through non-transient 142711583SDylan.Johnson@ARM.com te.nonCacheable = true; 142811583SDylan.Johnson@ARM.com } 142911583SDylan.Johnson@ARM.com 143011583SDylan.Johnson@ARM.com te.shareable = sh == 2; 143111583SDylan.Johnson@ARM.com te.outerShareable = (sh & 0x2) ? true : false; 143211583SDylan.Johnson@ARM.com // Attributes formatted according to the 64-bit PAR 143311583SDylan.Johnson@ARM.com te.attributes = ((uint64_t) attr << 56) | 143411583SDylan.Johnson@ARM.com (1 << 11) | // LPAE bit 143511583SDylan.Johnson@ARM.com (te.ns << 9) | // NS bit 143611583SDylan.Johnson@ARM.com (sh << 7); 143710037SARM gem5 Developers } 14387404SAli.Saidi@ARM.com} 14397404SAli.Saidi@ARM.com 14407404SAli.Saidi@ARM.comvoid 14417404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 14427404SAli.Saidi@ARM.com{ 144310037SARM gem5 Developers if (currState->fault != NoFault) { 144410037SARM gem5 Developers return; 144510037SARM gem5 Developers } 144610037SARM gem5 Developers 144712526Schuan.zhu@arm.com currState->l1Desc.data = htog(currState->l1Desc.data, 144812526Schuan.zhu@arm.com byteOrder(currState->tc)); 144912526Schuan.zhu@arm.com 14507439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 145110037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 14527404SAli.Saidi@ARM.com TlbEntry te; 14537404SAli.Saidi@ARM.com 14547439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 14557404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 14567404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 14577946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 14587439Sdam.sunwoo@arm.com currState->tc = NULL; 14597439Sdam.sunwoo@arm.com currState->req = NULL; 14607437Sdam.sunwoo@arm.com } 14617406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 14627439Sdam.sunwoo@arm.com if (currState->isFetch) 14637439Sdam.sunwoo@arm.com currState->fault = 146410474Sandreas.hansson@arm.com std::make_shared<PrefetchAbort>( 146510474Sandreas.hansson@arm.com currState->vaddr_tainted, 146610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 146710474Sandreas.hansson@arm.com isStage2, 146810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14697406SAli.Saidi@ARM.com else 14707439Sdam.sunwoo@arm.com currState->fault = 147110474Sandreas.hansson@arm.com std::make_shared<DataAbort>( 147210474Sandreas.hansson@arm.com currState->vaddr_tainted, 147310474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 147410474Sandreas.hansson@arm.com currState->isWrite, 147510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 147610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14777404SAli.Saidi@ARM.com return; 14787404SAli.Saidi@ARM.com case L1Descriptor::Section: 14797439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 14807436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 14817436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 14827436Sdam.sunwoo@arm.com * AccessFlag0 14837436Sdam.sunwoo@arm.com */ 14847436Sdam.sunwoo@arm.com 148510474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 148610474Sandreas.hansson@arm.com currState->vaddr_tainted, 148710474Sandreas.hansson@arm.com currState->l1Desc.domain(), 148810474Sandreas.hansson@arm.com currState->isWrite, 148910474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L1, 149010474Sandreas.hansson@arm.com isStage2, 149110474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14927436Sdam.sunwoo@arm.com } 14937439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 14947404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 14957404SAli.Saidi@ARM.com } 149610037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 149710037SARM gem5 Developers return; 149810037SARM gem5 Developers case L1Descriptor::PageTable: 149910037SARM gem5 Developers { 150010037SARM gem5 Developers Addr l2desc_addr; 150110037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 150210037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 150310037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 150410037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 15057404SAli.Saidi@ARM.com 150610037SARM gem5 Developers // Trickbox address check 150711395Sandreas.sandberg@arm.com currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 150811395Sandreas.sandberg@arm.com currState->l1Desc.domain(), L2); 15097404SAli.Saidi@ARM.com 151010037SARM gem5 Developers if (currState->fault) { 151110037SARM gem5 Developers if (!currState->timing) { 151210037SARM gem5 Developers currState->tc = NULL; 151310037SARM gem5 Developers currState->req = NULL; 151410037SARM gem5 Developers } 151510037SARM gem5 Developers return; 151610037SARM gem5 Developers } 151710037SARM gem5 Developers 151810836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 151910037SARM gem5 Developers if (currState->isSecure) 152010037SARM gem5 Developers flag.set(Request::SECURE); 152110037SARM gem5 Developers 152210037SARM gem5 Developers bool delayed; 152310037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 152410037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 152510037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 152610037SARM gem5 Developers &TableWalker::doL2Descriptor); 152710037SARM gem5 Developers if (delayed) { 152810037SARM gem5 Developers currState->delayed = true; 152910037SARM gem5 Developers } 153010037SARM gem5 Developers 153110037SARM gem5 Developers return; 153210037SARM gem5 Developers } 153310037SARM gem5 Developers default: 153410037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 153510037SARM gem5 Developers } 153610037SARM gem5 Developers} 153710037SARM gem5 Developers 153810037SARM gem5 Developersvoid 153910037SARM gem5 DevelopersTableWalker::doLongDescriptor() 154010037SARM gem5 Developers{ 154110037SARM gem5 Developers if (currState->fault != NoFault) { 154210037SARM gem5 Developers return; 154310037SARM gem5 Developers } 154410037SARM gem5 Developers 154512526Schuan.zhu@arm.com currState->longDesc.data = htog(currState->longDesc.data, 154612526Schuan.zhu@arm.com byteOrder(currState->tc)); 154712526Schuan.zhu@arm.com 154810037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 154910037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 155010037SARM gem5 Developers currState->longDesc.data, 155110037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 155210037SARM gem5 Developers 155310037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 155410037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 155510037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 155610037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 155710037SARM gem5 Developers currState->longDesc.lookupLevel, 155810037SARM gem5 Developers currState->longDesc.data, 155910037SARM gem5 Developers currState->longDesc.pxn(), 156010037SARM gem5 Developers currState->longDesc.xn(), 156110037SARM gem5 Developers currState->longDesc.ap(), 156210037SARM gem5 Developers currState->longDesc.af(), 156310037SARM gem5 Developers currState->longDesc.type()); 156410037SARM gem5 Developers } else { 156510037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 156610037SARM gem5 Developers currState->longDesc.lookupLevel, 156710037SARM gem5 Developers currState->longDesc.data, 156810037SARM gem5 Developers currState->longDesc.type()); 156910037SARM gem5 Developers } 157010037SARM gem5 Developers 157110037SARM gem5 Developers TlbEntry te; 157210037SARM gem5 Developers 157310037SARM gem5 Developers switch (currState->longDesc.type()) { 157410037SARM gem5 Developers case LongDescriptor::Invalid: 15757439Sdam.sunwoo@arm.com if (!currState->timing) { 15767439Sdam.sunwoo@arm.com currState->tc = NULL; 15777439Sdam.sunwoo@arm.com currState->req = NULL; 15787437Sdam.sunwoo@arm.com } 15797404SAli.Saidi@ARM.com 158010037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 158110037SARM gem5 Developers currState->longDesc.lookupLevel, 158210037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 158310037SARM gem5 Developers if (currState->isFetch) 158410474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 158510037SARM gem5 Developers currState->vaddr_tainted, 158610037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 158710037SARM gem5 Developers isStage2, 158810037SARM gem5 Developers ArmFault::LpaeTran); 158910037SARM gem5 Developers else 159010474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 159110037SARM gem5 Developers currState->vaddr_tainted, 159210037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 159310037SARM gem5 Developers currState->isWrite, 159410037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 159510037SARM gem5 Developers isStage2, 159610037SARM gem5 Developers ArmFault::LpaeTran); 15977404SAli.Saidi@ARM.com return; 159810037SARM gem5 Developers case LongDescriptor::Block: 159910037SARM gem5 Developers case LongDescriptor::Page: 160010037SARM gem5 Developers { 160110037SARM gem5 Developers bool fault = false; 160210037SARM gem5 Developers bool aff = false; 160310037SARM gem5 Developers // Check for address size fault 160410037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 160510037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 160610037SARM gem5 Developers currState->longDesc.offsetBits()), 160710037SARM gem5 Developers currState->physAddrRange)) { 160810037SARM gem5 Developers fault = true; 160910037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 161010037SARM gem5 Developers currState->longDesc.lookupLevel); 161110037SARM gem5 Developers // Check for access fault 161210037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 161310037SARM gem5 Developers fault = true; 161410037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 161510037SARM gem5 Developers currState->longDesc.lookupLevel); 161610037SARM gem5 Developers aff = true; 161710037SARM gem5 Developers } 161810037SARM gem5 Developers if (fault) { 161910037SARM gem5 Developers if (currState->isFetch) 162010474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 162110037SARM gem5 Developers currState->vaddr_tainted, 162210037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 162310037SARM gem5 Developers currState->longDesc.lookupLevel, 162410037SARM gem5 Developers isStage2, 162510037SARM gem5 Developers ArmFault::LpaeTran); 162610037SARM gem5 Developers else 162710474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 162810037SARM gem5 Developers currState->vaddr_tainted, 162910037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 163010037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 163110037SARM gem5 Developers currState->longDesc.lookupLevel, 163210037SARM gem5 Developers isStage2, 163310037SARM gem5 Developers ArmFault::LpaeTran); 163410037SARM gem5 Developers } else { 163510037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 163610037SARM gem5 Developers } 163710037SARM gem5 Developers } 163810037SARM gem5 Developers return; 163910037SARM gem5 Developers case LongDescriptor::Table: 164010037SARM gem5 Developers { 164110037SARM gem5 Developers // Set hierarchical permission flags 164210037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 164310037SARM gem5 Developers currState->longDesc.secureTable(); 164410037SARM gem5 Developers currState->rwTable = currState->rwTable && 164510037SARM gem5 Developers currState->longDesc.rwTable(); 164610037SARM gem5 Developers currState->userTable = currState->userTable && 164710037SARM gem5 Developers currState->longDesc.userTable(); 164810037SARM gem5 Developers currState->xnTable = currState->xnTable || 164910037SARM gem5 Developers currState->longDesc.xnTable(); 165010037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 165110037SARM gem5 Developers currState->longDesc.pxnTable(); 16527404SAli.Saidi@ARM.com 165310037SARM gem5 Developers // Set up next level lookup 165410037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 165510037SARM gem5 Developers currState->vaddr); 16567439Sdam.sunwoo@arm.com 165710037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 165810037SARM gem5 Developers currState->longDesc.lookupLevel, 165910037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 166010037SARM gem5 Developers next_desc_addr, 166110037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 166210037SARM gem5 Developers 166310037SARM gem5 Developers // Check for address size fault 166410037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 166510037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 166610037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 166710037SARM gem5 Developers currState->longDesc.lookupLevel); 166810037SARM gem5 Developers if (currState->isFetch) 166910474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 167010037SARM gem5 Developers currState->vaddr_tainted, 167110037SARM gem5 Developers ArmFault::AddressSizeLL 167210037SARM gem5 Developers + currState->longDesc.lookupLevel, 167310037SARM gem5 Developers isStage2, 167410037SARM gem5 Developers ArmFault::LpaeTran); 167510037SARM gem5 Developers else 167610474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 167710037SARM gem5 Developers currState->vaddr_tainted, 167810037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 167910037SARM gem5 Developers ArmFault::AddressSizeLL 168010037SARM gem5 Developers + currState->longDesc.lookupLevel, 168110037SARM gem5 Developers isStage2, 168210037SARM gem5 Developers ArmFault::LpaeTran); 168310037SARM gem5 Developers return; 16847437Sdam.sunwoo@arm.com } 16857404SAli.Saidi@ARM.com 168610037SARM gem5 Developers // Trickbox address check 168711395Sandreas.sandberg@arm.com currState->fault = testWalk( 168811395Sandreas.sandberg@arm.com next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 168911395Sandreas.sandberg@arm.com toLookupLevel(currState->longDesc.lookupLevel +1)); 16907404SAli.Saidi@ARM.com 169110037SARM gem5 Developers if (currState->fault) { 169210037SARM gem5 Developers if (!currState->timing) { 169310037SARM gem5 Developers currState->tc = NULL; 169410037SARM gem5 Developers currState->req = NULL; 169510037SARM gem5 Developers } 169610037SARM gem5 Developers return; 169710037SARM gem5 Developers } 169810037SARM gem5 Developers 169910836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 170010037SARM gem5 Developers if (currState->secureLookup) 170110037SARM gem5 Developers flag.set(Request::SECURE); 170210037SARM gem5 Developers 170311588SCurtis.Dunham@arm.com LookupLevel L = currState->longDesc.lookupLevel = 170410037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 170510037SARM gem5 Developers Event *event = NULL; 170611588SCurtis.Dunham@arm.com switch (L) { 170710037SARM gem5 Developers case L1: 170810037SARM gem5 Developers assert(currState->aarch64); 170910037SARM gem5 Developers case L2: 171010037SARM gem5 Developers case L3: 171111588SCurtis.Dunham@arm.com event = LongDescEventByLevel[L]; 171210037SARM gem5 Developers break; 171310037SARM gem5 Developers default: 171410037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 171510037SARM gem5 Developers break; 171610037SARM gem5 Developers } 171710037SARM gem5 Developers 171810037SARM gem5 Developers bool delayed; 171910037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 172010037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 172110037SARM gem5 Developers &TableWalker::doLongDescriptor); 172210037SARM gem5 Developers if (delayed) { 172310037SARM gem5 Developers currState->delayed = true; 172410037SARM gem5 Developers } 17257404SAli.Saidi@ARM.com } 17267404SAli.Saidi@ARM.com return; 17277404SAli.Saidi@ARM.com default: 17287404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 17297404SAli.Saidi@ARM.com } 17307404SAli.Saidi@ARM.com} 17317404SAli.Saidi@ARM.com 17327404SAli.Saidi@ARM.comvoid 17337404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 17347404SAli.Saidi@ARM.com{ 173510037SARM gem5 Developers if (currState->fault != NoFault) { 173610037SARM gem5 Developers return; 173710037SARM gem5 Developers } 173810037SARM gem5 Developers 173912526Schuan.zhu@arm.com currState->l2Desc.data = htog(currState->l2Desc.data, 174012526Schuan.zhu@arm.com byteOrder(currState->tc)); 174112526Schuan.zhu@arm.com 17427439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 174310037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 17447404SAli.Saidi@ARM.com TlbEntry te; 17457404SAli.Saidi@ARM.com 17467439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 17477404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 17487946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 17497439Sdam.sunwoo@arm.com currState->tc = NULL; 17507439Sdam.sunwoo@arm.com currState->req = NULL; 17517437Sdam.sunwoo@arm.com } 17527439Sdam.sunwoo@arm.com if (currState->isFetch) 175310474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 175410474Sandreas.hansson@arm.com currState->vaddr_tainted, 175510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L2, 175610474Sandreas.hansson@arm.com isStage2, 175710474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17587406SAli.Saidi@ARM.com else 175910474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 176010474Sandreas.hansson@arm.com currState->vaddr_tainted, currState->l1Desc.domain(), 176110474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L2, 176210474Sandreas.hansson@arm.com isStage2, 176310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17647404SAli.Saidi@ARM.com return; 17657404SAli.Saidi@ARM.com } 17667404SAli.Saidi@ARM.com 17677439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 17687436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 17697436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 17707436Sdam.sunwoo@arm.com */ 177110037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 177210037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 17737436Sdam.sunwoo@arm.com 177410474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 177510474Sandreas.hansson@arm.com currState->vaddr_tainted, 177610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 177710474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L2, isStage2, 177810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17797436Sdam.sunwoo@arm.com } 17807436Sdam.sunwoo@arm.com 178110037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 17827437Sdam.sunwoo@arm.com} 17837437Sdam.sunwoo@arm.com 17847437Sdam.sunwoo@arm.comvoid 17857437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 17867437Sdam.sunwoo@arm.com{ 178710037SARM gem5 Developers currState = stateQueues[L1].front(); 17887439Sdam.sunwoo@arm.com currState->delayed = false; 178910037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 179010037SARM gem5 Developers if (currState->stage2Tran) { 179110037SARM gem5 Developers delete currState->stage2Tran; 179210037SARM gem5 Developers currState->stage2Tran = NULL; 179310037SARM gem5 Developers } 179410037SARM gem5 Developers 17957437Sdam.sunwoo@arm.com 17967578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 17977578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 17987578Sdam.sunwoo@arm.com 179910037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 18007437Sdam.sunwoo@arm.com doL1Descriptor(); 18017437Sdam.sunwoo@arm.com 180210037SARM gem5 Developers stateQueues[L1].pop_front(); 18037437Sdam.sunwoo@arm.com // Check if fault was generated 18047439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18057439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18067439Sdam.sunwoo@arm.com currState->tc, currState->mode); 180710621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 18087437Sdam.sunwoo@arm.com 18097728SAli.Saidi@ARM.com pending = false; 18107728SAli.Saidi@ARM.com nextWalk(currState->tc); 18117728SAli.Saidi@ARM.com 18127439Sdam.sunwoo@arm.com currState->req = NULL; 18137439Sdam.sunwoo@arm.com currState->tc = NULL; 18147439Sdam.sunwoo@arm.com currState->delayed = false; 18158510SAli.Saidi@ARM.com delete currState; 18167437Sdam.sunwoo@arm.com } 18177439Sdam.sunwoo@arm.com else if (!currState->delayed) { 18187653Sgene.wu@arm.com // delay is not set so there is no L2 to do 181910037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 182010037SARM gem5 Developers if (!currState->doingStage2) { 182110621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 182210037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 182312406Sgabeblack@google.com tlb->translateTiming(currState->req, currState->tc, 182412406Sgabeblack@google.com currState->transState, currState->mode); 182510621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 182610037SARM gem5 Developers } 18277437Sdam.sunwoo@arm.com 18287728SAli.Saidi@ARM.com pending = false; 18297728SAli.Saidi@ARM.com nextWalk(currState->tc); 18307728SAli.Saidi@ARM.com 18317439Sdam.sunwoo@arm.com currState->req = NULL; 18327439Sdam.sunwoo@arm.com currState->tc = NULL; 18337439Sdam.sunwoo@arm.com currState->delayed = false; 18347653Sgene.wu@arm.com delete currState; 18357653Sgene.wu@arm.com } else { 18367653Sgene.wu@arm.com // need to do L2 descriptor 183710037SARM gem5 Developers stateQueues[L2].push_back(currState); 18387437Sdam.sunwoo@arm.com } 18397439Sdam.sunwoo@arm.com currState = NULL; 18407437Sdam.sunwoo@arm.com} 18417437Sdam.sunwoo@arm.com 18427437Sdam.sunwoo@arm.comvoid 18437437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 18447437Sdam.sunwoo@arm.com{ 184510037SARM gem5 Developers currState = stateQueues[L2].front(); 18467439Sdam.sunwoo@arm.com assert(currState->delayed); 184710037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 184810037SARM gem5 Developers if (currState->stage2Tran) { 184910037SARM gem5 Developers delete currState->stage2Tran; 185010037SARM gem5 Developers currState->stage2Tran = NULL; 185110037SARM gem5 Developers } 18527437Sdam.sunwoo@arm.com 18537439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 185410037SARM gem5 Developers currState->vaddr_tainted); 18557437Sdam.sunwoo@arm.com doL2Descriptor(); 18567437Sdam.sunwoo@arm.com 18577437Sdam.sunwoo@arm.com // Check if fault was generated 18587439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18597439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18607439Sdam.sunwoo@arm.com currState->tc, currState->mode); 186110621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 18627437Sdam.sunwoo@arm.com } 18637437Sdam.sunwoo@arm.com else { 186410037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 186510037SARM gem5 Developers if (!currState->doingStage2) { 186610621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 186710037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 186812406Sgabeblack@google.com tlb->translateTiming(currState->req, currState->tc, 186912406Sgabeblack@google.com currState->transState, currState->mode); 187010621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 187110037SARM gem5 Developers } 18727437Sdam.sunwoo@arm.com } 18737437Sdam.sunwoo@arm.com 18747728SAli.Saidi@ARM.com 187510037SARM gem5 Developers stateQueues[L2].pop_front(); 18767728SAli.Saidi@ARM.com pending = false; 18777728SAli.Saidi@ARM.com nextWalk(currState->tc); 18787728SAli.Saidi@ARM.com 18797439Sdam.sunwoo@arm.com currState->req = NULL; 18807439Sdam.sunwoo@arm.com currState->tc = NULL; 18817439Sdam.sunwoo@arm.com currState->delayed = false; 18827439Sdam.sunwoo@arm.com 18837653Sgene.wu@arm.com delete currState; 18847439Sdam.sunwoo@arm.com currState = NULL; 18857404SAli.Saidi@ARM.com} 18867404SAli.Saidi@ARM.com 18877728SAli.Saidi@ARM.comvoid 188810037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 188910037SARM gem5 Developers{ 189010037SARM gem5 Developers doLongDescriptorWrapper(L0); 189110037SARM gem5 Developers} 189210037SARM gem5 Developers 189310037SARM gem5 Developersvoid 189410037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 189510037SARM gem5 Developers{ 189610037SARM gem5 Developers doLongDescriptorWrapper(L1); 189710037SARM gem5 Developers} 189810037SARM gem5 Developers 189910037SARM gem5 Developersvoid 190010037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 190110037SARM gem5 Developers{ 190210037SARM gem5 Developers doLongDescriptorWrapper(L2); 190310037SARM gem5 Developers} 190410037SARM gem5 Developers 190510037SARM gem5 Developersvoid 190610037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 190710037SARM gem5 Developers{ 190810037SARM gem5 Developers doLongDescriptorWrapper(L3); 190910037SARM gem5 Developers} 191010037SARM gem5 Developers 191110037SARM gem5 Developersvoid 191210037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 191310037SARM gem5 Developers{ 191410037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 191510037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 191610037SARM gem5 Developers currState->delayed = false; 191710037SARM gem5 Developers 191810037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 191910037SARM gem5 Developers if (currState->stage2Tran) { 192010037SARM gem5 Developers delete currState->stage2Tran; 192110037SARM gem5 Developers currState->stage2Tran = NULL; 192210037SARM gem5 Developers } 192310037SARM gem5 Developers 192410037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 192510037SARM gem5 Developers currState->vaddr_tainted); 192610037SARM gem5 Developers doLongDescriptor(); 192710037SARM gem5 Developers 192810037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 192910037SARM gem5 Developers 193010037SARM gem5 Developers if (currState->fault != NoFault) { 193110037SARM gem5 Developers // A fault was generated 193210037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 193310037SARM gem5 Developers currState->tc, currState->mode); 193410037SARM gem5 Developers 193510037SARM gem5 Developers pending = false; 193610037SARM gem5 Developers nextWalk(currState->tc); 193710037SARM gem5 Developers 193810037SARM gem5 Developers currState->req = NULL; 193910037SARM gem5 Developers currState->tc = NULL; 194010037SARM gem5 Developers currState->delayed = false; 194110037SARM gem5 Developers delete currState; 194210037SARM gem5 Developers } else if (!currState->delayed) { 194310037SARM gem5 Developers // No additional lookups required 194410037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 194510037SARM gem5 Developers if (!currState->doingStage2) { 194610037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 194710621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 194812406Sgabeblack@google.com tlb->translateTiming(currState->req, currState->tc, 194912406Sgabeblack@google.com currState->transState, currState->mode); 195010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 195110037SARM gem5 Developers } 195210037SARM gem5 Developers 195310037SARM gem5 Developers pending = false; 195410037SARM gem5 Developers nextWalk(currState->tc); 195510037SARM gem5 Developers 195610037SARM gem5 Developers currState->req = NULL; 195710037SARM gem5 Developers currState->tc = NULL; 195810037SARM gem5 Developers currState->delayed = false; 195910037SARM gem5 Developers delete currState; 196010037SARM gem5 Developers } else { 196110037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 196210037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 196310037SARM gem5 Developers // Need to perform additional lookups 196410037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 196510037SARM gem5 Developers } 196610037SARM gem5 Developers currState = NULL; 196710037SARM gem5 Developers} 196810037SARM gem5 Developers 196910037SARM gem5 Developers 197010037SARM gem5 Developersvoid 19717728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 19727728SAli.Saidi@ARM.com{ 19737728SAli.Saidi@ARM.com if (pendingQueue.size()) 19749309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 197510509SAli.Saidi@ARM.com else 197610509SAli.Saidi@ARM.com completeDrain(); 19777728SAli.Saidi@ARM.com} 19787728SAli.Saidi@ARM.com 197910037SARM gem5 Developersbool 198010037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 198110037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 198210037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 198310037SARM gem5 Developers{ 198410037SARM gem5 Developers bool isTiming = currState->timing; 19857728SAli.Saidi@ARM.com 198611575SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 198711575SDylan.Johnson@ARM.com descAddr, currState->stage2Req); 198811575SDylan.Johnson@ARM.com 198911575SDylan.Johnson@ARM.com // If this translation has a stage 2 then we know descAddr is an IPA and 199011575SDylan.Johnson@ARM.com // needs to be translated before we can access the page table. Do that 199111575SDylan.Johnson@ARM.com // check here. 199210037SARM gem5 Developers if (currState->stage2Req) { 199310037SARM gem5 Developers Fault fault; 199410037SARM gem5 Developers flags = flags | TLB::MustBeOne; 199510037SARM gem5 Developers 199610037SARM gem5 Developers if (isTiming) { 199710037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 199810037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 199910037SARM gem5 Developers currState->vaddr); 200010037SARM gem5 Developers currState->stage2Tran = tran; 200110037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 200210717Sandreas.hansson@arm.com flags); 200310037SARM gem5 Developers fault = tran->fault; 200410037SARM gem5 Developers } else { 200510037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 200610717Sandreas.hansson@arm.com currState->vaddr, descAddr, data, numBytes, flags, 200710037SARM gem5 Developers currState->functional); 200810037SARM gem5 Developers } 200910037SARM gem5 Developers 201010037SARM gem5 Developers if (fault != NoFault) { 201110037SARM gem5 Developers currState->fault = fault; 201210037SARM gem5 Developers } 201310037SARM gem5 Developers if (isTiming) { 201410037SARM gem5 Developers if (queueIndex >= 0) { 201510037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 201610037SARM gem5 Developers stateQueues[queueIndex].size()); 201710037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 201810037SARM gem5 Developers currState = NULL; 201910037SARM gem5 Developers } 202010037SARM gem5 Developers } else { 202110037SARM gem5 Developers (this->*doDescriptor)(); 202210037SARM gem5 Developers } 202310037SARM gem5 Developers } else { 202410037SARM gem5 Developers if (isTiming) { 202510717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 202610621SCurtis.Dunham@arm.com currState->tc->getCpuPtr()->clockPeriod(),flags); 202710037SARM gem5 Developers if (queueIndex >= 0) { 202810037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 202910037SARM gem5 Developers stateQueues[queueIndex].size()); 203010037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 203110037SARM gem5 Developers currState = NULL; 203210037SARM gem5 Developers } 203310037SARM gem5 Developers } else if (!currState->functional) { 203410717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 203510037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 203610037SARM gem5 Developers (this->*doDescriptor)(); 203710037SARM gem5 Developers } else { 203810037SARM gem5 Developers RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 203910037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 204010037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 204110037SARM gem5 Developers pkt->dataStatic(data); 204210717Sandreas.hansson@arm.com port->sendFunctional(pkt); 204310037SARM gem5 Developers (this->*doDescriptor)(); 204410037SARM gem5 Developers delete req; 204510037SARM gem5 Developers delete pkt; 204610037SARM gem5 Developers } 204710037SARM gem5 Developers } 204810037SARM gem5 Developers return (isTiming); 204910037SARM gem5 Developers} 205010037SARM gem5 Developers 205110037SARM gem5 Developersvoid 205210037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 205310037SARM gem5 Developers{ 205410037SARM gem5 Developers TlbEntry te; 205510037SARM gem5 Developers 205610037SARM gem5 Developers // Create and fill a new page table entry 205710037SARM gem5 Developers te.valid = true; 205810037SARM gem5 Developers te.longDescFormat = longDescriptor; 205910037SARM gem5 Developers te.isHyp = currState->isHyp; 206010037SARM gem5 Developers te.asid = currState->asid; 206110037SARM gem5 Developers te.vmid = currState->vmid; 206210037SARM gem5 Developers te.N = descriptor.offsetBits(); 206310037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 206410037SARM gem5 Developers te.size = (1<<te.N) - 1; 206510037SARM gem5 Developers te.pfn = descriptor.pfn(); 206610037SARM gem5 Developers te.domain = descriptor.domain(); 206710037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 206810037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 206910037SARM gem5 Developers te.nstid = !currState->isSecure; 207010037SARM gem5 Developers te.xn = descriptor.xn(); 207110037SARM gem5 Developers if (currState->aarch64) 207210037SARM gem5 Developers te.el = currState->el; 207310037SARM gem5 Developers else 207410037SARM gem5 Developers te.el = 1; 207510037SARM gem5 Developers 207610621SCurtis.Dunham@arm.com statPageSizes[pageSizeNtoStatBin(te.N)]++; 207710621SCurtis.Dunham@arm.com statRequestOrigin[COMPLETED][currState->isFetch]++; 207810621SCurtis.Dunham@arm.com 207910037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 208010037SARM gem5 Developers // as global 208110037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 208210037SARM gem5 Developers if (longDescriptor) { 208310037SARM gem5 Developers LongDescriptor lDescriptor = 208410037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 208510037SARM gem5 Developers 208610037SARM gem5 Developers te.xn |= currState->xnTable; 208710037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 208810037SARM gem5 Developers if (isStage2) { 208910037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 209010037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 209110037SARM gem5 Developers te.hap = lDescriptor.ap(); 209210037SARM gem5 Developers } else { 209310037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 209410037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 209510037SARM gem5 Developers } 209610037SARM gem5 Developers if (currState->aarch64) 209711583SDylan.Johnson@ARM.com memAttrsAArch64(currState->tc, te, lDescriptor); 209810037SARM gem5 Developers else 209910037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 210010037SARM gem5 Developers } else { 210110037SARM gem5 Developers te.ap = descriptor.ap(); 210210037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 210310037SARM gem5 Developers descriptor.shareable()); 210410037SARM gem5 Developers } 210510037SARM gem5 Developers 210610037SARM gem5 Developers // Debug output 210710037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 210810037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 210910037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 211010037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 211110037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 211210037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 211310037SARM gem5 Developers te.nonCacheable, te.ns); 211410037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 211510037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 211610037SARM gem5 Developers descriptor.getRawData()); 211710037SARM gem5 Developers 211810037SARM gem5 Developers // Insert the entry into the TLB 211910037SARM gem5 Developers tlb->insert(currState->vaddr, te); 212010037SARM gem5 Developers if (!currState->timing) { 212110037SARM gem5 Developers currState->tc = NULL; 212210037SARM gem5 Developers currState->req = NULL; 212310037SARM gem5 Developers } 212410037SARM gem5 Developers} 21257728SAli.Saidi@ARM.com 21267404SAli.Saidi@ARM.comArmISA::TableWalker * 21277404SAli.Saidi@ARM.comArmTableWalkerParams::create() 21287404SAli.Saidi@ARM.com{ 21297404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 21307404SAli.Saidi@ARM.com} 21317404SAli.Saidi@ARM.com 213210037SARM gem5 DevelopersLookupLevel 213310037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 213410037SARM gem5 Developers{ 213510037SARM gem5 Developers switch (lookup_level_as_int) { 213610037SARM gem5 Developers case L1: 213710037SARM gem5 Developers return L1; 213810037SARM gem5 Developers case L2: 213910037SARM gem5 Developers return L2; 214010037SARM gem5 Developers case L3: 214110037SARM gem5 Developers return L3; 214210037SARM gem5 Developers default: 214310037SARM gem5 Developers panic("Invalid lookup level conversion"); 214410037SARM gem5 Developers } 214510037SARM gem5 Developers} 214610621SCurtis.Dunham@arm.com 214710621SCurtis.Dunham@arm.com/* this method keeps track of the table walker queue's residency, so 214810621SCurtis.Dunham@arm.com * needs to be called whenever requests start and complete. */ 214910621SCurtis.Dunham@arm.comvoid 215010621SCurtis.Dunham@arm.comTableWalker::pendingChange() 215110621SCurtis.Dunham@arm.com{ 215210621SCurtis.Dunham@arm.com unsigned n = pendingQueue.size(); 215310621SCurtis.Dunham@arm.com if ((currState != NULL) && (currState != pendingQueue.front())) { 215410621SCurtis.Dunham@arm.com ++n; 215510621SCurtis.Dunham@arm.com } 215610621SCurtis.Dunham@arm.com 215710621SCurtis.Dunham@arm.com if (n != pendingReqs) { 215810621SCurtis.Dunham@arm.com Tick now = curTick(); 215910621SCurtis.Dunham@arm.com statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 216010621SCurtis.Dunham@arm.com pendingReqs = n; 216110621SCurtis.Dunham@arm.com pendingChangeTick = now; 216210621SCurtis.Dunham@arm.com } 216310621SCurtis.Dunham@arm.com} 216410621SCurtis.Dunham@arm.com 216511395Sandreas.sandberg@arm.comFault 216611395Sandreas.sandberg@arm.comTableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 216711395Sandreas.sandberg@arm.com LookupLevel lookup_level) 216811395Sandreas.sandberg@arm.com{ 216911395Sandreas.sandberg@arm.com return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 217011395Sandreas.sandberg@arm.com currState->mode, domain, lookup_level); 217111395Sandreas.sandberg@arm.com} 217211395Sandreas.sandberg@arm.com 217311395Sandreas.sandberg@arm.com 217410621SCurtis.Dunham@arm.comuint8_t 217510621SCurtis.Dunham@arm.comTableWalker::pageSizeNtoStatBin(uint8_t N) 217610621SCurtis.Dunham@arm.com{ 217710621SCurtis.Dunham@arm.com /* for statPageSizes */ 217810621SCurtis.Dunham@arm.com switch(N) { 217910621SCurtis.Dunham@arm.com case 12: return 0; // 4K 218010621SCurtis.Dunham@arm.com case 14: return 1; // 16K (using 16K granule in v8-64) 218110621SCurtis.Dunham@arm.com case 16: return 2; // 64K 218210621SCurtis.Dunham@arm.com case 20: return 3; // 1M 218310621SCurtis.Dunham@arm.com case 21: return 4; // 2M-LPAE 218410621SCurtis.Dunham@arm.com case 24: return 5; // 16M 218510621SCurtis.Dunham@arm.com case 25: return 6; // 32M (using 16K granule in v8-64) 218610621SCurtis.Dunham@arm.com case 29: return 7; // 512M (using 64K granule in v8-64) 218710621SCurtis.Dunham@arm.com case 30: return 8; // 1G-LPAE 218810621SCurtis.Dunham@arm.com default: 218910621SCurtis.Dunham@arm.com panic("unknown page size"); 219010621SCurtis.Dunham@arm.com return 255; 219110621SCurtis.Dunham@arm.com } 219210621SCurtis.Dunham@arm.com} 219310621SCurtis.Dunham@arm.com 219410621SCurtis.Dunham@arm.comvoid 219510621SCurtis.Dunham@arm.comTableWalker::regStats() 219610621SCurtis.Dunham@arm.com{ 219711522Sstephan.diestelhorst@arm.com ClockedObject::regStats(); 219811522Sstephan.diestelhorst@arm.com 219910621SCurtis.Dunham@arm.com statWalks 220010621SCurtis.Dunham@arm.com .name(name() + ".walks") 220110621SCurtis.Dunham@arm.com .desc("Table walker walks requested") 220210621SCurtis.Dunham@arm.com ; 220310621SCurtis.Dunham@arm.com 220410621SCurtis.Dunham@arm.com statWalksShortDescriptor 220510621SCurtis.Dunham@arm.com .name(name() + ".walksShort") 220610621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with short descriptors") 220710621SCurtis.Dunham@arm.com .flags(Stats::nozero) 220810621SCurtis.Dunham@arm.com ; 220910621SCurtis.Dunham@arm.com 221010621SCurtis.Dunham@arm.com statWalksLongDescriptor 221110621SCurtis.Dunham@arm.com .name(name() + ".walksLong") 221210621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with long descriptors") 221310621SCurtis.Dunham@arm.com .flags(Stats::nozero) 221410621SCurtis.Dunham@arm.com ; 221510621SCurtis.Dunham@arm.com 221610621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel 221710621SCurtis.Dunham@arm.com .init(2) 221810621SCurtis.Dunham@arm.com .name(name() + ".walksShortTerminationLevel") 221910621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 222010621SCurtis.Dunham@arm.com "with short descriptors terminate") 222110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 222210621SCurtis.Dunham@arm.com ; 222310621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(0, "Level1"); 222410621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(1, "Level2"); 222510621SCurtis.Dunham@arm.com 222610621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel 222710621SCurtis.Dunham@arm.com .init(4) 222810621SCurtis.Dunham@arm.com .name(name() + ".walksLongTerminationLevel") 222910621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 223010621SCurtis.Dunham@arm.com "with long descriptors terminate") 223110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 223210621SCurtis.Dunham@arm.com ; 223310621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(0, "Level0"); 223410621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(1, "Level1"); 223510621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(2, "Level2"); 223610621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(3, "Level3"); 223710621SCurtis.Dunham@arm.com 223810621SCurtis.Dunham@arm.com statSquashedBefore 223910621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedBefore") 224010621SCurtis.Dunham@arm.com .desc("Table walks squashed before starting") 224110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 224210621SCurtis.Dunham@arm.com ; 224310621SCurtis.Dunham@arm.com 224410621SCurtis.Dunham@arm.com statSquashedAfter 224510621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedAfter") 224610621SCurtis.Dunham@arm.com .desc("Table walks squashed after completion") 224710621SCurtis.Dunham@arm.com .flags(Stats::nozero) 224810621SCurtis.Dunham@arm.com ; 224910621SCurtis.Dunham@arm.com 225010621SCurtis.Dunham@arm.com statWalkWaitTime 225110621SCurtis.Dunham@arm.com .init(16) 225210621SCurtis.Dunham@arm.com .name(name() + ".walkWaitTime") 225310621SCurtis.Dunham@arm.com .desc("Table walker wait (enqueue to first request) latency") 225410621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 225510621SCurtis.Dunham@arm.com ; 225610621SCurtis.Dunham@arm.com 225710621SCurtis.Dunham@arm.com statWalkServiceTime 225810621SCurtis.Dunham@arm.com .init(16) 225910621SCurtis.Dunham@arm.com .name(name() + ".walkCompletionTime") 226010621SCurtis.Dunham@arm.com .desc("Table walker service (enqueue to completion) latency") 226110621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 226210621SCurtis.Dunham@arm.com ; 226310621SCurtis.Dunham@arm.com 226410621SCurtis.Dunham@arm.com statPendingWalks 226510621SCurtis.Dunham@arm.com .init(16) 226610621SCurtis.Dunham@arm.com .name(name() + ".walksPending") 226710621SCurtis.Dunham@arm.com .desc("Table walker pending requests distribution") 226810621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 226910621SCurtis.Dunham@arm.com ; 227010621SCurtis.Dunham@arm.com 227110621SCurtis.Dunham@arm.com statPageSizes // see DDI 0487A D4-1661 227210621SCurtis.Dunham@arm.com .init(9) 227310621SCurtis.Dunham@arm.com .name(name() + ".walkPageSizes") 227410621SCurtis.Dunham@arm.com .desc("Table walker page sizes translated") 227510621SCurtis.Dunham@arm.com .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 227610621SCurtis.Dunham@arm.com ; 227710621SCurtis.Dunham@arm.com statPageSizes.subname(0, "4K"); 227810621SCurtis.Dunham@arm.com statPageSizes.subname(1, "16K"); 227910621SCurtis.Dunham@arm.com statPageSizes.subname(2, "64K"); 228010621SCurtis.Dunham@arm.com statPageSizes.subname(3, "1M"); 228110621SCurtis.Dunham@arm.com statPageSizes.subname(4, "2M"); 228210621SCurtis.Dunham@arm.com statPageSizes.subname(5, "16M"); 228310621SCurtis.Dunham@arm.com statPageSizes.subname(6, "32M"); 228410621SCurtis.Dunham@arm.com statPageSizes.subname(7, "512M"); 228510621SCurtis.Dunham@arm.com statPageSizes.subname(8, "1G"); 228610621SCurtis.Dunham@arm.com 228710621SCurtis.Dunham@arm.com statRequestOrigin 228810621SCurtis.Dunham@arm.com .init(2,2) // Instruction/Data, requests/completed 228910621SCurtis.Dunham@arm.com .name(name() + ".walkRequestOrigin") 229010621SCurtis.Dunham@arm.com .desc("Table walker requests started/completed, data/inst") 229110621SCurtis.Dunham@arm.com .flags(Stats::total) 229210621SCurtis.Dunham@arm.com ; 229310621SCurtis.Dunham@arm.com statRequestOrigin.subname(0,"Requested"); 229410621SCurtis.Dunham@arm.com statRequestOrigin.subname(1,"Completed"); 229510621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(0,"Data"); 229610621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(1,"Inst"); 229710621SCurtis.Dunham@arm.com} 2298