table_walker.cc revision 11938
17404SAli.Saidi@ARM.com/* 211938Snikos.nikoleris@arm.com * Copyright (c) 2010, 2012-2017 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 4010873Sandreas.sandberg@arm.com#include "arch/arm/table_walker.hh" 417404SAli.Saidi@ARM.com 4210474Sandreas.hansson@arm.com#include <memory> 4310474Sandreas.hansson@arm.com 447404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4510037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4610037SARM gem5 Developers#include "arch/arm/system.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 487728SAli.Saidi@ARM.com#include "cpu/base.hh" 497404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 508245Snate@binkert.org#include "debug/Checkpoint.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528245Snate@binkert.org#include "debug/TLB.hh" 538245Snate@binkert.org#include "debug/TLBVerbose.hh" 5410873Sandreas.sandberg@arm.com#include "dev/dma_device.hh" 557748SAli.Saidi@ARM.com#include "sim/system.hh" 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comusing namespace ArmISA; 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 6010913Sandreas.sandberg@arm.com : MemObject(p), 6110717Sandreas.hansson@arm.com stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 6210717Sandreas.hansson@arm.com isStage2(p->is_stage2), tlb(NULL), 6310717Sandreas.hansson@arm.com currState(NULL), pending(false), 649258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6510621SCurtis.Dunham@arm.com pendingReqs(0), 6610621SCurtis.Dunham@arm.com pendingChangeTick(curTick()), 6710037SARM gem5 Developers doL1DescEvent(this), doL2DescEvent(this), 6811588SCurtis.Dunham@arm.com doL0LongDescEvent(this), doL1LongDescEvent(this), 6911588SCurtis.Dunham@arm.com doL2LongDescEvent(this), doL3LongDescEvent(this), 7011588SCurtis.Dunham@arm.com LongDescEventByLevel { &doL0LongDescEvent, &doL1LongDescEvent, 7111588SCurtis.Dunham@arm.com &doL2LongDescEvent, &doL3LongDescEvent }, 7210037SARM gem5 Developers doProcessEvent(this) 737439Sdam.sunwoo@arm.com{ 747576SAli.Saidi@ARM.com sctlr = 0; 7510037SARM gem5 Developers 7610037SARM gem5 Developers // Cache system-level properties 7710037SARM gem5 Developers if (FullSystem) { 7810717Sandreas.hansson@arm.com ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 7910037SARM gem5 Developers assert(armSys); 8010037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 8110037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 8210037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 8310037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 8410037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 8510037SARM gem5 Developers } else { 8610037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 8710037SARM gem5 Developers _haveLargeAsid64 = false; 8810037SARM gem5 Developers physAddrRange = 32; 8910037SARM gem5 Developers } 9010037SARM gem5 Developers 917439Sdam.sunwoo@arm.com} 927404SAli.Saidi@ARM.com 937404SAli.Saidi@ARM.comTableWalker::~TableWalker() 947404SAli.Saidi@ARM.com{ 957404SAli.Saidi@ARM.com ; 967404SAli.Saidi@ARM.com} 977404SAli.Saidi@ARM.com 9810717Sandreas.hansson@arm.comvoid 9910717Sandreas.hansson@arm.comTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 10010717Sandreas.hansson@arm.com{ 10110717Sandreas.hansson@arm.com stage2Mmu = m; 10210717Sandreas.hansson@arm.com port = &m->getPort(); 10310717Sandreas.hansson@arm.com masterId = master_id; 10410717Sandreas.hansson@arm.com} 10510717Sandreas.hansson@arm.com 10610717Sandreas.hansson@arm.comvoid 10710717Sandreas.hansson@arm.comTableWalker::init() 10810717Sandreas.hansson@arm.com{ 10910717Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 11010717Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 11110717Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 11210717Sandreas.hansson@arm.com} 11310717Sandreas.hansson@arm.com 11410717Sandreas.hansson@arm.comBaseMasterPort& 11510717Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 11610717Sandreas.hansson@arm.com{ 11710717Sandreas.hansson@arm.com if (if_name == "port") { 11810717Sandreas.hansson@arm.com if (!isStage2) { 11910717Sandreas.hansson@arm.com return *port; 12010717Sandreas.hansson@arm.com } else { 12110717Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 12210717Sandreas.hansson@arm.com } 12310717Sandreas.hansson@arm.com } 12410717Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 12510717Sandreas.hansson@arm.com} 12610717Sandreas.hansson@arm.com 12710537Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 12810537Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 12910537Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 13010537Sandreas.hansson@arm.com vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 13110537Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 13210537Sandreas.hansson@arm.com pxnTable(false), stage2Req(false), doingStage2(false), 13310537Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 13410537Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 13510537Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 13610037SARM gem5 Developers{ 13710037SARM gem5 Developers} 13810037SARM gem5 Developers 1399152Satgutier@umich.eduvoid 1409152Satgutier@umich.eduTableWalker::completeDrain() 1419152Satgutier@umich.edu{ 14210913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 14311588SCurtis.Dunham@arm.com stateQueues[L0].empty() && stateQueues[L1].empty() && 14411588SCurtis.Dunham@arm.com stateQueues[L2].empty() && stateQueues[L3].empty() && 1459152Satgutier@umich.edu pendingQueue.empty()) { 14610913Sandreas.sandberg@arm.com 1479152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 14810913Sandreas.sandberg@arm.com signalDrainDone(); 1499152Satgutier@umich.edu } 1509152Satgutier@umich.edu} 1519152Satgutier@umich.edu 15210913Sandreas.sandberg@arm.comDrainState 15310913Sandreas.sandberg@arm.comTableWalker::drain() 1547404SAli.Saidi@ARM.com{ 15510037SARM gem5 Developers bool state_queues_not_empty = false; 1569152Satgutier@umich.edu 15710037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 15810037SARM gem5 Developers if (!stateQueues[i].empty()) { 15910037SARM gem5 Developers state_queues_not_empty = true; 16010037SARM gem5 Developers break; 16110037SARM gem5 Developers } 16210037SARM gem5 Developers } 16310037SARM gem5 Developers 16410037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1659152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 16610913Sandreas.sandberg@arm.com return DrainState::Draining; 16710037SARM gem5 Developers } else { 16810037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 16910913Sandreas.sandberg@arm.com return DrainState::Drained; 1707733SAli.Saidi@ARM.com } 1717404SAli.Saidi@ARM.com} 1727404SAli.Saidi@ARM.com 1737748SAli.Saidi@ARM.comvoid 1749342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1757748SAli.Saidi@ARM.com{ 1769524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1779152Satgutier@umich.edu delete currState; 1789152Satgutier@umich.edu currState = NULL; 17910621SCurtis.Dunham@arm.com pendingChange(); 1807748SAli.Saidi@ARM.com } 1817748SAli.Saidi@ARM.com} 1827748SAli.Saidi@ARM.com 1837404SAli.Saidi@ARM.comFault 18410037SARM gem5 DevelopersTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 18510037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 18610037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 18711580SDylan.Johnson@ARM.com bool secure, TLB::ArmTranslationType tranType, 18811580SDylan.Johnson@ARM.com bool _stage2Req) 1897404SAli.Saidi@ARM.com{ 1908733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 19110621SCurtis.Dunham@arm.com ++statWalks; 19210621SCurtis.Dunham@arm.com 19310109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 19410037SARM gem5 Developers 19510109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 1967439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1977439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1987439Sdam.sunwoo@arm.com // TLB miss. 1997439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 2007404SAli.Saidi@ARM.com 2017439Sdam.sunwoo@arm.com currState = new WalkerState(); 2027439Sdam.sunwoo@arm.com currState->tableWalker = this; 20310109SGeoffrey.Blake@arm.com } else if (_functional) { 20410109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 20510109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 20610109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 20710109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 20810109SGeoffrey.Blake@arm.com savedCurrState = currState; 20910109SGeoffrey.Blake@arm.com currState = new WalkerState(); 21010109SGeoffrey.Blake@arm.com currState->tableWalker = this; 2118202SAli.Saidi@ARM.com } else if (_timing) { 2128202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 2138202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 2148202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 2158202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 2168202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 2178202SAli.Saidi@ARM.com // up everything. 21810037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 21910621SCurtis.Dunham@arm.com ++statSquashedBefore; 22010474Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 2218202SAli.Saidi@ARM.com } 2227439Sdam.sunwoo@arm.com } 22310621SCurtis.Dunham@arm.com pendingChange(); 2247439Sdam.sunwoo@arm.com 22510621SCurtis.Dunham@arm.com currState->startTime = curTick(); 2267439Sdam.sunwoo@arm.com currState->tc = _tc; 22711517SCurtis.Dunham@arm.com // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 22811517SCurtis.Dunham@arm.com // aarch32/translation/translation/AArch32.TranslateAddress dictates 22911517SCurtis.Dunham@arm.com // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 23011574SCurtis.Dunham@arm.com currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || 23111517SCurtis.Dunham@arm.com ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); 23210037SARM gem5 Developers currState->el = currEL(_tc); 2337439Sdam.sunwoo@arm.com currState->transState = _trans; 2347439Sdam.sunwoo@arm.com currState->req = _req; 2357439Sdam.sunwoo@arm.com currState->fault = NoFault; 23610037SARM gem5 Developers currState->asid = _asid; 23710037SARM gem5 Developers currState->vmid = _vmid; 23810037SARM gem5 Developers currState->isHyp = _isHyp; 2397439Sdam.sunwoo@arm.com currState->timing = _timing; 2408733Sgeoffrey.blake@arm.com currState->functional = _functional; 2417439Sdam.sunwoo@arm.com currState->mode = _mode; 24210037SARM gem5 Developers currState->tranType = tranType; 24310037SARM gem5 Developers currState->isSecure = secure; 24410037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2457404SAli.Saidi@ARM.com 2467436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2477436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 24810037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 24910037SARM gem5 Developers if (currState->aarch64) 25010037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 25110037SARM gem5 Developers currState->tc, currState->el); 25210037SARM gem5 Developers else 25310037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 25410037SARM gem5 Developers 25510037SARM gem5 Developers if (currState->aarch64) { 25611575SDylan.Johnson@ARM.com if (isStage2) { 25711575SDylan.Johnson@ARM.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 25811575SDylan.Johnson@ARM.com currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 25911575SDylan.Johnson@ARM.com } else switch (currState->el) { 26010037SARM gem5 Developers case EL0: 26110037SARM gem5 Developers case EL1: 26210037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 26310324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 26410037SARM gem5 Developers break; 26511574SCurtis.Dunham@arm.com case EL2: 26611574SCurtis.Dunham@arm.com assert(_haveVirtualization); 26711574SCurtis.Dunham@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 26811574SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 26911574SCurtis.Dunham@arm.com break; 27010037SARM gem5 Developers case EL3: 27110037SARM gem5 Developers assert(haveSecurity); 27210037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 27310324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 27410037SARM gem5 Developers break; 27510037SARM gem5 Developers default: 27610037SARM gem5 Developers panic("Invalid exception level"); 27710037SARM gem5 Developers break; 27810037SARM gem5 Developers } 27911575SDylan.Johnson@ARM.com currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 28010037SARM gem5 Developers } else { 28110037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 28210037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 28310037SARM gem5 Developers currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 28410037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 28510037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 28610037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 28710037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 28810037SARM gem5 Developers } 2897439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 2907439Sdam.sunwoo@arm.com 2917439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 2927439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 2937439Sdam.sunwoo@arm.com 29410621SCurtis.Dunham@arm.com statRequestOrigin[REQUESTED][currState->isFetch]++; 29510621SCurtis.Dunham@arm.com 29610037SARM gem5 Developers // We only do a second stage of translation if we're not secure, or in 29710037SARM gem5 Developers // hyp mode, the second stage MMU is enabled, and this table walker 29810037SARM gem5 Developers // instance is the first stage. 29911580SDylan.Johnson@ARM.com // TODO: fix setting of doingStage2 for timing mode 30010037SARM gem5 Developers currState->doingStage2 = false; 30111580SDylan.Johnson@ARM.com currState->stage2Req = _stage2Req && !isStage2; 3027728SAli.Saidi@ARM.com 30311517SCurtis.Dunham@arm.com bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 30411517SCurtis.Dunham@arm.com longDescFormatInUse(currState->tc); 30510037SARM gem5 Developers 30610037SARM gem5 Developers if (long_desc_format) { 30710037SARM gem5 Developers // Helper variables used for hierarchical permissions 30810037SARM gem5 Developers currState->secureLookup = currState->isSecure; 30910037SARM gem5 Developers currState->rwTable = true; 31010037SARM gem5 Developers currState->userTable = true; 31110037SARM gem5 Developers currState->xnTable = false; 31210037SARM gem5 Developers currState->pxnTable = false; 31310621SCurtis.Dunham@arm.com 31410621SCurtis.Dunham@arm.com ++statWalksLongDescriptor; 31510621SCurtis.Dunham@arm.com } else { 31610621SCurtis.Dunham@arm.com ++statWalksShortDescriptor; 31710037SARM gem5 Developers } 31810037SARM gem5 Developers 31910037SARM gem5 Developers if (!currState->timing) { 32010109SGeoffrey.Blake@arm.com Fault fault = NoFault; 32110037SARM gem5 Developers if (currState->aarch64) 32210109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 32310037SARM gem5 Developers else if (long_desc_format) 32410109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 32510037SARM gem5 Developers else 32610109SGeoffrey.Blake@arm.com fault = processWalk(); 32710109SGeoffrey.Blake@arm.com 32810109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 32910109SGeoffrey.Blake@arm.com // how we found it. 33010109SGeoffrey.Blake@arm.com if (currState->functional) { 33110109SGeoffrey.Blake@arm.com delete currState; 33210109SGeoffrey.Blake@arm.com currState = savedCurrState; 33310109SGeoffrey.Blake@arm.com } 33410109SGeoffrey.Blake@arm.com return fault; 33510037SARM gem5 Developers } 3367728SAli.Saidi@ARM.com 3378067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 3387728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 3397728SAli.Saidi@ARM.com currState = NULL; 34010621SCurtis.Dunham@arm.com pendingChange(); 3417728SAli.Saidi@ARM.com } else { 3427728SAli.Saidi@ARM.com pending = true; 34310621SCurtis.Dunham@arm.com pendingChange(); 34410037SARM gem5 Developers if (currState->aarch64) 34510037SARM gem5 Developers return processWalkAArch64(); 34610037SARM gem5 Developers else if (long_desc_format) 34710037SARM gem5 Developers return processWalkLPAE(); 34810037SARM gem5 Developers else 34910037SARM gem5 Developers return processWalk(); 3507728SAli.Saidi@ARM.com } 3517728SAli.Saidi@ARM.com 3527728SAli.Saidi@ARM.com return NoFault; 3537728SAli.Saidi@ARM.com} 3547728SAli.Saidi@ARM.com 3557728SAli.Saidi@ARM.comvoid 3567728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3577728SAli.Saidi@ARM.com{ 3587728SAli.Saidi@ARM.com assert(!currState); 3597728SAli.Saidi@ARM.com assert(pendingQueue.size()); 36010621SCurtis.Dunham@arm.com pendingChange(); 3617728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3629258SAli.Saidi@ARM.com 36310037SARM gem5 Developers ExceptionLevel target_el = EL0; 36410037SARM gem5 Developers if (currState->aarch64) 36510037SARM gem5 Developers target_el = currEL(currState->tc); 36610037SARM gem5 Developers else 36710037SARM gem5 Developers target_el = EL1; 36810037SARM gem5 Developers 3699535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 37010037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 37110037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 37210037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 37310037SARM gem5 Developers target_el); 3749258SAli.Saidi@ARM.com 3759535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3769535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3779535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3789535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3799535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3809535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3819258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3829258SAli.Saidi@ARM.com pending = true; 3839258SAli.Saidi@ARM.com pendingQueue.pop_front(); 38410579SAndrew.Bardsley@arm.com // Keep currState in case one of the processWalk... calls NULLs it 38510579SAndrew.Bardsley@arm.com WalkerState *curr_state_copy = currState; 38610579SAndrew.Bardsley@arm.com Fault f; 38710037SARM gem5 Developers if (currState->aarch64) 38810579SAndrew.Bardsley@arm.com f = processWalkAArch64(); 38911517SCurtis.Dunham@arm.com else if (longDescFormatInUse(currState->tc) || 39011517SCurtis.Dunham@arm.com currState->isHyp || isStage2) 39110579SAndrew.Bardsley@arm.com f = processWalkLPAE(); 39210037SARM gem5 Developers else 39310579SAndrew.Bardsley@arm.com f = processWalk(); 39410579SAndrew.Bardsley@arm.com 39510579SAndrew.Bardsley@arm.com if (f != NoFault) { 39610579SAndrew.Bardsley@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 39710579SAndrew.Bardsley@arm.com curr_state_copy->tc, curr_state_copy->mode); 39810579SAndrew.Bardsley@arm.com 39910579SAndrew.Bardsley@arm.com delete curr_state_copy; 40010579SAndrew.Bardsley@arm.com } 4019258SAli.Saidi@ARM.com return; 4029258SAli.Saidi@ARM.com } 4039258SAli.Saidi@ARM.com 4049258SAli.Saidi@ARM.com 4059258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 4069258SAli.Saidi@ARM.com // squashed we shouldn't bother. 4079258SAli.Saidi@ARM.com unsigned num_squashed = 0; 4089258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 4099258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 4109535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 4119258SAli.Saidi@ARM.com pendingQueue.pop_front(); 4129258SAli.Saidi@ARM.com num_squashed++; 41310621SCurtis.Dunham@arm.com statSquashedBefore++; 4149258SAli.Saidi@ARM.com 41510037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 41610037SARM gem5 Developers currState->vaddr_tainted); 4179258SAli.Saidi@ARM.com 4189535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 4199535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 42010474Sandreas.hansson@arm.com currState->transState->finish( 42110474Sandreas.hansson@arm.com std::make_shared<UnimpFault>("Squashed Inst"), 42210474Sandreas.hansson@arm.com currState->req, currState->tc, currState->mode); 4239535Smrinmoy.ghosh@arm.com } else { 4249535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 42510621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 42610037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 42710037SARM gem5 Developers currState->transState, currState->mode); 42810037SARM gem5 Developers 4299535Smrinmoy.ghosh@arm.com } 4309258SAli.Saidi@ARM.com 4319258SAli.Saidi@ARM.com // delete the current request 4329258SAli.Saidi@ARM.com delete currState; 4339258SAli.Saidi@ARM.com 4349258SAli.Saidi@ARM.com // peak at the next one 4359535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 4369258SAli.Saidi@ARM.com currState = pendingQueue.front(); 43710037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 43810037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 43910037SARM gem5 Developers false, target_el); 4409535Smrinmoy.ghosh@arm.com } else { 4419535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 4429258SAli.Saidi@ARM.com currState = NULL; 4439535Smrinmoy.ghosh@arm.com } 4449258SAli.Saidi@ARM.com } 44510621SCurtis.Dunham@arm.com pendingChange(); 4469258SAli.Saidi@ARM.com 44710621SCurtis.Dunham@arm.com // if we still have pending translations, schedule more work 4489258SAli.Saidi@ARM.com nextWalk(tc); 4499258SAli.Saidi@ARM.com currState = NULL; 4507728SAli.Saidi@ARM.com} 4517728SAli.Saidi@ARM.com 4527728SAli.Saidi@ARM.comFault 4537728SAli.Saidi@ARM.comTableWalker::processWalk() 4547728SAli.Saidi@ARM.com{ 4557404SAli.Saidi@ARM.com Addr ttbr = 0; 4567404SAli.Saidi@ARM.com 4577404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 45810037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 4597404SAli.Saidi@ARM.com 46010037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 46110037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 46210037SARM gem5 Developers 32 - currState->ttbcr.n)); 4637406SAli.Saidi@ARM.com 46410621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 46510621SCurtis.Dunham@arm.com 46610037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 46710037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4687406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 46910037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 47010037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 47110037SARM gem5 Developers if (currState->isFetch) 47210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 47310474Sandreas.hansson@arm.com currState->vaddr_tainted, 47410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 47510474Sandreas.hansson@arm.com isStage2, 47610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 47710037SARM gem5 Developers else 47810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 47910474Sandreas.hansson@arm.com currState->vaddr_tainted, 48010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 48110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 48210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 48310037SARM gem5 Developers } 48410037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 48510037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4867404SAli.Saidi@ARM.com } else { 4877406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 48810037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 48910037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 49010037SARM gem5 Developers if (currState->isFetch) 49110474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 49210474Sandreas.hansson@arm.com currState->vaddr_tainted, 49310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 49410474Sandreas.hansson@arm.com isStage2, 49510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49610037SARM gem5 Developers else 49710474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 49810474Sandreas.hansson@arm.com currState->vaddr_tainted, 49910474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 50010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 50110474Sandreas.hansson@arm.com ArmFault::VmsaTran); 50210037SARM gem5 Developers } 50310037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 50410037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 50510037SARM gem5 Developers currState->ttbcr.n = 0; 5067404SAli.Saidi@ARM.com } 5077404SAli.Saidi@ARM.com 50810037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 50910037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 51010037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 51110037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 5127404SAli.Saidi@ARM.com 5137404SAli.Saidi@ARM.com // Trickbox address check 5147439Sdam.sunwoo@arm.com Fault f; 51511395Sandreas.sandberg@arm.com f = testWalk(l1desc_addr, sizeof(uint32_t), 51611395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, L1); 5177439Sdam.sunwoo@arm.com if (f) { 51810037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5197579Sminkyu.jeong@arm.com if (currState->timing) { 5207728SAli.Saidi@ARM.com pending = false; 5217728SAli.Saidi@ARM.com nextWalk(currState->tc); 5227579Sminkyu.jeong@arm.com currState = NULL; 5237579Sminkyu.jeong@arm.com } else { 5247579Sminkyu.jeong@arm.com currState->tc = NULL; 5257579Sminkyu.jeong@arm.com currState->req = NULL; 5267579Sminkyu.jeong@arm.com } 5277579Sminkyu.jeong@arm.com return f; 5287404SAli.Saidi@ARM.com } 5297404SAli.Saidi@ARM.com 53010836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 5317946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 53210836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 5337946SGiacomo.Gabrielli@arm.com } 5347946SGiacomo.Gabrielli@arm.com 53511181Snathananel.premillieu@arm.com if (currState->isSecure) { 53611181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 53711181Snathananel.premillieu@arm.com } 53811181Snathananel.premillieu@arm.com 53910037SARM gem5 Developers bool delayed; 54010037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 54110037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 54210037SARM gem5 Developers &TableWalker::doL1Descriptor); 54310037SARM gem5 Developers if (!delayed) { 54410037SARM gem5 Developers f = currState->fault; 54510037SARM gem5 Developers } 54610037SARM gem5 Developers 54710037SARM gem5 Developers return f; 54810037SARM gem5 Developers} 54910037SARM gem5 Developers 55010037SARM gem5 DevelopersFault 55110037SARM gem5 DevelopersTableWalker::processWalkLPAE() 55210037SARM gem5 Developers{ 55310037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 55410037SARM gem5 Developers int tsz, n; 55510037SARM gem5 Developers LookupLevel start_lookup_level = L1; 55610037SARM gem5 Developers 55710037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 55810037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 55910037SARM gem5 Developers 56010621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 56110621SCurtis.Dunham@arm.com 56210836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 56310037SARM gem5 Developers if (currState->isSecure) 56410037SARM gem5 Developers flag.set(Request::SECURE); 56510037SARM gem5 Developers 56610037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 56710037SARM gem5 Developers // use HTTBR 56810037SARM gem5 Developers if (isStage2) { 56910037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 57010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 57110037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 57210037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 57310037SARM gem5 Developers } else if (currState->isHyp) { 57410037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 57510037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 57610037SARM gem5 Developers tsz = currState->htcr.t0sz; 57710037SARM gem5 Developers } else { 57811517SCurtis.Dunham@arm.com assert(longDescFormatInUse(currState->tc)); 57910037SARM gem5 Developers 58010037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 58110037SARM gem5 Developers if (currState->ttbcr.t0sz) 58210037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 58310037SARM gem5 Developers else if (currState->ttbcr.t1sz) 58410037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 58510037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 58610037SARM gem5 Developers else 58710037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 58810037SARM gem5 Developers if (currState->ttbcr.t1sz) 58910037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 59010037SARM gem5 Developers else 59110037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 59210037SARM gem5 Developers 59310037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 59410037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 59510037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 59610037SARM gem5 Developers // ARM issue C B3.6.4) 59710037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 59810037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 59910037SARM gem5 Developers // Check if table walk is allowed 60010037SARM gem5 Developers if (currState->ttbcr.epd0) { 60110037SARM gem5 Developers if (currState->isFetch) 60210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 60310474Sandreas.hansson@arm.com currState->vaddr_tainted, 60410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60510474Sandreas.hansson@arm.com isStage2, 60610474Sandreas.hansson@arm.com ArmFault::LpaeTran); 60710037SARM gem5 Developers else 60810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 60910474Sandreas.hansson@arm.com currState->vaddr_tainted, 61010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 61110474Sandreas.hansson@arm.com currState->isWrite, 61210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 61310474Sandreas.hansson@arm.com isStage2, 61410474Sandreas.hansson@arm.com ArmFault::LpaeTran); 61510037SARM gem5 Developers } 61610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 61710037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 61810037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 61910037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 62010037SARM gem5 Developers start_lookup_level = L2; 62110037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 62210037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 62310037SARM gem5 Developers // Check if table walk is allowed 62410037SARM gem5 Developers if (currState->ttbcr.epd1) { 62510037SARM gem5 Developers if (currState->isFetch) 62610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 62710474Sandreas.hansson@arm.com currState->vaddr_tainted, 62810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 62910474Sandreas.hansson@arm.com isStage2, 63010474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63110037SARM gem5 Developers else 63210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 63310474Sandreas.hansson@arm.com currState->vaddr_tainted, 63410474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 63510474Sandreas.hansson@arm.com currState->isWrite, 63610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63710474Sandreas.hansson@arm.com isStage2, 63810474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63910037SARM gem5 Developers } 64010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 64110037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 64210037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 64310037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 64410037SARM gem5 Developers start_lookup_level = L2; 64510037SARM gem5 Developers } else { 64610037SARM gem5 Developers // Out of boundaries -> translation fault 64710037SARM gem5 Developers if (currState->isFetch) 64810474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64910474Sandreas.hansson@arm.com currState->vaddr_tainted, 65010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 65110474Sandreas.hansson@arm.com isStage2, 65210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 65310037SARM gem5 Developers else 65410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65510474Sandreas.hansson@arm.com currState->vaddr_tainted, 65610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 65710474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 65810474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 65910037SARM gem5 Developers } 66010037SARM gem5 Developers 66110037SARM gem5 Developers } 66210037SARM gem5 Developers 66310037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 66410037SARM gem5 Developers if (start_lookup_level == L1) { 66510037SARM gem5 Developers n = 5 - tsz; 66610037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 66710037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 66810037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 66910037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67010037SARM gem5 Developers } else { 67110037SARM gem5 Developers // Skip first-level lookup 67210037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 67310037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 67410037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 67510037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67610037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67710037SARM gem5 Developers } 67810037SARM gem5 Developers 67910037SARM gem5 Developers // Trickbox address check 68011395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 68111395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 68210037SARM gem5 Developers if (f) { 68310037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 68410037SARM gem5 Developers if (currState->timing) { 68510037SARM gem5 Developers pending = false; 68610037SARM gem5 Developers nextWalk(currState->tc); 68710037SARM gem5 Developers currState = NULL; 68810037SARM gem5 Developers } else { 68910037SARM gem5 Developers currState->tc = NULL; 69010037SARM gem5 Developers currState->req = NULL; 69110037SARM gem5 Developers } 69210037SARM gem5 Developers return f; 69310037SARM gem5 Developers } 69410037SARM gem5 Developers 69510037SARM gem5 Developers if (currState->sctlr.c == 0) { 69610836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 69710037SARM gem5 Developers } 69810037SARM gem5 Developers 69910037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 70010037SARM gem5 Developers currState->longDesc.aarch64 = false; 70110324SCurtis.Dunham@arm.com currState->longDesc.grainSize = Grain4KB; 70210037SARM gem5 Developers 70310037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70410037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 70511588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], 70611588SCurtis.Dunham@arm.com &TableWalker::doLongDescriptor); 70710037SARM gem5 Developers if (!delayed) { 70810037SARM gem5 Developers f = currState->fault; 70910037SARM gem5 Developers } 71010037SARM gem5 Developers 71110037SARM gem5 Developers return f; 71210037SARM gem5 Developers} 71310037SARM gem5 Developers 71410037SARM gem5 Developersunsigned 71510037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 71610037SARM gem5 Developers{ 71710037SARM gem5 Developers if (tsz < 25) 71810037SARM gem5 Developers return 25; 71910037SARM gem5 Developers if (tsz > 48) 72010037SARM gem5 Developers return 48; 72110037SARM gem5 Developers return tsz; 72210037SARM gem5 Developers} 72310037SARM gem5 Developers 72410037SARM gem5 Developersbool 72510037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 72610037SARM gem5 Developers{ 72710037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 72810037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 72910037SARM gem5 Developers} 73010037SARM gem5 Developers 73110037SARM gem5 DevelopersFault 73210037SARM gem5 DevelopersTableWalker::processWalkAArch64() 73310037SARM gem5 Developers{ 73410037SARM gem5 Developers assert(currState->aarch64); 73510037SARM gem5 Developers 73610324SCurtis.Dunham@arm.com DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 73710324SCurtis.Dunham@arm.com currState->vaddr_tainted, currState->tcr); 73810324SCurtis.Dunham@arm.com 73910324SCurtis.Dunham@arm.com static const GrainSize GrainMapDefault[] = 74010324SCurtis.Dunham@arm.com { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 74110324SCurtis.Dunham@arm.com static const GrainSize GrainMap_EL1_tg1[] = 74210324SCurtis.Dunham@arm.com { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 74310037SARM gem5 Developers 74410621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 74510621SCurtis.Dunham@arm.com 74610037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 74710037SARM gem5 Developers Addr ttbr = 0; 74810037SARM gem5 Developers int tsz = 0, ps = 0; 74910324SCurtis.Dunham@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 75010037SARM gem5 Developers bool fault = false; 75111575SDylan.Johnson@ARM.com 75211575SDylan.Johnson@ARM.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 75311575SDylan.Johnson@ARM.com 75410037SARM gem5 Developers switch (currState->el) { 75510037SARM gem5 Developers case EL0: 75610037SARM gem5 Developers case EL1: 75711575SDylan.Johnson@ARM.com if (isStage2) { 75811575SDylan.Johnson@ARM.com DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 75911575SDylan.Johnson@ARM.com ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 76011575SDylan.Johnson@ARM.com tsz = 64 - currState->vtcr.t0sz64; 76111575SDylan.Johnson@ARM.com tg = GrainMapDefault[currState->vtcr.tg0]; 76211575SDylan.Johnson@ARM.com // ARM DDI 0487A.f D7-2148 76311575SDylan.Johnson@ARM.com // The starting level of stage 2 translation depends on 76411575SDylan.Johnson@ARM.com // VTCR_EL2.SL0 and VTCR_EL2.TG0 76511575SDylan.Johnson@ARM.com LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 76611575SDylan.Johnson@ARM.com uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 76711575SDylan.Johnson@ARM.com static const LookupLevel SLL[] = { 76811575SDylan.Johnson@ARM.com L2, L3, L3, __, // sl0 == 0 76911575SDylan.Johnson@ARM.com L1, L2, L2, __, // sl0 == 1, etc. 77011575SDylan.Johnson@ARM.com L0, L1, L1, __, 77111575SDylan.Johnson@ARM.com __, __, __, __ 77211575SDylan.Johnson@ARM.com }; 77311575SDylan.Johnson@ARM.com start_lookup_level = SLL[sl_tg]; 77411575SDylan.Johnson@ARM.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 77511575SDylan.Johnson@ARM.com "Cannot discern lookup level from vtcr.{sl0,tg0}"); 77611575SDylan.Johnson@ARM.com } else switch (bits(currState->vaddr, 63,48)) { 77710037SARM gem5 Developers case 0: 77810037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 77910037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 78010324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 78110324SCurtis.Dunham@arm.com tg = GrainMapDefault[currState->tcr.tg0]; 78210037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != 0x0 || 78310324SCurtis.Dunham@arm.com currState->tcr.epd0) 78410037SARM gem5 Developers fault = true; 78510037SARM gem5 Developers break; 78610037SARM gem5 Developers case 0xffff: 78710037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 78810037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 78910324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 79010324SCurtis.Dunham@arm.com tg = GrainMap_EL1_tg1[currState->tcr.tg1]; 79110037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 79210324SCurtis.Dunham@arm.com currState->tcr.epd1) 79310037SARM gem5 Developers fault = true; 79410037SARM gem5 Developers break; 79510037SARM gem5 Developers default: 79610037SARM gem5 Developers // top two bytes must be all 0s or all 1s, else invalid addr 79710037SARM gem5 Developers fault = true; 79810037SARM gem5 Developers } 79910324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 80010037SARM gem5 Developers break; 80110037SARM gem5 Developers case EL2: 80210037SARM gem5 Developers case EL3: 80310037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 80410037SARM gem5 Developers case 0: 80510324SCurtis.Dunham@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 80610324SCurtis.Dunham@arm.com if (currState->el == EL2) 80710324SCurtis.Dunham@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 80810324SCurtis.Dunham@arm.com else 80910324SCurtis.Dunham@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 81010324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 81110324SCurtis.Dunham@arm.com tg = GrainMapDefault[currState->tcr.tg0]; 81210037SARM gem5 Developers break; 81310037SARM gem5 Developers default: 81410037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 81510324SCurtis.Dunham@arm.com fault = true; 81610037SARM gem5 Developers } 81710324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 81810037SARM gem5 Developers break; 81910037SARM gem5 Developers } 82010037SARM gem5 Developers 82110037SARM gem5 Developers if (fault) { 82210037SARM gem5 Developers Fault f; 82310037SARM gem5 Developers if (currState->isFetch) 82410474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 82510474Sandreas.hansson@arm.com currState->vaddr_tainted, 82610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 82710474Sandreas.hansson@arm.com ArmFault::LpaeTran); 82810037SARM gem5 Developers else 82910474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 83010474Sandreas.hansson@arm.com currState->vaddr_tainted, 83110474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 83210474Sandreas.hansson@arm.com currState->isWrite, 83310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, 83410474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 83510037SARM gem5 Developers 83610037SARM gem5 Developers if (currState->timing) { 83710037SARM gem5 Developers pending = false; 83810037SARM gem5 Developers nextWalk(currState->tc); 83910037SARM gem5 Developers currState = NULL; 84010037SARM gem5 Developers } else { 84110037SARM gem5 Developers currState->tc = NULL; 84210037SARM gem5 Developers currState->req = NULL; 84310037SARM gem5 Developers } 84410037SARM gem5 Developers return f; 84510037SARM gem5 Developers 84610037SARM gem5 Developers } 84710037SARM gem5 Developers 84810324SCurtis.Dunham@arm.com if (tg == ReservedGrain) { 84910324SCurtis.Dunham@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 85010324SCurtis.Dunham@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 85110324SCurtis.Dunham@arm.com tg = Grain4KB; 85210324SCurtis.Dunham@arm.com } 85310324SCurtis.Dunham@arm.com 85410037SARM gem5 Developers // Determine starting lookup level 85510324SCurtis.Dunham@arm.com // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 85610324SCurtis.Dunham@arm.com // in ARM DDI 0487A. These table values correspond to the cascading tests 85710324SCurtis.Dunham@arm.com // to compute the lookup level and are of the form 85810324SCurtis.Dunham@arm.com // (grain_size + N*stride), for N = {1, 2, 3}. 85910324SCurtis.Dunham@arm.com // A value of 64 will never succeed and a value of 0 will always succeed. 86011575SDylan.Johnson@ARM.com if (start_lookup_level == MAX_LOOKUP_LEVELS) { 86110324SCurtis.Dunham@arm.com struct GrainMap { 86210324SCurtis.Dunham@arm.com GrainSize grain_size; 86310324SCurtis.Dunham@arm.com unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 86410324SCurtis.Dunham@arm.com }; 86510324SCurtis.Dunham@arm.com static const GrainMap GM[] = { 86610324SCurtis.Dunham@arm.com { Grain4KB, { 39, 30, 0, 0 } }, 86710324SCurtis.Dunham@arm.com { Grain16KB, { 47, 36, 25, 0 } }, 86810324SCurtis.Dunham@arm.com { Grain64KB, { 64, 42, 29, 0 } } 86910324SCurtis.Dunham@arm.com }; 87010324SCurtis.Dunham@arm.com 87110324SCurtis.Dunham@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 87210324SCurtis.Dunham@arm.com 87310324SCurtis.Dunham@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 87410324SCurtis.Dunham@arm.com if (tg == GM[i].grain_size) { 87510324SCurtis.Dunham@arm.com lookup = GM[i].lookup_level_cutoff; 87610324SCurtis.Dunham@arm.com break; 87710324SCurtis.Dunham@arm.com } 87810324SCurtis.Dunham@arm.com } 87910324SCurtis.Dunham@arm.com assert(lookup); 88010324SCurtis.Dunham@arm.com 88110324SCurtis.Dunham@arm.com for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 88210324SCurtis.Dunham@arm.com if (tsz > lookup[L]) { 88310324SCurtis.Dunham@arm.com start_lookup_level = (LookupLevel) L; 88410324SCurtis.Dunham@arm.com break; 88510324SCurtis.Dunham@arm.com } 88610324SCurtis.Dunham@arm.com } 88710324SCurtis.Dunham@arm.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 88810324SCurtis.Dunham@arm.com "Table walker couldn't find lookup level\n"); 88910037SARM gem5 Developers } 89010037SARM gem5 Developers 89111575SDylan.Johnson@ARM.com int stride = tg - 3; 89211575SDylan.Johnson@ARM.com 89310037SARM gem5 Developers // Determine table base address 89410324SCurtis.Dunham@arm.com int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 89510037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 89610037SARM gem5 Developers 89710037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 89810037SARM gem5 Developers // necessary 89910037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 90010037SARM gem5 Developers // Clamp to lower limit 90110037SARM gem5 Developers if (pa_range > physAddrRange) 90210037SARM gem5 Developers currState->physAddrRange = physAddrRange; 90310037SARM gem5 Developers else 90410037SARM gem5 Developers currState->physAddrRange = pa_range; 90510037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 90610037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 90710037SARM gem5 Developers Fault f; 90810037SARM gem5 Developers if (currState->isFetch) 90910474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 91010474Sandreas.hansson@arm.com currState->vaddr_tainted, 91110474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 91210474Sandreas.hansson@arm.com isStage2, 91310474Sandreas.hansson@arm.com ArmFault::LpaeTran); 91410037SARM gem5 Developers else 91510474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 91610474Sandreas.hansson@arm.com currState->vaddr_tainted, 91710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 91810474Sandreas.hansson@arm.com currState->isWrite, 91910474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 92010474Sandreas.hansson@arm.com isStage2, 92110474Sandreas.hansson@arm.com ArmFault::LpaeTran); 92210037SARM gem5 Developers 92310037SARM gem5 Developers 92410037SARM gem5 Developers if (currState->timing) { 92510037SARM gem5 Developers pending = false; 92610037SARM gem5 Developers nextWalk(currState->tc); 92710037SARM gem5 Developers currState = NULL; 92810037SARM gem5 Developers } else { 92910037SARM gem5 Developers currState->tc = NULL; 93010037SARM gem5 Developers currState->req = NULL; 93110037SARM gem5 Developers } 93210037SARM gem5 Developers return f; 93310037SARM gem5 Developers 93410037SARM gem5 Developers } 93510037SARM gem5 Developers 93610037SARM gem5 Developers // Determine descriptor address 93710037SARM gem5 Developers Addr desc_addr = base_addr | 93810037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 93910324SCurtis.Dunham@arm.com stride * (3 - start_lookup_level) + tg) << 3); 94010037SARM gem5 Developers 94110037SARM gem5 Developers // Trickbox address check 94211395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 94311395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 94410037SARM gem5 Developers if (f) { 94510037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 94610037SARM gem5 Developers if (currState->timing) { 94710037SARM gem5 Developers pending = false; 94810037SARM gem5 Developers nextWalk(currState->tc); 94910037SARM gem5 Developers currState = NULL; 95010037SARM gem5 Developers } else { 95110037SARM gem5 Developers currState->tc = NULL; 95210037SARM gem5 Developers currState->req = NULL; 95310037SARM gem5 Developers } 95410037SARM gem5 Developers return f; 95510037SARM gem5 Developers } 95610037SARM gem5 Developers 95710836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 95810037SARM gem5 Developers if (currState->sctlr.c == 0) { 95910836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 96010037SARM gem5 Developers } 96110037SARM gem5 Developers 96211181Snathananel.premillieu@arm.com if (currState->isSecure) { 96311181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 96411181Snathananel.premillieu@arm.com } 96511181Snathananel.premillieu@arm.com 96610037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 96710037SARM gem5 Developers currState->longDesc.aarch64 = true; 96810324SCurtis.Dunham@arm.com currState->longDesc.grainSize = tg; 96910037SARM gem5 Developers 9707439Sdam.sunwoo@arm.com if (currState->timing) { 97111588SCurtis.Dunham@arm.com fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data, 97211588SCurtis.Dunham@arm.com sizeof(uint64_t), flag, start_lookup_level, 97311588SCurtis.Dunham@arm.com LongDescEventByLevel[start_lookup_level], NULL); 97411579SDylan.Johnson@ARM.com } else { 97511575SDylan.Johnson@ARM.com fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 97611575SDylan.Johnson@ARM.com sizeof(uint64_t), flag, -1, NULL, 97711575SDylan.Johnson@ARM.com &TableWalker::doLongDescriptor); 9787439Sdam.sunwoo@arm.com f = currState->fault; 9797404SAli.Saidi@ARM.com } 9807404SAli.Saidi@ARM.com 9817439Sdam.sunwoo@arm.com return f; 9827404SAli.Saidi@ARM.com} 9837404SAli.Saidi@ARM.com 9847404SAli.Saidi@ARM.comvoid 9857439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 9867439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 9877404SAli.Saidi@ARM.com{ 9887439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 9897439Sdam.sunwoo@arm.com // variables 9907436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 9917436Sdam.sunwoo@arm.com te.shareable = false; // default value 9927582SAli.Saidi@arm.com te.nonCacheable = false; 99310037SARM gem5 Developers te.outerShareable = false; 9947439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 9957404SAli.Saidi@ARM.com switch(texcb) { 9967436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 9977404SAli.Saidi@ARM.com te.nonCacheable = true; 99810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 9997436Sdam.sunwoo@arm.com te.shareable = true; 10007436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10017436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10027404SAli.Saidi@ARM.com break; 10037436Sdam.sunwoo@arm.com case 1: // Shareable Device 10047436Sdam.sunwoo@arm.com te.nonCacheable = true; 100510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10067436Sdam.sunwoo@arm.com te.shareable = true; 10077436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10087436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10097436Sdam.sunwoo@arm.com break; 10107436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 101110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10127436Sdam.sunwoo@arm.com te.shareable = s; 10137436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10147436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10157436Sdam.sunwoo@arm.com break; 10167436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 101710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10187436Sdam.sunwoo@arm.com te.shareable = s; 10197436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10207436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10217436Sdam.sunwoo@arm.com break; 10227436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 10237436Sdam.sunwoo@arm.com te.nonCacheable = true; 102410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10257436Sdam.sunwoo@arm.com te.shareable = s; 10267436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10277436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10287436Sdam.sunwoo@arm.com break; 10297436Sdam.sunwoo@arm.com case 5: // Reserved 10307439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10317436Sdam.sunwoo@arm.com break; 10327436Sdam.sunwoo@arm.com case 6: // Implementation Defined 10337439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 10347436Sdam.sunwoo@arm.com break; 10357436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 103610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10377436Sdam.sunwoo@arm.com te.shareable = s; 10387436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10397436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10407436Sdam.sunwoo@arm.com break; 10417436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 10427436Sdam.sunwoo@arm.com te.nonCacheable = true; 104310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10447436Sdam.sunwoo@arm.com te.shareable = false; 10457436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10467436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10477436Sdam.sunwoo@arm.com break; 10487436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 10497439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10507436Sdam.sunwoo@arm.com break; 10517436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 105210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10537436Sdam.sunwoo@arm.com te.shareable = s; 10547404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 10557404SAli.Saidi@ARM.com te.nonCacheable = true; 10567436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 10577436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 10587404SAli.Saidi@ARM.com break; 10597436Sdam.sunwoo@arm.com default: 10607436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 10617404SAli.Saidi@ARM.com } 10627404SAli.Saidi@ARM.com } else { 10637438SAli.Saidi@ARM.com assert(tc); 106410037SARM gem5 Developers PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 106510037SARM gem5 Developers currState->tc, !currState->isSecure)); 106610037SARM gem5 Developers NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 106710037SARM gem5 Developers currState->tc, !currState->isSecure)); 10687436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 10697582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 10707404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 10717404SAli.Saidi@ARM.com case 0: 10727436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 10737436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 10747436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 107510037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 10767404SAli.Saidi@ARM.com break; 10777404SAli.Saidi@ARM.com case 1: 10787436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 10797436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 10807436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 108110037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 10827404SAli.Saidi@ARM.com break; 10837404SAli.Saidi@ARM.com case 2: 10847436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 10857436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 10867436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 108710037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 10887404SAli.Saidi@ARM.com break; 10897404SAli.Saidi@ARM.com case 3: 10907436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 10917436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 10927436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 109310037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 10947404SAli.Saidi@ARM.com break; 10957404SAli.Saidi@ARM.com case 4: 10967436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 10977436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 10987436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 109910037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 11007404SAli.Saidi@ARM.com break; 11017404SAli.Saidi@ARM.com case 5: 11027436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 11037436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 11047436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 110510037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 11067404SAli.Saidi@ARM.com break; 11077404SAli.Saidi@ARM.com case 6: 11087404SAli.Saidi@ARM.com panic("Imp defined type\n"); 11097404SAli.Saidi@ARM.com case 7: 11107436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 11117436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 11127436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 111310037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 11147404SAli.Saidi@ARM.com break; 11157404SAli.Saidi@ARM.com } 11167436Sdam.sunwoo@arm.com 11177436Sdam.sunwoo@arm.com switch(curr_tr) { 11187436Sdam.sunwoo@arm.com case 0: 11197436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 112010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 11217436Sdam.sunwoo@arm.com te.nonCacheable = true; 11227436Sdam.sunwoo@arm.com te.innerAttrs = 1; 11237436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11247436Sdam.sunwoo@arm.com te.shareable = true; 11257436Sdam.sunwoo@arm.com break; 11267436Sdam.sunwoo@arm.com case 1: 11277436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 11287436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 112910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 11307436Sdam.sunwoo@arm.com te.nonCacheable = true; 11317436Sdam.sunwoo@arm.com te.innerAttrs = 3; 11327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11337436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 11347436Sdam.sunwoo@arm.com te.shareable = true; 11357436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 11367436Sdam.sunwoo@arm.com te.shareable = true; 11377436Sdam.sunwoo@arm.com break; 11387436Sdam.sunwoo@arm.com case 2: 11397436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 11407436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 114110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 11427436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 11437436Sdam.sunwoo@arm.com te.shareable = true; 11447436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 11457436Sdam.sunwoo@arm.com te.shareable = true; 11467436Sdam.sunwoo@arm.com break; 11477436Sdam.sunwoo@arm.com case 3: 11487436Sdam.sunwoo@arm.com panic("Reserved type"); 11497436Sdam.sunwoo@arm.com } 11507436Sdam.sunwoo@arm.com 115110037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 11527436Sdam.sunwoo@arm.com switch(curr_ir) { 11537436Sdam.sunwoo@arm.com case 0: 11547436Sdam.sunwoo@arm.com te.nonCacheable = true; 11557436Sdam.sunwoo@arm.com te.innerAttrs = 0; 11567436Sdam.sunwoo@arm.com break; 11577436Sdam.sunwoo@arm.com case 1: 11587436Sdam.sunwoo@arm.com te.innerAttrs = 5; 11597436Sdam.sunwoo@arm.com break; 11607436Sdam.sunwoo@arm.com case 2: 11617436Sdam.sunwoo@arm.com te.innerAttrs = 6; 11627436Sdam.sunwoo@arm.com break; 11637436Sdam.sunwoo@arm.com case 3: 11647436Sdam.sunwoo@arm.com te.innerAttrs = 7; 11657436Sdam.sunwoo@arm.com break; 11667436Sdam.sunwoo@arm.com } 11677436Sdam.sunwoo@arm.com 11687436Sdam.sunwoo@arm.com switch(curr_or) { 11697436Sdam.sunwoo@arm.com case 0: 11707436Sdam.sunwoo@arm.com te.nonCacheable = true; 11717436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11727436Sdam.sunwoo@arm.com break; 11737436Sdam.sunwoo@arm.com case 1: 11747436Sdam.sunwoo@arm.com te.outerAttrs = 1; 11757436Sdam.sunwoo@arm.com break; 11767436Sdam.sunwoo@arm.com case 2: 11777436Sdam.sunwoo@arm.com te.outerAttrs = 2; 11787436Sdam.sunwoo@arm.com break; 11797436Sdam.sunwoo@arm.com case 3: 11807436Sdam.sunwoo@arm.com te.outerAttrs = 3; 11817436Sdam.sunwoo@arm.com break; 11827436Sdam.sunwoo@arm.com } 11837436Sdam.sunwoo@arm.com } 11847404SAli.Saidi@ARM.com } 118510367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 118610367SAndrew.Bardsley@arm.com "outerAttrs: %d\n", 11877439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 118810037SARM gem5 Developers te.setAttributes(false); 118910037SARM gem5 Developers} 11907436Sdam.sunwoo@arm.com 119110037SARM gem5 Developersvoid 119210037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 119310037SARM gem5 Developers LongDescriptor &lDescriptor) 119410037SARM gem5 Developers{ 119510037SARM gem5 Developers assert(_haveLPAE); 11967436Sdam.sunwoo@arm.com 119710037SARM gem5 Developers uint8_t attr; 119810037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 119910037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 120010037SARM gem5 Developers // translation 120110037SARM gem5 Developers if (isStage2) { 120210037SARM gem5 Developers attr = lDescriptor.memAttr(); 120310037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 120410037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 12057436Sdam.sunwoo@arm.com 120610037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 120710037SARM gem5 Developers 120810037SARM gem5 Developers if (attr_3_2 == 0) { 120910037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 121010037SARM gem5 Developers : TlbEntry::MemoryType::Device; 121110037SARM gem5 Developers te.outerAttrs = 0; 121210037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 121310037SARM gem5 Developers te.nonCacheable = true; 121410037SARM gem5 Developers } else { 121510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 121610037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 121710037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 121810037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 121910037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 122010037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 122110037SARM gem5 Developers } 122210037SARM gem5 Developers } else { 122310037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 122410037SARM gem5 Developers 122510037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 122610037SARM gem5 Developers // value of SCTLR.TRE 122710421Sandreas.hansson@arm.com MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 122810421Sandreas.hansson@arm.com int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, 122910421Sandreas.hansson@arm.com !currState->isSecure); 123010421Sandreas.hansson@arm.com uint32_t mair = currState->tc->readMiscReg(reg_as_int); 123110037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 123210037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 123310037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 123410037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 123510037SARM gem5 Developers 123610037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 123710037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 123810037SARM gem5 Developers // accordingly to provide the illusion of full support 123910037SARM gem5 Developers te.nonCacheable = false; 124010037SARM gem5 Developers 124110037SARM gem5 Developers switch (attr_7_4) { 124210037SARM gem5 Developers case 0x0: 124310037SARM gem5 Developers // Strongly-ordered or Device memory 124410037SARM gem5 Developers if (attr_3_0 == 0x0) 124510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 124610037SARM gem5 Developers else if (attr_3_0 == 0x4) 124710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 124810037SARM gem5 Developers else 124910037SARM gem5 Developers panic("Unpredictable behavior\n"); 125010037SARM gem5 Developers te.nonCacheable = true; 125110037SARM gem5 Developers te.outerAttrs = 0; 125210037SARM gem5 Developers break; 125310037SARM gem5 Developers case 0x4: 125410037SARM gem5 Developers // Normal memory, Outer Non-cacheable 125510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 125610037SARM gem5 Developers te.outerAttrs = 0; 125710037SARM gem5 Developers if (attr_3_0 == 0x4) 125810037SARM gem5 Developers // Inner Non-cacheable 125910037SARM gem5 Developers te.nonCacheable = true; 126010037SARM gem5 Developers else if (attr_3_0 < 0x8) 126110037SARM gem5 Developers panic("Unpredictable behavior\n"); 126210037SARM gem5 Developers break; 126310037SARM gem5 Developers case 0x8: 126410037SARM gem5 Developers case 0x9: 126510037SARM gem5 Developers case 0xa: 126610037SARM gem5 Developers case 0xb: 126710037SARM gem5 Developers case 0xc: 126810037SARM gem5 Developers case 0xd: 126910037SARM gem5 Developers case 0xe: 127010037SARM gem5 Developers case 0xf: 127110037SARM gem5 Developers if (attr_7_4 & 0x4) { 127210037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 127310037SARM gem5 Developers } else { 127410037SARM gem5 Developers te.outerAttrs = 0x2; 127510037SARM gem5 Developers } 127610037SARM gem5 Developers // Normal memory, Outer Cacheable 127710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 127810037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 127910037SARM gem5 Developers panic("Unpredictable behavior\n"); 128010037SARM gem5 Developers break; 128110037SARM gem5 Developers default: 128210037SARM gem5 Developers panic("Unpredictable behavior\n"); 128310037SARM gem5 Developers break; 128410037SARM gem5 Developers } 128510037SARM gem5 Developers 128610037SARM gem5 Developers switch (attr_3_0) { 128710037SARM gem5 Developers case 0x0: 128810037SARM gem5 Developers te.innerAttrs = 0x1; 128910037SARM gem5 Developers break; 129010037SARM gem5 Developers case 0x4: 129110037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 129210037SARM gem5 Developers break; 129310037SARM gem5 Developers case 0x8: 129410037SARM gem5 Developers case 0x9: 129510037SARM gem5 Developers case 0xA: 129610037SARM gem5 Developers case 0xB: 129710037SARM gem5 Developers te.innerAttrs = 6; 129810037SARM gem5 Developers break; 129910037SARM gem5 Developers case 0xC: 130010037SARM gem5 Developers case 0xD: 130110037SARM gem5 Developers case 0xE: 130210037SARM gem5 Developers case 0xF: 130310037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 130410037SARM gem5 Developers break; 130510037SARM gem5 Developers default: 130610037SARM gem5 Developers panic("Unpredictable behavior\n"); 130710037SARM gem5 Developers break; 130810037SARM gem5 Developers } 130910037SARM gem5 Developers } 131010037SARM gem5 Developers 131110037SARM gem5 Developers te.outerShareable = sh == 2; 131210037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 131310037SARM gem5 Developers te.setAttributes(true); 131410037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 131510037SARM gem5 Developers} 131610037SARM gem5 Developers 131710037SARM gem5 Developersvoid 131811583SDylan.Johnson@ARM.comTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, 131911583SDylan.Johnson@ARM.com LongDescriptor &lDescriptor) 132010037SARM gem5 Developers{ 132111583SDylan.Johnson@ARM.com uint8_t attr; 132211583SDylan.Johnson@ARM.com uint8_t attr_hi; 132311583SDylan.Johnson@ARM.com uint8_t attr_lo; 132411583SDylan.Johnson@ARM.com uint8_t sh = lDescriptor.sh(); 132510037SARM gem5 Developers 132611583SDylan.Johnson@ARM.com if (isStage2) { 132711583SDylan.Johnson@ARM.com attr = lDescriptor.memAttr(); 132811583SDylan.Johnson@ARM.com uint8_t attr_hi = (attr >> 2) & 0x3; 132911583SDylan.Johnson@ARM.com uint8_t attr_lo = attr & 0x3; 133011583SDylan.Johnson@ARM.com 133111583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh); 133211583SDylan.Johnson@ARM.com 133311583SDylan.Johnson@ARM.com if (attr_hi == 0) { 133411583SDylan.Johnson@ARM.com te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered 133511583SDylan.Johnson@ARM.com : TlbEntry::MemoryType::Device; 133611583SDylan.Johnson@ARM.com te.outerAttrs = 0; 133711583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 0 ? 1 : 3; 133811583SDylan.Johnson@ARM.com te.nonCacheable = true; 133911583SDylan.Johnson@ARM.com } else { 134011583SDylan.Johnson@ARM.com te.mtype = TlbEntry::MemoryType::Normal; 134111583SDylan.Johnson@ARM.com te.outerAttrs = attr_hi == 1 ? 0 : 134211583SDylan.Johnson@ARM.com attr_hi == 2 ? 2 : 1; 134311583SDylan.Johnson@ARM.com te.innerAttrs = attr_lo == 1 ? 0 : 134411583SDylan.Johnson@ARM.com attr_lo == 2 ? 6 : 5; 134511938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 134611938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 134711938Snikos.nikoleris@arm.com te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) || 134811938Snikos.nikoleris@arm.com (attr_lo == 1) || (attr_lo == 2); 134911583SDylan.Johnson@ARM.com } 135011583SDylan.Johnson@ARM.com } else { 135111583SDylan.Johnson@ARM.com uint8_t attrIndx = lDescriptor.attrIndx(); 135211583SDylan.Johnson@ARM.com 135311583SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 135411583SDylan.Johnson@ARM.com 135511583SDylan.Johnson@ARM.com // Select MAIR 135611583SDylan.Johnson@ARM.com uint64_t mair; 135711583SDylan.Johnson@ARM.com switch (currState->el) { 135811583SDylan.Johnson@ARM.com case EL0: 135911583SDylan.Johnson@ARM.com case EL1: 136011583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL1); 136111583SDylan.Johnson@ARM.com break; 136211583SDylan.Johnson@ARM.com case EL2: 136311583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL2); 136411583SDylan.Johnson@ARM.com break; 136511583SDylan.Johnson@ARM.com case EL3: 136611583SDylan.Johnson@ARM.com mair = tc->readMiscReg(MISCREG_MAIR_EL3); 136711583SDylan.Johnson@ARM.com break; 136811583SDylan.Johnson@ARM.com default: 136911583SDylan.Johnson@ARM.com panic("Invalid exception level"); 137011583SDylan.Johnson@ARM.com break; 137111583SDylan.Johnson@ARM.com } 137211583SDylan.Johnson@ARM.com 137311583SDylan.Johnson@ARM.com // Select attributes 137411583SDylan.Johnson@ARM.com attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 137511583SDylan.Johnson@ARM.com attr_lo = bits(attr, 3, 0); 137611583SDylan.Johnson@ARM.com attr_hi = bits(attr, 7, 4); 137711583SDylan.Johnson@ARM.com 137811583SDylan.Johnson@ARM.com // Memory type 137911583SDylan.Johnson@ARM.com te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 138011583SDylan.Johnson@ARM.com 138111583SDylan.Johnson@ARM.com // Cacheability 138211583SDylan.Johnson@ARM.com te.nonCacheable = false; 138311938Snikos.nikoleris@arm.com if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory 138411938Snikos.nikoleris@arm.com te.nonCacheable = true; 138511938Snikos.nikoleris@arm.com } 138611938Snikos.nikoleris@arm.com // Treat write-through memory as uncacheable, this is safe 138711938Snikos.nikoleris@arm.com // but for performance reasons not optimal. 138811938Snikos.nikoleris@arm.com switch (attr_hi) { 138911938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 139011938Snikos.nikoleris@arm.com case 0x4: // Normal memory, Outer Non-cacheable 139111938Snikos.nikoleris@arm.com case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 139211938Snikos.nikoleris@arm.com te.nonCacheable = true; 139311938Snikos.nikoleris@arm.com } 139411938Snikos.nikoleris@arm.com switch (attr_lo) { 139511938Snikos.nikoleris@arm.com case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 139611938Snikos.nikoleris@arm.com case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 139711938Snikos.nikoleris@arm.com warn_if(!attr_hi, "Unpredictable behavior"); 139811938Snikos.nikoleris@arm.com case 0x4: // Device-nGnRE memory or 139911938Snikos.nikoleris@arm.com // Normal memory, Inner Non-cacheable 140011938Snikos.nikoleris@arm.com case 0x8: // Device-nGRE memory or 140111938Snikos.nikoleris@arm.com // Normal memory, Inner Write-through non-transient 140211583SDylan.Johnson@ARM.com te.nonCacheable = true; 140311583SDylan.Johnson@ARM.com } 140411583SDylan.Johnson@ARM.com 140511583SDylan.Johnson@ARM.com te.shareable = sh == 2; 140611583SDylan.Johnson@ARM.com te.outerShareable = (sh & 0x2) ? true : false; 140711583SDylan.Johnson@ARM.com // Attributes formatted according to the 64-bit PAR 140811583SDylan.Johnson@ARM.com te.attributes = ((uint64_t) attr << 56) | 140911583SDylan.Johnson@ARM.com (1 << 11) | // LPAE bit 141011583SDylan.Johnson@ARM.com (te.ns << 9) | // NS bit 141111583SDylan.Johnson@ARM.com (sh << 7); 141210037SARM gem5 Developers } 14137404SAli.Saidi@ARM.com} 14147404SAli.Saidi@ARM.com 14157404SAli.Saidi@ARM.comvoid 14167404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 14177404SAli.Saidi@ARM.com{ 141810037SARM gem5 Developers if (currState->fault != NoFault) { 141910037SARM gem5 Developers return; 142010037SARM gem5 Developers } 142110037SARM gem5 Developers 14227439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 142310037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 14247404SAli.Saidi@ARM.com TlbEntry te; 14257404SAli.Saidi@ARM.com 14267439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 14277404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 14287404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 14297946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 14307439Sdam.sunwoo@arm.com currState->tc = NULL; 14317439Sdam.sunwoo@arm.com currState->req = NULL; 14327437Sdam.sunwoo@arm.com } 14337406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 14347439Sdam.sunwoo@arm.com if (currState->isFetch) 14357439Sdam.sunwoo@arm.com currState->fault = 143610474Sandreas.hansson@arm.com std::make_shared<PrefetchAbort>( 143710474Sandreas.hansson@arm.com currState->vaddr_tainted, 143810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 143910474Sandreas.hansson@arm.com isStage2, 144010474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14417406SAli.Saidi@ARM.com else 14427439Sdam.sunwoo@arm.com currState->fault = 144310474Sandreas.hansson@arm.com std::make_shared<DataAbort>( 144410474Sandreas.hansson@arm.com currState->vaddr_tainted, 144510474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 144610474Sandreas.hansson@arm.com currState->isWrite, 144710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 144810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14497404SAli.Saidi@ARM.com return; 14507404SAli.Saidi@ARM.com case L1Descriptor::Section: 14517439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 14527436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 14537436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 14547436Sdam.sunwoo@arm.com * AccessFlag0 14557436Sdam.sunwoo@arm.com */ 14567436Sdam.sunwoo@arm.com 145710474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 145810474Sandreas.hansson@arm.com currState->vaddr_tainted, 145910474Sandreas.hansson@arm.com currState->l1Desc.domain(), 146010474Sandreas.hansson@arm.com currState->isWrite, 146110474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L1, 146210474Sandreas.hansson@arm.com isStage2, 146310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14647436Sdam.sunwoo@arm.com } 14657439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 14667404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 14677404SAli.Saidi@ARM.com } 146810037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 146910037SARM gem5 Developers return; 147010037SARM gem5 Developers case L1Descriptor::PageTable: 147110037SARM gem5 Developers { 147210037SARM gem5 Developers Addr l2desc_addr; 147310037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 147410037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 147510037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 147610037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 14777404SAli.Saidi@ARM.com 147810037SARM gem5 Developers // Trickbox address check 147911395Sandreas.sandberg@arm.com currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 148011395Sandreas.sandberg@arm.com currState->l1Desc.domain(), L2); 14817404SAli.Saidi@ARM.com 148210037SARM gem5 Developers if (currState->fault) { 148310037SARM gem5 Developers if (!currState->timing) { 148410037SARM gem5 Developers currState->tc = NULL; 148510037SARM gem5 Developers currState->req = NULL; 148610037SARM gem5 Developers } 148710037SARM gem5 Developers return; 148810037SARM gem5 Developers } 148910037SARM gem5 Developers 149010836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 149110037SARM gem5 Developers if (currState->isSecure) 149210037SARM gem5 Developers flag.set(Request::SECURE); 149310037SARM gem5 Developers 149410037SARM gem5 Developers bool delayed; 149510037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 149610037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 149710037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 149810037SARM gem5 Developers &TableWalker::doL2Descriptor); 149910037SARM gem5 Developers if (delayed) { 150010037SARM gem5 Developers currState->delayed = true; 150110037SARM gem5 Developers } 150210037SARM gem5 Developers 150310037SARM gem5 Developers return; 150410037SARM gem5 Developers } 150510037SARM gem5 Developers default: 150610037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 150710037SARM gem5 Developers } 150810037SARM gem5 Developers} 150910037SARM gem5 Developers 151010037SARM gem5 Developersvoid 151110037SARM gem5 DevelopersTableWalker::doLongDescriptor() 151210037SARM gem5 Developers{ 151310037SARM gem5 Developers if (currState->fault != NoFault) { 151410037SARM gem5 Developers return; 151510037SARM gem5 Developers } 151610037SARM gem5 Developers 151710037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 151810037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 151910037SARM gem5 Developers currState->longDesc.data, 152010037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 152110037SARM gem5 Developers 152210037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 152310037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 152410037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 152510037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 152610037SARM gem5 Developers currState->longDesc.lookupLevel, 152710037SARM gem5 Developers currState->longDesc.data, 152810037SARM gem5 Developers currState->longDesc.pxn(), 152910037SARM gem5 Developers currState->longDesc.xn(), 153010037SARM gem5 Developers currState->longDesc.ap(), 153110037SARM gem5 Developers currState->longDesc.af(), 153210037SARM gem5 Developers currState->longDesc.type()); 153310037SARM gem5 Developers } else { 153410037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 153510037SARM gem5 Developers currState->longDesc.lookupLevel, 153610037SARM gem5 Developers currState->longDesc.data, 153710037SARM gem5 Developers currState->longDesc.type()); 153810037SARM gem5 Developers } 153910037SARM gem5 Developers 154010037SARM gem5 Developers TlbEntry te; 154110037SARM gem5 Developers 154210037SARM gem5 Developers switch (currState->longDesc.type()) { 154310037SARM gem5 Developers case LongDescriptor::Invalid: 15447439Sdam.sunwoo@arm.com if (!currState->timing) { 15457439Sdam.sunwoo@arm.com currState->tc = NULL; 15467439Sdam.sunwoo@arm.com currState->req = NULL; 15477437Sdam.sunwoo@arm.com } 15487404SAli.Saidi@ARM.com 154910037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 155010037SARM gem5 Developers currState->longDesc.lookupLevel, 155110037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 155210037SARM gem5 Developers if (currState->isFetch) 155310474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 155410037SARM gem5 Developers currState->vaddr_tainted, 155510037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 155610037SARM gem5 Developers isStage2, 155710037SARM gem5 Developers ArmFault::LpaeTran); 155810037SARM gem5 Developers else 155910474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 156010037SARM gem5 Developers currState->vaddr_tainted, 156110037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 156210037SARM gem5 Developers currState->isWrite, 156310037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 156410037SARM gem5 Developers isStage2, 156510037SARM gem5 Developers ArmFault::LpaeTran); 15667404SAli.Saidi@ARM.com return; 156710037SARM gem5 Developers case LongDescriptor::Block: 156810037SARM gem5 Developers case LongDescriptor::Page: 156910037SARM gem5 Developers { 157010037SARM gem5 Developers bool fault = false; 157110037SARM gem5 Developers bool aff = false; 157210037SARM gem5 Developers // Check for address size fault 157310037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 157410037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 157510037SARM gem5 Developers currState->longDesc.offsetBits()), 157610037SARM gem5 Developers currState->physAddrRange)) { 157710037SARM gem5 Developers fault = true; 157810037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 157910037SARM gem5 Developers currState->longDesc.lookupLevel); 158010037SARM gem5 Developers // Check for access fault 158110037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 158210037SARM gem5 Developers fault = true; 158310037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 158410037SARM gem5 Developers currState->longDesc.lookupLevel); 158510037SARM gem5 Developers aff = true; 158610037SARM gem5 Developers } 158710037SARM gem5 Developers if (fault) { 158810037SARM gem5 Developers if (currState->isFetch) 158910474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 159010037SARM gem5 Developers currState->vaddr_tainted, 159110037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 159210037SARM gem5 Developers currState->longDesc.lookupLevel, 159310037SARM gem5 Developers isStage2, 159410037SARM gem5 Developers ArmFault::LpaeTran); 159510037SARM gem5 Developers else 159610474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 159710037SARM gem5 Developers currState->vaddr_tainted, 159810037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 159910037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 160010037SARM gem5 Developers currState->longDesc.lookupLevel, 160110037SARM gem5 Developers isStage2, 160210037SARM gem5 Developers ArmFault::LpaeTran); 160310037SARM gem5 Developers } else { 160410037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 160510037SARM gem5 Developers } 160610037SARM gem5 Developers } 160710037SARM gem5 Developers return; 160810037SARM gem5 Developers case LongDescriptor::Table: 160910037SARM gem5 Developers { 161010037SARM gem5 Developers // Set hierarchical permission flags 161110037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 161210037SARM gem5 Developers currState->longDesc.secureTable(); 161310037SARM gem5 Developers currState->rwTable = currState->rwTable && 161410037SARM gem5 Developers currState->longDesc.rwTable(); 161510037SARM gem5 Developers currState->userTable = currState->userTable && 161610037SARM gem5 Developers currState->longDesc.userTable(); 161710037SARM gem5 Developers currState->xnTable = currState->xnTable || 161810037SARM gem5 Developers currState->longDesc.xnTable(); 161910037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 162010037SARM gem5 Developers currState->longDesc.pxnTable(); 16217404SAli.Saidi@ARM.com 162210037SARM gem5 Developers // Set up next level lookup 162310037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 162410037SARM gem5 Developers currState->vaddr); 16257439Sdam.sunwoo@arm.com 162610037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 162710037SARM gem5 Developers currState->longDesc.lookupLevel, 162810037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 162910037SARM gem5 Developers next_desc_addr, 163010037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 163110037SARM gem5 Developers 163210037SARM gem5 Developers // Check for address size fault 163310037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 163410037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 163510037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 163610037SARM gem5 Developers currState->longDesc.lookupLevel); 163710037SARM gem5 Developers if (currState->isFetch) 163810474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 163910037SARM gem5 Developers currState->vaddr_tainted, 164010037SARM gem5 Developers ArmFault::AddressSizeLL 164110037SARM gem5 Developers + currState->longDesc.lookupLevel, 164210037SARM gem5 Developers isStage2, 164310037SARM gem5 Developers ArmFault::LpaeTran); 164410037SARM gem5 Developers else 164510474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 164610037SARM gem5 Developers currState->vaddr_tainted, 164710037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 164810037SARM gem5 Developers ArmFault::AddressSizeLL 164910037SARM gem5 Developers + currState->longDesc.lookupLevel, 165010037SARM gem5 Developers isStage2, 165110037SARM gem5 Developers ArmFault::LpaeTran); 165210037SARM gem5 Developers return; 16537437Sdam.sunwoo@arm.com } 16547404SAli.Saidi@ARM.com 165510037SARM gem5 Developers // Trickbox address check 165611395Sandreas.sandberg@arm.com currState->fault = testWalk( 165711395Sandreas.sandberg@arm.com next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 165811395Sandreas.sandberg@arm.com toLookupLevel(currState->longDesc.lookupLevel +1)); 16597404SAli.Saidi@ARM.com 166010037SARM gem5 Developers if (currState->fault) { 166110037SARM gem5 Developers if (!currState->timing) { 166210037SARM gem5 Developers currState->tc = NULL; 166310037SARM gem5 Developers currState->req = NULL; 166410037SARM gem5 Developers } 166510037SARM gem5 Developers return; 166610037SARM gem5 Developers } 166710037SARM gem5 Developers 166810836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 166910037SARM gem5 Developers if (currState->secureLookup) 167010037SARM gem5 Developers flag.set(Request::SECURE); 167110037SARM gem5 Developers 167211588SCurtis.Dunham@arm.com LookupLevel L = currState->longDesc.lookupLevel = 167310037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 167410037SARM gem5 Developers Event *event = NULL; 167511588SCurtis.Dunham@arm.com switch (L) { 167610037SARM gem5 Developers case L1: 167710037SARM gem5 Developers assert(currState->aarch64); 167810037SARM gem5 Developers case L2: 167910037SARM gem5 Developers case L3: 168011588SCurtis.Dunham@arm.com event = LongDescEventByLevel[L]; 168110037SARM gem5 Developers break; 168210037SARM gem5 Developers default: 168310037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 168410037SARM gem5 Developers break; 168510037SARM gem5 Developers } 168610037SARM gem5 Developers 168710037SARM gem5 Developers bool delayed; 168810037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 168910037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 169010037SARM gem5 Developers &TableWalker::doLongDescriptor); 169110037SARM gem5 Developers if (delayed) { 169210037SARM gem5 Developers currState->delayed = true; 169310037SARM gem5 Developers } 16947404SAli.Saidi@ARM.com } 16957404SAli.Saidi@ARM.com return; 16967404SAli.Saidi@ARM.com default: 16977404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 16987404SAli.Saidi@ARM.com } 16997404SAli.Saidi@ARM.com} 17007404SAli.Saidi@ARM.com 17017404SAli.Saidi@ARM.comvoid 17027404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 17037404SAli.Saidi@ARM.com{ 170410037SARM gem5 Developers if (currState->fault != NoFault) { 170510037SARM gem5 Developers return; 170610037SARM gem5 Developers } 170710037SARM gem5 Developers 17087439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 170910037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 17107404SAli.Saidi@ARM.com TlbEntry te; 17117404SAli.Saidi@ARM.com 17127439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 17137404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 17147946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 17157439Sdam.sunwoo@arm.com currState->tc = NULL; 17167439Sdam.sunwoo@arm.com currState->req = NULL; 17177437Sdam.sunwoo@arm.com } 17187439Sdam.sunwoo@arm.com if (currState->isFetch) 171910474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 172010474Sandreas.hansson@arm.com currState->vaddr_tainted, 172110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L2, 172210474Sandreas.hansson@arm.com isStage2, 172310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17247406SAli.Saidi@ARM.com else 172510474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 172610474Sandreas.hansson@arm.com currState->vaddr_tainted, currState->l1Desc.domain(), 172710474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L2, 172810474Sandreas.hansson@arm.com isStage2, 172910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17307404SAli.Saidi@ARM.com return; 17317404SAli.Saidi@ARM.com } 17327404SAli.Saidi@ARM.com 17337439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 17347436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 17357436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 17367436Sdam.sunwoo@arm.com */ 173710037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 173810037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 17397436Sdam.sunwoo@arm.com 174010474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 174110474Sandreas.hansson@arm.com currState->vaddr_tainted, 174210474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 174310474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L2, isStage2, 174410474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17457436Sdam.sunwoo@arm.com } 17467436Sdam.sunwoo@arm.com 174710037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 17487437Sdam.sunwoo@arm.com} 17497437Sdam.sunwoo@arm.com 17507437Sdam.sunwoo@arm.comvoid 17517437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 17527437Sdam.sunwoo@arm.com{ 175310037SARM gem5 Developers currState = stateQueues[L1].front(); 17547439Sdam.sunwoo@arm.com currState->delayed = false; 175510037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 175610037SARM gem5 Developers if (currState->stage2Tran) { 175710037SARM gem5 Developers delete currState->stage2Tran; 175810037SARM gem5 Developers currState->stage2Tran = NULL; 175910037SARM gem5 Developers } 176010037SARM gem5 Developers 17617437Sdam.sunwoo@arm.com 17627578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 17637578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 17647578Sdam.sunwoo@arm.com 176510037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 17667437Sdam.sunwoo@arm.com doL1Descriptor(); 17677437Sdam.sunwoo@arm.com 176810037SARM gem5 Developers stateQueues[L1].pop_front(); 17697437Sdam.sunwoo@arm.com // Check if fault was generated 17707439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 17717439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 17727439Sdam.sunwoo@arm.com currState->tc, currState->mode); 177310621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 17747437Sdam.sunwoo@arm.com 17757728SAli.Saidi@ARM.com pending = false; 17767728SAli.Saidi@ARM.com nextWalk(currState->tc); 17777728SAli.Saidi@ARM.com 17787439Sdam.sunwoo@arm.com currState->req = NULL; 17797439Sdam.sunwoo@arm.com currState->tc = NULL; 17807439Sdam.sunwoo@arm.com currState->delayed = false; 17818510SAli.Saidi@ARM.com delete currState; 17827437Sdam.sunwoo@arm.com } 17837439Sdam.sunwoo@arm.com else if (!currState->delayed) { 17847653Sgene.wu@arm.com // delay is not set so there is no L2 to do 178510037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 178610037SARM gem5 Developers if (!currState->doingStage2) { 178710621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 178810037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 178910037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 179010037SARM gem5 Developers currState->transState, currState->mode); 179110621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 179210037SARM gem5 Developers } 17937437Sdam.sunwoo@arm.com 17947728SAli.Saidi@ARM.com pending = false; 17957728SAli.Saidi@ARM.com nextWalk(currState->tc); 17967728SAli.Saidi@ARM.com 17977439Sdam.sunwoo@arm.com currState->req = NULL; 17987439Sdam.sunwoo@arm.com currState->tc = NULL; 17997439Sdam.sunwoo@arm.com currState->delayed = false; 18007653Sgene.wu@arm.com delete currState; 18017653Sgene.wu@arm.com } else { 18027653Sgene.wu@arm.com // need to do L2 descriptor 180310037SARM gem5 Developers stateQueues[L2].push_back(currState); 18047437Sdam.sunwoo@arm.com } 18057439Sdam.sunwoo@arm.com currState = NULL; 18067437Sdam.sunwoo@arm.com} 18077437Sdam.sunwoo@arm.com 18087437Sdam.sunwoo@arm.comvoid 18097437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 18107437Sdam.sunwoo@arm.com{ 181110037SARM gem5 Developers currState = stateQueues[L2].front(); 18127439Sdam.sunwoo@arm.com assert(currState->delayed); 181310037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 181410037SARM gem5 Developers if (currState->stage2Tran) { 181510037SARM gem5 Developers delete currState->stage2Tran; 181610037SARM gem5 Developers currState->stage2Tran = NULL; 181710037SARM gem5 Developers } 18187437Sdam.sunwoo@arm.com 18197439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 182010037SARM gem5 Developers currState->vaddr_tainted); 18217437Sdam.sunwoo@arm.com doL2Descriptor(); 18227437Sdam.sunwoo@arm.com 18237437Sdam.sunwoo@arm.com // Check if fault was generated 18247439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18257439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18267439Sdam.sunwoo@arm.com currState->tc, currState->mode); 182710621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 18287437Sdam.sunwoo@arm.com } 18297437Sdam.sunwoo@arm.com else { 183010037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 183110037SARM gem5 Developers if (!currState->doingStage2) { 183210621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 183310037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 183410037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, 183510037SARM gem5 Developers currState->tc, currState->transState, currState->mode); 183610621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 183710037SARM gem5 Developers } 18387437Sdam.sunwoo@arm.com } 18397437Sdam.sunwoo@arm.com 18407728SAli.Saidi@ARM.com 184110037SARM gem5 Developers stateQueues[L2].pop_front(); 18427728SAli.Saidi@ARM.com pending = false; 18437728SAli.Saidi@ARM.com nextWalk(currState->tc); 18447728SAli.Saidi@ARM.com 18457439Sdam.sunwoo@arm.com currState->req = NULL; 18467439Sdam.sunwoo@arm.com currState->tc = NULL; 18477439Sdam.sunwoo@arm.com currState->delayed = false; 18487439Sdam.sunwoo@arm.com 18497653Sgene.wu@arm.com delete currState; 18507439Sdam.sunwoo@arm.com currState = NULL; 18517404SAli.Saidi@ARM.com} 18527404SAli.Saidi@ARM.com 18537728SAli.Saidi@ARM.comvoid 185410037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 185510037SARM gem5 Developers{ 185610037SARM gem5 Developers doLongDescriptorWrapper(L0); 185710037SARM gem5 Developers} 185810037SARM gem5 Developers 185910037SARM gem5 Developersvoid 186010037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 186110037SARM gem5 Developers{ 186210037SARM gem5 Developers doLongDescriptorWrapper(L1); 186310037SARM gem5 Developers} 186410037SARM gem5 Developers 186510037SARM gem5 Developersvoid 186610037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 186710037SARM gem5 Developers{ 186810037SARM gem5 Developers doLongDescriptorWrapper(L2); 186910037SARM gem5 Developers} 187010037SARM gem5 Developers 187110037SARM gem5 Developersvoid 187210037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 187310037SARM gem5 Developers{ 187410037SARM gem5 Developers doLongDescriptorWrapper(L3); 187510037SARM gem5 Developers} 187610037SARM gem5 Developers 187710037SARM gem5 Developersvoid 187810037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 187910037SARM gem5 Developers{ 188010037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 188110037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 188210037SARM gem5 Developers currState->delayed = false; 188310037SARM gem5 Developers 188410037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 188510037SARM gem5 Developers if (currState->stage2Tran) { 188610037SARM gem5 Developers delete currState->stage2Tran; 188710037SARM gem5 Developers currState->stage2Tran = NULL; 188810037SARM gem5 Developers } 188910037SARM gem5 Developers 189010037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 189110037SARM gem5 Developers currState->vaddr_tainted); 189210037SARM gem5 Developers doLongDescriptor(); 189310037SARM gem5 Developers 189410037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 189510037SARM gem5 Developers 189610037SARM gem5 Developers if (currState->fault != NoFault) { 189710037SARM gem5 Developers // A fault was generated 189810037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 189910037SARM gem5 Developers currState->tc, currState->mode); 190010037SARM gem5 Developers 190110037SARM gem5 Developers pending = false; 190210037SARM gem5 Developers nextWalk(currState->tc); 190310037SARM gem5 Developers 190410037SARM gem5 Developers currState->req = NULL; 190510037SARM gem5 Developers currState->tc = NULL; 190610037SARM gem5 Developers currState->delayed = false; 190710037SARM gem5 Developers delete currState; 190810037SARM gem5 Developers } else if (!currState->delayed) { 190910037SARM gem5 Developers // No additional lookups required 191010037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 191110037SARM gem5 Developers if (!currState->doingStage2) { 191210037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 191310621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 191410037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 191510037SARM gem5 Developers currState->transState, 191610037SARM gem5 Developers currState->mode); 191710621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 191810037SARM gem5 Developers } 191910037SARM gem5 Developers 192010037SARM gem5 Developers pending = false; 192110037SARM gem5 Developers nextWalk(currState->tc); 192210037SARM gem5 Developers 192310037SARM gem5 Developers currState->req = NULL; 192410037SARM gem5 Developers currState->tc = NULL; 192510037SARM gem5 Developers currState->delayed = false; 192610037SARM gem5 Developers delete currState; 192710037SARM gem5 Developers } else { 192810037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 192910037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 193010037SARM gem5 Developers // Need to perform additional lookups 193110037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 193210037SARM gem5 Developers } 193310037SARM gem5 Developers currState = NULL; 193410037SARM gem5 Developers} 193510037SARM gem5 Developers 193610037SARM gem5 Developers 193710037SARM gem5 Developersvoid 19387728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 19397728SAli.Saidi@ARM.com{ 19407728SAli.Saidi@ARM.com if (pendingQueue.size()) 19419309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 194210509SAli.Saidi@ARM.com else 194310509SAli.Saidi@ARM.com completeDrain(); 19447728SAli.Saidi@ARM.com} 19457728SAli.Saidi@ARM.com 194610037SARM gem5 Developersbool 194710037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 194810037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 194910037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 195010037SARM gem5 Developers{ 195110037SARM gem5 Developers bool isTiming = currState->timing; 19527728SAli.Saidi@ARM.com 195311575SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 195411575SDylan.Johnson@ARM.com descAddr, currState->stage2Req); 195511575SDylan.Johnson@ARM.com 195611575SDylan.Johnson@ARM.com // If this translation has a stage 2 then we know descAddr is an IPA and 195711575SDylan.Johnson@ARM.com // needs to be translated before we can access the page table. Do that 195811575SDylan.Johnson@ARM.com // check here. 195910037SARM gem5 Developers if (currState->stage2Req) { 196010037SARM gem5 Developers Fault fault; 196110037SARM gem5 Developers flags = flags | TLB::MustBeOne; 196210037SARM gem5 Developers 196310037SARM gem5 Developers if (isTiming) { 196410037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 196510037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 196610037SARM gem5 Developers currState->vaddr); 196710037SARM gem5 Developers currState->stage2Tran = tran; 196810037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 196910717Sandreas.hansson@arm.com flags); 197010037SARM gem5 Developers fault = tran->fault; 197110037SARM gem5 Developers } else { 197210037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 197310717Sandreas.hansson@arm.com currState->vaddr, descAddr, data, numBytes, flags, 197410037SARM gem5 Developers currState->functional); 197510037SARM gem5 Developers } 197610037SARM gem5 Developers 197710037SARM gem5 Developers if (fault != NoFault) { 197810037SARM gem5 Developers currState->fault = fault; 197910037SARM gem5 Developers } 198010037SARM gem5 Developers if (isTiming) { 198110037SARM gem5 Developers if (queueIndex >= 0) { 198210037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 198310037SARM gem5 Developers stateQueues[queueIndex].size()); 198410037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 198510037SARM gem5 Developers currState = NULL; 198610037SARM gem5 Developers } 198710037SARM gem5 Developers } else { 198810037SARM gem5 Developers (this->*doDescriptor)(); 198910037SARM gem5 Developers } 199010037SARM gem5 Developers } else { 199110037SARM gem5 Developers if (isTiming) { 199210717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 199310621SCurtis.Dunham@arm.com currState->tc->getCpuPtr()->clockPeriod(),flags); 199410037SARM gem5 Developers if (queueIndex >= 0) { 199510037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 199610037SARM gem5 Developers stateQueues[queueIndex].size()); 199710037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 199810037SARM gem5 Developers currState = NULL; 199910037SARM gem5 Developers } 200010037SARM gem5 Developers } else if (!currState->functional) { 200110717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 200210037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 200310037SARM gem5 Developers (this->*doDescriptor)(); 200410037SARM gem5 Developers } else { 200510037SARM gem5 Developers RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 200610037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 200710037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 200810037SARM gem5 Developers pkt->dataStatic(data); 200910717Sandreas.hansson@arm.com port->sendFunctional(pkt); 201010037SARM gem5 Developers (this->*doDescriptor)(); 201110037SARM gem5 Developers delete req; 201210037SARM gem5 Developers delete pkt; 201310037SARM gem5 Developers } 201410037SARM gem5 Developers } 201510037SARM gem5 Developers return (isTiming); 201610037SARM gem5 Developers} 201710037SARM gem5 Developers 201810037SARM gem5 Developersvoid 201910037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 202010037SARM gem5 Developers{ 202110037SARM gem5 Developers TlbEntry te; 202210037SARM gem5 Developers 202310037SARM gem5 Developers // Create and fill a new page table entry 202410037SARM gem5 Developers te.valid = true; 202510037SARM gem5 Developers te.longDescFormat = longDescriptor; 202610037SARM gem5 Developers te.isHyp = currState->isHyp; 202710037SARM gem5 Developers te.asid = currState->asid; 202810037SARM gem5 Developers te.vmid = currState->vmid; 202910037SARM gem5 Developers te.N = descriptor.offsetBits(); 203010037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 203110037SARM gem5 Developers te.size = (1<<te.N) - 1; 203210037SARM gem5 Developers te.pfn = descriptor.pfn(); 203310037SARM gem5 Developers te.domain = descriptor.domain(); 203410037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 203510037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 203610037SARM gem5 Developers te.nstid = !currState->isSecure; 203710037SARM gem5 Developers te.xn = descriptor.xn(); 203810037SARM gem5 Developers if (currState->aarch64) 203910037SARM gem5 Developers te.el = currState->el; 204010037SARM gem5 Developers else 204110037SARM gem5 Developers te.el = 1; 204210037SARM gem5 Developers 204310621SCurtis.Dunham@arm.com statPageSizes[pageSizeNtoStatBin(te.N)]++; 204410621SCurtis.Dunham@arm.com statRequestOrigin[COMPLETED][currState->isFetch]++; 204510621SCurtis.Dunham@arm.com 204610037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 204710037SARM gem5 Developers // as global 204810037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 204910037SARM gem5 Developers if (longDescriptor) { 205010037SARM gem5 Developers LongDescriptor lDescriptor = 205110037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 205210037SARM gem5 Developers 205310037SARM gem5 Developers te.xn |= currState->xnTable; 205410037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 205510037SARM gem5 Developers if (isStage2) { 205610037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 205710037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 205810037SARM gem5 Developers te.hap = lDescriptor.ap(); 205910037SARM gem5 Developers } else { 206010037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 206110037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 206210037SARM gem5 Developers } 206310037SARM gem5 Developers if (currState->aarch64) 206411583SDylan.Johnson@ARM.com memAttrsAArch64(currState->tc, te, lDescriptor); 206510037SARM gem5 Developers else 206610037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 206710037SARM gem5 Developers } else { 206810037SARM gem5 Developers te.ap = descriptor.ap(); 206910037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 207010037SARM gem5 Developers descriptor.shareable()); 207110037SARM gem5 Developers } 207210037SARM gem5 Developers 207310037SARM gem5 Developers // Debug output 207410037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 207510037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 207610037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 207710037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 207810037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 207910037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 208010037SARM gem5 Developers te.nonCacheable, te.ns); 208110037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 208210037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 208310037SARM gem5 Developers descriptor.getRawData()); 208410037SARM gem5 Developers 208510037SARM gem5 Developers // Insert the entry into the TLB 208610037SARM gem5 Developers tlb->insert(currState->vaddr, te); 208710037SARM gem5 Developers if (!currState->timing) { 208810037SARM gem5 Developers currState->tc = NULL; 208910037SARM gem5 Developers currState->req = NULL; 209010037SARM gem5 Developers } 209110037SARM gem5 Developers} 20927728SAli.Saidi@ARM.com 20937404SAli.Saidi@ARM.comArmISA::TableWalker * 20947404SAli.Saidi@ARM.comArmTableWalkerParams::create() 20957404SAli.Saidi@ARM.com{ 20967404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 20977404SAli.Saidi@ARM.com} 20987404SAli.Saidi@ARM.com 209910037SARM gem5 DevelopersLookupLevel 210010037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 210110037SARM gem5 Developers{ 210210037SARM gem5 Developers switch (lookup_level_as_int) { 210310037SARM gem5 Developers case L1: 210410037SARM gem5 Developers return L1; 210510037SARM gem5 Developers case L2: 210610037SARM gem5 Developers return L2; 210710037SARM gem5 Developers case L3: 210810037SARM gem5 Developers return L3; 210910037SARM gem5 Developers default: 211010037SARM gem5 Developers panic("Invalid lookup level conversion"); 211110037SARM gem5 Developers } 211210037SARM gem5 Developers} 211310621SCurtis.Dunham@arm.com 211410621SCurtis.Dunham@arm.com/* this method keeps track of the table walker queue's residency, so 211510621SCurtis.Dunham@arm.com * needs to be called whenever requests start and complete. */ 211610621SCurtis.Dunham@arm.comvoid 211710621SCurtis.Dunham@arm.comTableWalker::pendingChange() 211810621SCurtis.Dunham@arm.com{ 211910621SCurtis.Dunham@arm.com unsigned n = pendingQueue.size(); 212010621SCurtis.Dunham@arm.com if ((currState != NULL) && (currState != pendingQueue.front())) { 212110621SCurtis.Dunham@arm.com ++n; 212210621SCurtis.Dunham@arm.com } 212310621SCurtis.Dunham@arm.com 212410621SCurtis.Dunham@arm.com if (n != pendingReqs) { 212510621SCurtis.Dunham@arm.com Tick now = curTick(); 212610621SCurtis.Dunham@arm.com statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 212710621SCurtis.Dunham@arm.com pendingReqs = n; 212810621SCurtis.Dunham@arm.com pendingChangeTick = now; 212910621SCurtis.Dunham@arm.com } 213010621SCurtis.Dunham@arm.com} 213110621SCurtis.Dunham@arm.com 213211395Sandreas.sandberg@arm.comFault 213311395Sandreas.sandberg@arm.comTableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 213411395Sandreas.sandberg@arm.com LookupLevel lookup_level) 213511395Sandreas.sandberg@arm.com{ 213611395Sandreas.sandberg@arm.com return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 213711395Sandreas.sandberg@arm.com currState->mode, domain, lookup_level); 213811395Sandreas.sandberg@arm.com} 213911395Sandreas.sandberg@arm.com 214011395Sandreas.sandberg@arm.com 214110621SCurtis.Dunham@arm.comuint8_t 214210621SCurtis.Dunham@arm.comTableWalker::pageSizeNtoStatBin(uint8_t N) 214310621SCurtis.Dunham@arm.com{ 214410621SCurtis.Dunham@arm.com /* for statPageSizes */ 214510621SCurtis.Dunham@arm.com switch(N) { 214610621SCurtis.Dunham@arm.com case 12: return 0; // 4K 214710621SCurtis.Dunham@arm.com case 14: return 1; // 16K (using 16K granule in v8-64) 214810621SCurtis.Dunham@arm.com case 16: return 2; // 64K 214910621SCurtis.Dunham@arm.com case 20: return 3; // 1M 215010621SCurtis.Dunham@arm.com case 21: return 4; // 2M-LPAE 215110621SCurtis.Dunham@arm.com case 24: return 5; // 16M 215210621SCurtis.Dunham@arm.com case 25: return 6; // 32M (using 16K granule in v8-64) 215310621SCurtis.Dunham@arm.com case 29: return 7; // 512M (using 64K granule in v8-64) 215410621SCurtis.Dunham@arm.com case 30: return 8; // 1G-LPAE 215510621SCurtis.Dunham@arm.com default: 215610621SCurtis.Dunham@arm.com panic("unknown page size"); 215710621SCurtis.Dunham@arm.com return 255; 215810621SCurtis.Dunham@arm.com } 215910621SCurtis.Dunham@arm.com} 216010621SCurtis.Dunham@arm.com 216110621SCurtis.Dunham@arm.comvoid 216210621SCurtis.Dunham@arm.comTableWalker::regStats() 216310621SCurtis.Dunham@arm.com{ 216411522Sstephan.diestelhorst@arm.com ClockedObject::regStats(); 216511522Sstephan.diestelhorst@arm.com 216610621SCurtis.Dunham@arm.com statWalks 216710621SCurtis.Dunham@arm.com .name(name() + ".walks") 216810621SCurtis.Dunham@arm.com .desc("Table walker walks requested") 216910621SCurtis.Dunham@arm.com ; 217010621SCurtis.Dunham@arm.com 217110621SCurtis.Dunham@arm.com statWalksShortDescriptor 217210621SCurtis.Dunham@arm.com .name(name() + ".walksShort") 217310621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with short descriptors") 217410621SCurtis.Dunham@arm.com .flags(Stats::nozero) 217510621SCurtis.Dunham@arm.com ; 217610621SCurtis.Dunham@arm.com 217710621SCurtis.Dunham@arm.com statWalksLongDescriptor 217810621SCurtis.Dunham@arm.com .name(name() + ".walksLong") 217910621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with long descriptors") 218010621SCurtis.Dunham@arm.com .flags(Stats::nozero) 218110621SCurtis.Dunham@arm.com ; 218210621SCurtis.Dunham@arm.com 218310621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel 218410621SCurtis.Dunham@arm.com .init(2) 218510621SCurtis.Dunham@arm.com .name(name() + ".walksShortTerminationLevel") 218610621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 218710621SCurtis.Dunham@arm.com "with short descriptors terminate") 218810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 218910621SCurtis.Dunham@arm.com ; 219010621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(0, "Level1"); 219110621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(1, "Level2"); 219210621SCurtis.Dunham@arm.com 219310621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel 219410621SCurtis.Dunham@arm.com .init(4) 219510621SCurtis.Dunham@arm.com .name(name() + ".walksLongTerminationLevel") 219610621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 219710621SCurtis.Dunham@arm.com "with long descriptors terminate") 219810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 219910621SCurtis.Dunham@arm.com ; 220010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(0, "Level0"); 220110621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(1, "Level1"); 220210621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(2, "Level2"); 220310621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(3, "Level3"); 220410621SCurtis.Dunham@arm.com 220510621SCurtis.Dunham@arm.com statSquashedBefore 220610621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedBefore") 220710621SCurtis.Dunham@arm.com .desc("Table walks squashed before starting") 220810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 220910621SCurtis.Dunham@arm.com ; 221010621SCurtis.Dunham@arm.com 221110621SCurtis.Dunham@arm.com statSquashedAfter 221210621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedAfter") 221310621SCurtis.Dunham@arm.com .desc("Table walks squashed after completion") 221410621SCurtis.Dunham@arm.com .flags(Stats::nozero) 221510621SCurtis.Dunham@arm.com ; 221610621SCurtis.Dunham@arm.com 221710621SCurtis.Dunham@arm.com statWalkWaitTime 221810621SCurtis.Dunham@arm.com .init(16) 221910621SCurtis.Dunham@arm.com .name(name() + ".walkWaitTime") 222010621SCurtis.Dunham@arm.com .desc("Table walker wait (enqueue to first request) latency") 222110621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 222210621SCurtis.Dunham@arm.com ; 222310621SCurtis.Dunham@arm.com 222410621SCurtis.Dunham@arm.com statWalkServiceTime 222510621SCurtis.Dunham@arm.com .init(16) 222610621SCurtis.Dunham@arm.com .name(name() + ".walkCompletionTime") 222710621SCurtis.Dunham@arm.com .desc("Table walker service (enqueue to completion) latency") 222810621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 222910621SCurtis.Dunham@arm.com ; 223010621SCurtis.Dunham@arm.com 223110621SCurtis.Dunham@arm.com statPendingWalks 223210621SCurtis.Dunham@arm.com .init(16) 223310621SCurtis.Dunham@arm.com .name(name() + ".walksPending") 223410621SCurtis.Dunham@arm.com .desc("Table walker pending requests distribution") 223510621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 223610621SCurtis.Dunham@arm.com ; 223710621SCurtis.Dunham@arm.com 223810621SCurtis.Dunham@arm.com statPageSizes // see DDI 0487A D4-1661 223910621SCurtis.Dunham@arm.com .init(9) 224010621SCurtis.Dunham@arm.com .name(name() + ".walkPageSizes") 224110621SCurtis.Dunham@arm.com .desc("Table walker page sizes translated") 224210621SCurtis.Dunham@arm.com .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 224310621SCurtis.Dunham@arm.com ; 224410621SCurtis.Dunham@arm.com statPageSizes.subname(0, "4K"); 224510621SCurtis.Dunham@arm.com statPageSizes.subname(1, "16K"); 224610621SCurtis.Dunham@arm.com statPageSizes.subname(2, "64K"); 224710621SCurtis.Dunham@arm.com statPageSizes.subname(3, "1M"); 224810621SCurtis.Dunham@arm.com statPageSizes.subname(4, "2M"); 224910621SCurtis.Dunham@arm.com statPageSizes.subname(5, "16M"); 225010621SCurtis.Dunham@arm.com statPageSizes.subname(6, "32M"); 225110621SCurtis.Dunham@arm.com statPageSizes.subname(7, "512M"); 225210621SCurtis.Dunham@arm.com statPageSizes.subname(8, "1G"); 225310621SCurtis.Dunham@arm.com 225410621SCurtis.Dunham@arm.com statRequestOrigin 225510621SCurtis.Dunham@arm.com .init(2,2) // Instruction/Data, requests/completed 225610621SCurtis.Dunham@arm.com .name(name() + ".walkRequestOrigin") 225710621SCurtis.Dunham@arm.com .desc("Table walker requests started/completed, data/inst") 225810621SCurtis.Dunham@arm.com .flags(Stats::total) 225910621SCurtis.Dunham@arm.com ; 226010621SCurtis.Dunham@arm.com statRequestOrigin.subname(0,"Requested"); 226110621SCurtis.Dunham@arm.com statRequestOrigin.subname(1,"Completed"); 226210621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(0,"Data"); 226310621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(1,"Inst"); 226410621SCurtis.Dunham@arm.com} 2265