table_walker.cc revision 11583
15245Sgblack@eecs.umich.edu/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010, 2012-2016 ARM Limited 38948Sandreas.hansson@arm.com * All rights reserved 48948Sandreas.hansson@arm.com * 58948Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68948Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78948Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88948Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98948Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108948Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118948Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128948Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138948Sandreas.hansson@arm.com * 145245Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 155245Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 165245Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 227087Snate@binkert.org * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 247087Snate@binkert.org * 255245Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267087Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277087Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287087Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307087Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317087Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327087Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337087Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345245Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357087Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365245Sgblack@eecs.umich.edu * 375245Sgblack@eecs.umich.edu * Authors: Ali Saidi 385245Sgblack@eecs.umich.edu * Giacomo Gabrielli 395245Sgblack@eecs.umich.edu */ 405245Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 415245Sgblack@eecs.umich.edu 425245Sgblack@eecs.umich.edu#include <memory> 435245Sgblack@eecs.umich.edu 445245Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 455245Sgblack@eecs.umich.edu#include "arch/arm/stage2_mmu.hh" 465245Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 475245Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 485245Sgblack@eecs.umich.edu#include "cpu/base.hh" 495245Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 505245Sgblack@eecs.umich.edu#include "debug/Checkpoint.hh" 515245Sgblack@eecs.umich.edu#include "debug/Drain.hh" 525245Sgblack@eecs.umich.edu#include "debug/TLB.hh" 535245Sgblack@eecs.umich.edu#include "debug/TLBVerbose.hh" 545245Sgblack@eecs.umich.edu#include "dev/dma_device.hh" 557912Shestness@cs.utexas.edu#include "sim/system.hh" 565245Sgblack@eecs.umich.edu 578953Sgblack@eecs.umich.eduusing namespace ArmISA; 588229Snate@binkert.org 595245Sgblack@eecs.umich.eduTableWalker::TableWalker(const Params *p) 608232Snate@binkert.org : MemObject(p), 615245Sgblack@eecs.umich.edu stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 625245Sgblack@eecs.umich.edu isStage2(p->is_stage2), tlb(NULL), 635245Sgblack@eecs.umich.edu currState(NULL), pending(false), 645245Sgblack@eecs.umich.edu numSquashable(p->num_squash_per_cycle), 655245Sgblack@eecs.umich.edu pendingReqs(0), 665245Sgblack@eecs.umich.edu pendingChangeTick(curTick()), 675245Sgblack@eecs.umich.edu doL1DescEvent(this), doL2DescEvent(this), 685245Sgblack@eecs.umich.edu doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this), 695245Sgblack@eecs.umich.edu doL3LongDescEvent(this), 705245Sgblack@eecs.umich.edu doProcessEvent(this) 715245Sgblack@eecs.umich.edu{ 725245Sgblack@eecs.umich.edu sctlr = 0; 735245Sgblack@eecs.umich.edu 745245Sgblack@eecs.umich.edu // Cache system-level properties 755245Sgblack@eecs.umich.edu if (FullSystem) { 765245Sgblack@eecs.umich.edu ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 775245Sgblack@eecs.umich.edu assert(armSys); 785245Sgblack@eecs.umich.edu haveSecurity = armSys->haveSecurity(); 795245Sgblack@eecs.umich.edu _haveLPAE = armSys->haveLPAE(); 805245Sgblack@eecs.umich.edu _haveVirtualization = armSys->haveVirtualization(); 815245Sgblack@eecs.umich.edu physAddrRange = armSys->physAddrRange(); 825245Sgblack@eecs.umich.edu _haveLargeAsid64 = armSys->haveLargeAsid64(); 835895Sgblack@eecs.umich.edu } else { 847912Shestness@cs.utexas.edu haveSecurity = _haveLPAE = _haveVirtualization = false; 857912Shestness@cs.utexas.edu _haveLargeAsid64 = false; 865245Sgblack@eecs.umich.edu physAddrRange = 32; 877912Shestness@cs.utexas.edu } 887912Shestness@cs.utexas.edu 897912Shestness@cs.utexas.edu} 907912Shestness@cs.utexas.edu 917912Shestness@cs.utexas.eduTableWalker::~TableWalker() 927912Shestness@cs.utexas.edu{ 937912Shestness@cs.utexas.edu ; 947912Shestness@cs.utexas.edu} 957912Shestness@cs.utexas.edu 967912Shestness@cs.utexas.eduvoid 977912Shestness@cs.utexas.eduTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 987912Shestness@cs.utexas.edu{ 997912Shestness@cs.utexas.edu stage2Mmu = m; 1007912Shestness@cs.utexas.edu port = &m->getPort(); 1017912Shestness@cs.utexas.edu masterId = master_id; 1027912Shestness@cs.utexas.edu} 1035895Sgblack@eecs.umich.edu 1047912Shestness@cs.utexas.eduvoid 1055245Sgblack@eecs.umich.eduTableWalker::init() 1065245Sgblack@eecs.umich.edu{ 1075245Sgblack@eecs.umich.edu fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 1085895Sgblack@eecs.umich.edu fatal_if(!port, "Table walker must have a valid port\n"); 1098953Sgblack@eecs.umich.edu fatal_if(!tlb, "Table walker must have a valid TLB\n"); 1107912Shestness@cs.utexas.edu} 1115245Sgblack@eecs.umich.edu 1127912Shestness@cs.utexas.eduBaseMasterPort& 1138953Sgblack@eecs.umich.eduTableWalker::getMasterPort(const std::string &if_name, PortID idx) 1145245Sgblack@eecs.umich.edu{ 1155245Sgblack@eecs.umich.edu if (if_name == "port") { 1165245Sgblack@eecs.umich.edu if (!isStage2) { 1178975Sandreas.hansson@arm.com return *port; 1185245Sgblack@eecs.umich.edu } else { 1198975Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 1205245Sgblack@eecs.umich.edu } 1215245Sgblack@eecs.umich.edu } 1225245Sgblack@eecs.umich.edu return MemObject::getMasterPort(if_name, idx); 1238975Sandreas.hansson@arm.com} 1245245Sgblack@eecs.umich.edu 1258948Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 1268948Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 1278948Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 1288948Sandreas.hansson@arm.com vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 1298948Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 1308948Sandreas.hansson@arm.com pxnTable(false), stage2Req(false), doingStage2(false), 1318948Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 1328948Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 1338948Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 1348948Sandreas.hansson@arm.com{ 1358948Sandreas.hansson@arm.com} 1368948Sandreas.hansson@arm.com 1378948Sandreas.hansson@arm.comvoid 1385895Sgblack@eecs.umich.eduTableWalker::completeDrain() 1395245Sgblack@eecs.umich.edu{ 1408948Sandreas.hansson@arm.com if (drainState() == DrainState::Draining && 1418948Sandreas.hansson@arm.com stateQueues[L1].empty() && stateQueues[L2].empty() && 1428948Sandreas.hansson@arm.com pendingQueue.empty()) { 1438948Sandreas.hansson@arm.com 1448948Sandreas.hansson@arm.com DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 1458948Sandreas.hansson@arm.com signalDrainDone(); 1468948Sandreas.hansson@arm.com } 1478948Sandreas.hansson@arm.com} 1485245Sgblack@eecs.umich.edu 1495245Sgblack@eecs.umich.eduDrainState 1505245Sgblack@eecs.umich.eduTableWalker::drain() 1515245Sgblack@eecs.umich.edu{ 1525245Sgblack@eecs.umich.edu bool state_queues_not_empty = false; 1535245Sgblack@eecs.umich.edu 1545245Sgblack@eecs.umich.edu for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 1555245Sgblack@eecs.umich.edu if (!stateQueues[i].empty()) { 1565245Sgblack@eecs.umich.edu state_queues_not_empty = true; 1575245Sgblack@eecs.umich.edu break; 1585245Sgblack@eecs.umich.edu } 1595245Sgblack@eecs.umich.edu } 1605245Sgblack@eecs.umich.edu 1617912Shestness@cs.utexas.edu if (state_queues_not_empty || pendingQueue.size()) { 1627912Shestness@cs.utexas.edu DPRINTF(Drain, "TableWalker not drained\n"); 1637912Shestness@cs.utexas.edu return DrainState::Draining; 1647912Shestness@cs.utexas.edu } else { 1657912Shestness@cs.utexas.edu DPRINTF(Drain, "TableWalker free, no need to drain\n"); 1667912Shestness@cs.utexas.edu return DrainState::Drained; 1677912Shestness@cs.utexas.edu } 1687912Shestness@cs.utexas.edu} 1697912Shestness@cs.utexas.edu 1707912Shestness@cs.utexas.eduvoid 1717912Shestness@cs.utexas.eduTableWalker::drainResume() 1727912Shestness@cs.utexas.edu{ 1738975Sandreas.hansson@arm.com if (params()->sys->isTimingMode() && currState) { 1747912Shestness@cs.utexas.edu delete currState; 1757912Shestness@cs.utexas.edu currState = NULL; 1768922Swilliam.wang@arm.com pendingChange(); 1778922Swilliam.wang@arm.com } 1787912Shestness@cs.utexas.edu} 1797912Shestness@cs.utexas.edu 1808922Swilliam.wang@arm.comFault 1817912Shestness@cs.utexas.eduTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 1828922Swilliam.wang@arm.com uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 1835245Sgblack@eecs.umich.edu TLB::Translation *_trans, bool _timing, bool _functional, 1845245Sgblack@eecs.umich.edu bool secure, TLB::ArmTranslationType tranType, 1855245Sgblack@eecs.umich.edu bool _stage2Req) 1867912Shestness@cs.utexas.edu{ 1877912Shestness@cs.utexas.edu assert(!(_functional && _timing)); 1887912Shestness@cs.utexas.edu ++statWalks; 1897912Shestness@cs.utexas.edu 1907912Shestness@cs.utexas.edu WalkerState *savedCurrState = NULL; 1917912Shestness@cs.utexas.edu 1927912Shestness@cs.utexas.edu if (!currState && !_functional) { 1937912Shestness@cs.utexas.edu // For atomic mode, a new WalkerState instance should be only created 1947912Shestness@cs.utexas.edu // once per TLB. For timing mode, a new instance is generated for every 1957912Shestness@cs.utexas.edu // TLB miss. 1967912Shestness@cs.utexas.edu DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1977912Shestness@cs.utexas.edu 1987912Shestness@cs.utexas.edu currState = new WalkerState(); 1997912Shestness@cs.utexas.edu currState->tableWalker = this; 2007912Shestness@cs.utexas.edu } else if (_functional) { 2017912Shestness@cs.utexas.edu // If we are mixing functional mode with timing (or even 2027912Shestness@cs.utexas.edu // atomic), we need to to be careful and clean up after 2037912Shestness@cs.utexas.edu // ourselves to not risk getting into an inconsistent state. 2047912Shestness@cs.utexas.edu DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 2057912Shestness@cs.utexas.edu savedCurrState = currState; 2067912Shestness@cs.utexas.edu currState = new WalkerState(); 2077912Shestness@cs.utexas.edu currState->tableWalker = this; 2087912Shestness@cs.utexas.edu } else if (_timing) { 2097912Shestness@cs.utexas.edu // This is a translation that was completed and then faulted again 2107912Shestness@cs.utexas.edu // because some underlying parameters that affect the translation 2117912Shestness@cs.utexas.edu // changed out from under us (e.g. asid). It will either be a 2127912Shestness@cs.utexas.edu // misprediction, in which case nothing will happen or we'll use 2137912Shestness@cs.utexas.edu // this fault to re-execute the faulting instruction which should clean 2147912Shestness@cs.utexas.edu // up everything. 2157912Shestness@cs.utexas.edu if (currState->vaddr_tainted == _req->getVaddr()) { 2167912Shestness@cs.utexas.edu ++statSquashedBefore; 2177912Shestness@cs.utexas.edu return std::make_shared<ReExec>(); 2187912Shestness@cs.utexas.edu } 2197912Shestness@cs.utexas.edu } 2207912Shestness@cs.utexas.edu pendingChange(); 2217912Shestness@cs.utexas.edu 2227912Shestness@cs.utexas.edu currState->startTime = curTick(); 2237912Shestness@cs.utexas.edu currState->tc = _tc; 2247912Shestness@cs.utexas.edu // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 2257912Shestness@cs.utexas.edu // aarch32/translation/translation/AArch32.TranslateAddress dictates 2268953Sgblack@eecs.umich.edu // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 2277912Shestness@cs.utexas.edu currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || 2287912Shestness@cs.utexas.edu ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); 2297912Shestness@cs.utexas.edu currState->el = currEL(_tc); 2307912Shestness@cs.utexas.edu currState->transState = _trans; 2317912Shestness@cs.utexas.edu currState->req = _req; 2327912Shestness@cs.utexas.edu currState->fault = NoFault; 2337912Shestness@cs.utexas.edu currState->asid = _asid; 2347912Shestness@cs.utexas.edu currState->vmid = _vmid; 2357912Shestness@cs.utexas.edu currState->isHyp = _isHyp; 2367912Shestness@cs.utexas.edu currState->timing = _timing; 2377912Shestness@cs.utexas.edu currState->functional = _functional; 2387912Shestness@cs.utexas.edu currState->mode = _mode; 2397912Shestness@cs.utexas.edu currState->tranType = tranType; 2407912Shestness@cs.utexas.edu currState->isSecure = secure; 2417912Shestness@cs.utexas.edu currState->physAddrRange = physAddrRange; 2427912Shestness@cs.utexas.edu 2438953Sgblack@eecs.umich.edu /** @todo These should be cached or grabbed from cached copies in 2447912Shestness@cs.utexas.edu the TLB, all these miscreg reads are expensive */ 2457912Shestness@cs.utexas.edu currState->vaddr_tainted = currState->req->getVaddr(); 2467912Shestness@cs.utexas.edu if (currState->aarch64) 2477912Shestness@cs.utexas.edu currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 2487912Shestness@cs.utexas.edu currState->tc, currState->el); 2497912Shestness@cs.utexas.edu else 2507912Shestness@cs.utexas.edu currState->vaddr = currState->vaddr_tainted; 2517912Shestness@cs.utexas.edu 2527912Shestness@cs.utexas.edu if (currState->aarch64) { 2537912Shestness@cs.utexas.edu if (isStage2) { 2547912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 2557912Shestness@cs.utexas.edu currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 2567912Shestness@cs.utexas.edu } else switch (currState->el) { 2577912Shestness@cs.utexas.edu case EL0: 2587912Shestness@cs.utexas.edu case EL1: 2597912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 2607912Shestness@cs.utexas.edu currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 2617912Shestness@cs.utexas.edu break; 2627912Shestness@cs.utexas.edu case EL2: 2637912Shestness@cs.utexas.edu assert(_haveVirtualization); 2647912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 2657912Shestness@cs.utexas.edu currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 2667912Shestness@cs.utexas.edu break; 2677912Shestness@cs.utexas.edu case EL3: 2687912Shestness@cs.utexas.edu assert(haveSecurity); 2697912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 2707912Shestness@cs.utexas.edu currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 2717912Shestness@cs.utexas.edu break; 2727912Shestness@cs.utexas.edu default: 2737912Shestness@cs.utexas.edu panic("Invalid exception level"); 2747912Shestness@cs.utexas.edu break; 2757912Shestness@cs.utexas.edu } 2767912Shestness@cs.utexas.edu currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 2777912Shestness@cs.utexas.edu } else { 2787912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 2797912Shestness@cs.utexas.edu MISCREG_SCTLR, currState->tc, !currState->isSecure)); 2807912Shestness@cs.utexas.edu currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 2817912Shestness@cs.utexas.edu MISCREG_TTBCR, currState->tc, !currState->isSecure)); 2827912Shestness@cs.utexas.edu currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 2837912Shestness@cs.utexas.edu currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 2847912Shestness@cs.utexas.edu currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 2857912Shestness@cs.utexas.edu } 2867912Shestness@cs.utexas.edu sctlr = currState->sctlr; 2877912Shestness@cs.utexas.edu 2887912Shestness@cs.utexas.edu currState->isFetch = (currState->mode == TLB::Execute); 2897912Shestness@cs.utexas.edu currState->isWrite = (currState->mode == TLB::Write); 2907912Shestness@cs.utexas.edu 2917912Shestness@cs.utexas.edu statRequestOrigin[REQUESTED][currState->isFetch]++; 2927912Shestness@cs.utexas.edu 2937912Shestness@cs.utexas.edu // We only do a second stage of translation if we're not secure, or in 2947912Shestness@cs.utexas.edu // hyp mode, the second stage MMU is enabled, and this table walker 2957912Shestness@cs.utexas.edu // instance is the first stage. 2967912Shestness@cs.utexas.edu // TODO: fix setting of doingStage2 for timing mode 2977912Shestness@cs.utexas.edu currState->doingStage2 = false; 2987912Shestness@cs.utexas.edu currState->stage2Req = _stage2Req && !isStage2; 2997912Shestness@cs.utexas.edu 3007912Shestness@cs.utexas.edu bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 3017912Shestness@cs.utexas.edu longDescFormatInUse(currState->tc); 3027912Shestness@cs.utexas.edu 3037912Shestness@cs.utexas.edu if (long_desc_format) { 3047912Shestness@cs.utexas.edu // Helper variables used for hierarchical permissions 3057912Shestness@cs.utexas.edu currState->secureLookup = currState->isSecure; 3067912Shestness@cs.utexas.edu currState->rwTable = true; 3077912Shestness@cs.utexas.edu currState->userTable = true; 3087912Shestness@cs.utexas.edu currState->xnTable = false; 3097912Shestness@cs.utexas.edu currState->pxnTable = false; 3107912Shestness@cs.utexas.edu 3117912Shestness@cs.utexas.edu ++statWalksLongDescriptor; 3127912Shestness@cs.utexas.edu } else { 3138953Sgblack@eecs.umich.edu ++statWalksShortDescriptor; 3147912Shestness@cs.utexas.edu } 3157912Shestness@cs.utexas.edu 3167912Shestness@cs.utexas.edu if (!currState->timing) { 3177912Shestness@cs.utexas.edu Fault fault = NoFault; 3187912Shestness@cs.utexas.edu if (currState->aarch64) 3197912Shestness@cs.utexas.edu fault = processWalkAArch64(); 3208953Sgblack@eecs.umich.edu else if (long_desc_format) 3217912Shestness@cs.utexas.edu fault = processWalkLPAE(); 3227912Shestness@cs.utexas.edu else 3237912Shestness@cs.utexas.edu fault = processWalk(); 3247912Shestness@cs.utexas.edu 3257912Shestness@cs.utexas.edu // If this was a functional non-timing access restore state to 3267912Shestness@cs.utexas.edu // how we found it. 3277912Shestness@cs.utexas.edu if (currState->functional) { 3287912Shestness@cs.utexas.edu delete currState; 3297912Shestness@cs.utexas.edu currState = savedCurrState; 3307912Shestness@cs.utexas.edu } 3317912Shestness@cs.utexas.edu return fault; 3327912Shestness@cs.utexas.edu } 3337912Shestness@cs.utexas.edu 3347912Shestness@cs.utexas.edu if (pending || pendingQueue.size()) { 3357912Shestness@cs.utexas.edu pendingQueue.push_back(currState); 3367912Shestness@cs.utexas.edu currState = NULL; 3377912Shestness@cs.utexas.edu pendingChange(); 3387912Shestness@cs.utexas.edu } else { 3397912Shestness@cs.utexas.edu pending = true; 3407912Shestness@cs.utexas.edu pendingChange(); 3417912Shestness@cs.utexas.edu if (currState->aarch64) 3427912Shestness@cs.utexas.edu return processWalkAArch64(); 3437912Shestness@cs.utexas.edu else if (long_desc_format) 3447912Shestness@cs.utexas.edu return processWalkLPAE(); 3457912Shestness@cs.utexas.edu else 3467912Shestness@cs.utexas.edu return processWalk(); 3477912Shestness@cs.utexas.edu } 3487912Shestness@cs.utexas.edu 3497912Shestness@cs.utexas.edu return NoFault; 3507912Shestness@cs.utexas.edu} 3517912Shestness@cs.utexas.edu 3527912Shestness@cs.utexas.eduvoid 3537912Shestness@cs.utexas.eduTableWalker::processWalkWrapper() 3547912Shestness@cs.utexas.edu{ 3557912Shestness@cs.utexas.edu assert(!currState); 3567912Shestness@cs.utexas.edu assert(pendingQueue.size()); 3577912Shestness@cs.utexas.edu pendingChange(); 3587912Shestness@cs.utexas.edu currState = pendingQueue.front(); 3597912Shestness@cs.utexas.edu 3607912Shestness@cs.utexas.edu ExceptionLevel target_el = EL0; 3617912Shestness@cs.utexas.edu if (currState->aarch64) 3627912Shestness@cs.utexas.edu target_el = currEL(currState->tc); 3637912Shestness@cs.utexas.edu else 3647912Shestness@cs.utexas.edu target_el = EL1; 3657912Shestness@cs.utexas.edu 3667912Shestness@cs.utexas.edu // Check if a previous walk filled this request already 3677912Shestness@cs.utexas.edu // @TODO Should this always be the TLB or should we look in the stage2 TLB? 3687912Shestness@cs.utexas.edu TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 3697912Shestness@cs.utexas.edu currState->vmid, currState->isHyp, currState->isSecure, true, false, 3707912Shestness@cs.utexas.edu target_el); 3717912Shestness@cs.utexas.edu 3727912Shestness@cs.utexas.edu // Check if we still need to have a walk for this request. If the requesting 3737912Shestness@cs.utexas.edu // instruction has been squashed, or a previous walk has filled the TLB with 3747912Shestness@cs.utexas.edu // a match, we just want to get rid of the walk. The latter could happen 3758953Sgblack@eecs.umich.edu // when there are multiple outstanding misses to a single page and a 3767912Shestness@cs.utexas.edu // previous request has been successfully translated. 3777912Shestness@cs.utexas.edu if (!currState->transState->squashed() && !te) { 3787912Shestness@cs.utexas.edu // We've got a valid request, lets process it 3797912Shestness@cs.utexas.edu pending = true; 3807912Shestness@cs.utexas.edu pendingQueue.pop_front(); 3818953Sgblack@eecs.umich.edu // Keep currState in case one of the processWalk... calls NULLs it 3827912Shestness@cs.utexas.edu WalkerState *curr_state_copy = currState; 3837912Shestness@cs.utexas.edu Fault f; 3847912Shestness@cs.utexas.edu if (currState->aarch64) 3857912Shestness@cs.utexas.edu f = processWalkAArch64(); 3867912Shestness@cs.utexas.edu else if (longDescFormatInUse(currState->tc) || 3877912Shestness@cs.utexas.edu currState->isHyp || isStage2) 3887912Shestness@cs.utexas.edu f = processWalkLPAE(); 3897912Shestness@cs.utexas.edu else 3907912Shestness@cs.utexas.edu f = processWalk(); 3917912Shestness@cs.utexas.edu 3927912Shestness@cs.utexas.edu if (f != NoFault) { 3937912Shestness@cs.utexas.edu curr_state_copy->transState->finish(f, curr_state_copy->req, 3947912Shestness@cs.utexas.edu curr_state_copy->tc, curr_state_copy->mode); 3957912Shestness@cs.utexas.edu 3967912Shestness@cs.utexas.edu delete curr_state_copy; 3977912Shestness@cs.utexas.edu } 3987912Shestness@cs.utexas.edu return; 3997912Shestness@cs.utexas.edu } 4007912Shestness@cs.utexas.edu 4017912Shestness@cs.utexas.edu 4027912Shestness@cs.utexas.edu // If the instruction that we were translating for has been 4037912Shestness@cs.utexas.edu // squashed we shouldn't bother. 4047912Shestness@cs.utexas.edu unsigned num_squashed = 0; 4057912Shestness@cs.utexas.edu ThreadContext *tc = currState->tc; 4067912Shestness@cs.utexas.edu while ((num_squashed < numSquashable) && currState && 4077912Shestness@cs.utexas.edu (currState->transState->squashed() || te)) { 4087912Shestness@cs.utexas.edu pendingQueue.pop_front(); 4097912Shestness@cs.utexas.edu num_squashed++; 4107912Shestness@cs.utexas.edu statSquashedBefore++; 4117912Shestness@cs.utexas.edu 4127912Shestness@cs.utexas.edu DPRINTF(TLB, "Squashing table walk for address %#x\n", 4137912Shestness@cs.utexas.edu currState->vaddr_tainted); 4147912Shestness@cs.utexas.edu 4157912Shestness@cs.utexas.edu if (currState->transState->squashed()) { 4167912Shestness@cs.utexas.edu // finish the translation which will delete the translation object 4177912Shestness@cs.utexas.edu currState->transState->finish( 4187912Shestness@cs.utexas.edu std::make_shared<UnimpFault>("Squashed Inst"), 4197912Shestness@cs.utexas.edu currState->req, currState->tc, currState->mode); 4207912Shestness@cs.utexas.edu } else { 4217912Shestness@cs.utexas.edu // translate the request now that we know it will work 4227912Shestness@cs.utexas.edu statWalkServiceTime.sample(curTick() - currState->startTime); 4237912Shestness@cs.utexas.edu tlb->translateTiming(currState->req, currState->tc, 4247912Shestness@cs.utexas.edu currState->transState, currState->mode); 4258953Sgblack@eecs.umich.edu 4267912Shestness@cs.utexas.edu } 4277912Shestness@cs.utexas.edu 4287912Shestness@cs.utexas.edu // delete the current request 4297912Shestness@cs.utexas.edu delete currState; 4307912Shestness@cs.utexas.edu 4317912Shestness@cs.utexas.edu // peak at the next one 4328953Sgblack@eecs.umich.edu if (pendingQueue.size()) { 4337912Shestness@cs.utexas.edu currState = pendingQueue.front(); 4347912Shestness@cs.utexas.edu te = tlb->lookup(currState->vaddr, currState->asid, 4357912Shestness@cs.utexas.edu currState->vmid, currState->isHyp, currState->isSecure, true, 4367912Shestness@cs.utexas.edu false, target_el); 4377912Shestness@cs.utexas.edu } else { 4387912Shestness@cs.utexas.edu // Terminate the loop, nothing more to do 4397912Shestness@cs.utexas.edu currState = NULL; 4407912Shestness@cs.utexas.edu } 4417912Shestness@cs.utexas.edu } 4427912Shestness@cs.utexas.edu pendingChange(); 4437912Shestness@cs.utexas.edu 4447912Shestness@cs.utexas.edu // if we still have pending translations, schedule more work 4457912Shestness@cs.utexas.edu nextWalk(tc); 4467912Shestness@cs.utexas.edu currState = NULL; 4477912Shestness@cs.utexas.edu} 4487912Shestness@cs.utexas.edu 4497912Shestness@cs.utexas.eduFault 4507912Shestness@cs.utexas.eduTableWalker::processWalk() 4517912Shestness@cs.utexas.edu{ 4527912Shestness@cs.utexas.edu Addr ttbr = 0; 4537912Shestness@cs.utexas.edu 4547912Shestness@cs.utexas.edu // If translation isn't enabled, we shouldn't be here 4558953Sgblack@eecs.umich.edu assert(currState->sctlr.m || isStage2); 4567912Shestness@cs.utexas.edu 4577912Shestness@cs.utexas.edu DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 4587912Shestness@cs.utexas.edu currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 4597912Shestness@cs.utexas.edu 32 - currState->ttbcr.n)); 4607912Shestness@cs.utexas.edu 4617912Shestness@cs.utexas.edu statWalkWaitTime.sample(curTick() - currState->startTime); 4627912Shestness@cs.utexas.edu 4637912Shestness@cs.utexas.edu if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 4647912Shestness@cs.utexas.edu 32 - currState->ttbcr.n)) { 4657912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR0\n"); 4667912Shestness@cs.utexas.edu // Check if table walk is allowed when Security Extensions are enabled 4677912Shestness@cs.utexas.edu if (haveSecurity && currState->ttbcr.pd0) { 4687912Shestness@cs.utexas.edu if (currState->isFetch) 4697912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 4707912Shestness@cs.utexas.edu currState->vaddr_tainted, 4717912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 4727912Shestness@cs.utexas.edu isStage2, 4737912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4747912Shestness@cs.utexas.edu else 4757912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 4767912Shestness@cs.utexas.edu currState->vaddr_tainted, 4777912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, currState->isWrite, 4787912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, isStage2, 4797912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4807912Shestness@cs.utexas.edu } 4817912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 4827912Shestness@cs.utexas.edu MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4837912Shestness@cs.utexas.edu } else { 4847912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR1\n"); 4857912Shestness@cs.utexas.edu // Check if table walk is allowed when Security Extensions are enabled 4867912Shestness@cs.utexas.edu if (haveSecurity && currState->ttbcr.pd1) { 4877912Shestness@cs.utexas.edu if (currState->isFetch) 4887912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 4897912Shestness@cs.utexas.edu currState->vaddr_tainted, 4907912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 4917912Shestness@cs.utexas.edu isStage2, 4927912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4938832SAli.Saidi@ARM.com else 4948949Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 4957912Shestness@cs.utexas.edu currState->vaddr_tainted, 4967912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, currState->isWrite, 4977912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, isStage2, 4987912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4997912Shestness@cs.utexas.edu } 5007912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 5017912Shestness@cs.utexas.edu MISCREG_TTBR1, currState->tc, !currState->isSecure)); 5028949Sandreas.hansson@arm.com currState->ttbcr.n = 0; 5037912Shestness@cs.utexas.edu } 5047912Shestness@cs.utexas.edu 5057912Shestness@cs.utexas.edu Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 5067912Shestness@cs.utexas.edu (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 5077912Shestness@cs.utexas.edu DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 5087912Shestness@cs.utexas.edu currState->isSecure ? "s" : "ns"); 5097912Shestness@cs.utexas.edu 5107912Shestness@cs.utexas.edu // Trickbox address check 5117912Shestness@cs.utexas.edu Fault f; 5127912Shestness@cs.utexas.edu f = testWalk(l1desc_addr, sizeof(uint32_t), 5137912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, L1); 5147912Shestness@cs.utexas.edu if (f) { 5157912Shestness@cs.utexas.edu DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5167912Shestness@cs.utexas.edu if (currState->timing) { 5177912Shestness@cs.utexas.edu pending = false; 5187912Shestness@cs.utexas.edu nextWalk(currState->tc); 5197912Shestness@cs.utexas.edu currState = NULL; 5207912Shestness@cs.utexas.edu } else { 5217912Shestness@cs.utexas.edu currState->tc = NULL; 5227912Shestness@cs.utexas.edu currState->req = NULL; 5237912Shestness@cs.utexas.edu } 5247912Shestness@cs.utexas.edu return f; 5257912Shestness@cs.utexas.edu } 5267912Shestness@cs.utexas.edu 5277912Shestness@cs.utexas.edu Request::Flags flag = Request::PT_WALK; 5287912Shestness@cs.utexas.edu if (currState->sctlr.c == 0) { 5297912Shestness@cs.utexas.edu flag.set(Request::UNCACHEABLE); 5307912Shestness@cs.utexas.edu } 5317912Shestness@cs.utexas.edu 5327912Shestness@cs.utexas.edu if (currState->isSecure) { 5337912Shestness@cs.utexas.edu flag.set(Request::SECURE); 5347912Shestness@cs.utexas.edu } 5357912Shestness@cs.utexas.edu 5367912Shestness@cs.utexas.edu bool delayed; 5377912Shestness@cs.utexas.edu delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 5387912Shestness@cs.utexas.edu sizeof(uint32_t), flag, L1, &doL1DescEvent, 5397912Shestness@cs.utexas.edu &TableWalker::doL1Descriptor); 5407912Shestness@cs.utexas.edu if (!delayed) { 5417912Shestness@cs.utexas.edu f = currState->fault; 5427912Shestness@cs.utexas.edu } 5437912Shestness@cs.utexas.edu 5447912Shestness@cs.utexas.edu return f; 5457912Shestness@cs.utexas.edu} 5467912Shestness@cs.utexas.edu 5477912Shestness@cs.utexas.eduFault 5487912Shestness@cs.utexas.eduTableWalker::processWalkLPAE() 5497912Shestness@cs.utexas.edu{ 5507912Shestness@cs.utexas.edu Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 5517912Shestness@cs.utexas.edu int tsz, n; 5527912Shestness@cs.utexas.edu LookupLevel start_lookup_level = L1; 5537912Shestness@cs.utexas.edu 5547912Shestness@cs.utexas.edu DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 5557912Shestness@cs.utexas.edu currState->vaddr_tainted, currState->ttbcr); 5567912Shestness@cs.utexas.edu 5577912Shestness@cs.utexas.edu statWalkWaitTime.sample(curTick() - currState->startTime); 5587912Shestness@cs.utexas.edu 5597912Shestness@cs.utexas.edu Request::Flags flag = Request::PT_WALK; 5607912Shestness@cs.utexas.edu if (currState->isSecure) 5617912Shestness@cs.utexas.edu flag.set(Request::SECURE); 5627912Shestness@cs.utexas.edu 5638949Sandreas.hansson@arm.com // work out which base address register to use, if in hyp mode we always 5648949Sandreas.hansson@arm.com // use HTTBR 5658949Sandreas.hansson@arm.com if (isStage2) { 5667912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 5677912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 5687912Shestness@cs.utexas.edu tsz = sext<4>(currState->vtcr.t0sz); 5697912Shestness@cs.utexas.edu start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 5707912Shestness@cs.utexas.edu } else if (currState->isHyp) { 5717912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 5728948Sandreas.hansson@arm.com ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 5738948Sandreas.hansson@arm.com tsz = currState->htcr.t0sz; 5747912Shestness@cs.utexas.edu } else { 5757912Shestness@cs.utexas.edu assert(longDescFormatInUse(currState->tc)); 5767912Shestness@cs.utexas.edu 5777912Shestness@cs.utexas.edu // Determine boundaries of TTBR0/1 regions 5787912Shestness@cs.utexas.edu if (currState->ttbcr.t0sz) 5797912Shestness@cs.utexas.edu ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 5807912Shestness@cs.utexas.edu else if (currState->ttbcr.t1sz) 5817912Shestness@cs.utexas.edu ttbr0_max = (1ULL << 32) - 5827912Shestness@cs.utexas.edu (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 5837912Shestness@cs.utexas.edu else 5847912Shestness@cs.utexas.edu ttbr0_max = (1ULL << 32) - 1; 5857912Shestness@cs.utexas.edu if (currState->ttbcr.t1sz) 5867912Shestness@cs.utexas.edu ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 5877912Shestness@cs.utexas.edu else 5887912Shestness@cs.utexas.edu ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 5897912Shestness@cs.utexas.edu 5907912Shestness@cs.utexas.edu // The following code snippet selects the appropriate translation table base 5917912Shestness@cs.utexas.edu // address (TTBR0 or TTBR1) and the appropriate starting lookup level 5927912Shestness@cs.utexas.edu // depending on the address range supported by the translation table (ARM 5937912Shestness@cs.utexas.edu // ARM issue C B3.6.4) 5947912Shestness@cs.utexas.edu if (currState->vaddr <= ttbr0_max) { 5957912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 5967912Shestness@cs.utexas.edu // Check if table walk is allowed 5977912Shestness@cs.utexas.edu if (currState->ttbcr.epd0) { 5987912Shestness@cs.utexas.edu if (currState->isFetch) 5997912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 6007912Shestness@cs.utexas.edu currState->vaddr_tainted, 6017912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6027912Shestness@cs.utexas.edu isStage2, 6037912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6047912Shestness@cs.utexas.edu else 6057912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 6067912Shestness@cs.utexas.edu currState->vaddr_tainted, 6077912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, 6087912Shestness@cs.utexas.edu currState->isWrite, 6097912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6107912Shestness@cs.utexas.edu isStage2, 6117912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6127912Shestness@cs.utexas.edu } 6137912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 6147912Shestness@cs.utexas.edu MISCREG_TTBR0, currState->tc, !currState->isSecure)); 6157912Shestness@cs.utexas.edu tsz = currState->ttbcr.t0sz; 6168948Sandreas.hansson@arm.com if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 6177912Shestness@cs.utexas.edu start_lookup_level = L2; 6187912Shestness@cs.utexas.edu } else if (currState->vaddr >= ttbr1_min) { 6197912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 6207912Shestness@cs.utexas.edu // Check if table walk is allowed 6217912Shestness@cs.utexas.edu if (currState->ttbcr.epd1) { 6227912Shestness@cs.utexas.edu if (currState->isFetch) 6237912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 6247912Shestness@cs.utexas.edu currState->vaddr_tainted, 6257912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6267912Shestness@cs.utexas.edu isStage2, 6277912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6287912Shestness@cs.utexas.edu else 6297912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 6307912Shestness@cs.utexas.edu currState->vaddr_tainted, 6317912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, 6327912Shestness@cs.utexas.edu currState->isWrite, 6337912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6347912Shestness@cs.utexas.edu isStage2, 6355245Sgblack@eecs.umich.edu ArmFault::LpaeTran); 6365245Sgblack@eecs.umich.edu } 6375245Sgblack@eecs.umich.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 6385245Sgblack@eecs.umich.edu MISCREG_TTBR1, currState->tc, !currState->isSecure)); 6395245Sgblack@eecs.umich.edu tsz = currState->ttbcr.t1sz; 6405245Sgblack@eecs.umich.edu if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 6415245Sgblack@eecs.umich.edu start_lookup_level = L2; 6425897Sgblack@eecs.umich.edu } else { 6435897Sgblack@eecs.umich.edu // Out of boundaries -> translation fault 6445897Sgblack@eecs.umich.edu if (currState->isFetch) 6457912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 6465245Sgblack@eecs.umich.edu currState->vaddr_tainted, 6475897Sgblack@eecs.umich.edu ArmFault::TranslationLL + L1, 6485897Sgblack@eecs.umich.edu isStage2, 6495245Sgblack@eecs.umich.edu ArmFault::LpaeTran); 6505245Sgblack@eecs.umich.edu else 6515245Sgblack@eecs.umich.edu return std::make_shared<DataAbort>( 6525245Sgblack@eecs.umich.edu currState->vaddr_tainted, 6535245Sgblack@eecs.umich.edu TlbEntry::DomainType::NoAccess, 6545245Sgblack@eecs.umich.edu currState->isWrite, ArmFault::TranslationLL + L1, 6555897Sgblack@eecs.umich.edu isStage2, ArmFault::LpaeTran); 6565897Sgblack@eecs.umich.edu } 6577912Shestness@cs.utexas.edu 6585245Sgblack@eecs.umich.edu } 6595897Sgblack@eecs.umich.edu 6605897Sgblack@eecs.umich.edu // Perform lookup (ARM ARM issue C B3.6.6) 6615245Sgblack@eecs.umich.edu if (start_lookup_level == L1) { 6625245Sgblack@eecs.umich.edu n = 5 - tsz; 6635245Sgblack@eecs.umich.edu desc_addr = mbits(ttbr, 39, n) | 6645245Sgblack@eecs.umich.edu (bits(currState->vaddr, n + 26, 30) << 3); 6655245Sgblack@eecs.umich.edu DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 6667912Shestness@cs.utexas.edu desc_addr, currState->isSecure ? "s" : "ns"); 6677912Shestness@cs.utexas.edu } else { 6685245Sgblack@eecs.umich.edu // Skip first-level lookup 6697912Shestness@cs.utexas.edu n = (tsz >= 2 ? 14 - tsz : 12); 6707912Shestness@cs.utexas.edu desc_addr = mbits(ttbr, 39, n) | 6717912Shestness@cs.utexas.edu (bits(currState->vaddr, n + 17, 21) << 3); 6727912Shestness@cs.utexas.edu DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 6737912Shestness@cs.utexas.edu desc_addr, currState->isSecure ? "s" : "ns"); 6747912Shestness@cs.utexas.edu } 6757912Shestness@cs.utexas.edu 6767912Shestness@cs.utexas.edu // Trickbox address check 6777912Shestness@cs.utexas.edu Fault f = testWalk(desc_addr, sizeof(uint64_t), 6787912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, start_lookup_level); 6797912Shestness@cs.utexas.edu if (f) { 6807912Shestness@cs.utexas.edu DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 6817912Shestness@cs.utexas.edu if (currState->timing) { 6827912Shestness@cs.utexas.edu pending = false; 6837912Shestness@cs.utexas.edu nextWalk(currState->tc); 6847912Shestness@cs.utexas.edu currState = NULL; 6857912Shestness@cs.utexas.edu } else { 6867912Shestness@cs.utexas.edu currState->tc = NULL; 6877912Shestness@cs.utexas.edu currState->req = NULL; 6887912Shestness@cs.utexas.edu } 6895245Sgblack@eecs.umich.edu return f; 6905245Sgblack@eecs.umich.edu } 6915895Sgblack@eecs.umich.edu 6927912Shestness@cs.utexas.edu if (currState->sctlr.c == 0) { 6935895Sgblack@eecs.umich.edu flag.set(Request::UNCACHEABLE); 6945904Sgblack@eecs.umich.edu } 6955895Sgblack@eecs.umich.edu 6966023Snate@binkert.org currState->longDesc.lookupLevel = start_lookup_level; 6976023Snate@binkert.org currState->longDesc.aarch64 = false; 6986023Snate@binkert.org currState->longDesc.grainSize = Grain4KB; 6995895Sgblack@eecs.umich.edu 7005895Sgblack@eecs.umich.edu Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent 7017912Shestness@cs.utexas.edu : (Event *) &doL2LongDescEvent; 7025245Sgblack@eecs.umich.edu 7035245Sgblack@eecs.umich.edu bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 7045245Sgblack@eecs.umich.edu sizeof(uint64_t), flag, start_lookup_level, 7055245Sgblack@eecs.umich.edu event, &TableWalker::doLongDescriptor); 7065245Sgblack@eecs.umich.edu if (!delayed) { 7075245Sgblack@eecs.umich.edu f = currState->fault; 708 } 709 710 return f; 711} 712 713unsigned 714TableWalker::adjustTableSizeAArch64(unsigned tsz) 715{ 716 if (tsz < 25) 717 return 25; 718 if (tsz > 48) 719 return 48; 720 return tsz; 721} 722 723bool 724TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 725{ 726 return (currPhysAddrRange != MaxPhysAddrRange && 727 bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 728} 729 730Fault 731TableWalker::processWalkAArch64() 732{ 733 assert(currState->aarch64); 734 735 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 736 currState->vaddr_tainted, currState->tcr); 737 738 static const GrainSize GrainMapDefault[] = 739 { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 740 static const GrainSize GrainMap_EL1_tg1[] = 741 { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 742 743 statWalkWaitTime.sample(curTick() - currState->startTime); 744 745 // Determine TTBR, table size, granule size and phys. address range 746 Addr ttbr = 0; 747 int tsz = 0, ps = 0; 748 GrainSize tg = Grain4KB; // grain size computed from tg* field 749 bool fault = false; 750 751 LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 752 753 switch (currState->el) { 754 case EL0: 755 case EL1: 756 if (isStage2) { 757 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 758 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 759 tsz = 64 - currState->vtcr.t0sz64; 760 tg = GrainMapDefault[currState->vtcr.tg0]; 761 // ARM DDI 0487A.f D7-2148 762 // The starting level of stage 2 translation depends on 763 // VTCR_EL2.SL0 and VTCR_EL2.TG0 764 LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 765 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 766 static const LookupLevel SLL[] = { 767 L2, L3, L3, __, // sl0 == 0 768 L1, L2, L2, __, // sl0 == 1, etc. 769 L0, L1, L1, __, 770 __, __, __, __ 771 }; 772 start_lookup_level = SLL[sl_tg]; 773 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 774 "Cannot discern lookup level from vtcr.{sl0,tg0}"); 775 } else switch (bits(currState->vaddr, 63,48)) { 776 case 0: 777 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 778 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 779 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 780 tg = GrainMapDefault[currState->tcr.tg0]; 781 if (bits(currState->vaddr, 63, tsz) != 0x0 || 782 currState->tcr.epd0) 783 fault = true; 784 break; 785 case 0xffff: 786 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 787 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 788 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 789 tg = GrainMap_EL1_tg1[currState->tcr.tg1]; 790 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 791 currState->tcr.epd1) 792 fault = true; 793 break; 794 default: 795 // top two bytes must be all 0s or all 1s, else invalid addr 796 fault = true; 797 } 798 ps = currState->tcr.ips; 799 break; 800 case EL2: 801 case EL3: 802 switch(bits(currState->vaddr, 63,48)) { 803 case 0: 804 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 805 if (currState->el == EL2) 806 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 807 else 808 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 809 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 810 tg = GrainMapDefault[currState->tcr.tg0]; 811 break; 812 default: 813 // invalid addr if top two bytes are not all 0s 814 fault = true; 815 } 816 ps = currState->tcr.ips; 817 break; 818 } 819 820 if (fault) { 821 Fault f; 822 if (currState->isFetch) 823 f = std::make_shared<PrefetchAbort>( 824 currState->vaddr_tainted, 825 ArmFault::TranslationLL + L0, isStage2, 826 ArmFault::LpaeTran); 827 else 828 f = std::make_shared<DataAbort>( 829 currState->vaddr_tainted, 830 TlbEntry::DomainType::NoAccess, 831 currState->isWrite, 832 ArmFault::TranslationLL + L0, 833 isStage2, ArmFault::LpaeTran); 834 835 if (currState->timing) { 836 pending = false; 837 nextWalk(currState->tc); 838 currState = NULL; 839 } else { 840 currState->tc = NULL; 841 currState->req = NULL; 842 } 843 return f; 844 845 } 846 847 if (tg == ReservedGrain) { 848 warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 849 "DEFINED behavior takes this to mean 4KB granules\n"); 850 tg = Grain4KB; 851 } 852 853 // Determine starting lookup level 854 // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 855 // in ARM DDI 0487A. These table values correspond to the cascading tests 856 // to compute the lookup level and are of the form 857 // (grain_size + N*stride), for N = {1, 2, 3}. 858 // A value of 64 will never succeed and a value of 0 will always succeed. 859 if (start_lookup_level == MAX_LOOKUP_LEVELS) { 860 struct GrainMap { 861 GrainSize grain_size; 862 unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 863 }; 864 static const GrainMap GM[] = { 865 { Grain4KB, { 39, 30, 0, 0 } }, 866 { Grain16KB, { 47, 36, 25, 0 } }, 867 { Grain64KB, { 64, 42, 29, 0 } } 868 }; 869 870 const unsigned *lookup = NULL; // points to a lookup_level_cutoff 871 872 for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 873 if (tg == GM[i].grain_size) { 874 lookup = GM[i].lookup_level_cutoff; 875 break; 876 } 877 } 878 assert(lookup); 879 880 for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 881 if (tsz > lookup[L]) { 882 start_lookup_level = (LookupLevel) L; 883 break; 884 } 885 } 886 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 887 "Table walker couldn't find lookup level\n"); 888 } 889 890 int stride = tg - 3; 891 892 // Determine table base address 893 int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 894 Addr base_addr = mbits(ttbr, 47, base_addr_lo); 895 896 // Determine physical address size and raise an Address Size Fault if 897 // necessary 898 int pa_range = decodePhysAddrRange64(ps); 899 // Clamp to lower limit 900 if (pa_range > physAddrRange) 901 currState->physAddrRange = physAddrRange; 902 else 903 currState->physAddrRange = pa_range; 904 if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 905 DPRINTF(TLB, "Address size fault before any lookup\n"); 906 Fault f; 907 if (currState->isFetch) 908 f = std::make_shared<PrefetchAbort>( 909 currState->vaddr_tainted, 910 ArmFault::AddressSizeLL + start_lookup_level, 911 isStage2, 912 ArmFault::LpaeTran); 913 else 914 f = std::make_shared<DataAbort>( 915 currState->vaddr_tainted, 916 TlbEntry::DomainType::NoAccess, 917 currState->isWrite, 918 ArmFault::AddressSizeLL + start_lookup_level, 919 isStage2, 920 ArmFault::LpaeTran); 921 922 923 if (currState->timing) { 924 pending = false; 925 nextWalk(currState->tc); 926 currState = NULL; 927 } else { 928 currState->tc = NULL; 929 currState->req = NULL; 930 } 931 return f; 932 933 } 934 935 // Determine descriptor address 936 Addr desc_addr = base_addr | 937 (bits(currState->vaddr, tsz - 1, 938 stride * (3 - start_lookup_level) + tg) << 3); 939 940 // Trickbox address check 941 Fault f = testWalk(desc_addr, sizeof(uint64_t), 942 TlbEntry::DomainType::NoAccess, start_lookup_level); 943 if (f) { 944 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 945 if (currState->timing) { 946 pending = false; 947 nextWalk(currState->tc); 948 currState = NULL; 949 } else { 950 currState->tc = NULL; 951 currState->req = NULL; 952 } 953 return f; 954 } 955 956 Request::Flags flag = Request::PT_WALK; 957 if (currState->sctlr.c == 0) { 958 flag.set(Request::UNCACHEABLE); 959 } 960 961 if (currState->isSecure) { 962 flag.set(Request::SECURE); 963 } 964 965 currState->longDesc.lookupLevel = start_lookup_level; 966 currState->longDesc.aarch64 = true; 967 currState->longDesc.grainSize = tg; 968 969 if (currState->timing) { 970 Event *event; 971 switch (start_lookup_level) { 972 case L0: 973 event = (Event *) &doL0LongDescEvent; 974 break; 975 case L1: 976 event = (Event *) &doL1LongDescEvent; 977 break; 978 case L2: 979 event = (Event *) &doL2LongDescEvent; 980 break; 981 case L3: 982 event = (Event *) &doL3LongDescEvent; 983 break; 984 default: 985 panic("Invalid table lookup level"); 986 break; 987 } 988 port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 989 event, (uint8_t*) &currState->longDesc.data, 990 currState->tc->getCpuPtr()->clockPeriod(), flag); 991 DPRINTF(TLBVerbose, 992 "Adding to walker fifo: queue size before adding: %d\n", 993 stateQueues[start_lookup_level].size()); 994 stateQueues[start_lookup_level].push_back(currState); 995 currState = NULL; 996 } else { 997 fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 998 sizeof(uint64_t), flag, -1, NULL, 999 &TableWalker::doLongDescriptor); 1000 f = currState->fault; 1001 } 1002 1003 return f; 1004} 1005 1006void 1007TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 1008 uint8_t texcb, bool s) 1009{ 1010 // Note: tc and sctlr local variables are hiding tc and sctrl class 1011 // variables 1012 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1013 te.shareable = false; // default value 1014 te.nonCacheable = false; 1015 te.outerShareable = false; 1016 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 1017 switch(texcb) { 1018 case 0: // Stongly-ordered 1019 te.nonCacheable = true; 1020 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1021 te.shareable = true; 1022 te.innerAttrs = 1; 1023 te.outerAttrs = 0; 1024 break; 1025 case 1: // Shareable Device 1026 te.nonCacheable = true; 1027 te.mtype = TlbEntry::MemoryType::Device; 1028 te.shareable = true; 1029 te.innerAttrs = 3; 1030 te.outerAttrs = 0; 1031 break; 1032 case 2: // Outer and Inner Write-Through, no Write-Allocate 1033 te.mtype = TlbEntry::MemoryType::Normal; 1034 te.shareable = s; 1035 te.innerAttrs = 6; 1036 te.outerAttrs = bits(texcb, 1, 0); 1037 break; 1038 case 3: // Outer and Inner Write-Back, no Write-Allocate 1039 te.mtype = TlbEntry::MemoryType::Normal; 1040 te.shareable = s; 1041 te.innerAttrs = 7; 1042 te.outerAttrs = bits(texcb, 1, 0); 1043 break; 1044 case 4: // Outer and Inner Non-cacheable 1045 te.nonCacheable = true; 1046 te.mtype = TlbEntry::MemoryType::Normal; 1047 te.shareable = s; 1048 te.innerAttrs = 0; 1049 te.outerAttrs = bits(texcb, 1, 0); 1050 break; 1051 case 5: // Reserved 1052 panic("Reserved texcb value!\n"); 1053 break; 1054 case 6: // Implementation Defined 1055 panic("Implementation-defined texcb value!\n"); 1056 break; 1057 case 7: // Outer and Inner Write-Back, Write-Allocate 1058 te.mtype = TlbEntry::MemoryType::Normal; 1059 te.shareable = s; 1060 te.innerAttrs = 5; 1061 te.outerAttrs = 1; 1062 break; 1063 case 8: // Non-shareable Device 1064 te.nonCacheable = true; 1065 te.mtype = TlbEntry::MemoryType::Device; 1066 te.shareable = false; 1067 te.innerAttrs = 3; 1068 te.outerAttrs = 0; 1069 break; 1070 case 9 ... 15: // Reserved 1071 panic("Reserved texcb value!\n"); 1072 break; 1073 case 16 ... 31: // Cacheable Memory 1074 te.mtype = TlbEntry::MemoryType::Normal; 1075 te.shareable = s; 1076 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 1077 te.nonCacheable = true; 1078 te.innerAttrs = bits(texcb, 1, 0); 1079 te.outerAttrs = bits(texcb, 3, 2); 1080 break; 1081 default: 1082 panic("More than 32 states for 5 bits?\n"); 1083 } 1084 } else { 1085 assert(tc); 1086 PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 1087 currState->tc, !currState->isSecure)); 1088 NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 1089 currState->tc, !currState->isSecure)); 1090 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 1091 uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 1092 switch(bits(texcb, 2,0)) { 1093 case 0: 1094 curr_tr = prrr.tr0; 1095 curr_ir = nmrr.ir0; 1096 curr_or = nmrr.or0; 1097 te.outerShareable = (prrr.nos0 == 0); 1098 break; 1099 case 1: 1100 curr_tr = prrr.tr1; 1101 curr_ir = nmrr.ir1; 1102 curr_or = nmrr.or1; 1103 te.outerShareable = (prrr.nos1 == 0); 1104 break; 1105 case 2: 1106 curr_tr = prrr.tr2; 1107 curr_ir = nmrr.ir2; 1108 curr_or = nmrr.or2; 1109 te.outerShareable = (prrr.nos2 == 0); 1110 break; 1111 case 3: 1112 curr_tr = prrr.tr3; 1113 curr_ir = nmrr.ir3; 1114 curr_or = nmrr.or3; 1115 te.outerShareable = (prrr.nos3 == 0); 1116 break; 1117 case 4: 1118 curr_tr = prrr.tr4; 1119 curr_ir = nmrr.ir4; 1120 curr_or = nmrr.or4; 1121 te.outerShareable = (prrr.nos4 == 0); 1122 break; 1123 case 5: 1124 curr_tr = prrr.tr5; 1125 curr_ir = nmrr.ir5; 1126 curr_or = nmrr.or5; 1127 te.outerShareable = (prrr.nos5 == 0); 1128 break; 1129 case 6: 1130 panic("Imp defined type\n"); 1131 case 7: 1132 curr_tr = prrr.tr7; 1133 curr_ir = nmrr.ir7; 1134 curr_or = nmrr.or7; 1135 te.outerShareable = (prrr.nos7 == 0); 1136 break; 1137 } 1138 1139 switch(curr_tr) { 1140 case 0: 1141 DPRINTF(TLBVerbose, "StronglyOrdered\n"); 1142 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1143 te.nonCacheable = true; 1144 te.innerAttrs = 1; 1145 te.outerAttrs = 0; 1146 te.shareable = true; 1147 break; 1148 case 1: 1149 DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 1150 prrr.ds1, prrr.ds0, s); 1151 te.mtype = TlbEntry::MemoryType::Device; 1152 te.nonCacheable = true; 1153 te.innerAttrs = 3; 1154 te.outerAttrs = 0; 1155 if (prrr.ds1 && s) 1156 te.shareable = true; 1157 if (prrr.ds0 && !s) 1158 te.shareable = true; 1159 break; 1160 case 2: 1161 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 1162 prrr.ns1, prrr.ns0, s); 1163 te.mtype = TlbEntry::MemoryType::Normal; 1164 if (prrr.ns1 && s) 1165 te.shareable = true; 1166 if (prrr.ns0 && !s) 1167 te.shareable = true; 1168 break; 1169 case 3: 1170 panic("Reserved type"); 1171 } 1172 1173 if (te.mtype == TlbEntry::MemoryType::Normal){ 1174 switch(curr_ir) { 1175 case 0: 1176 te.nonCacheable = true; 1177 te.innerAttrs = 0; 1178 break; 1179 case 1: 1180 te.innerAttrs = 5; 1181 break; 1182 case 2: 1183 te.innerAttrs = 6; 1184 break; 1185 case 3: 1186 te.innerAttrs = 7; 1187 break; 1188 } 1189 1190 switch(curr_or) { 1191 case 0: 1192 te.nonCacheable = true; 1193 te.outerAttrs = 0; 1194 break; 1195 case 1: 1196 te.outerAttrs = 1; 1197 break; 1198 case 2: 1199 te.outerAttrs = 2; 1200 break; 1201 case 3: 1202 te.outerAttrs = 3; 1203 break; 1204 } 1205 } 1206 } 1207 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 1208 "outerAttrs: %d\n", 1209 te.shareable, te.innerAttrs, te.outerAttrs); 1210 te.setAttributes(false); 1211} 1212 1213void 1214TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 1215 LongDescriptor &lDescriptor) 1216{ 1217 assert(_haveLPAE); 1218 1219 uint8_t attr; 1220 uint8_t sh = lDescriptor.sh(); 1221 // Different format and source of attributes if this is a stage 2 1222 // translation 1223 if (isStage2) { 1224 attr = lDescriptor.memAttr(); 1225 uint8_t attr_3_2 = (attr >> 2) & 0x3; 1226 uint8_t attr_1_0 = attr & 0x3; 1227 1228 DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 1229 1230 if (attr_3_2 == 0) { 1231 te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 1232 : TlbEntry::MemoryType::Device; 1233 te.outerAttrs = 0; 1234 te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 1235 te.nonCacheable = true; 1236 } else { 1237 te.mtype = TlbEntry::MemoryType::Normal; 1238 te.outerAttrs = attr_3_2 == 1 ? 0 : 1239 attr_3_2 == 2 ? 2 : 1; 1240 te.innerAttrs = attr_1_0 == 1 ? 0 : 1241 attr_1_0 == 2 ? 6 : 5; 1242 te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 1243 } 1244 } else { 1245 uint8_t attrIndx = lDescriptor.attrIndx(); 1246 1247 // LPAE always uses remapping of memory attributes, irrespective of the 1248 // value of SCTLR.TRE 1249 MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 1250 int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, 1251 !currState->isSecure); 1252 uint32_t mair = currState->tc->readMiscReg(reg_as_int); 1253 attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 1254 uint8_t attr_7_4 = bits(attr, 7, 4); 1255 uint8_t attr_3_0 = bits(attr, 3, 0); 1256 DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 1257 1258 // Note: the memory subsystem only cares about the 'cacheable' memory 1259 // attribute. The other attributes are only used to fill the PAR register 1260 // accordingly to provide the illusion of full support 1261 te.nonCacheable = false; 1262 1263 switch (attr_7_4) { 1264 case 0x0: 1265 // Strongly-ordered or Device memory 1266 if (attr_3_0 == 0x0) 1267 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1268 else if (attr_3_0 == 0x4) 1269 te.mtype = TlbEntry::MemoryType::Device; 1270 else 1271 panic("Unpredictable behavior\n"); 1272 te.nonCacheable = true; 1273 te.outerAttrs = 0; 1274 break; 1275 case 0x4: 1276 // Normal memory, Outer Non-cacheable 1277 te.mtype = TlbEntry::MemoryType::Normal; 1278 te.outerAttrs = 0; 1279 if (attr_3_0 == 0x4) 1280 // Inner Non-cacheable 1281 te.nonCacheable = true; 1282 else if (attr_3_0 < 0x8) 1283 panic("Unpredictable behavior\n"); 1284 break; 1285 case 0x8: 1286 case 0x9: 1287 case 0xa: 1288 case 0xb: 1289 case 0xc: 1290 case 0xd: 1291 case 0xe: 1292 case 0xf: 1293 if (attr_7_4 & 0x4) { 1294 te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 1295 } else { 1296 te.outerAttrs = 0x2; 1297 } 1298 // Normal memory, Outer Cacheable 1299 te.mtype = TlbEntry::MemoryType::Normal; 1300 if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 1301 panic("Unpredictable behavior\n"); 1302 break; 1303 default: 1304 panic("Unpredictable behavior\n"); 1305 break; 1306 } 1307 1308 switch (attr_3_0) { 1309 case 0x0: 1310 te.innerAttrs = 0x1; 1311 break; 1312 case 0x4: 1313 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 1314 break; 1315 case 0x8: 1316 case 0x9: 1317 case 0xA: 1318 case 0xB: 1319 te.innerAttrs = 6; 1320 break; 1321 case 0xC: 1322 case 0xD: 1323 case 0xE: 1324 case 0xF: 1325 te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 1326 break; 1327 default: 1328 panic("Unpredictable behavior\n"); 1329 break; 1330 } 1331 } 1332 1333 te.outerShareable = sh == 2; 1334 te.shareable = (sh & 0x2) ? true : false; 1335 te.setAttributes(true); 1336 te.attributes |= (uint64_t) attr << 56; 1337} 1338 1339void 1340TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, 1341 LongDescriptor &lDescriptor) 1342{ 1343 uint8_t attr; 1344 uint8_t attr_hi; 1345 uint8_t attr_lo; 1346 uint8_t sh = lDescriptor.sh(); 1347 1348 if (isStage2) { 1349 attr = lDescriptor.memAttr(); 1350 uint8_t attr_hi = (attr >> 2) & 0x3; 1351 uint8_t attr_lo = attr & 0x3; 1352 1353 DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh); 1354 1355 if (attr_hi == 0) { 1356 te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered 1357 : TlbEntry::MemoryType::Device; 1358 te.outerAttrs = 0; 1359 te.innerAttrs = attr_lo == 0 ? 1 : 3; 1360 te.nonCacheable = true; 1361 } else { 1362 te.mtype = TlbEntry::MemoryType::Normal; 1363 te.outerAttrs = attr_hi == 1 ? 0 : 1364 attr_hi == 2 ? 2 : 1; 1365 te.innerAttrs = attr_lo == 1 ? 0 : 1366 attr_lo == 2 ? 6 : 5; 1367 te.nonCacheable = (attr_hi == 1) || (attr_lo == 1); 1368 } 1369 } else { 1370 uint8_t attrIndx = lDescriptor.attrIndx(); 1371 1372 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 1373 1374 // Select MAIR 1375 uint64_t mair; 1376 switch (currState->el) { 1377 case EL0: 1378 case EL1: 1379 mair = tc->readMiscReg(MISCREG_MAIR_EL1); 1380 break; 1381 case EL2: 1382 mair = tc->readMiscReg(MISCREG_MAIR_EL2); 1383 break; 1384 case EL3: 1385 mair = tc->readMiscReg(MISCREG_MAIR_EL3); 1386 break; 1387 default: 1388 panic("Invalid exception level"); 1389 break; 1390 } 1391 1392 // Select attributes 1393 attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 1394 attr_lo = bits(attr, 3, 0); 1395 attr_hi = bits(attr, 7, 4); 1396 1397 // Memory type 1398 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 1399 1400 // Cacheability 1401 te.nonCacheable = false; 1402 if (te.mtype == TlbEntry::MemoryType::Device || // Device memory 1403 attr_hi == 0x8 || // Normal memory, Outer Non-cacheable 1404 attr_lo == 0x8) { // Normal memory, Inner Non-cacheable 1405 te.nonCacheable = true; 1406 } 1407 1408 te.shareable = sh == 2; 1409 te.outerShareable = (sh & 0x2) ? true : false; 1410 // Attributes formatted according to the 64-bit PAR 1411 te.attributes = ((uint64_t) attr << 56) | 1412 (1 << 11) | // LPAE bit 1413 (te.ns << 9) | // NS bit 1414 (sh << 7); 1415 } 1416} 1417 1418void 1419TableWalker::doL1Descriptor() 1420{ 1421 if (currState->fault != NoFault) { 1422 return; 1423 } 1424 1425 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 1426 currState->vaddr_tainted, currState->l1Desc.data); 1427 TlbEntry te; 1428 1429 switch (currState->l1Desc.type()) { 1430 case L1Descriptor::Ignore: 1431 case L1Descriptor::Reserved: 1432 if (!currState->timing) { 1433 currState->tc = NULL; 1434 currState->req = NULL; 1435 } 1436 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 1437 if (currState->isFetch) 1438 currState->fault = 1439 std::make_shared<PrefetchAbort>( 1440 currState->vaddr_tainted, 1441 ArmFault::TranslationLL + L1, 1442 isStage2, 1443 ArmFault::VmsaTran); 1444 else 1445 currState->fault = 1446 std::make_shared<DataAbort>( 1447 currState->vaddr_tainted, 1448 TlbEntry::DomainType::NoAccess, 1449 currState->isWrite, 1450 ArmFault::TranslationLL + L1, isStage2, 1451 ArmFault::VmsaTran); 1452 return; 1453 case L1Descriptor::Section: 1454 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 1455 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 1456 * enabled if set, do l1.Desc.setAp0() instead of generating 1457 * AccessFlag0 1458 */ 1459 1460 currState->fault = std::make_shared<DataAbort>( 1461 currState->vaddr_tainted, 1462 currState->l1Desc.domain(), 1463 currState->isWrite, 1464 ArmFault::AccessFlagLL + L1, 1465 isStage2, 1466 ArmFault::VmsaTran); 1467 } 1468 if (currState->l1Desc.supersection()) { 1469 panic("Haven't implemented supersections\n"); 1470 } 1471 insertTableEntry(currState->l1Desc, false); 1472 return; 1473 case L1Descriptor::PageTable: 1474 { 1475 Addr l2desc_addr; 1476 l2desc_addr = currState->l1Desc.l2Addr() | 1477 (bits(currState->vaddr, 19, 12) << 2); 1478 DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 1479 l2desc_addr, currState->isSecure ? "s" : "ns"); 1480 1481 // Trickbox address check 1482 currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 1483 currState->l1Desc.domain(), L2); 1484 1485 if (currState->fault) { 1486 if (!currState->timing) { 1487 currState->tc = NULL; 1488 currState->req = NULL; 1489 } 1490 return; 1491 } 1492 1493 Request::Flags flag = Request::PT_WALK; 1494 if (currState->isSecure) 1495 flag.set(Request::SECURE); 1496 1497 bool delayed; 1498 delayed = fetchDescriptor(l2desc_addr, 1499 (uint8_t*)&currState->l2Desc.data, 1500 sizeof(uint32_t), flag, -1, &doL2DescEvent, 1501 &TableWalker::doL2Descriptor); 1502 if (delayed) { 1503 currState->delayed = true; 1504 } 1505 1506 return; 1507 } 1508 default: 1509 panic("A new type in a 2 bit field?\n"); 1510 } 1511} 1512 1513void 1514TableWalker::doLongDescriptor() 1515{ 1516 if (currState->fault != NoFault) { 1517 return; 1518 } 1519 1520 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 1521 currState->longDesc.lookupLevel, currState->vaddr_tainted, 1522 currState->longDesc.data, 1523 currState->aarch64 ? "AArch64" : "long-desc."); 1524 1525 if ((currState->longDesc.type() == LongDescriptor::Block) || 1526 (currState->longDesc.type() == LongDescriptor::Page)) { 1527 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 1528 "xn: %d, ap: %d, af: %d, type: %d\n", 1529 currState->longDesc.lookupLevel, 1530 currState->longDesc.data, 1531 currState->longDesc.pxn(), 1532 currState->longDesc.xn(), 1533 currState->longDesc.ap(), 1534 currState->longDesc.af(), 1535 currState->longDesc.type()); 1536 } else { 1537 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 1538 currState->longDesc.lookupLevel, 1539 currState->longDesc.data, 1540 currState->longDesc.type()); 1541 } 1542 1543 TlbEntry te; 1544 1545 switch (currState->longDesc.type()) { 1546 case LongDescriptor::Invalid: 1547 if (!currState->timing) { 1548 currState->tc = NULL; 1549 currState->req = NULL; 1550 } 1551 1552 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 1553 currState->longDesc.lookupLevel, 1554 ArmFault::TranslationLL + currState->longDesc.lookupLevel); 1555 if (currState->isFetch) 1556 currState->fault = std::make_shared<PrefetchAbort>( 1557 currState->vaddr_tainted, 1558 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1559 isStage2, 1560 ArmFault::LpaeTran); 1561 else 1562 currState->fault = std::make_shared<DataAbort>( 1563 currState->vaddr_tainted, 1564 TlbEntry::DomainType::NoAccess, 1565 currState->isWrite, 1566 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1567 isStage2, 1568 ArmFault::LpaeTran); 1569 return; 1570 case LongDescriptor::Block: 1571 case LongDescriptor::Page: 1572 { 1573 bool fault = false; 1574 bool aff = false; 1575 // Check for address size fault 1576 if (checkAddrSizeFaultAArch64( 1577 mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 1578 currState->longDesc.offsetBits()), 1579 currState->physAddrRange)) { 1580 fault = true; 1581 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1582 currState->longDesc.lookupLevel); 1583 // Check for access fault 1584 } else if (currState->longDesc.af() == 0) { 1585 fault = true; 1586 DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 1587 currState->longDesc.lookupLevel); 1588 aff = true; 1589 } 1590 if (fault) { 1591 if (currState->isFetch) 1592 currState->fault = std::make_shared<PrefetchAbort>( 1593 currState->vaddr_tainted, 1594 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1595 currState->longDesc.lookupLevel, 1596 isStage2, 1597 ArmFault::LpaeTran); 1598 else 1599 currState->fault = std::make_shared<DataAbort>( 1600 currState->vaddr_tainted, 1601 TlbEntry::DomainType::NoAccess, currState->isWrite, 1602 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1603 currState->longDesc.lookupLevel, 1604 isStage2, 1605 ArmFault::LpaeTran); 1606 } else { 1607 insertTableEntry(currState->longDesc, true); 1608 } 1609 } 1610 return; 1611 case LongDescriptor::Table: 1612 { 1613 // Set hierarchical permission flags 1614 currState->secureLookup = currState->secureLookup && 1615 currState->longDesc.secureTable(); 1616 currState->rwTable = currState->rwTable && 1617 currState->longDesc.rwTable(); 1618 currState->userTable = currState->userTable && 1619 currState->longDesc.userTable(); 1620 currState->xnTable = currState->xnTable || 1621 currState->longDesc.xnTable(); 1622 currState->pxnTable = currState->pxnTable || 1623 currState->longDesc.pxnTable(); 1624 1625 // Set up next level lookup 1626 Addr next_desc_addr = currState->longDesc.nextDescAddr( 1627 currState->vaddr); 1628 1629 DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 1630 currState->longDesc.lookupLevel, 1631 currState->longDesc.lookupLevel + 1, 1632 next_desc_addr, 1633 currState->secureLookup ? "s" : "ns"); 1634 1635 // Check for address size fault 1636 if (currState->aarch64 && checkAddrSizeFaultAArch64( 1637 next_desc_addr, currState->physAddrRange)) { 1638 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1639 currState->longDesc.lookupLevel); 1640 if (currState->isFetch) 1641 currState->fault = std::make_shared<PrefetchAbort>( 1642 currState->vaddr_tainted, 1643 ArmFault::AddressSizeLL 1644 + currState->longDesc.lookupLevel, 1645 isStage2, 1646 ArmFault::LpaeTran); 1647 else 1648 currState->fault = std::make_shared<DataAbort>( 1649 currState->vaddr_tainted, 1650 TlbEntry::DomainType::NoAccess, currState->isWrite, 1651 ArmFault::AddressSizeLL 1652 + currState->longDesc.lookupLevel, 1653 isStage2, 1654 ArmFault::LpaeTran); 1655 return; 1656 } 1657 1658 // Trickbox address check 1659 currState->fault = testWalk( 1660 next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 1661 toLookupLevel(currState->longDesc.lookupLevel +1)); 1662 1663 if (currState->fault) { 1664 if (!currState->timing) { 1665 currState->tc = NULL; 1666 currState->req = NULL; 1667 } 1668 return; 1669 } 1670 1671 Request::Flags flag = Request::PT_WALK; 1672 if (currState->secureLookup) 1673 flag.set(Request::SECURE); 1674 1675 currState->longDesc.lookupLevel = 1676 (LookupLevel) (currState->longDesc.lookupLevel + 1); 1677 Event *event = NULL; 1678 switch (currState->longDesc.lookupLevel) { 1679 case L1: 1680 assert(currState->aarch64); 1681 event = &doL1LongDescEvent; 1682 break; 1683 case L2: 1684 event = &doL2LongDescEvent; 1685 break; 1686 case L3: 1687 event = &doL3LongDescEvent; 1688 break; 1689 default: 1690 panic("Wrong lookup level in table walk\n"); 1691 break; 1692 } 1693 1694 bool delayed; 1695 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 1696 sizeof(uint64_t), flag, -1, event, 1697 &TableWalker::doLongDescriptor); 1698 if (delayed) { 1699 currState->delayed = true; 1700 } 1701 } 1702 return; 1703 default: 1704 panic("A new type in a 2 bit field?\n"); 1705 } 1706} 1707 1708void 1709TableWalker::doL2Descriptor() 1710{ 1711 if (currState->fault != NoFault) { 1712 return; 1713 } 1714 1715 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 1716 currState->vaddr_tainted, currState->l2Desc.data); 1717 TlbEntry te; 1718 1719 if (currState->l2Desc.invalid()) { 1720 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 1721 if (!currState->timing) { 1722 currState->tc = NULL; 1723 currState->req = NULL; 1724 } 1725 if (currState->isFetch) 1726 currState->fault = std::make_shared<PrefetchAbort>( 1727 currState->vaddr_tainted, 1728 ArmFault::TranslationLL + L2, 1729 isStage2, 1730 ArmFault::VmsaTran); 1731 else 1732 currState->fault = std::make_shared<DataAbort>( 1733 currState->vaddr_tainted, currState->l1Desc.domain(), 1734 currState->isWrite, ArmFault::TranslationLL + L2, 1735 isStage2, 1736 ArmFault::VmsaTran); 1737 return; 1738 } 1739 1740 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 1741 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 1742 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 1743 */ 1744 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 1745 currState->sctlr.afe, currState->l2Desc.ap()); 1746 1747 currState->fault = std::make_shared<DataAbort>( 1748 currState->vaddr_tainted, 1749 TlbEntry::DomainType::NoAccess, currState->isWrite, 1750 ArmFault::AccessFlagLL + L2, isStage2, 1751 ArmFault::VmsaTran); 1752 } 1753 1754 insertTableEntry(currState->l2Desc, false); 1755} 1756 1757void 1758TableWalker::doL1DescriptorWrapper() 1759{ 1760 currState = stateQueues[L1].front(); 1761 currState->delayed = false; 1762 // if there's a stage2 translation object we don't need it any more 1763 if (currState->stage2Tran) { 1764 delete currState->stage2Tran; 1765 currState->stage2Tran = NULL; 1766 } 1767 1768 1769 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 1770 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 1771 1772 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 1773 doL1Descriptor(); 1774 1775 stateQueues[L1].pop_front(); 1776 // Check if fault was generated 1777 if (currState->fault != NoFault) { 1778 currState->transState->finish(currState->fault, currState->req, 1779 currState->tc, currState->mode); 1780 statWalksShortTerminatedAtLevel[0]++; 1781 1782 pending = false; 1783 nextWalk(currState->tc); 1784 1785 currState->req = NULL; 1786 currState->tc = NULL; 1787 currState->delayed = false; 1788 delete currState; 1789 } 1790 else if (!currState->delayed) { 1791 // delay is not set so there is no L2 to do 1792 // Don't finish the translation if a stage 2 look up is underway 1793 if (!currState->doingStage2) { 1794 statWalkServiceTime.sample(curTick() - currState->startTime); 1795 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1796 currState->fault = tlb->translateTiming(currState->req, currState->tc, 1797 currState->transState, currState->mode); 1798 statWalksShortTerminatedAtLevel[0]++; 1799 } 1800 1801 pending = false; 1802 nextWalk(currState->tc); 1803 1804 currState->req = NULL; 1805 currState->tc = NULL; 1806 currState->delayed = false; 1807 delete currState; 1808 } else { 1809 // need to do L2 descriptor 1810 stateQueues[L2].push_back(currState); 1811 } 1812 currState = NULL; 1813} 1814 1815void 1816TableWalker::doL2DescriptorWrapper() 1817{ 1818 currState = stateQueues[L2].front(); 1819 assert(currState->delayed); 1820 // if there's a stage2 translation object we don't need it any more 1821 if (currState->stage2Tran) { 1822 delete currState->stage2Tran; 1823 currState->stage2Tran = NULL; 1824 } 1825 1826 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 1827 currState->vaddr_tainted); 1828 doL2Descriptor(); 1829 1830 // Check if fault was generated 1831 if (currState->fault != NoFault) { 1832 currState->transState->finish(currState->fault, currState->req, 1833 currState->tc, currState->mode); 1834 statWalksShortTerminatedAtLevel[1]++; 1835 } 1836 else { 1837 // Don't finish the translation if a stage 2 look up is underway 1838 if (!currState->doingStage2) { 1839 statWalkServiceTime.sample(curTick() - currState->startTime); 1840 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1841 currState->fault = tlb->translateTiming(currState->req, 1842 currState->tc, currState->transState, currState->mode); 1843 statWalksShortTerminatedAtLevel[1]++; 1844 } 1845 } 1846 1847 1848 stateQueues[L2].pop_front(); 1849 pending = false; 1850 nextWalk(currState->tc); 1851 1852 currState->req = NULL; 1853 currState->tc = NULL; 1854 currState->delayed = false; 1855 1856 delete currState; 1857 currState = NULL; 1858} 1859 1860void 1861TableWalker::doL0LongDescriptorWrapper() 1862{ 1863 doLongDescriptorWrapper(L0); 1864} 1865 1866void 1867TableWalker::doL1LongDescriptorWrapper() 1868{ 1869 doLongDescriptorWrapper(L1); 1870} 1871 1872void 1873TableWalker::doL2LongDescriptorWrapper() 1874{ 1875 doLongDescriptorWrapper(L2); 1876} 1877 1878void 1879TableWalker::doL3LongDescriptorWrapper() 1880{ 1881 doLongDescriptorWrapper(L3); 1882} 1883 1884void 1885TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 1886{ 1887 currState = stateQueues[curr_lookup_level].front(); 1888 assert(curr_lookup_level == currState->longDesc.lookupLevel); 1889 currState->delayed = false; 1890 1891 // if there's a stage2 translation object we don't need it any more 1892 if (currState->stage2Tran) { 1893 delete currState->stage2Tran; 1894 currState->stage2Tran = NULL; 1895 } 1896 1897 DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 1898 currState->vaddr_tainted); 1899 doLongDescriptor(); 1900 1901 stateQueues[curr_lookup_level].pop_front(); 1902 1903 if (currState->fault != NoFault) { 1904 // A fault was generated 1905 currState->transState->finish(currState->fault, currState->req, 1906 currState->tc, currState->mode); 1907 1908 pending = false; 1909 nextWalk(currState->tc); 1910 1911 currState->req = NULL; 1912 currState->tc = NULL; 1913 currState->delayed = false; 1914 delete currState; 1915 } else if (!currState->delayed) { 1916 // No additional lookups required 1917 // Don't finish the translation if a stage 2 look up is underway 1918 if (!currState->doingStage2) { 1919 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1920 statWalkServiceTime.sample(curTick() - currState->startTime); 1921 currState->fault = tlb->translateTiming(currState->req, currState->tc, 1922 currState->transState, 1923 currState->mode); 1924 statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 1925 } 1926 1927 pending = false; 1928 nextWalk(currState->tc); 1929 1930 currState->req = NULL; 1931 currState->tc = NULL; 1932 currState->delayed = false; 1933 delete currState; 1934 } else { 1935 if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 1936 panic("Max. number of lookups already reached in table walk\n"); 1937 // Need to perform additional lookups 1938 stateQueues[currState->longDesc.lookupLevel].push_back(currState); 1939 } 1940 currState = NULL; 1941} 1942 1943 1944void 1945TableWalker::nextWalk(ThreadContext *tc) 1946{ 1947 if (pendingQueue.size()) 1948 schedule(doProcessEvent, clockEdge(Cycles(1))); 1949 else 1950 completeDrain(); 1951} 1952 1953bool 1954TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 1955 Request::Flags flags, int queueIndex, Event *event, 1956 void (TableWalker::*doDescriptor)()) 1957{ 1958 bool isTiming = currState->timing; 1959 1960 DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 1961 descAddr, currState->stage2Req); 1962 1963 // If this translation has a stage 2 then we know descAddr is an IPA and 1964 // needs to be translated before we can access the page table. Do that 1965 // check here. 1966 if (currState->stage2Req) { 1967 Fault fault; 1968 flags = flags | TLB::MustBeOne; 1969 1970 if (isTiming) { 1971 Stage2MMU::Stage2Translation *tran = new 1972 Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 1973 currState->vaddr); 1974 currState->stage2Tran = tran; 1975 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 1976 flags); 1977 fault = tran->fault; 1978 } else { 1979 fault = stage2Mmu->readDataUntimed(currState->tc, 1980 currState->vaddr, descAddr, data, numBytes, flags, 1981 currState->functional); 1982 } 1983 1984 if (fault != NoFault) { 1985 currState->fault = fault; 1986 } 1987 if (isTiming) { 1988 if (queueIndex >= 0) { 1989 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1990 stateQueues[queueIndex].size()); 1991 stateQueues[queueIndex].push_back(currState); 1992 currState = NULL; 1993 } 1994 } else { 1995 (this->*doDescriptor)(); 1996 } 1997 } else { 1998 if (isTiming) { 1999 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 2000 currState->tc->getCpuPtr()->clockPeriod(),flags); 2001 if (queueIndex >= 0) { 2002 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 2003 stateQueues[queueIndex].size()); 2004 stateQueues[queueIndex].push_back(currState); 2005 currState = NULL; 2006 } 2007 } else if (!currState->functional) { 2008 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 2009 currState->tc->getCpuPtr()->clockPeriod(), flags); 2010 (this->*doDescriptor)(); 2011 } else { 2012 RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 2013 req->taskId(ContextSwitchTaskId::DMA); 2014 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2015 pkt->dataStatic(data); 2016 port->sendFunctional(pkt); 2017 (this->*doDescriptor)(); 2018 delete req; 2019 delete pkt; 2020 } 2021 } 2022 return (isTiming); 2023} 2024 2025void 2026TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 2027{ 2028 TlbEntry te; 2029 2030 // Create and fill a new page table entry 2031 te.valid = true; 2032 te.longDescFormat = longDescriptor; 2033 te.isHyp = currState->isHyp; 2034 te.asid = currState->asid; 2035 te.vmid = currState->vmid; 2036 te.N = descriptor.offsetBits(); 2037 te.vpn = currState->vaddr >> te.N; 2038 te.size = (1<<te.N) - 1; 2039 te.pfn = descriptor.pfn(); 2040 te.domain = descriptor.domain(); 2041 te.lookupLevel = descriptor.lookupLevel; 2042 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 2043 te.nstid = !currState->isSecure; 2044 te.xn = descriptor.xn(); 2045 if (currState->aarch64) 2046 te.el = currState->el; 2047 else 2048 te.el = 1; 2049 2050 statPageSizes[pageSizeNtoStatBin(te.N)]++; 2051 statRequestOrigin[COMPLETED][currState->isFetch]++; 2052 2053 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 2054 // as global 2055 te.global = descriptor.global(currState) || isStage2; 2056 if (longDescriptor) { 2057 LongDescriptor lDescriptor = 2058 dynamic_cast<LongDescriptor &>(descriptor); 2059 2060 te.xn |= currState->xnTable; 2061 te.pxn = currState->pxnTable || lDescriptor.pxn(); 2062 if (isStage2) { 2063 // this is actually the HAP field, but its stored in the same bit 2064 // possitions as the AP field in a stage 1 translation. 2065 te.hap = lDescriptor.ap(); 2066 } else { 2067 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 2068 (currState->userTable && (descriptor.ap() & 0x1)); 2069 } 2070 if (currState->aarch64) 2071 memAttrsAArch64(currState->tc, te, lDescriptor); 2072 else 2073 memAttrsLPAE(currState->tc, te, lDescriptor); 2074 } else { 2075 te.ap = descriptor.ap(); 2076 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 2077 descriptor.shareable()); 2078 } 2079 2080 // Debug output 2081 DPRINTF(TLB, descriptor.dbgHeader().c_str()); 2082 DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 2083 te.N, te.pfn, te.size, te.global, te.valid); 2084 DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 2085 "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 2086 te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 2087 te.nonCacheable, te.ns); 2088 DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 2089 descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 2090 descriptor.getRawData()); 2091 2092 // Insert the entry into the TLB 2093 tlb->insert(currState->vaddr, te); 2094 if (!currState->timing) { 2095 currState->tc = NULL; 2096 currState->req = NULL; 2097 } 2098} 2099 2100ArmISA::TableWalker * 2101ArmTableWalkerParams::create() 2102{ 2103 return new ArmISA::TableWalker(this); 2104} 2105 2106LookupLevel 2107TableWalker::toLookupLevel(uint8_t lookup_level_as_int) 2108{ 2109 switch (lookup_level_as_int) { 2110 case L1: 2111 return L1; 2112 case L2: 2113 return L2; 2114 case L3: 2115 return L3; 2116 default: 2117 panic("Invalid lookup level conversion"); 2118 } 2119} 2120 2121/* this method keeps track of the table walker queue's residency, so 2122 * needs to be called whenever requests start and complete. */ 2123void 2124TableWalker::pendingChange() 2125{ 2126 unsigned n = pendingQueue.size(); 2127 if ((currState != NULL) && (currState != pendingQueue.front())) { 2128 ++n; 2129 } 2130 2131 if (n != pendingReqs) { 2132 Tick now = curTick(); 2133 statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 2134 pendingReqs = n; 2135 pendingChangeTick = now; 2136 } 2137} 2138 2139Fault 2140TableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 2141 LookupLevel lookup_level) 2142{ 2143 return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 2144 currState->mode, domain, lookup_level); 2145} 2146 2147 2148uint8_t 2149TableWalker::pageSizeNtoStatBin(uint8_t N) 2150{ 2151 /* for statPageSizes */ 2152 switch(N) { 2153 case 12: return 0; // 4K 2154 case 14: return 1; // 16K (using 16K granule in v8-64) 2155 case 16: return 2; // 64K 2156 case 20: return 3; // 1M 2157 case 21: return 4; // 2M-LPAE 2158 case 24: return 5; // 16M 2159 case 25: return 6; // 32M (using 16K granule in v8-64) 2160 case 29: return 7; // 512M (using 64K granule in v8-64) 2161 case 30: return 8; // 1G-LPAE 2162 default: 2163 panic("unknown page size"); 2164 return 255; 2165 } 2166} 2167 2168void 2169TableWalker::regStats() 2170{ 2171 ClockedObject::regStats(); 2172 2173 statWalks 2174 .name(name() + ".walks") 2175 .desc("Table walker walks requested") 2176 ; 2177 2178 statWalksShortDescriptor 2179 .name(name() + ".walksShort") 2180 .desc("Table walker walks initiated with short descriptors") 2181 .flags(Stats::nozero) 2182 ; 2183 2184 statWalksLongDescriptor 2185 .name(name() + ".walksLong") 2186 .desc("Table walker walks initiated with long descriptors") 2187 .flags(Stats::nozero) 2188 ; 2189 2190 statWalksShortTerminatedAtLevel 2191 .init(2) 2192 .name(name() + ".walksShortTerminationLevel") 2193 .desc("Level at which table walker walks " 2194 "with short descriptors terminate") 2195 .flags(Stats::nozero) 2196 ; 2197 statWalksShortTerminatedAtLevel.subname(0, "Level1"); 2198 statWalksShortTerminatedAtLevel.subname(1, "Level2"); 2199 2200 statWalksLongTerminatedAtLevel 2201 .init(4) 2202 .name(name() + ".walksLongTerminationLevel") 2203 .desc("Level at which table walker walks " 2204 "with long descriptors terminate") 2205 .flags(Stats::nozero) 2206 ; 2207 statWalksLongTerminatedAtLevel.subname(0, "Level0"); 2208 statWalksLongTerminatedAtLevel.subname(1, "Level1"); 2209 statWalksLongTerminatedAtLevel.subname(2, "Level2"); 2210 statWalksLongTerminatedAtLevel.subname(3, "Level3"); 2211 2212 statSquashedBefore 2213 .name(name() + ".walksSquashedBefore") 2214 .desc("Table walks squashed before starting") 2215 .flags(Stats::nozero) 2216 ; 2217 2218 statSquashedAfter 2219 .name(name() + ".walksSquashedAfter") 2220 .desc("Table walks squashed after completion") 2221 .flags(Stats::nozero) 2222 ; 2223 2224 statWalkWaitTime 2225 .init(16) 2226 .name(name() + ".walkWaitTime") 2227 .desc("Table walker wait (enqueue to first request) latency") 2228 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2229 ; 2230 2231 statWalkServiceTime 2232 .init(16) 2233 .name(name() + ".walkCompletionTime") 2234 .desc("Table walker service (enqueue to completion) latency") 2235 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2236 ; 2237 2238 statPendingWalks 2239 .init(16) 2240 .name(name() + ".walksPending") 2241 .desc("Table walker pending requests distribution") 2242 .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 2243 ; 2244 2245 statPageSizes // see DDI 0487A D4-1661 2246 .init(9) 2247 .name(name() + ".walkPageSizes") 2248 .desc("Table walker page sizes translated") 2249 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 2250 ; 2251 statPageSizes.subname(0, "4K"); 2252 statPageSizes.subname(1, "16K"); 2253 statPageSizes.subname(2, "64K"); 2254 statPageSizes.subname(3, "1M"); 2255 statPageSizes.subname(4, "2M"); 2256 statPageSizes.subname(5, "16M"); 2257 statPageSizes.subname(6, "32M"); 2258 statPageSizes.subname(7, "512M"); 2259 statPageSizes.subname(8, "1G"); 2260 2261 statRequestOrigin 2262 .init(2,2) // Instruction/Data, requests/completed 2263 .name(name() + ".walkRequestOrigin") 2264 .desc("Table walker requests started/completed, data/inst") 2265 .flags(Stats::total) 2266 ; 2267 statRequestOrigin.subname(0,"Requested"); 2268 statRequestOrigin.subname(1,"Completed"); 2269 statRequestOrigin.ysubname(0,"Data"); 2270 statRequestOrigin.ysubname(1,"Inst"); 2271} 2272