table_walker.cc revision 11579
15245Sgblack@eecs.umich.edu/* 25245Sgblack@eecs.umich.edu * Copyright (c) 2010, 2012-2016 ARM Limited 35245Sgblack@eecs.umich.edu * All rights reserved 45245Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135245Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 225245Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 245245Sgblack@eecs.umich.edu * 255245Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265245Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275245Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285245Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295245Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305245Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315245Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325245Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335245Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345245Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355245Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365245Sgblack@eecs.umich.edu * 375245Sgblack@eecs.umich.edu * Authors: Ali Saidi 385245Sgblack@eecs.umich.edu * Giacomo Gabrielli 395245Sgblack@eecs.umich.edu */ 405245Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 415245Sgblack@eecs.umich.edu 425245Sgblack@eecs.umich.edu#include <memory> 437912Shestness@cs.utexas.edu 445245Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 455245Sgblack@eecs.umich.edu#include "arch/arm/stage2_mmu.hh" 465245Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 475245Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 485245Sgblack@eecs.umich.edu#include "cpu/base.hh" 495245Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 505245Sgblack@eecs.umich.edu#include "debug/Checkpoint.hh" 515245Sgblack@eecs.umich.edu#include "debug/Drain.hh" 525245Sgblack@eecs.umich.edu#include "debug/TLB.hh" 535245Sgblack@eecs.umich.edu#include "debug/TLBVerbose.hh" 545245Sgblack@eecs.umich.edu#include "dev/dma_device.hh" 555245Sgblack@eecs.umich.edu#include "sim/system.hh" 565245Sgblack@eecs.umich.edu 575245Sgblack@eecs.umich.eduusing namespace ArmISA; 585245Sgblack@eecs.umich.edu 595245Sgblack@eecs.umich.eduTableWalker::TableWalker(const Params *p) 605245Sgblack@eecs.umich.edu : MemObject(p), 615245Sgblack@eecs.umich.edu stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 625245Sgblack@eecs.umich.edu isStage2(p->is_stage2), tlb(NULL), 635245Sgblack@eecs.umich.edu currState(NULL), pending(false), 645245Sgblack@eecs.umich.edu numSquashable(p->num_squash_per_cycle), 655245Sgblack@eecs.umich.edu pendingReqs(0), 665245Sgblack@eecs.umich.edu pendingChangeTick(curTick()), 675245Sgblack@eecs.umich.edu doL1DescEvent(this), doL2DescEvent(this), 685245Sgblack@eecs.umich.edu doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this), 695245Sgblack@eecs.umich.edu doL3LongDescEvent(this), 705895Sgblack@eecs.umich.edu doProcessEvent(this) 717912Shestness@cs.utexas.edu{ 727912Shestness@cs.utexas.edu sctlr = 0; 735245Sgblack@eecs.umich.edu 747912Shestness@cs.utexas.edu // Cache system-level properties 757912Shestness@cs.utexas.edu if (FullSystem) { 767912Shestness@cs.utexas.edu ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 777912Shestness@cs.utexas.edu assert(armSys); 787912Shestness@cs.utexas.edu haveSecurity = armSys->haveSecurity(); 797912Shestness@cs.utexas.edu _haveLPAE = armSys->haveLPAE(); 807912Shestness@cs.utexas.edu _haveVirtualization = armSys->haveVirtualization(); 817912Shestness@cs.utexas.edu physAddrRange = armSys->physAddrRange(); 827912Shestness@cs.utexas.edu _haveLargeAsid64 = armSys->haveLargeAsid64(); 837912Shestness@cs.utexas.edu } else { 847912Shestness@cs.utexas.edu haveSecurity = _haveLPAE = _haveVirtualization = false; 857912Shestness@cs.utexas.edu _haveLargeAsid64 = false; 867912Shestness@cs.utexas.edu physAddrRange = 32; 877912Shestness@cs.utexas.edu } 887912Shestness@cs.utexas.edu 897912Shestness@cs.utexas.edu} 905895Sgblack@eecs.umich.edu 917912Shestness@cs.utexas.eduTableWalker::~TableWalker() 925245Sgblack@eecs.umich.edu{ 935245Sgblack@eecs.umich.edu ; 945245Sgblack@eecs.umich.edu} 955895Sgblack@eecs.umich.edu 967912Shestness@cs.utexas.eduvoid 977912Shestness@cs.utexas.eduTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 985245Sgblack@eecs.umich.edu{ 997912Shestness@cs.utexas.edu stage2Mmu = m; 1007912Shestness@cs.utexas.edu port = &m->getPort(); 1015245Sgblack@eecs.umich.edu masterId = master_id; 1025245Sgblack@eecs.umich.edu} 1035245Sgblack@eecs.umich.edu 1045245Sgblack@eecs.umich.eduvoid 1055245Sgblack@eecs.umich.eduTableWalker::init() 1065245Sgblack@eecs.umich.edu{ 1075245Sgblack@eecs.umich.edu fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 1085245Sgblack@eecs.umich.edu fatal_if(!port, "Table walker must have a valid port\n"); 1095245Sgblack@eecs.umich.edu fatal_if(!tlb, "Table walker must have a valid TLB\n"); 1105245Sgblack@eecs.umich.edu} 1115245Sgblack@eecs.umich.edu 1127912Shestness@cs.utexas.eduBaseMasterPort& 1137912Shestness@cs.utexas.eduTableWalker::getMasterPort(const std::string &if_name, PortID idx) 1147912Shestness@cs.utexas.edu{ 1157912Shestness@cs.utexas.edu if (if_name == "port") { 1167912Shestness@cs.utexas.edu if (!isStage2) { 1177912Shestness@cs.utexas.edu return *port; 1187912Shestness@cs.utexas.edu } else { 1197912Shestness@cs.utexas.edu fatal("Cannot access table walker port through stage-two walker\n"); 1207912Shestness@cs.utexas.edu } 1217912Shestness@cs.utexas.edu } 1227912Shestness@cs.utexas.edu return MemObject::getMasterPort(if_name, idx); 1237912Shestness@cs.utexas.edu} 1247912Shestness@cs.utexas.edu 1257912Shestness@cs.utexas.eduTableWalker::WalkerState::WalkerState() : 1267912Shestness@cs.utexas.edu tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 1275245Sgblack@eecs.umich.edu asid(0), vmid(0), isHyp(false), transState(nullptr), 1287912Shestness@cs.utexas.edu vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 1297912Shestness@cs.utexas.edu secureLookup(false), rwTable(false), userTable(false), xnTable(false), 1307912Shestness@cs.utexas.edu pxnTable(false), stage2Req(false), doingStage2(false), 1317912Shestness@cs.utexas.edu stage2Tran(nullptr), timing(false), functional(false), 1327912Shestness@cs.utexas.edu mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 1337912Shestness@cs.utexas.edu delayed(false), tableWalker(nullptr) 1347912Shestness@cs.utexas.edu{ 1355895Sgblack@eecs.umich.edu} 1365245Sgblack@eecs.umich.edu 1377912Shestness@cs.utexas.eduvoid 1387912Shestness@cs.utexas.eduTableWalker::completeDrain() 1395245Sgblack@eecs.umich.edu{ 1405245Sgblack@eecs.umich.edu if (drainState() == DrainState::Draining && 1415245Sgblack@eecs.umich.edu stateQueues[L1].empty() && stateQueues[L2].empty() && 1425245Sgblack@eecs.umich.edu pendingQueue.empty()) { 1435245Sgblack@eecs.umich.edu 1445245Sgblack@eecs.umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 1455245Sgblack@eecs.umich.edu signalDrainDone(); 1465245Sgblack@eecs.umich.edu } 1475245Sgblack@eecs.umich.edu} 1485245Sgblack@eecs.umich.edu 1495245Sgblack@eecs.umich.eduDrainState 1505245Sgblack@eecs.umich.eduTableWalker::drain() 1515245Sgblack@eecs.umich.edu{ 1525245Sgblack@eecs.umich.edu bool state_queues_not_empty = false; 1535245Sgblack@eecs.umich.edu 1545245Sgblack@eecs.umich.edu for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 1555245Sgblack@eecs.umich.edu if (!stateQueues[i].empty()) { 1565245Sgblack@eecs.umich.edu state_queues_not_empty = true; 1575245Sgblack@eecs.umich.edu break; 1585245Sgblack@eecs.umich.edu } 1595245Sgblack@eecs.umich.edu } 1605245Sgblack@eecs.umich.edu 1615245Sgblack@eecs.umich.edu if (state_queues_not_empty || pendingQueue.size()) { 1625245Sgblack@eecs.umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 1635245Sgblack@eecs.umich.edu return DrainState::Draining; 1645245Sgblack@eecs.umich.edu } else { 1655245Sgblack@eecs.umich.edu DPRINTF(Drain, "TableWalker free, no need to drain\n"); 1665245Sgblack@eecs.umich.edu return DrainState::Drained; 1675245Sgblack@eecs.umich.edu } 1685245Sgblack@eecs.umich.edu} 1695245Sgblack@eecs.umich.edu 1705245Sgblack@eecs.umich.eduvoid 1715245Sgblack@eecs.umich.eduTableWalker::drainResume() 1725245Sgblack@eecs.umich.edu{ 1735245Sgblack@eecs.umich.edu if (params()->sys->isTimingMode() && currState) { 1745245Sgblack@eecs.umich.edu delete currState; 1755245Sgblack@eecs.umich.edu currState = NULL; 1765245Sgblack@eecs.umich.edu pendingChange(); 1775245Sgblack@eecs.umich.edu } 1787912Shestness@cs.utexas.edu} 1797912Shestness@cs.utexas.edu 1807912Shestness@cs.utexas.eduFault 1817912Shestness@cs.utexas.eduTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 1827912Shestness@cs.utexas.edu uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 1837912Shestness@cs.utexas.edu TLB::Translation *_trans, bool _timing, bool _functional, 1847912Shestness@cs.utexas.edu bool secure, TLB::ArmTranslationType tranType) 1857912Shestness@cs.utexas.edu{ 1867912Shestness@cs.utexas.edu assert(!(_functional && _timing)); 1877912Shestness@cs.utexas.edu ++statWalks; 1887912Shestness@cs.utexas.edu 1897912Shestness@cs.utexas.edu WalkerState *savedCurrState = NULL; 1907912Shestness@cs.utexas.edu 1917912Shestness@cs.utexas.edu if (!currState && !_functional) { 1927912Shestness@cs.utexas.edu // For atomic mode, a new WalkerState instance should be only created 1937912Shestness@cs.utexas.edu // once per TLB. For timing mode, a new instance is generated for every 1947912Shestness@cs.utexas.edu // TLB miss. 1957912Shestness@cs.utexas.edu DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1967912Shestness@cs.utexas.edu 1977912Shestness@cs.utexas.edu currState = new WalkerState(); 1987912Shestness@cs.utexas.edu currState->tableWalker = this; 1997912Shestness@cs.utexas.edu } else if (_functional) { 2005245Sgblack@eecs.umich.edu // If we are mixing functional mode with timing (or even 2015245Sgblack@eecs.umich.edu // atomic), we need to to be careful and clean up after 2025245Sgblack@eecs.umich.edu // ourselves to not risk getting into an inconsistent state. 2037912Shestness@cs.utexas.edu DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 2047912Shestness@cs.utexas.edu savedCurrState = currState; 2057912Shestness@cs.utexas.edu currState = new WalkerState(); 2067912Shestness@cs.utexas.edu currState->tableWalker = this; 2077912Shestness@cs.utexas.edu } else if (_timing) { 2087912Shestness@cs.utexas.edu // This is a translation that was completed and then faulted again 2097912Shestness@cs.utexas.edu // because some underlying parameters that affect the translation 2107912Shestness@cs.utexas.edu // changed out from under us (e.g. asid). It will either be a 2117912Shestness@cs.utexas.edu // misprediction, in which case nothing will happen or we'll use 2127912Shestness@cs.utexas.edu // this fault to re-execute the faulting instruction which should clean 2137912Shestness@cs.utexas.edu // up everything. 2147912Shestness@cs.utexas.edu if (currState->vaddr_tainted == _req->getVaddr()) { 2157912Shestness@cs.utexas.edu ++statSquashedBefore; 2167912Shestness@cs.utexas.edu return std::make_shared<ReExec>(); 2177912Shestness@cs.utexas.edu } 2187912Shestness@cs.utexas.edu } 2197912Shestness@cs.utexas.edu pendingChange(); 2207912Shestness@cs.utexas.edu 2217912Shestness@cs.utexas.edu currState->startTime = curTick(); 2227912Shestness@cs.utexas.edu currState->tc = _tc; 2237912Shestness@cs.utexas.edu // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 2247912Shestness@cs.utexas.edu // aarch32/translation/translation/AArch32.TranslateAddress dictates 2257912Shestness@cs.utexas.edu // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 2267912Shestness@cs.utexas.edu currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || 2277912Shestness@cs.utexas.edu ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); 2287912Shestness@cs.utexas.edu currState->el = currEL(_tc); 2297912Shestness@cs.utexas.edu currState->transState = _trans; 2307912Shestness@cs.utexas.edu currState->req = _req; 2317912Shestness@cs.utexas.edu currState->fault = NoFault; 2327912Shestness@cs.utexas.edu currState->asid = _asid; 2337912Shestness@cs.utexas.edu currState->vmid = _vmid; 2347912Shestness@cs.utexas.edu currState->isHyp = _isHyp; 2357912Shestness@cs.utexas.edu currState->timing = _timing; 2367912Shestness@cs.utexas.edu currState->functional = _functional; 2377912Shestness@cs.utexas.edu currState->mode = _mode; 2387912Shestness@cs.utexas.edu currState->tranType = tranType; 2397912Shestness@cs.utexas.edu currState->isSecure = secure; 2407912Shestness@cs.utexas.edu currState->physAddrRange = physAddrRange; 2417912Shestness@cs.utexas.edu 2427912Shestness@cs.utexas.edu /** @todo These should be cached or grabbed from cached copies in 2437912Shestness@cs.utexas.edu the TLB, all these miscreg reads are expensive */ 2447912Shestness@cs.utexas.edu currState->vaddr_tainted = currState->req->getVaddr(); 2457912Shestness@cs.utexas.edu if (currState->aarch64) 2467912Shestness@cs.utexas.edu currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 2477912Shestness@cs.utexas.edu currState->tc, currState->el); 2487912Shestness@cs.utexas.edu else 2497912Shestness@cs.utexas.edu currState->vaddr = currState->vaddr_tainted; 2507912Shestness@cs.utexas.edu 2517912Shestness@cs.utexas.edu if (currState->aarch64) { 2527912Shestness@cs.utexas.edu if (isStage2) { 2537912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 2547912Shestness@cs.utexas.edu currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 2557912Shestness@cs.utexas.edu } else switch (currState->el) { 2567912Shestness@cs.utexas.edu case EL0: 2577912Shestness@cs.utexas.edu case EL1: 2587912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 2597912Shestness@cs.utexas.edu currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 2607912Shestness@cs.utexas.edu break; 2617912Shestness@cs.utexas.edu case EL2: 2627912Shestness@cs.utexas.edu assert(_haveVirtualization); 2637912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 2647912Shestness@cs.utexas.edu currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 2657912Shestness@cs.utexas.edu break; 2667912Shestness@cs.utexas.edu case EL3: 2677912Shestness@cs.utexas.edu assert(haveSecurity); 2687912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 2697912Shestness@cs.utexas.edu currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 2707912Shestness@cs.utexas.edu break; 2717912Shestness@cs.utexas.edu default: 2727912Shestness@cs.utexas.edu panic("Invalid exception level"); 2737912Shestness@cs.utexas.edu break; 2747912Shestness@cs.utexas.edu } 2757912Shestness@cs.utexas.edu currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 2767912Shestness@cs.utexas.edu } else { 2777912Shestness@cs.utexas.edu currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 2787912Shestness@cs.utexas.edu MISCREG_SCTLR, currState->tc, !currState->isSecure)); 2797912Shestness@cs.utexas.edu currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 2807912Shestness@cs.utexas.edu MISCREG_TTBCR, currState->tc, !currState->isSecure)); 2817912Shestness@cs.utexas.edu currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 2827912Shestness@cs.utexas.edu currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 2837912Shestness@cs.utexas.edu currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 2847912Shestness@cs.utexas.edu } 2857912Shestness@cs.utexas.edu sctlr = currState->sctlr; 2867912Shestness@cs.utexas.edu 2877912Shestness@cs.utexas.edu currState->isFetch = (currState->mode == TLB::Execute); 2887912Shestness@cs.utexas.edu currState->isWrite = (currState->mode == TLB::Write); 2897912Shestness@cs.utexas.edu 2907912Shestness@cs.utexas.edu statRequestOrigin[REQUESTED][currState->isFetch]++; 2917912Shestness@cs.utexas.edu 2927912Shestness@cs.utexas.edu // We only do a second stage of translation if we're not secure, or in 2937912Shestness@cs.utexas.edu // hyp mode, the second stage MMU is enabled, and this table walker 2947912Shestness@cs.utexas.edu // instance is the first stage. 2957912Shestness@cs.utexas.edu currState->doingStage2 = false; 2967912Shestness@cs.utexas.edu currState->stage2Req = currState->hcr.vm && !isStage2 && 2977912Shestness@cs.utexas.edu !currState->isSecure && !currState->isHyp; 2987912Shestness@cs.utexas.edu 2997912Shestness@cs.utexas.edu bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 3007912Shestness@cs.utexas.edu longDescFormatInUse(currState->tc); 3017912Shestness@cs.utexas.edu 3027912Shestness@cs.utexas.edu if (long_desc_format) { 3037912Shestness@cs.utexas.edu // Helper variables used for hierarchical permissions 3047912Shestness@cs.utexas.edu currState->secureLookup = currState->isSecure; 3057912Shestness@cs.utexas.edu currState->rwTable = true; 3067912Shestness@cs.utexas.edu currState->userTable = true; 3077912Shestness@cs.utexas.edu currState->xnTable = false; 3087912Shestness@cs.utexas.edu currState->pxnTable = false; 3097912Shestness@cs.utexas.edu 3107912Shestness@cs.utexas.edu ++statWalksLongDescriptor; 3117912Shestness@cs.utexas.edu } else { 3127912Shestness@cs.utexas.edu ++statWalksShortDescriptor; 3137912Shestness@cs.utexas.edu } 3147912Shestness@cs.utexas.edu 3157912Shestness@cs.utexas.edu if (!currState->timing) { 3167912Shestness@cs.utexas.edu Fault fault = NoFault; 3177912Shestness@cs.utexas.edu if (currState->aarch64) 3187912Shestness@cs.utexas.edu fault = processWalkAArch64(); 3197912Shestness@cs.utexas.edu else if (long_desc_format) 3207912Shestness@cs.utexas.edu fault = processWalkLPAE(); 3217912Shestness@cs.utexas.edu else 3227912Shestness@cs.utexas.edu fault = processWalk(); 3237912Shestness@cs.utexas.edu 3247912Shestness@cs.utexas.edu // If this was a functional non-timing access restore state to 3257912Shestness@cs.utexas.edu // how we found it. 3267912Shestness@cs.utexas.edu if (currState->functional) { 3277912Shestness@cs.utexas.edu delete currState; 3287912Shestness@cs.utexas.edu currState = savedCurrState; 3297912Shestness@cs.utexas.edu } 3307912Shestness@cs.utexas.edu return fault; 3317912Shestness@cs.utexas.edu } 3327912Shestness@cs.utexas.edu 3337912Shestness@cs.utexas.edu if (pending || pendingQueue.size()) { 3347912Shestness@cs.utexas.edu pendingQueue.push_back(currState); 3357912Shestness@cs.utexas.edu currState = NULL; 3367912Shestness@cs.utexas.edu pendingChange(); 3377912Shestness@cs.utexas.edu } else { 3387912Shestness@cs.utexas.edu pending = true; 3397912Shestness@cs.utexas.edu pendingChange(); 3407912Shestness@cs.utexas.edu if (currState->aarch64) 3417912Shestness@cs.utexas.edu return processWalkAArch64(); 3427912Shestness@cs.utexas.edu else if (long_desc_format) 3437912Shestness@cs.utexas.edu return processWalkLPAE(); 3447912Shestness@cs.utexas.edu else 3457912Shestness@cs.utexas.edu return processWalk(); 3467912Shestness@cs.utexas.edu } 3477912Shestness@cs.utexas.edu 3487912Shestness@cs.utexas.edu return NoFault; 3497912Shestness@cs.utexas.edu} 3507912Shestness@cs.utexas.edu 3517912Shestness@cs.utexas.eduvoid 3527912Shestness@cs.utexas.eduTableWalker::processWalkWrapper() 3537912Shestness@cs.utexas.edu{ 3547912Shestness@cs.utexas.edu assert(!currState); 3557912Shestness@cs.utexas.edu assert(pendingQueue.size()); 3567912Shestness@cs.utexas.edu pendingChange(); 3577912Shestness@cs.utexas.edu currState = pendingQueue.front(); 3587912Shestness@cs.utexas.edu 3597912Shestness@cs.utexas.edu ExceptionLevel target_el = EL0; 3607912Shestness@cs.utexas.edu if (currState->aarch64) 3617912Shestness@cs.utexas.edu target_el = currEL(currState->tc); 3627912Shestness@cs.utexas.edu else 3637912Shestness@cs.utexas.edu target_el = EL1; 3647912Shestness@cs.utexas.edu 3657912Shestness@cs.utexas.edu // Check if a previous walk filled this request already 3667912Shestness@cs.utexas.edu // @TODO Should this always be the TLB or should we look in the stage2 TLB? 3677912Shestness@cs.utexas.edu TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 3687912Shestness@cs.utexas.edu currState->vmid, currState->isHyp, currState->isSecure, true, false, 3697912Shestness@cs.utexas.edu target_el); 3707912Shestness@cs.utexas.edu 3717912Shestness@cs.utexas.edu // Check if we still need to have a walk for this request. If the requesting 3727912Shestness@cs.utexas.edu // instruction has been squashed, or a previous walk has filled the TLB with 3737912Shestness@cs.utexas.edu // a match, we just want to get rid of the walk. The latter could happen 3747912Shestness@cs.utexas.edu // when there are multiple outstanding misses to a single page and a 3757912Shestness@cs.utexas.edu // previous request has been successfully translated. 3767912Shestness@cs.utexas.edu if (!currState->transState->squashed() && !te) { 3777912Shestness@cs.utexas.edu // We've got a valid request, lets process it 3787912Shestness@cs.utexas.edu pending = true; 3797912Shestness@cs.utexas.edu pendingQueue.pop_front(); 3807912Shestness@cs.utexas.edu // Keep currState in case one of the processWalk... calls NULLs it 3817912Shestness@cs.utexas.edu WalkerState *curr_state_copy = currState; 3827912Shestness@cs.utexas.edu Fault f; 3837912Shestness@cs.utexas.edu if (currState->aarch64) 3847912Shestness@cs.utexas.edu f = processWalkAArch64(); 3857912Shestness@cs.utexas.edu else if (longDescFormatInUse(currState->tc) || 3867912Shestness@cs.utexas.edu currState->isHyp || isStage2) 3877912Shestness@cs.utexas.edu f = processWalkLPAE(); 3887912Shestness@cs.utexas.edu else 3897912Shestness@cs.utexas.edu f = processWalk(); 3907912Shestness@cs.utexas.edu 3917912Shestness@cs.utexas.edu if (f != NoFault) { 3927912Shestness@cs.utexas.edu curr_state_copy->transState->finish(f, curr_state_copy->req, 3937912Shestness@cs.utexas.edu curr_state_copy->tc, curr_state_copy->mode); 3947912Shestness@cs.utexas.edu 3957912Shestness@cs.utexas.edu delete curr_state_copy; 3967912Shestness@cs.utexas.edu } 3977912Shestness@cs.utexas.edu return; 3987912Shestness@cs.utexas.edu } 3997912Shestness@cs.utexas.edu 4007912Shestness@cs.utexas.edu 4017912Shestness@cs.utexas.edu // If the instruction that we were translating for has been 4027912Shestness@cs.utexas.edu // squashed we shouldn't bother. 4037912Shestness@cs.utexas.edu unsigned num_squashed = 0; 4047912Shestness@cs.utexas.edu ThreadContext *tc = currState->tc; 4057912Shestness@cs.utexas.edu while ((num_squashed < numSquashable) && currState && 4067912Shestness@cs.utexas.edu (currState->transState->squashed() || te)) { 4077912Shestness@cs.utexas.edu pendingQueue.pop_front(); 4087912Shestness@cs.utexas.edu num_squashed++; 4097912Shestness@cs.utexas.edu statSquashedBefore++; 4107912Shestness@cs.utexas.edu 4117912Shestness@cs.utexas.edu DPRINTF(TLB, "Squashing table walk for address %#x\n", 4127912Shestness@cs.utexas.edu currState->vaddr_tainted); 4137912Shestness@cs.utexas.edu 4147912Shestness@cs.utexas.edu if (currState->transState->squashed()) { 4157912Shestness@cs.utexas.edu // finish the translation which will delete the translation object 4167912Shestness@cs.utexas.edu currState->transState->finish( 4177912Shestness@cs.utexas.edu std::make_shared<UnimpFault>("Squashed Inst"), 4187912Shestness@cs.utexas.edu currState->req, currState->tc, currState->mode); 4197912Shestness@cs.utexas.edu } else { 4207912Shestness@cs.utexas.edu // translate the request now that we know it will work 4217912Shestness@cs.utexas.edu statWalkServiceTime.sample(curTick() - currState->startTime); 4227912Shestness@cs.utexas.edu tlb->translateTiming(currState->req, currState->tc, 4237912Shestness@cs.utexas.edu currState->transState, currState->mode); 4247912Shestness@cs.utexas.edu 4257912Shestness@cs.utexas.edu } 4267912Shestness@cs.utexas.edu 4277912Shestness@cs.utexas.edu // delete the current request 4287912Shestness@cs.utexas.edu delete currState; 4297912Shestness@cs.utexas.edu 4307912Shestness@cs.utexas.edu // peak at the next one 4317912Shestness@cs.utexas.edu if (pendingQueue.size()) { 4327912Shestness@cs.utexas.edu currState = pendingQueue.front(); 4337912Shestness@cs.utexas.edu te = tlb->lookup(currState->vaddr, currState->asid, 4347912Shestness@cs.utexas.edu currState->vmid, currState->isHyp, currState->isSecure, true, 4357912Shestness@cs.utexas.edu false, target_el); 4367912Shestness@cs.utexas.edu } else { 4377912Shestness@cs.utexas.edu // Terminate the loop, nothing more to do 4387912Shestness@cs.utexas.edu currState = NULL; 4397912Shestness@cs.utexas.edu } 4407912Shestness@cs.utexas.edu } 4417912Shestness@cs.utexas.edu pendingChange(); 4427912Shestness@cs.utexas.edu 4437912Shestness@cs.utexas.edu // if we still have pending translations, schedule more work 4447912Shestness@cs.utexas.edu nextWalk(tc); 4457912Shestness@cs.utexas.edu currState = NULL; 4467912Shestness@cs.utexas.edu} 4477912Shestness@cs.utexas.edu 4487912Shestness@cs.utexas.eduFault 4497912Shestness@cs.utexas.eduTableWalker::processWalk() 4507912Shestness@cs.utexas.edu{ 4517912Shestness@cs.utexas.edu Addr ttbr = 0; 4527912Shestness@cs.utexas.edu 4537912Shestness@cs.utexas.edu // If translation isn't enabled, we shouldn't be here 4547912Shestness@cs.utexas.edu assert(currState->sctlr.m || isStage2); 4557912Shestness@cs.utexas.edu 4567912Shestness@cs.utexas.edu DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 4577912Shestness@cs.utexas.edu currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 4587912Shestness@cs.utexas.edu 32 - currState->ttbcr.n)); 4597912Shestness@cs.utexas.edu 4607912Shestness@cs.utexas.edu statWalkWaitTime.sample(curTick() - currState->startTime); 4617912Shestness@cs.utexas.edu 4627912Shestness@cs.utexas.edu if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 4637912Shestness@cs.utexas.edu 32 - currState->ttbcr.n)) { 4647912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR0\n"); 4657912Shestness@cs.utexas.edu // Check if table walk is allowed when Security Extensions are enabled 4667912Shestness@cs.utexas.edu if (haveSecurity && currState->ttbcr.pd0) { 4677912Shestness@cs.utexas.edu if (currState->isFetch) 4687912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 4697912Shestness@cs.utexas.edu currState->vaddr_tainted, 4707912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 4717912Shestness@cs.utexas.edu isStage2, 4727912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4737912Shestness@cs.utexas.edu else 4747912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 4757912Shestness@cs.utexas.edu currState->vaddr_tainted, 4767912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, currState->isWrite, 4777912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, isStage2, 4787912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4797912Shestness@cs.utexas.edu } 4807912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 4817912Shestness@cs.utexas.edu MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4827912Shestness@cs.utexas.edu } else { 4837912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR1\n"); 4847912Shestness@cs.utexas.edu // Check if table walk is allowed when Security Extensions are enabled 4857912Shestness@cs.utexas.edu if (haveSecurity && currState->ttbcr.pd1) { 4867912Shestness@cs.utexas.edu if (currState->isFetch) 4877912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 4887912Shestness@cs.utexas.edu currState->vaddr_tainted, 4897912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 4907912Shestness@cs.utexas.edu isStage2, 4917912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4927912Shestness@cs.utexas.edu else 4937912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 4947912Shestness@cs.utexas.edu currState->vaddr_tainted, 4957912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, currState->isWrite, 4967912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, isStage2, 4977912Shestness@cs.utexas.edu ArmFault::VmsaTran); 4987912Shestness@cs.utexas.edu } 4997912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 5007912Shestness@cs.utexas.edu MISCREG_TTBR1, currState->tc, !currState->isSecure)); 5017912Shestness@cs.utexas.edu currState->ttbcr.n = 0; 5027912Shestness@cs.utexas.edu } 5037912Shestness@cs.utexas.edu 5047912Shestness@cs.utexas.edu Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 5057912Shestness@cs.utexas.edu (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 5067912Shestness@cs.utexas.edu DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 5077912Shestness@cs.utexas.edu currState->isSecure ? "s" : "ns"); 5087912Shestness@cs.utexas.edu 5097912Shestness@cs.utexas.edu // Trickbox address check 5107912Shestness@cs.utexas.edu Fault f; 5117912Shestness@cs.utexas.edu f = testWalk(l1desc_addr, sizeof(uint32_t), 5127912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, L1); 5137912Shestness@cs.utexas.edu if (f) { 5147912Shestness@cs.utexas.edu DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5157912Shestness@cs.utexas.edu if (currState->timing) { 5167912Shestness@cs.utexas.edu pending = false; 5177912Shestness@cs.utexas.edu nextWalk(currState->tc); 5187912Shestness@cs.utexas.edu currState = NULL; 5197912Shestness@cs.utexas.edu } else { 5207912Shestness@cs.utexas.edu currState->tc = NULL; 5217912Shestness@cs.utexas.edu currState->req = NULL; 5227912Shestness@cs.utexas.edu } 5237912Shestness@cs.utexas.edu return f; 5247912Shestness@cs.utexas.edu } 5257912Shestness@cs.utexas.edu 5267912Shestness@cs.utexas.edu Request::Flags flag = Request::PT_WALK; 5277912Shestness@cs.utexas.edu if (currState->sctlr.c == 0) { 5287912Shestness@cs.utexas.edu flag.set(Request::UNCACHEABLE); 5297912Shestness@cs.utexas.edu } 5307912Shestness@cs.utexas.edu 5317912Shestness@cs.utexas.edu if (currState->isSecure) { 5327912Shestness@cs.utexas.edu flag.set(Request::SECURE); 5337912Shestness@cs.utexas.edu } 5347912Shestness@cs.utexas.edu 5357912Shestness@cs.utexas.edu bool delayed; 5367912Shestness@cs.utexas.edu delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 5377912Shestness@cs.utexas.edu sizeof(uint32_t), flag, L1, &doL1DescEvent, 5387912Shestness@cs.utexas.edu &TableWalker::doL1Descriptor); 5397912Shestness@cs.utexas.edu if (!delayed) { 5407912Shestness@cs.utexas.edu f = currState->fault; 5417912Shestness@cs.utexas.edu } 5427912Shestness@cs.utexas.edu 5437912Shestness@cs.utexas.edu return f; 5447912Shestness@cs.utexas.edu} 5457912Shestness@cs.utexas.edu 5467912Shestness@cs.utexas.eduFault 5477912Shestness@cs.utexas.eduTableWalker::processWalkLPAE() 5487912Shestness@cs.utexas.edu{ 5497912Shestness@cs.utexas.edu Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 5507912Shestness@cs.utexas.edu int tsz, n; 5517912Shestness@cs.utexas.edu LookupLevel start_lookup_level = L1; 5527912Shestness@cs.utexas.edu 5537912Shestness@cs.utexas.edu DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 5547912Shestness@cs.utexas.edu currState->vaddr_tainted, currState->ttbcr); 5557912Shestness@cs.utexas.edu 5567912Shestness@cs.utexas.edu statWalkWaitTime.sample(curTick() - currState->startTime); 5577912Shestness@cs.utexas.edu 5587912Shestness@cs.utexas.edu Request::Flags flag = Request::PT_WALK; 5597912Shestness@cs.utexas.edu if (currState->isSecure) 5607912Shestness@cs.utexas.edu flag.set(Request::SECURE); 5617912Shestness@cs.utexas.edu 5627912Shestness@cs.utexas.edu // work out which base address register to use, if in hyp mode we always 5637912Shestness@cs.utexas.edu // use HTTBR 5647912Shestness@cs.utexas.edu if (isStage2) { 5657912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 5667912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 5677912Shestness@cs.utexas.edu tsz = sext<4>(currState->vtcr.t0sz); 5687912Shestness@cs.utexas.edu start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 5697912Shestness@cs.utexas.edu } else if (currState->isHyp) { 5707912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 5717912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 5727912Shestness@cs.utexas.edu tsz = currState->htcr.t0sz; 5737912Shestness@cs.utexas.edu } else { 5747912Shestness@cs.utexas.edu assert(longDescFormatInUse(currState->tc)); 5757912Shestness@cs.utexas.edu 5767912Shestness@cs.utexas.edu // Determine boundaries of TTBR0/1 regions 5777912Shestness@cs.utexas.edu if (currState->ttbcr.t0sz) 5787912Shestness@cs.utexas.edu ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 5797912Shestness@cs.utexas.edu else if (currState->ttbcr.t1sz) 5807912Shestness@cs.utexas.edu ttbr0_max = (1ULL << 32) - 5817912Shestness@cs.utexas.edu (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 5827912Shestness@cs.utexas.edu else 5837912Shestness@cs.utexas.edu ttbr0_max = (1ULL << 32) - 1; 5847912Shestness@cs.utexas.edu if (currState->ttbcr.t1sz) 5857912Shestness@cs.utexas.edu ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 5867912Shestness@cs.utexas.edu else 5877912Shestness@cs.utexas.edu ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 5887912Shestness@cs.utexas.edu 5897912Shestness@cs.utexas.edu // The following code snippet selects the appropriate translation table base 5907912Shestness@cs.utexas.edu // address (TTBR0 or TTBR1) and the appropriate starting lookup level 5917912Shestness@cs.utexas.edu // depending on the address range supported by the translation table (ARM 5927912Shestness@cs.utexas.edu // ARM issue C B3.6.4) 5937912Shestness@cs.utexas.edu if (currState->vaddr <= ttbr0_max) { 5947912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 5957912Shestness@cs.utexas.edu // Check if table walk is allowed 5967912Shestness@cs.utexas.edu if (currState->ttbcr.epd0) { 5977912Shestness@cs.utexas.edu if (currState->isFetch) 5987912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 5997912Shestness@cs.utexas.edu currState->vaddr_tainted, 6007912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6017912Shestness@cs.utexas.edu isStage2, 6027912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6037912Shestness@cs.utexas.edu else 6047912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 6057912Shestness@cs.utexas.edu currState->vaddr_tainted, 6067912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, 6077912Shestness@cs.utexas.edu currState->isWrite, 6087912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6097912Shestness@cs.utexas.edu isStage2, 6107912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6117912Shestness@cs.utexas.edu } 6127912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 6137912Shestness@cs.utexas.edu MISCREG_TTBR0, currState->tc, !currState->isSecure)); 6147912Shestness@cs.utexas.edu tsz = currState->ttbcr.t0sz; 6157912Shestness@cs.utexas.edu if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 6167912Shestness@cs.utexas.edu start_lookup_level = L2; 6177912Shestness@cs.utexas.edu } else if (currState->vaddr >= ttbr1_min) { 6187912Shestness@cs.utexas.edu DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 6197912Shestness@cs.utexas.edu // Check if table walk is allowed 6207912Shestness@cs.utexas.edu if (currState->ttbcr.epd1) { 6217912Shestness@cs.utexas.edu if (currState->isFetch) 6227912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 6237912Shestness@cs.utexas.edu currState->vaddr_tainted, 6247912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6257912Shestness@cs.utexas.edu isStage2, 6267912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6277912Shestness@cs.utexas.edu else 6287912Shestness@cs.utexas.edu return std::make_shared<DataAbort>( 6297912Shestness@cs.utexas.edu currState->vaddr_tainted, 6307912Shestness@cs.utexas.edu TlbEntry::DomainType::NoAccess, 6317912Shestness@cs.utexas.edu currState->isWrite, 6327912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6337912Shestness@cs.utexas.edu isStage2, 6347912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6357912Shestness@cs.utexas.edu } 6367912Shestness@cs.utexas.edu ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 6377912Shestness@cs.utexas.edu MISCREG_TTBR1, currState->tc, !currState->isSecure)); 6387912Shestness@cs.utexas.edu tsz = currState->ttbcr.t1sz; 6397912Shestness@cs.utexas.edu if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 6407912Shestness@cs.utexas.edu start_lookup_level = L2; 6417912Shestness@cs.utexas.edu } else { 6427912Shestness@cs.utexas.edu // Out of boundaries -> translation fault 6437912Shestness@cs.utexas.edu if (currState->isFetch) 6447912Shestness@cs.utexas.edu return std::make_shared<PrefetchAbort>( 6457912Shestness@cs.utexas.edu currState->vaddr_tainted, 6467912Shestness@cs.utexas.edu ArmFault::TranslationLL + L1, 6477912Shestness@cs.utexas.edu isStage2, 6487912Shestness@cs.utexas.edu ArmFault::LpaeTran); 6497912Shestness@cs.utexas.edu else 6505245Sgblack@eecs.umich.edu return std::make_shared<DataAbort>( 6515245Sgblack@eecs.umich.edu currState->vaddr_tainted, 6525245Sgblack@eecs.umich.edu TlbEntry::DomainType::NoAccess, 6535245Sgblack@eecs.umich.edu currState->isWrite, ArmFault::TranslationLL + L1, 6545245Sgblack@eecs.umich.edu isStage2, ArmFault::LpaeTran); 6555245Sgblack@eecs.umich.edu } 6565245Sgblack@eecs.umich.edu 6575897Sgblack@eecs.umich.edu } 6585897Sgblack@eecs.umich.edu 6595897Sgblack@eecs.umich.edu // Perform lookup (ARM ARM issue C B3.6.6) 6607912Shestness@cs.utexas.edu if (start_lookup_level == L1) { 6615245Sgblack@eecs.umich.edu n = 5 - tsz; 6625897Sgblack@eecs.umich.edu desc_addr = mbits(ttbr, 39, n) | 6635897Sgblack@eecs.umich.edu (bits(currState->vaddr, n + 26, 30) << 3); 6645245Sgblack@eecs.umich.edu DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 6655245Sgblack@eecs.umich.edu desc_addr, currState->isSecure ? "s" : "ns"); 6665245Sgblack@eecs.umich.edu } else { 6675245Sgblack@eecs.umich.edu // Skip first-level lookup 6685245Sgblack@eecs.umich.edu n = (tsz >= 2 ? 14 - tsz : 12); 6695245Sgblack@eecs.umich.edu desc_addr = mbits(ttbr, 39, n) | 6705897Sgblack@eecs.umich.edu (bits(currState->vaddr, n + 17, 21) << 3); 6715897Sgblack@eecs.umich.edu DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 6727912Shestness@cs.utexas.edu desc_addr, currState->isSecure ? "s" : "ns"); 6735245Sgblack@eecs.umich.edu } 6745897Sgblack@eecs.umich.edu 6755897Sgblack@eecs.umich.edu // Trickbox address check 6765245Sgblack@eecs.umich.edu Fault f = testWalk(desc_addr, sizeof(uint64_t), 6775245Sgblack@eecs.umich.edu TlbEntry::DomainType::NoAccess, start_lookup_level); 6785245Sgblack@eecs.umich.edu if (f) { 6795245Sgblack@eecs.umich.edu DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 6805245Sgblack@eecs.umich.edu if (currState->timing) { 6817912Shestness@cs.utexas.edu pending = false; 6827912Shestness@cs.utexas.edu nextWalk(currState->tc); 6835245Sgblack@eecs.umich.edu currState = NULL; 6847912Shestness@cs.utexas.edu } else { 6857912Shestness@cs.utexas.edu currState->tc = NULL; 6867912Shestness@cs.utexas.edu currState->req = NULL; 6877912Shestness@cs.utexas.edu } 6887912Shestness@cs.utexas.edu return f; 6897912Shestness@cs.utexas.edu } 6907912Shestness@cs.utexas.edu 6917912Shestness@cs.utexas.edu if (currState->sctlr.c == 0) { 6927912Shestness@cs.utexas.edu flag.set(Request::UNCACHEABLE); 6937912Shestness@cs.utexas.edu } 6947912Shestness@cs.utexas.edu 6957912Shestness@cs.utexas.edu currState->longDesc.lookupLevel = start_lookup_level; 6967912Shestness@cs.utexas.edu currState->longDesc.aarch64 = false; 6977912Shestness@cs.utexas.edu currState->longDesc.grainSize = Grain4KB; 6987912Shestness@cs.utexas.edu 6997912Shestness@cs.utexas.edu Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent 7007912Shestness@cs.utexas.edu : (Event *) &doL2LongDescEvent; 7017912Shestness@cs.utexas.edu 7027912Shestness@cs.utexas.edu bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 7037912Shestness@cs.utexas.edu sizeof(uint64_t), flag, start_lookup_level, 7045245Sgblack@eecs.umich.edu event, &TableWalker::doLongDescriptor); 7055245Sgblack@eecs.umich.edu if (!delayed) { 7065895Sgblack@eecs.umich.edu f = currState->fault; 7077912Shestness@cs.utexas.edu } 7085895Sgblack@eecs.umich.edu 7095904Sgblack@eecs.umich.edu return f; 7105895Sgblack@eecs.umich.edu} 7116023Snate@binkert.org 7126023Snate@binkert.orgunsigned 7136023Snate@binkert.orgTableWalker::adjustTableSizeAArch64(unsigned tsz) 7145895Sgblack@eecs.umich.edu{ 7155895Sgblack@eecs.umich.edu if (tsz < 25) 7167912Shestness@cs.utexas.edu return 25; 7175245Sgblack@eecs.umich.edu if (tsz > 48) 7185245Sgblack@eecs.umich.edu return 48; 7195245Sgblack@eecs.umich.edu return tsz; 7205245Sgblack@eecs.umich.edu} 7215245Sgblack@eecs.umich.edu 7225245Sgblack@eecs.umich.edubool 723TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 724{ 725 return (currPhysAddrRange != MaxPhysAddrRange && 726 bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 727} 728 729Fault 730TableWalker::processWalkAArch64() 731{ 732 assert(currState->aarch64); 733 734 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 735 currState->vaddr_tainted, currState->tcr); 736 737 static const GrainSize GrainMapDefault[] = 738 { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 739 static const GrainSize GrainMap_EL1_tg1[] = 740 { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 741 742 statWalkWaitTime.sample(curTick() - currState->startTime); 743 744 // Determine TTBR, table size, granule size and phys. address range 745 Addr ttbr = 0; 746 int tsz = 0, ps = 0; 747 GrainSize tg = Grain4KB; // grain size computed from tg* field 748 bool fault = false; 749 750 LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 751 752 switch (currState->el) { 753 case EL0: 754 case EL1: 755 if (isStage2) { 756 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 757 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 758 tsz = 64 - currState->vtcr.t0sz64; 759 tg = GrainMapDefault[currState->vtcr.tg0]; 760 // ARM DDI 0487A.f D7-2148 761 // The starting level of stage 2 translation depends on 762 // VTCR_EL2.SL0 and VTCR_EL2.TG0 763 LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 764 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 765 static const LookupLevel SLL[] = { 766 L2, L3, L3, __, // sl0 == 0 767 L1, L2, L2, __, // sl0 == 1, etc. 768 L0, L1, L1, __, 769 __, __, __, __ 770 }; 771 start_lookup_level = SLL[sl_tg]; 772 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 773 "Cannot discern lookup level from vtcr.{sl0,tg0}"); 774 } else switch (bits(currState->vaddr, 63,48)) { 775 case 0: 776 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 777 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 778 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 779 tg = GrainMapDefault[currState->tcr.tg0]; 780 if (bits(currState->vaddr, 63, tsz) != 0x0 || 781 currState->tcr.epd0) 782 fault = true; 783 break; 784 case 0xffff: 785 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 786 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 787 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 788 tg = GrainMap_EL1_tg1[currState->tcr.tg1]; 789 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 790 currState->tcr.epd1) 791 fault = true; 792 break; 793 default: 794 // top two bytes must be all 0s or all 1s, else invalid addr 795 fault = true; 796 } 797 ps = currState->tcr.ips; 798 break; 799 case EL2: 800 case EL3: 801 switch(bits(currState->vaddr, 63,48)) { 802 case 0: 803 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 804 if (currState->el == EL2) 805 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 806 else 807 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 808 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 809 tg = GrainMapDefault[currState->tcr.tg0]; 810 break; 811 default: 812 // invalid addr if top two bytes are not all 0s 813 fault = true; 814 } 815 ps = currState->tcr.ips; 816 break; 817 } 818 819 if (fault) { 820 Fault f; 821 if (currState->isFetch) 822 f = std::make_shared<PrefetchAbort>( 823 currState->vaddr_tainted, 824 ArmFault::TranslationLL + L0, isStage2, 825 ArmFault::LpaeTran); 826 else 827 f = std::make_shared<DataAbort>( 828 currState->vaddr_tainted, 829 TlbEntry::DomainType::NoAccess, 830 currState->isWrite, 831 ArmFault::TranslationLL + L0, 832 isStage2, ArmFault::LpaeTran); 833 834 if (currState->timing) { 835 pending = false; 836 nextWalk(currState->tc); 837 currState = NULL; 838 } else { 839 currState->tc = NULL; 840 currState->req = NULL; 841 } 842 return f; 843 844 } 845 846 if (tg == ReservedGrain) { 847 warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 848 "DEFINED behavior takes this to mean 4KB granules\n"); 849 tg = Grain4KB; 850 } 851 852 // Determine starting lookup level 853 // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 854 // in ARM DDI 0487A. These table values correspond to the cascading tests 855 // to compute the lookup level and are of the form 856 // (grain_size + N*stride), for N = {1, 2, 3}. 857 // A value of 64 will never succeed and a value of 0 will always succeed. 858 if (start_lookup_level == MAX_LOOKUP_LEVELS) { 859 struct GrainMap { 860 GrainSize grain_size; 861 unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 862 }; 863 static const GrainMap GM[] = { 864 { Grain4KB, { 39, 30, 0, 0 } }, 865 { Grain16KB, { 47, 36, 25, 0 } }, 866 { Grain64KB, { 64, 42, 29, 0 } } 867 }; 868 869 const unsigned *lookup = NULL; // points to a lookup_level_cutoff 870 871 for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 872 if (tg == GM[i].grain_size) { 873 lookup = GM[i].lookup_level_cutoff; 874 break; 875 } 876 } 877 assert(lookup); 878 879 for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 880 if (tsz > lookup[L]) { 881 start_lookup_level = (LookupLevel) L; 882 break; 883 } 884 } 885 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 886 "Table walker couldn't find lookup level\n"); 887 } 888 889 int stride = tg - 3; 890 891 // Determine table base address 892 int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 893 Addr base_addr = mbits(ttbr, 47, base_addr_lo); 894 895 // Determine physical address size and raise an Address Size Fault if 896 // necessary 897 int pa_range = decodePhysAddrRange64(ps); 898 // Clamp to lower limit 899 if (pa_range > physAddrRange) 900 currState->physAddrRange = physAddrRange; 901 else 902 currState->physAddrRange = pa_range; 903 if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 904 DPRINTF(TLB, "Address size fault before any lookup\n"); 905 Fault f; 906 if (currState->isFetch) 907 f = std::make_shared<PrefetchAbort>( 908 currState->vaddr_tainted, 909 ArmFault::AddressSizeLL + start_lookup_level, 910 isStage2, 911 ArmFault::LpaeTran); 912 else 913 f = std::make_shared<DataAbort>( 914 currState->vaddr_tainted, 915 TlbEntry::DomainType::NoAccess, 916 currState->isWrite, 917 ArmFault::AddressSizeLL + start_lookup_level, 918 isStage2, 919 ArmFault::LpaeTran); 920 921 922 if (currState->timing) { 923 pending = false; 924 nextWalk(currState->tc); 925 currState = NULL; 926 } else { 927 currState->tc = NULL; 928 currState->req = NULL; 929 } 930 return f; 931 932 } 933 934 // Determine descriptor address 935 Addr desc_addr = base_addr | 936 (bits(currState->vaddr, tsz - 1, 937 stride * (3 - start_lookup_level) + tg) << 3); 938 939 // Trickbox address check 940 Fault f = testWalk(desc_addr, sizeof(uint64_t), 941 TlbEntry::DomainType::NoAccess, start_lookup_level); 942 if (f) { 943 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 944 if (currState->timing) { 945 pending = false; 946 nextWalk(currState->tc); 947 currState = NULL; 948 } else { 949 currState->tc = NULL; 950 currState->req = NULL; 951 } 952 return f; 953 } 954 955 Request::Flags flag = Request::PT_WALK; 956 if (currState->sctlr.c == 0) { 957 flag.set(Request::UNCACHEABLE); 958 } 959 960 if (currState->isSecure) { 961 flag.set(Request::SECURE); 962 } 963 964 currState->longDesc.lookupLevel = start_lookup_level; 965 currState->longDesc.aarch64 = true; 966 currState->longDesc.grainSize = tg; 967 968 if (currState->timing) { 969 Event *event; 970 switch (start_lookup_level) { 971 case L0: 972 event = (Event *) &doL0LongDescEvent; 973 break; 974 case L1: 975 event = (Event *) &doL1LongDescEvent; 976 break; 977 case L2: 978 event = (Event *) &doL2LongDescEvent; 979 break; 980 case L3: 981 event = (Event *) &doL3LongDescEvent; 982 break; 983 default: 984 panic("Invalid table lookup level"); 985 break; 986 } 987 port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 988 event, (uint8_t*) &currState->longDesc.data, 989 currState->tc->getCpuPtr()->clockPeriod(), flag); 990 DPRINTF(TLBVerbose, 991 "Adding to walker fifo: queue size before adding: %d\n", 992 stateQueues[start_lookup_level].size()); 993 stateQueues[start_lookup_level].push_back(currState); 994 currState = NULL; 995 } else { 996 fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 997 sizeof(uint64_t), flag, -1, NULL, 998 &TableWalker::doLongDescriptor); 999 f = currState->fault; 1000 } 1001 1002 return f; 1003} 1004 1005void 1006TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 1007 uint8_t texcb, bool s) 1008{ 1009 // Note: tc and sctlr local variables are hiding tc and sctrl class 1010 // variables 1011 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1012 te.shareable = false; // default value 1013 te.nonCacheable = false; 1014 te.outerShareable = false; 1015 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 1016 switch(texcb) { 1017 case 0: // Stongly-ordered 1018 te.nonCacheable = true; 1019 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1020 te.shareable = true; 1021 te.innerAttrs = 1; 1022 te.outerAttrs = 0; 1023 break; 1024 case 1: // Shareable Device 1025 te.nonCacheable = true; 1026 te.mtype = TlbEntry::MemoryType::Device; 1027 te.shareable = true; 1028 te.innerAttrs = 3; 1029 te.outerAttrs = 0; 1030 break; 1031 case 2: // Outer and Inner Write-Through, no Write-Allocate 1032 te.mtype = TlbEntry::MemoryType::Normal; 1033 te.shareable = s; 1034 te.innerAttrs = 6; 1035 te.outerAttrs = bits(texcb, 1, 0); 1036 break; 1037 case 3: // Outer and Inner Write-Back, no Write-Allocate 1038 te.mtype = TlbEntry::MemoryType::Normal; 1039 te.shareable = s; 1040 te.innerAttrs = 7; 1041 te.outerAttrs = bits(texcb, 1, 0); 1042 break; 1043 case 4: // Outer and Inner Non-cacheable 1044 te.nonCacheable = true; 1045 te.mtype = TlbEntry::MemoryType::Normal; 1046 te.shareable = s; 1047 te.innerAttrs = 0; 1048 te.outerAttrs = bits(texcb, 1, 0); 1049 break; 1050 case 5: // Reserved 1051 panic("Reserved texcb value!\n"); 1052 break; 1053 case 6: // Implementation Defined 1054 panic("Implementation-defined texcb value!\n"); 1055 break; 1056 case 7: // Outer and Inner Write-Back, Write-Allocate 1057 te.mtype = TlbEntry::MemoryType::Normal; 1058 te.shareable = s; 1059 te.innerAttrs = 5; 1060 te.outerAttrs = 1; 1061 break; 1062 case 8: // Non-shareable Device 1063 te.nonCacheable = true; 1064 te.mtype = TlbEntry::MemoryType::Device; 1065 te.shareable = false; 1066 te.innerAttrs = 3; 1067 te.outerAttrs = 0; 1068 break; 1069 case 9 ... 15: // Reserved 1070 panic("Reserved texcb value!\n"); 1071 break; 1072 case 16 ... 31: // Cacheable Memory 1073 te.mtype = TlbEntry::MemoryType::Normal; 1074 te.shareable = s; 1075 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 1076 te.nonCacheable = true; 1077 te.innerAttrs = bits(texcb, 1, 0); 1078 te.outerAttrs = bits(texcb, 3, 2); 1079 break; 1080 default: 1081 panic("More than 32 states for 5 bits?\n"); 1082 } 1083 } else { 1084 assert(tc); 1085 PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 1086 currState->tc, !currState->isSecure)); 1087 NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 1088 currState->tc, !currState->isSecure)); 1089 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 1090 uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 1091 switch(bits(texcb, 2,0)) { 1092 case 0: 1093 curr_tr = prrr.tr0; 1094 curr_ir = nmrr.ir0; 1095 curr_or = nmrr.or0; 1096 te.outerShareable = (prrr.nos0 == 0); 1097 break; 1098 case 1: 1099 curr_tr = prrr.tr1; 1100 curr_ir = nmrr.ir1; 1101 curr_or = nmrr.or1; 1102 te.outerShareable = (prrr.nos1 == 0); 1103 break; 1104 case 2: 1105 curr_tr = prrr.tr2; 1106 curr_ir = nmrr.ir2; 1107 curr_or = nmrr.or2; 1108 te.outerShareable = (prrr.nos2 == 0); 1109 break; 1110 case 3: 1111 curr_tr = prrr.tr3; 1112 curr_ir = nmrr.ir3; 1113 curr_or = nmrr.or3; 1114 te.outerShareable = (prrr.nos3 == 0); 1115 break; 1116 case 4: 1117 curr_tr = prrr.tr4; 1118 curr_ir = nmrr.ir4; 1119 curr_or = nmrr.or4; 1120 te.outerShareable = (prrr.nos4 == 0); 1121 break; 1122 case 5: 1123 curr_tr = prrr.tr5; 1124 curr_ir = nmrr.ir5; 1125 curr_or = nmrr.or5; 1126 te.outerShareable = (prrr.nos5 == 0); 1127 break; 1128 case 6: 1129 panic("Imp defined type\n"); 1130 case 7: 1131 curr_tr = prrr.tr7; 1132 curr_ir = nmrr.ir7; 1133 curr_or = nmrr.or7; 1134 te.outerShareable = (prrr.nos7 == 0); 1135 break; 1136 } 1137 1138 switch(curr_tr) { 1139 case 0: 1140 DPRINTF(TLBVerbose, "StronglyOrdered\n"); 1141 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1142 te.nonCacheable = true; 1143 te.innerAttrs = 1; 1144 te.outerAttrs = 0; 1145 te.shareable = true; 1146 break; 1147 case 1: 1148 DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 1149 prrr.ds1, prrr.ds0, s); 1150 te.mtype = TlbEntry::MemoryType::Device; 1151 te.nonCacheable = true; 1152 te.innerAttrs = 3; 1153 te.outerAttrs = 0; 1154 if (prrr.ds1 && s) 1155 te.shareable = true; 1156 if (prrr.ds0 && !s) 1157 te.shareable = true; 1158 break; 1159 case 2: 1160 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 1161 prrr.ns1, prrr.ns0, s); 1162 te.mtype = TlbEntry::MemoryType::Normal; 1163 if (prrr.ns1 && s) 1164 te.shareable = true; 1165 if (prrr.ns0 && !s) 1166 te.shareable = true; 1167 break; 1168 case 3: 1169 panic("Reserved type"); 1170 } 1171 1172 if (te.mtype == TlbEntry::MemoryType::Normal){ 1173 switch(curr_ir) { 1174 case 0: 1175 te.nonCacheable = true; 1176 te.innerAttrs = 0; 1177 break; 1178 case 1: 1179 te.innerAttrs = 5; 1180 break; 1181 case 2: 1182 te.innerAttrs = 6; 1183 break; 1184 case 3: 1185 te.innerAttrs = 7; 1186 break; 1187 } 1188 1189 switch(curr_or) { 1190 case 0: 1191 te.nonCacheable = true; 1192 te.outerAttrs = 0; 1193 break; 1194 case 1: 1195 te.outerAttrs = 1; 1196 break; 1197 case 2: 1198 te.outerAttrs = 2; 1199 break; 1200 case 3: 1201 te.outerAttrs = 3; 1202 break; 1203 } 1204 } 1205 } 1206 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 1207 "outerAttrs: %d\n", 1208 te.shareable, te.innerAttrs, te.outerAttrs); 1209 te.setAttributes(false); 1210} 1211 1212void 1213TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 1214 LongDescriptor &lDescriptor) 1215{ 1216 assert(_haveLPAE); 1217 1218 uint8_t attr; 1219 uint8_t sh = lDescriptor.sh(); 1220 // Different format and source of attributes if this is a stage 2 1221 // translation 1222 if (isStage2) { 1223 attr = lDescriptor.memAttr(); 1224 uint8_t attr_3_2 = (attr >> 2) & 0x3; 1225 uint8_t attr_1_0 = attr & 0x3; 1226 1227 DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 1228 1229 if (attr_3_2 == 0) { 1230 te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 1231 : TlbEntry::MemoryType::Device; 1232 te.outerAttrs = 0; 1233 te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 1234 te.nonCacheable = true; 1235 } else { 1236 te.mtype = TlbEntry::MemoryType::Normal; 1237 te.outerAttrs = attr_3_2 == 1 ? 0 : 1238 attr_3_2 == 2 ? 2 : 1; 1239 te.innerAttrs = attr_1_0 == 1 ? 0 : 1240 attr_1_0 == 2 ? 6 : 5; 1241 te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 1242 } 1243 } else { 1244 uint8_t attrIndx = lDescriptor.attrIndx(); 1245 1246 // LPAE always uses remapping of memory attributes, irrespective of the 1247 // value of SCTLR.TRE 1248 MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 1249 int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, 1250 !currState->isSecure); 1251 uint32_t mair = currState->tc->readMiscReg(reg_as_int); 1252 attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 1253 uint8_t attr_7_4 = bits(attr, 7, 4); 1254 uint8_t attr_3_0 = bits(attr, 3, 0); 1255 DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 1256 1257 // Note: the memory subsystem only cares about the 'cacheable' memory 1258 // attribute. The other attributes are only used to fill the PAR register 1259 // accordingly to provide the illusion of full support 1260 te.nonCacheable = false; 1261 1262 switch (attr_7_4) { 1263 case 0x0: 1264 // Strongly-ordered or Device memory 1265 if (attr_3_0 == 0x0) 1266 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1267 else if (attr_3_0 == 0x4) 1268 te.mtype = TlbEntry::MemoryType::Device; 1269 else 1270 panic("Unpredictable behavior\n"); 1271 te.nonCacheable = true; 1272 te.outerAttrs = 0; 1273 break; 1274 case 0x4: 1275 // Normal memory, Outer Non-cacheable 1276 te.mtype = TlbEntry::MemoryType::Normal; 1277 te.outerAttrs = 0; 1278 if (attr_3_0 == 0x4) 1279 // Inner Non-cacheable 1280 te.nonCacheable = true; 1281 else if (attr_3_0 < 0x8) 1282 panic("Unpredictable behavior\n"); 1283 break; 1284 case 0x8: 1285 case 0x9: 1286 case 0xa: 1287 case 0xb: 1288 case 0xc: 1289 case 0xd: 1290 case 0xe: 1291 case 0xf: 1292 if (attr_7_4 & 0x4) { 1293 te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 1294 } else { 1295 te.outerAttrs = 0x2; 1296 } 1297 // Normal memory, Outer Cacheable 1298 te.mtype = TlbEntry::MemoryType::Normal; 1299 if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 1300 panic("Unpredictable behavior\n"); 1301 break; 1302 default: 1303 panic("Unpredictable behavior\n"); 1304 break; 1305 } 1306 1307 switch (attr_3_0) { 1308 case 0x0: 1309 te.innerAttrs = 0x1; 1310 break; 1311 case 0x4: 1312 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 1313 break; 1314 case 0x8: 1315 case 0x9: 1316 case 0xA: 1317 case 0xB: 1318 te.innerAttrs = 6; 1319 break; 1320 case 0xC: 1321 case 0xD: 1322 case 0xE: 1323 case 0xF: 1324 te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 1325 break; 1326 default: 1327 panic("Unpredictable behavior\n"); 1328 break; 1329 } 1330 } 1331 1332 te.outerShareable = sh == 2; 1333 te.shareable = (sh & 0x2) ? true : false; 1334 te.setAttributes(true); 1335 te.attributes |= (uint64_t) attr << 56; 1336} 1337 1338void 1339TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 1340 uint8_t sh) 1341{ 1342 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 1343 1344 // Select MAIR 1345 uint64_t mair; 1346 switch (currState->el) { 1347 case EL0: 1348 case EL1: 1349 mair = tc->readMiscReg(MISCREG_MAIR_EL1); 1350 break; 1351 case EL2: 1352 mair = tc->readMiscReg(MISCREG_MAIR_EL2); 1353 break; 1354 case EL3: 1355 mair = tc->readMiscReg(MISCREG_MAIR_EL3); 1356 break; 1357 default: 1358 panic("Invalid exception level"); 1359 break; 1360 } 1361 1362 // Select attributes 1363 uint8_t attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 1364 uint8_t attr_lo = bits(attr, 3, 0); 1365 uint8_t attr_hi = bits(attr, 7, 4); 1366 1367 // Memory type 1368 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 1369 1370 // Cacheability 1371 te.nonCacheable = false; 1372 if (te.mtype == TlbEntry::MemoryType::Device || // Device memory 1373 attr_hi == 0x8 || // Normal memory, Outer Non-cacheable 1374 attr_lo == 0x8) { // Normal memory, Inner Non-cacheable 1375 te.nonCacheable = true; 1376 } 1377 1378 te.shareable = sh == 2; 1379 te.outerShareable = (sh & 0x2) ? true : false; 1380 // Attributes formatted according to the 64-bit PAR 1381 te.attributes = ((uint64_t) attr << 56) | 1382 (1 << 11) | // LPAE bit 1383 (te.ns << 9) | // NS bit 1384 (sh << 7); 1385} 1386 1387void 1388TableWalker::doL1Descriptor() 1389{ 1390 if (currState->fault != NoFault) { 1391 return; 1392 } 1393 1394 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 1395 currState->vaddr_tainted, currState->l1Desc.data); 1396 TlbEntry te; 1397 1398 switch (currState->l1Desc.type()) { 1399 case L1Descriptor::Ignore: 1400 case L1Descriptor::Reserved: 1401 if (!currState->timing) { 1402 currState->tc = NULL; 1403 currState->req = NULL; 1404 } 1405 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 1406 if (currState->isFetch) 1407 currState->fault = 1408 std::make_shared<PrefetchAbort>( 1409 currState->vaddr_tainted, 1410 ArmFault::TranslationLL + L1, 1411 isStage2, 1412 ArmFault::VmsaTran); 1413 else 1414 currState->fault = 1415 std::make_shared<DataAbort>( 1416 currState->vaddr_tainted, 1417 TlbEntry::DomainType::NoAccess, 1418 currState->isWrite, 1419 ArmFault::TranslationLL + L1, isStage2, 1420 ArmFault::VmsaTran); 1421 return; 1422 case L1Descriptor::Section: 1423 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 1424 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 1425 * enabled if set, do l1.Desc.setAp0() instead of generating 1426 * AccessFlag0 1427 */ 1428 1429 currState->fault = std::make_shared<DataAbort>( 1430 currState->vaddr_tainted, 1431 currState->l1Desc.domain(), 1432 currState->isWrite, 1433 ArmFault::AccessFlagLL + L1, 1434 isStage2, 1435 ArmFault::VmsaTran); 1436 } 1437 if (currState->l1Desc.supersection()) { 1438 panic("Haven't implemented supersections\n"); 1439 } 1440 insertTableEntry(currState->l1Desc, false); 1441 return; 1442 case L1Descriptor::PageTable: 1443 { 1444 Addr l2desc_addr; 1445 l2desc_addr = currState->l1Desc.l2Addr() | 1446 (bits(currState->vaddr, 19, 12) << 2); 1447 DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 1448 l2desc_addr, currState->isSecure ? "s" : "ns"); 1449 1450 // Trickbox address check 1451 currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 1452 currState->l1Desc.domain(), L2); 1453 1454 if (currState->fault) { 1455 if (!currState->timing) { 1456 currState->tc = NULL; 1457 currState->req = NULL; 1458 } 1459 return; 1460 } 1461 1462 Request::Flags flag = Request::PT_WALK; 1463 if (currState->isSecure) 1464 flag.set(Request::SECURE); 1465 1466 bool delayed; 1467 delayed = fetchDescriptor(l2desc_addr, 1468 (uint8_t*)&currState->l2Desc.data, 1469 sizeof(uint32_t), flag, -1, &doL2DescEvent, 1470 &TableWalker::doL2Descriptor); 1471 if (delayed) { 1472 currState->delayed = true; 1473 } 1474 1475 return; 1476 } 1477 default: 1478 panic("A new type in a 2 bit field?\n"); 1479 } 1480} 1481 1482void 1483TableWalker::doLongDescriptor() 1484{ 1485 if (currState->fault != NoFault) { 1486 return; 1487 } 1488 1489 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 1490 currState->longDesc.lookupLevel, currState->vaddr_tainted, 1491 currState->longDesc.data, 1492 currState->aarch64 ? "AArch64" : "long-desc."); 1493 1494 if ((currState->longDesc.type() == LongDescriptor::Block) || 1495 (currState->longDesc.type() == LongDescriptor::Page)) { 1496 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 1497 "xn: %d, ap: %d, af: %d, type: %d\n", 1498 currState->longDesc.lookupLevel, 1499 currState->longDesc.data, 1500 currState->longDesc.pxn(), 1501 currState->longDesc.xn(), 1502 currState->longDesc.ap(), 1503 currState->longDesc.af(), 1504 currState->longDesc.type()); 1505 } else { 1506 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 1507 currState->longDesc.lookupLevel, 1508 currState->longDesc.data, 1509 currState->longDesc.type()); 1510 } 1511 1512 TlbEntry te; 1513 1514 switch (currState->longDesc.type()) { 1515 case LongDescriptor::Invalid: 1516 if (!currState->timing) { 1517 currState->tc = NULL; 1518 currState->req = NULL; 1519 } 1520 1521 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 1522 currState->longDesc.lookupLevel, 1523 ArmFault::TranslationLL + currState->longDesc.lookupLevel); 1524 if (currState->isFetch) 1525 currState->fault = std::make_shared<PrefetchAbort>( 1526 currState->vaddr_tainted, 1527 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1528 isStage2, 1529 ArmFault::LpaeTran); 1530 else 1531 currState->fault = std::make_shared<DataAbort>( 1532 currState->vaddr_tainted, 1533 TlbEntry::DomainType::NoAccess, 1534 currState->isWrite, 1535 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1536 isStage2, 1537 ArmFault::LpaeTran); 1538 return; 1539 case LongDescriptor::Block: 1540 case LongDescriptor::Page: 1541 { 1542 bool fault = false; 1543 bool aff = false; 1544 // Check for address size fault 1545 if (checkAddrSizeFaultAArch64( 1546 mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 1547 currState->longDesc.offsetBits()), 1548 currState->physAddrRange)) { 1549 fault = true; 1550 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1551 currState->longDesc.lookupLevel); 1552 // Check for access fault 1553 } else if (currState->longDesc.af() == 0) { 1554 fault = true; 1555 DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 1556 currState->longDesc.lookupLevel); 1557 aff = true; 1558 } 1559 if (fault) { 1560 if (currState->isFetch) 1561 currState->fault = std::make_shared<PrefetchAbort>( 1562 currState->vaddr_tainted, 1563 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1564 currState->longDesc.lookupLevel, 1565 isStage2, 1566 ArmFault::LpaeTran); 1567 else 1568 currState->fault = std::make_shared<DataAbort>( 1569 currState->vaddr_tainted, 1570 TlbEntry::DomainType::NoAccess, currState->isWrite, 1571 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1572 currState->longDesc.lookupLevel, 1573 isStage2, 1574 ArmFault::LpaeTran); 1575 } else { 1576 insertTableEntry(currState->longDesc, true); 1577 } 1578 } 1579 return; 1580 case LongDescriptor::Table: 1581 { 1582 // Set hierarchical permission flags 1583 currState->secureLookup = currState->secureLookup && 1584 currState->longDesc.secureTable(); 1585 currState->rwTable = currState->rwTable && 1586 currState->longDesc.rwTable(); 1587 currState->userTable = currState->userTable && 1588 currState->longDesc.userTable(); 1589 currState->xnTable = currState->xnTable || 1590 currState->longDesc.xnTable(); 1591 currState->pxnTable = currState->pxnTable || 1592 currState->longDesc.pxnTable(); 1593 1594 // Set up next level lookup 1595 Addr next_desc_addr = currState->longDesc.nextDescAddr( 1596 currState->vaddr); 1597 1598 DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 1599 currState->longDesc.lookupLevel, 1600 currState->longDesc.lookupLevel + 1, 1601 next_desc_addr, 1602 currState->secureLookup ? "s" : "ns"); 1603 1604 // Check for address size fault 1605 if (currState->aarch64 && checkAddrSizeFaultAArch64( 1606 next_desc_addr, currState->physAddrRange)) { 1607 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1608 currState->longDesc.lookupLevel); 1609 if (currState->isFetch) 1610 currState->fault = std::make_shared<PrefetchAbort>( 1611 currState->vaddr_tainted, 1612 ArmFault::AddressSizeLL 1613 + currState->longDesc.lookupLevel, 1614 isStage2, 1615 ArmFault::LpaeTran); 1616 else 1617 currState->fault = std::make_shared<DataAbort>( 1618 currState->vaddr_tainted, 1619 TlbEntry::DomainType::NoAccess, currState->isWrite, 1620 ArmFault::AddressSizeLL 1621 + currState->longDesc.lookupLevel, 1622 isStage2, 1623 ArmFault::LpaeTran); 1624 return; 1625 } 1626 1627 // Trickbox address check 1628 currState->fault = testWalk( 1629 next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 1630 toLookupLevel(currState->longDesc.lookupLevel +1)); 1631 1632 if (currState->fault) { 1633 if (!currState->timing) { 1634 currState->tc = NULL; 1635 currState->req = NULL; 1636 } 1637 return; 1638 } 1639 1640 Request::Flags flag = Request::PT_WALK; 1641 if (currState->secureLookup) 1642 flag.set(Request::SECURE); 1643 1644 currState->longDesc.lookupLevel = 1645 (LookupLevel) (currState->longDesc.lookupLevel + 1); 1646 Event *event = NULL; 1647 switch (currState->longDesc.lookupLevel) { 1648 case L1: 1649 assert(currState->aarch64); 1650 event = &doL1LongDescEvent; 1651 break; 1652 case L2: 1653 event = &doL2LongDescEvent; 1654 break; 1655 case L3: 1656 event = &doL3LongDescEvent; 1657 break; 1658 default: 1659 panic("Wrong lookup level in table walk\n"); 1660 break; 1661 } 1662 1663 bool delayed; 1664 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 1665 sizeof(uint64_t), flag, -1, event, 1666 &TableWalker::doLongDescriptor); 1667 if (delayed) { 1668 currState->delayed = true; 1669 } 1670 } 1671 return; 1672 default: 1673 panic("A new type in a 2 bit field?\n"); 1674 } 1675} 1676 1677void 1678TableWalker::doL2Descriptor() 1679{ 1680 if (currState->fault != NoFault) { 1681 return; 1682 } 1683 1684 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 1685 currState->vaddr_tainted, currState->l2Desc.data); 1686 TlbEntry te; 1687 1688 if (currState->l2Desc.invalid()) { 1689 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 1690 if (!currState->timing) { 1691 currState->tc = NULL; 1692 currState->req = NULL; 1693 } 1694 if (currState->isFetch) 1695 currState->fault = std::make_shared<PrefetchAbort>( 1696 currState->vaddr_tainted, 1697 ArmFault::TranslationLL + L2, 1698 isStage2, 1699 ArmFault::VmsaTran); 1700 else 1701 currState->fault = std::make_shared<DataAbort>( 1702 currState->vaddr_tainted, currState->l1Desc.domain(), 1703 currState->isWrite, ArmFault::TranslationLL + L2, 1704 isStage2, 1705 ArmFault::VmsaTran); 1706 return; 1707 } 1708 1709 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 1710 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 1711 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 1712 */ 1713 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 1714 currState->sctlr.afe, currState->l2Desc.ap()); 1715 1716 currState->fault = std::make_shared<DataAbort>( 1717 currState->vaddr_tainted, 1718 TlbEntry::DomainType::NoAccess, currState->isWrite, 1719 ArmFault::AccessFlagLL + L2, isStage2, 1720 ArmFault::VmsaTran); 1721 } 1722 1723 insertTableEntry(currState->l2Desc, false); 1724} 1725 1726void 1727TableWalker::doL1DescriptorWrapper() 1728{ 1729 currState = stateQueues[L1].front(); 1730 currState->delayed = false; 1731 // if there's a stage2 translation object we don't need it any more 1732 if (currState->stage2Tran) { 1733 delete currState->stage2Tran; 1734 currState->stage2Tran = NULL; 1735 } 1736 1737 1738 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 1739 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 1740 1741 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 1742 doL1Descriptor(); 1743 1744 stateQueues[L1].pop_front(); 1745 // Check if fault was generated 1746 if (currState->fault != NoFault) { 1747 currState->transState->finish(currState->fault, currState->req, 1748 currState->tc, currState->mode); 1749 statWalksShortTerminatedAtLevel[0]++; 1750 1751 pending = false; 1752 nextWalk(currState->tc); 1753 1754 currState->req = NULL; 1755 currState->tc = NULL; 1756 currState->delayed = false; 1757 delete currState; 1758 } 1759 else if (!currState->delayed) { 1760 // delay is not set so there is no L2 to do 1761 // Don't finish the translation if a stage 2 look up is underway 1762 if (!currState->doingStage2) { 1763 statWalkServiceTime.sample(curTick() - currState->startTime); 1764 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1765 currState->fault = tlb->translateTiming(currState->req, currState->tc, 1766 currState->transState, currState->mode); 1767 statWalksShortTerminatedAtLevel[0]++; 1768 } 1769 1770 pending = false; 1771 nextWalk(currState->tc); 1772 1773 currState->req = NULL; 1774 currState->tc = NULL; 1775 currState->delayed = false; 1776 delete currState; 1777 } else { 1778 // need to do L2 descriptor 1779 stateQueues[L2].push_back(currState); 1780 } 1781 currState = NULL; 1782} 1783 1784void 1785TableWalker::doL2DescriptorWrapper() 1786{ 1787 currState = stateQueues[L2].front(); 1788 assert(currState->delayed); 1789 // if there's a stage2 translation object we don't need it any more 1790 if (currState->stage2Tran) { 1791 delete currState->stage2Tran; 1792 currState->stage2Tran = NULL; 1793 } 1794 1795 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 1796 currState->vaddr_tainted); 1797 doL2Descriptor(); 1798 1799 // Check if fault was generated 1800 if (currState->fault != NoFault) { 1801 currState->transState->finish(currState->fault, currState->req, 1802 currState->tc, currState->mode); 1803 statWalksShortTerminatedAtLevel[1]++; 1804 } 1805 else { 1806 // Don't finish the translation if a stage 2 look up is underway 1807 if (!currState->doingStage2) { 1808 statWalkServiceTime.sample(curTick() - currState->startTime); 1809 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1810 currState->fault = tlb->translateTiming(currState->req, 1811 currState->tc, currState->transState, currState->mode); 1812 statWalksShortTerminatedAtLevel[1]++; 1813 } 1814 } 1815 1816 1817 stateQueues[L2].pop_front(); 1818 pending = false; 1819 nextWalk(currState->tc); 1820 1821 currState->req = NULL; 1822 currState->tc = NULL; 1823 currState->delayed = false; 1824 1825 delete currState; 1826 currState = NULL; 1827} 1828 1829void 1830TableWalker::doL0LongDescriptorWrapper() 1831{ 1832 doLongDescriptorWrapper(L0); 1833} 1834 1835void 1836TableWalker::doL1LongDescriptorWrapper() 1837{ 1838 doLongDescriptorWrapper(L1); 1839} 1840 1841void 1842TableWalker::doL2LongDescriptorWrapper() 1843{ 1844 doLongDescriptorWrapper(L2); 1845} 1846 1847void 1848TableWalker::doL3LongDescriptorWrapper() 1849{ 1850 doLongDescriptorWrapper(L3); 1851} 1852 1853void 1854TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 1855{ 1856 currState = stateQueues[curr_lookup_level].front(); 1857 assert(curr_lookup_level == currState->longDesc.lookupLevel); 1858 currState->delayed = false; 1859 1860 // if there's a stage2 translation object we don't need it any more 1861 if (currState->stage2Tran) { 1862 delete currState->stage2Tran; 1863 currState->stage2Tran = NULL; 1864 } 1865 1866 DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 1867 currState->vaddr_tainted); 1868 doLongDescriptor(); 1869 1870 stateQueues[curr_lookup_level].pop_front(); 1871 1872 if (currState->fault != NoFault) { 1873 // A fault was generated 1874 currState->transState->finish(currState->fault, currState->req, 1875 currState->tc, currState->mode); 1876 1877 pending = false; 1878 nextWalk(currState->tc); 1879 1880 currState->req = NULL; 1881 currState->tc = NULL; 1882 currState->delayed = false; 1883 delete currState; 1884 } else if (!currState->delayed) { 1885 // No additional lookups required 1886 // Don't finish the translation if a stage 2 look up is underway 1887 if (!currState->doingStage2) { 1888 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1889 statWalkServiceTime.sample(curTick() - currState->startTime); 1890 currState->fault = tlb->translateTiming(currState->req, currState->tc, 1891 currState->transState, 1892 currState->mode); 1893 statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 1894 } 1895 1896 pending = false; 1897 nextWalk(currState->tc); 1898 1899 currState->req = NULL; 1900 currState->tc = NULL; 1901 currState->delayed = false; 1902 delete currState; 1903 } else { 1904 if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 1905 panic("Max. number of lookups already reached in table walk\n"); 1906 // Need to perform additional lookups 1907 stateQueues[currState->longDesc.lookupLevel].push_back(currState); 1908 } 1909 currState = NULL; 1910} 1911 1912 1913void 1914TableWalker::nextWalk(ThreadContext *tc) 1915{ 1916 if (pendingQueue.size()) 1917 schedule(doProcessEvent, clockEdge(Cycles(1))); 1918 else 1919 completeDrain(); 1920} 1921 1922bool 1923TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 1924 Request::Flags flags, int queueIndex, Event *event, 1925 void (TableWalker::*doDescriptor)()) 1926{ 1927 bool isTiming = currState->timing; 1928 1929 DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 1930 descAddr, currState->stage2Req); 1931 1932 // If this translation has a stage 2 then we know descAddr is an IPA and 1933 // needs to be translated before we can access the page table. Do that 1934 // check here. 1935 if (currState->stage2Req) { 1936 Fault fault; 1937 flags = flags | TLB::MustBeOne; 1938 1939 if (isTiming) { 1940 Stage2MMU::Stage2Translation *tran = new 1941 Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 1942 currState->vaddr); 1943 currState->stage2Tran = tran; 1944 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 1945 flags); 1946 fault = tran->fault; 1947 } else { 1948 fault = stage2Mmu->readDataUntimed(currState->tc, 1949 currState->vaddr, descAddr, data, numBytes, flags, 1950 currState->functional); 1951 } 1952 1953 if (fault != NoFault) { 1954 currState->fault = fault; 1955 } 1956 if (isTiming) { 1957 if (queueIndex >= 0) { 1958 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1959 stateQueues[queueIndex].size()); 1960 stateQueues[queueIndex].push_back(currState); 1961 currState = NULL; 1962 } 1963 } else { 1964 (this->*doDescriptor)(); 1965 } 1966 } else { 1967 if (isTiming) { 1968 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 1969 currState->tc->getCpuPtr()->clockPeriod(),flags); 1970 if (queueIndex >= 0) { 1971 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1972 stateQueues[queueIndex].size()); 1973 stateQueues[queueIndex].push_back(currState); 1974 currState = NULL; 1975 } 1976 } else if (!currState->functional) { 1977 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 1978 currState->tc->getCpuPtr()->clockPeriod(), flags); 1979 (this->*doDescriptor)(); 1980 } else { 1981 RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 1982 req->taskId(ContextSwitchTaskId::DMA); 1983 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 1984 pkt->dataStatic(data); 1985 port->sendFunctional(pkt); 1986 (this->*doDescriptor)(); 1987 delete req; 1988 delete pkt; 1989 } 1990 } 1991 return (isTiming); 1992} 1993 1994void 1995TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 1996{ 1997 TlbEntry te; 1998 1999 // Create and fill a new page table entry 2000 te.valid = true; 2001 te.longDescFormat = longDescriptor; 2002 te.isHyp = currState->isHyp; 2003 te.asid = currState->asid; 2004 te.vmid = currState->vmid; 2005 te.N = descriptor.offsetBits(); 2006 te.vpn = currState->vaddr >> te.N; 2007 te.size = (1<<te.N) - 1; 2008 te.pfn = descriptor.pfn(); 2009 te.domain = descriptor.domain(); 2010 te.lookupLevel = descriptor.lookupLevel; 2011 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 2012 te.nstid = !currState->isSecure; 2013 te.xn = descriptor.xn(); 2014 if (currState->aarch64) 2015 te.el = currState->el; 2016 else 2017 te.el = 1; 2018 2019 statPageSizes[pageSizeNtoStatBin(te.N)]++; 2020 statRequestOrigin[COMPLETED][currState->isFetch]++; 2021 2022 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 2023 // as global 2024 te.global = descriptor.global(currState) || isStage2; 2025 if (longDescriptor) { 2026 LongDescriptor lDescriptor = 2027 dynamic_cast<LongDescriptor &>(descriptor); 2028 2029 te.xn |= currState->xnTable; 2030 te.pxn = currState->pxnTable || lDescriptor.pxn(); 2031 if (isStage2) { 2032 // this is actually the HAP field, but its stored in the same bit 2033 // possitions as the AP field in a stage 1 translation. 2034 te.hap = lDescriptor.ap(); 2035 } else { 2036 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 2037 (currState->userTable && (descriptor.ap() & 0x1)); 2038 } 2039 if (currState->aarch64) 2040 memAttrsAArch64(currState->tc, te, currState->longDesc.attrIndx(), 2041 currState->longDesc.sh()); 2042 else 2043 memAttrsLPAE(currState->tc, te, lDescriptor); 2044 } else { 2045 te.ap = descriptor.ap(); 2046 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 2047 descriptor.shareable()); 2048 } 2049 2050 // Debug output 2051 DPRINTF(TLB, descriptor.dbgHeader().c_str()); 2052 DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 2053 te.N, te.pfn, te.size, te.global, te.valid); 2054 DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 2055 "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 2056 te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 2057 te.nonCacheable, te.ns); 2058 DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 2059 descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 2060 descriptor.getRawData()); 2061 2062 // Insert the entry into the TLB 2063 tlb->insert(currState->vaddr, te); 2064 if (!currState->timing) { 2065 currState->tc = NULL; 2066 currState->req = NULL; 2067 } 2068} 2069 2070ArmISA::TableWalker * 2071ArmTableWalkerParams::create() 2072{ 2073 return new ArmISA::TableWalker(this); 2074} 2075 2076LookupLevel 2077TableWalker::toLookupLevel(uint8_t lookup_level_as_int) 2078{ 2079 switch (lookup_level_as_int) { 2080 case L1: 2081 return L1; 2082 case L2: 2083 return L2; 2084 case L3: 2085 return L3; 2086 default: 2087 panic("Invalid lookup level conversion"); 2088 } 2089} 2090 2091/* this method keeps track of the table walker queue's residency, so 2092 * needs to be called whenever requests start and complete. */ 2093void 2094TableWalker::pendingChange() 2095{ 2096 unsigned n = pendingQueue.size(); 2097 if ((currState != NULL) && (currState != pendingQueue.front())) { 2098 ++n; 2099 } 2100 2101 if (n != pendingReqs) { 2102 Tick now = curTick(); 2103 statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 2104 pendingReqs = n; 2105 pendingChangeTick = now; 2106 } 2107} 2108 2109Fault 2110TableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 2111 LookupLevel lookup_level) 2112{ 2113 return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 2114 currState->mode, domain, lookup_level); 2115} 2116 2117 2118uint8_t 2119TableWalker::pageSizeNtoStatBin(uint8_t N) 2120{ 2121 /* for statPageSizes */ 2122 switch(N) { 2123 case 12: return 0; // 4K 2124 case 14: return 1; // 16K (using 16K granule in v8-64) 2125 case 16: return 2; // 64K 2126 case 20: return 3; // 1M 2127 case 21: return 4; // 2M-LPAE 2128 case 24: return 5; // 16M 2129 case 25: return 6; // 32M (using 16K granule in v8-64) 2130 case 29: return 7; // 512M (using 64K granule in v8-64) 2131 case 30: return 8; // 1G-LPAE 2132 default: 2133 panic("unknown page size"); 2134 return 255; 2135 } 2136} 2137 2138void 2139TableWalker::regStats() 2140{ 2141 ClockedObject::regStats(); 2142 2143 statWalks 2144 .name(name() + ".walks") 2145 .desc("Table walker walks requested") 2146 ; 2147 2148 statWalksShortDescriptor 2149 .name(name() + ".walksShort") 2150 .desc("Table walker walks initiated with short descriptors") 2151 .flags(Stats::nozero) 2152 ; 2153 2154 statWalksLongDescriptor 2155 .name(name() + ".walksLong") 2156 .desc("Table walker walks initiated with long descriptors") 2157 .flags(Stats::nozero) 2158 ; 2159 2160 statWalksShortTerminatedAtLevel 2161 .init(2) 2162 .name(name() + ".walksShortTerminationLevel") 2163 .desc("Level at which table walker walks " 2164 "with short descriptors terminate") 2165 .flags(Stats::nozero) 2166 ; 2167 statWalksShortTerminatedAtLevel.subname(0, "Level1"); 2168 statWalksShortTerminatedAtLevel.subname(1, "Level2"); 2169 2170 statWalksLongTerminatedAtLevel 2171 .init(4) 2172 .name(name() + ".walksLongTerminationLevel") 2173 .desc("Level at which table walker walks " 2174 "with long descriptors terminate") 2175 .flags(Stats::nozero) 2176 ; 2177 statWalksLongTerminatedAtLevel.subname(0, "Level0"); 2178 statWalksLongTerminatedAtLevel.subname(1, "Level1"); 2179 statWalksLongTerminatedAtLevel.subname(2, "Level2"); 2180 statWalksLongTerminatedAtLevel.subname(3, "Level3"); 2181 2182 statSquashedBefore 2183 .name(name() + ".walksSquashedBefore") 2184 .desc("Table walks squashed before starting") 2185 .flags(Stats::nozero) 2186 ; 2187 2188 statSquashedAfter 2189 .name(name() + ".walksSquashedAfter") 2190 .desc("Table walks squashed after completion") 2191 .flags(Stats::nozero) 2192 ; 2193 2194 statWalkWaitTime 2195 .init(16) 2196 .name(name() + ".walkWaitTime") 2197 .desc("Table walker wait (enqueue to first request) latency") 2198 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2199 ; 2200 2201 statWalkServiceTime 2202 .init(16) 2203 .name(name() + ".walkCompletionTime") 2204 .desc("Table walker service (enqueue to completion) latency") 2205 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2206 ; 2207 2208 statPendingWalks 2209 .init(16) 2210 .name(name() + ".walksPending") 2211 .desc("Table walker pending requests distribution") 2212 .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 2213 ; 2214 2215 statPageSizes // see DDI 0487A D4-1661 2216 .init(9) 2217 .name(name() + ".walkPageSizes") 2218 .desc("Table walker page sizes translated") 2219 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 2220 ; 2221 statPageSizes.subname(0, "4K"); 2222 statPageSizes.subname(1, "16K"); 2223 statPageSizes.subname(2, "64K"); 2224 statPageSizes.subname(3, "1M"); 2225 statPageSizes.subname(4, "2M"); 2226 statPageSizes.subname(5, "16M"); 2227 statPageSizes.subname(6, "32M"); 2228 statPageSizes.subname(7, "512M"); 2229 statPageSizes.subname(8, "1G"); 2230 2231 statRequestOrigin 2232 .init(2,2) // Instruction/Data, requests/completed 2233 .name(name() + ".walkRequestOrigin") 2234 .desc("Table walker requests started/completed, data/inst") 2235 .flags(Stats::total) 2236 ; 2237 statRequestOrigin.subname(0,"Requested"); 2238 statRequestOrigin.subname(1,"Completed"); 2239 statRequestOrigin.ysubname(0,"Data"); 2240 statRequestOrigin.ysubname(1,"Inst"); 2241} 2242