table_walker.cc revision 11575
17404SAli.Saidi@ARM.com/* 211574SCurtis.Dunham@arm.com * Copyright (c) 2010, 2012-2016 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 4010873Sandreas.sandberg@arm.com#include "arch/arm/table_walker.hh" 417404SAli.Saidi@ARM.com 4210474Sandreas.hansson@arm.com#include <memory> 4310474Sandreas.hansson@arm.com 447404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4510037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4610037SARM gem5 Developers#include "arch/arm/system.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 487728SAli.Saidi@ARM.com#include "cpu/base.hh" 497404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 508245Snate@binkert.org#include "debug/Checkpoint.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528245Snate@binkert.org#include "debug/TLB.hh" 538245Snate@binkert.org#include "debug/TLBVerbose.hh" 5410873Sandreas.sandberg@arm.com#include "dev/dma_device.hh" 557748SAli.Saidi@ARM.com#include "sim/system.hh" 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comusing namespace ArmISA; 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 6010913Sandreas.sandberg@arm.com : MemObject(p), 6110717Sandreas.hansson@arm.com stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 6210717Sandreas.hansson@arm.com isStage2(p->is_stage2), tlb(NULL), 6310717Sandreas.hansson@arm.com currState(NULL), pending(false), 649258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6510621SCurtis.Dunham@arm.com pendingReqs(0), 6610621SCurtis.Dunham@arm.com pendingChangeTick(curTick()), 6710037SARM gem5 Developers doL1DescEvent(this), doL2DescEvent(this), 6810037SARM gem5 Developers doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this), 6910037SARM gem5 Developers doL3LongDescEvent(this), 7010037SARM gem5 Developers doProcessEvent(this) 717439Sdam.sunwoo@arm.com{ 727576SAli.Saidi@ARM.com sctlr = 0; 7310037SARM gem5 Developers 7410037SARM gem5 Developers // Cache system-level properties 7510037SARM gem5 Developers if (FullSystem) { 7610717Sandreas.hansson@arm.com ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 7710037SARM gem5 Developers assert(armSys); 7810037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 7910037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 8010037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 8110037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 8210037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 8310037SARM gem5 Developers } else { 8410037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 8510037SARM gem5 Developers _haveLargeAsid64 = false; 8610037SARM gem5 Developers physAddrRange = 32; 8710037SARM gem5 Developers } 8810037SARM gem5 Developers 897439Sdam.sunwoo@arm.com} 907404SAli.Saidi@ARM.com 917404SAli.Saidi@ARM.comTableWalker::~TableWalker() 927404SAli.Saidi@ARM.com{ 937404SAli.Saidi@ARM.com ; 947404SAli.Saidi@ARM.com} 957404SAli.Saidi@ARM.com 9610717Sandreas.hansson@arm.comvoid 9710717Sandreas.hansson@arm.comTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 9810717Sandreas.hansson@arm.com{ 9910717Sandreas.hansson@arm.com stage2Mmu = m; 10010717Sandreas.hansson@arm.com port = &m->getPort(); 10110717Sandreas.hansson@arm.com masterId = master_id; 10210717Sandreas.hansson@arm.com} 10310717Sandreas.hansson@arm.com 10410717Sandreas.hansson@arm.comvoid 10510717Sandreas.hansson@arm.comTableWalker::init() 10610717Sandreas.hansson@arm.com{ 10710717Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 10810717Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 10910717Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 11010717Sandreas.hansson@arm.com} 11110717Sandreas.hansson@arm.com 11210717Sandreas.hansson@arm.comBaseMasterPort& 11310717Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 11410717Sandreas.hansson@arm.com{ 11510717Sandreas.hansson@arm.com if (if_name == "port") { 11610717Sandreas.hansson@arm.com if (!isStage2) { 11710717Sandreas.hansson@arm.com return *port; 11810717Sandreas.hansson@arm.com } else { 11910717Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 12010717Sandreas.hansson@arm.com } 12110717Sandreas.hansson@arm.com } 12210717Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 12310717Sandreas.hansson@arm.com} 12410717Sandreas.hansson@arm.com 12510537Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 12610537Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 12710537Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 12810537Sandreas.hansson@arm.com vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 12910537Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 13010537Sandreas.hansson@arm.com pxnTable(false), stage2Req(false), doingStage2(false), 13110537Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 13210537Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 13310537Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 13410037SARM gem5 Developers{ 13510037SARM gem5 Developers} 13610037SARM gem5 Developers 1379152Satgutier@umich.eduvoid 1389152Satgutier@umich.eduTableWalker::completeDrain() 1399152Satgutier@umich.edu{ 14010913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 14110913Sandreas.sandberg@arm.com stateQueues[L1].empty() && stateQueues[L2].empty() && 1429152Satgutier@umich.edu pendingQueue.empty()) { 14310913Sandreas.sandberg@arm.com 1449152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 14510913Sandreas.sandberg@arm.com signalDrainDone(); 1469152Satgutier@umich.edu } 1479152Satgutier@umich.edu} 1489152Satgutier@umich.edu 14910913Sandreas.sandberg@arm.comDrainState 15010913Sandreas.sandberg@arm.comTableWalker::drain() 1517404SAli.Saidi@ARM.com{ 15210037SARM gem5 Developers bool state_queues_not_empty = false; 1539152Satgutier@umich.edu 15410037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 15510037SARM gem5 Developers if (!stateQueues[i].empty()) { 15610037SARM gem5 Developers state_queues_not_empty = true; 15710037SARM gem5 Developers break; 15810037SARM gem5 Developers } 15910037SARM gem5 Developers } 16010037SARM gem5 Developers 16110037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1629152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 16310913Sandreas.sandberg@arm.com return DrainState::Draining; 16410037SARM gem5 Developers } else { 16510037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 16610913Sandreas.sandberg@arm.com return DrainState::Drained; 1677733SAli.Saidi@ARM.com } 1687404SAli.Saidi@ARM.com} 1697404SAli.Saidi@ARM.com 1707748SAli.Saidi@ARM.comvoid 1719342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1727748SAli.Saidi@ARM.com{ 1739524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1749152Satgutier@umich.edu delete currState; 1759152Satgutier@umich.edu currState = NULL; 17610621SCurtis.Dunham@arm.com pendingChange(); 1777748SAli.Saidi@ARM.com } 1787748SAli.Saidi@ARM.com} 1797748SAli.Saidi@ARM.com 1807404SAli.Saidi@ARM.comFault 18110037SARM gem5 DevelopersTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 18210037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 18310037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 18410037SARM gem5 Developers bool secure, TLB::ArmTranslationType tranType) 1857404SAli.Saidi@ARM.com{ 1868733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 18710621SCurtis.Dunham@arm.com ++statWalks; 18810621SCurtis.Dunham@arm.com 18910109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 19010037SARM gem5 Developers 19110109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 1927439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1937439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1947439Sdam.sunwoo@arm.com // TLB miss. 1957439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1967404SAli.Saidi@ARM.com 1977439Sdam.sunwoo@arm.com currState = new WalkerState(); 1987439Sdam.sunwoo@arm.com currState->tableWalker = this; 19910109SGeoffrey.Blake@arm.com } else if (_functional) { 20010109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 20110109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 20210109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 20310109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 20410109SGeoffrey.Blake@arm.com savedCurrState = currState; 20510109SGeoffrey.Blake@arm.com currState = new WalkerState(); 20610109SGeoffrey.Blake@arm.com currState->tableWalker = this; 2078202SAli.Saidi@ARM.com } else if (_timing) { 2088202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 2098202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 2108202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 2118202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 2128202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 2138202SAli.Saidi@ARM.com // up everything. 21410037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 21510621SCurtis.Dunham@arm.com ++statSquashedBefore; 21610474Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 2178202SAli.Saidi@ARM.com } 2187439Sdam.sunwoo@arm.com } 21910621SCurtis.Dunham@arm.com pendingChange(); 2207439Sdam.sunwoo@arm.com 22110621SCurtis.Dunham@arm.com currState->startTime = curTick(); 2227439Sdam.sunwoo@arm.com currState->tc = _tc; 22311517SCurtis.Dunham@arm.com // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 22411517SCurtis.Dunham@arm.com // aarch32/translation/translation/AArch32.TranslateAddress dictates 22511517SCurtis.Dunham@arm.com // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. 22611574SCurtis.Dunham@arm.com currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || 22711517SCurtis.Dunham@arm.com ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); 22810037SARM gem5 Developers currState->el = currEL(_tc); 2297439Sdam.sunwoo@arm.com currState->transState = _trans; 2307439Sdam.sunwoo@arm.com currState->req = _req; 2317439Sdam.sunwoo@arm.com currState->fault = NoFault; 23210037SARM gem5 Developers currState->asid = _asid; 23310037SARM gem5 Developers currState->vmid = _vmid; 23410037SARM gem5 Developers currState->isHyp = _isHyp; 2357439Sdam.sunwoo@arm.com currState->timing = _timing; 2368733Sgeoffrey.blake@arm.com currState->functional = _functional; 2377439Sdam.sunwoo@arm.com currState->mode = _mode; 23810037SARM gem5 Developers currState->tranType = tranType; 23910037SARM gem5 Developers currState->isSecure = secure; 24010037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2417404SAli.Saidi@ARM.com 2427436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2437436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 24410037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 24510037SARM gem5 Developers if (currState->aarch64) 24610037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 24710037SARM gem5 Developers currState->tc, currState->el); 24810037SARM gem5 Developers else 24910037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 25010037SARM gem5 Developers 25110037SARM gem5 Developers if (currState->aarch64) { 25211575SDylan.Johnson@ARM.com if (isStage2) { 25311575SDylan.Johnson@ARM.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 25411575SDylan.Johnson@ARM.com currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2); 25511575SDylan.Johnson@ARM.com } else switch (currState->el) { 25610037SARM gem5 Developers case EL0: 25710037SARM gem5 Developers case EL1: 25810037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 25910324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 26010037SARM gem5 Developers break; 26111574SCurtis.Dunham@arm.com case EL2: 26211574SCurtis.Dunham@arm.com assert(_haveVirtualization); 26311574SCurtis.Dunham@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 26411574SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 26511574SCurtis.Dunham@arm.com break; 26610037SARM gem5 Developers case EL3: 26710037SARM gem5 Developers assert(haveSecurity); 26810037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 26910324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 27010037SARM gem5 Developers break; 27110037SARM gem5 Developers default: 27210037SARM gem5 Developers panic("Invalid exception level"); 27310037SARM gem5 Developers break; 27410037SARM gem5 Developers } 27511575SDylan.Johnson@ARM.com currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); 27610037SARM gem5 Developers } else { 27710037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 27810037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 27910037SARM gem5 Developers currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 28010037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 28110037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 28210037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 28310037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 28410037SARM gem5 Developers } 2857439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 2867439Sdam.sunwoo@arm.com 2877439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 2887439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 2897439Sdam.sunwoo@arm.com 29010621SCurtis.Dunham@arm.com statRequestOrigin[REQUESTED][currState->isFetch]++; 29110621SCurtis.Dunham@arm.com 29210037SARM gem5 Developers // We only do a second stage of translation if we're not secure, or in 29310037SARM gem5 Developers // hyp mode, the second stage MMU is enabled, and this table walker 29410037SARM gem5 Developers // instance is the first stage. 29510037SARM gem5 Developers currState->doingStage2 = false; 29611575SDylan.Johnson@ARM.com currState->stage2Req = currState->hcr.vm && !isStage2 && 29711575SDylan.Johnson@ARM.com !currState->isSecure && !currState->isHyp; 2987728SAli.Saidi@ARM.com 29911517SCurtis.Dunham@arm.com bool long_desc_format = currState->aarch64 || _isHyp || isStage2 || 30011517SCurtis.Dunham@arm.com longDescFormatInUse(currState->tc); 30110037SARM gem5 Developers 30210037SARM gem5 Developers if (long_desc_format) { 30310037SARM gem5 Developers // Helper variables used for hierarchical permissions 30410037SARM gem5 Developers currState->secureLookup = currState->isSecure; 30510037SARM gem5 Developers currState->rwTable = true; 30610037SARM gem5 Developers currState->userTable = true; 30710037SARM gem5 Developers currState->xnTable = false; 30810037SARM gem5 Developers currState->pxnTable = false; 30910621SCurtis.Dunham@arm.com 31010621SCurtis.Dunham@arm.com ++statWalksLongDescriptor; 31110621SCurtis.Dunham@arm.com } else { 31210621SCurtis.Dunham@arm.com ++statWalksShortDescriptor; 31310037SARM gem5 Developers } 31410037SARM gem5 Developers 31510037SARM gem5 Developers if (!currState->timing) { 31610109SGeoffrey.Blake@arm.com Fault fault = NoFault; 31710037SARM gem5 Developers if (currState->aarch64) 31810109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 31910037SARM gem5 Developers else if (long_desc_format) 32010109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 32110037SARM gem5 Developers else 32210109SGeoffrey.Blake@arm.com fault = processWalk(); 32310109SGeoffrey.Blake@arm.com 32410109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 32510109SGeoffrey.Blake@arm.com // how we found it. 32610109SGeoffrey.Blake@arm.com if (currState->functional) { 32710109SGeoffrey.Blake@arm.com delete currState; 32810109SGeoffrey.Blake@arm.com currState = savedCurrState; 32910109SGeoffrey.Blake@arm.com } 33010109SGeoffrey.Blake@arm.com return fault; 33110037SARM gem5 Developers } 3327728SAli.Saidi@ARM.com 3338067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 3347728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 3357728SAli.Saidi@ARM.com currState = NULL; 33610621SCurtis.Dunham@arm.com pendingChange(); 3377728SAli.Saidi@ARM.com } else { 3387728SAli.Saidi@ARM.com pending = true; 33910621SCurtis.Dunham@arm.com pendingChange(); 34010037SARM gem5 Developers if (currState->aarch64) 34110037SARM gem5 Developers return processWalkAArch64(); 34210037SARM gem5 Developers else if (long_desc_format) 34310037SARM gem5 Developers return processWalkLPAE(); 34410037SARM gem5 Developers else 34510037SARM gem5 Developers return processWalk(); 3467728SAli.Saidi@ARM.com } 3477728SAli.Saidi@ARM.com 3487728SAli.Saidi@ARM.com return NoFault; 3497728SAli.Saidi@ARM.com} 3507728SAli.Saidi@ARM.com 3517728SAli.Saidi@ARM.comvoid 3527728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3537728SAli.Saidi@ARM.com{ 3547728SAli.Saidi@ARM.com assert(!currState); 3557728SAli.Saidi@ARM.com assert(pendingQueue.size()); 35610621SCurtis.Dunham@arm.com pendingChange(); 3577728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3589258SAli.Saidi@ARM.com 35910037SARM gem5 Developers ExceptionLevel target_el = EL0; 36010037SARM gem5 Developers if (currState->aarch64) 36110037SARM gem5 Developers target_el = currEL(currState->tc); 36210037SARM gem5 Developers else 36310037SARM gem5 Developers target_el = EL1; 36410037SARM gem5 Developers 3659535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 36610037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 36710037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 36810037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 36910037SARM gem5 Developers target_el); 3709258SAli.Saidi@ARM.com 3719535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3729535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3739535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3749535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3759535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3769535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3779258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3789258SAli.Saidi@ARM.com pending = true; 3799258SAli.Saidi@ARM.com pendingQueue.pop_front(); 38010579SAndrew.Bardsley@arm.com // Keep currState in case one of the processWalk... calls NULLs it 38110579SAndrew.Bardsley@arm.com WalkerState *curr_state_copy = currState; 38210579SAndrew.Bardsley@arm.com Fault f; 38310037SARM gem5 Developers if (currState->aarch64) 38410579SAndrew.Bardsley@arm.com f = processWalkAArch64(); 38511517SCurtis.Dunham@arm.com else if (longDescFormatInUse(currState->tc) || 38611517SCurtis.Dunham@arm.com currState->isHyp || isStage2) 38710579SAndrew.Bardsley@arm.com f = processWalkLPAE(); 38810037SARM gem5 Developers else 38910579SAndrew.Bardsley@arm.com f = processWalk(); 39010579SAndrew.Bardsley@arm.com 39110579SAndrew.Bardsley@arm.com if (f != NoFault) { 39210579SAndrew.Bardsley@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 39310579SAndrew.Bardsley@arm.com curr_state_copy->tc, curr_state_copy->mode); 39410579SAndrew.Bardsley@arm.com 39510579SAndrew.Bardsley@arm.com delete curr_state_copy; 39610579SAndrew.Bardsley@arm.com } 3979258SAli.Saidi@ARM.com return; 3989258SAli.Saidi@ARM.com } 3999258SAli.Saidi@ARM.com 4009258SAli.Saidi@ARM.com 4019258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 4029258SAli.Saidi@ARM.com // squashed we shouldn't bother. 4039258SAli.Saidi@ARM.com unsigned num_squashed = 0; 4049258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 4059258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 4069535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 4079258SAli.Saidi@ARM.com pendingQueue.pop_front(); 4089258SAli.Saidi@ARM.com num_squashed++; 40910621SCurtis.Dunham@arm.com statSquashedBefore++; 4109258SAli.Saidi@ARM.com 41110037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 41210037SARM gem5 Developers currState->vaddr_tainted); 4139258SAli.Saidi@ARM.com 4149535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 4159535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 41610474Sandreas.hansson@arm.com currState->transState->finish( 41710474Sandreas.hansson@arm.com std::make_shared<UnimpFault>("Squashed Inst"), 41810474Sandreas.hansson@arm.com currState->req, currState->tc, currState->mode); 4199535Smrinmoy.ghosh@arm.com } else { 4209535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 42110621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 42210037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 42310037SARM gem5 Developers currState->transState, currState->mode); 42410037SARM gem5 Developers 4259535Smrinmoy.ghosh@arm.com } 4269258SAli.Saidi@ARM.com 4279258SAli.Saidi@ARM.com // delete the current request 4289258SAli.Saidi@ARM.com delete currState; 4299258SAli.Saidi@ARM.com 4309258SAli.Saidi@ARM.com // peak at the next one 4319535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 4329258SAli.Saidi@ARM.com currState = pendingQueue.front(); 43310037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 43410037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 43510037SARM gem5 Developers false, target_el); 4369535Smrinmoy.ghosh@arm.com } else { 4379535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 4389258SAli.Saidi@ARM.com currState = NULL; 4399535Smrinmoy.ghosh@arm.com } 4409258SAli.Saidi@ARM.com } 44110621SCurtis.Dunham@arm.com pendingChange(); 4429258SAli.Saidi@ARM.com 44310621SCurtis.Dunham@arm.com // if we still have pending translations, schedule more work 4449258SAli.Saidi@ARM.com nextWalk(tc); 4459258SAli.Saidi@ARM.com currState = NULL; 4467728SAli.Saidi@ARM.com} 4477728SAli.Saidi@ARM.com 4487728SAli.Saidi@ARM.comFault 4497728SAli.Saidi@ARM.comTableWalker::processWalk() 4507728SAli.Saidi@ARM.com{ 4517404SAli.Saidi@ARM.com Addr ttbr = 0; 4527404SAli.Saidi@ARM.com 4537404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 45410037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 4557404SAli.Saidi@ARM.com 45610037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 45710037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 45810037SARM gem5 Developers 32 - currState->ttbcr.n)); 4597406SAli.Saidi@ARM.com 46010621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 46110621SCurtis.Dunham@arm.com 46210037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 46310037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4647406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 46510037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 46610037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 46710037SARM gem5 Developers if (currState->isFetch) 46810474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 46910474Sandreas.hansson@arm.com currState->vaddr_tainted, 47010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 47110474Sandreas.hansson@arm.com isStage2, 47210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 47310037SARM gem5 Developers else 47410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 47510474Sandreas.hansson@arm.com currState->vaddr_tainted, 47610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 47710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 47810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 47910037SARM gem5 Developers } 48010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 48110037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4827404SAli.Saidi@ARM.com } else { 4837406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 48410037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 48510037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 48610037SARM gem5 Developers if (currState->isFetch) 48710474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 48810474Sandreas.hansson@arm.com currState->vaddr_tainted, 48910474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 49010474Sandreas.hansson@arm.com isStage2, 49110474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49210037SARM gem5 Developers else 49310474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 49410474Sandreas.hansson@arm.com currState->vaddr_tainted, 49510474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 49610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 49710474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49810037SARM gem5 Developers } 49910037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 50010037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 50110037SARM gem5 Developers currState->ttbcr.n = 0; 5027404SAli.Saidi@ARM.com } 5037404SAli.Saidi@ARM.com 50410037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 50510037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 50610037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 50710037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 5087404SAli.Saidi@ARM.com 5097404SAli.Saidi@ARM.com // Trickbox address check 5107439Sdam.sunwoo@arm.com Fault f; 51111395Sandreas.sandberg@arm.com f = testWalk(l1desc_addr, sizeof(uint32_t), 51211395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, L1); 5137439Sdam.sunwoo@arm.com if (f) { 51410037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5157579Sminkyu.jeong@arm.com if (currState->timing) { 5167728SAli.Saidi@ARM.com pending = false; 5177728SAli.Saidi@ARM.com nextWalk(currState->tc); 5187579Sminkyu.jeong@arm.com currState = NULL; 5197579Sminkyu.jeong@arm.com } else { 5207579Sminkyu.jeong@arm.com currState->tc = NULL; 5217579Sminkyu.jeong@arm.com currState->req = NULL; 5227579Sminkyu.jeong@arm.com } 5237579Sminkyu.jeong@arm.com return f; 5247404SAli.Saidi@ARM.com } 5257404SAli.Saidi@ARM.com 52610836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 5277946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 52810836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 5297946SGiacomo.Gabrielli@arm.com } 5307946SGiacomo.Gabrielli@arm.com 53111181Snathananel.premillieu@arm.com if (currState->isSecure) { 53211181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 53311181Snathananel.premillieu@arm.com } 53411181Snathananel.premillieu@arm.com 53510037SARM gem5 Developers bool delayed; 53610037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 53710037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 53810037SARM gem5 Developers &TableWalker::doL1Descriptor); 53910037SARM gem5 Developers if (!delayed) { 54010037SARM gem5 Developers f = currState->fault; 54110037SARM gem5 Developers } 54210037SARM gem5 Developers 54310037SARM gem5 Developers return f; 54410037SARM gem5 Developers} 54510037SARM gem5 Developers 54610037SARM gem5 DevelopersFault 54710037SARM gem5 DevelopersTableWalker::processWalkLPAE() 54810037SARM gem5 Developers{ 54910037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 55010037SARM gem5 Developers int tsz, n; 55110037SARM gem5 Developers LookupLevel start_lookup_level = L1; 55210037SARM gem5 Developers 55310037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 55410037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 55510037SARM gem5 Developers 55610621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 55710621SCurtis.Dunham@arm.com 55810836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 55910037SARM gem5 Developers if (currState->isSecure) 56010037SARM gem5 Developers flag.set(Request::SECURE); 56110037SARM gem5 Developers 56210037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 56310037SARM gem5 Developers // use HTTBR 56410037SARM gem5 Developers if (isStage2) { 56510037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 56610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 56710037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 56810037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 56910037SARM gem5 Developers } else if (currState->isHyp) { 57010037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 57110037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 57210037SARM gem5 Developers tsz = currState->htcr.t0sz; 57310037SARM gem5 Developers } else { 57411517SCurtis.Dunham@arm.com assert(longDescFormatInUse(currState->tc)); 57510037SARM gem5 Developers 57610037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 57710037SARM gem5 Developers if (currState->ttbcr.t0sz) 57810037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 57910037SARM gem5 Developers else if (currState->ttbcr.t1sz) 58010037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 58110037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 58210037SARM gem5 Developers else 58310037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 58410037SARM gem5 Developers if (currState->ttbcr.t1sz) 58510037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 58610037SARM gem5 Developers else 58710037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 58810037SARM gem5 Developers 58910037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 59010037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 59110037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 59210037SARM gem5 Developers // ARM issue C B3.6.4) 59310037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 59410037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 59510037SARM gem5 Developers // Check if table walk is allowed 59610037SARM gem5 Developers if (currState->ttbcr.epd0) { 59710037SARM gem5 Developers if (currState->isFetch) 59810474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 59910474Sandreas.hansson@arm.com currState->vaddr_tainted, 60010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60110474Sandreas.hansson@arm.com isStage2, 60210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 60310037SARM gem5 Developers else 60410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 60510474Sandreas.hansson@arm.com currState->vaddr_tainted, 60610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 60710474Sandreas.hansson@arm.com currState->isWrite, 60810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60910474Sandreas.hansson@arm.com isStage2, 61010474Sandreas.hansson@arm.com ArmFault::LpaeTran); 61110037SARM gem5 Developers } 61210037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 61310037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 61410037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 61510037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 61610037SARM gem5 Developers start_lookup_level = L2; 61710037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 61810037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 61910037SARM gem5 Developers // Check if table walk is allowed 62010037SARM gem5 Developers if (currState->ttbcr.epd1) { 62110037SARM gem5 Developers if (currState->isFetch) 62210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 62310474Sandreas.hansson@arm.com currState->vaddr_tainted, 62410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 62510474Sandreas.hansson@arm.com isStage2, 62610474Sandreas.hansson@arm.com ArmFault::LpaeTran); 62710037SARM gem5 Developers else 62810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 62910474Sandreas.hansson@arm.com currState->vaddr_tainted, 63010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 63110474Sandreas.hansson@arm.com currState->isWrite, 63210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63310474Sandreas.hansson@arm.com isStage2, 63410474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63510037SARM gem5 Developers } 63610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 63710037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 63810037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 63910037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 64010037SARM gem5 Developers start_lookup_level = L2; 64110037SARM gem5 Developers } else { 64210037SARM gem5 Developers // Out of boundaries -> translation fault 64310037SARM gem5 Developers if (currState->isFetch) 64410474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64510474Sandreas.hansson@arm.com currState->vaddr_tainted, 64610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 64710474Sandreas.hansson@arm.com isStage2, 64810474Sandreas.hansson@arm.com ArmFault::LpaeTran); 64910037SARM gem5 Developers else 65010474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 65110474Sandreas.hansson@arm.com currState->vaddr_tainted, 65210474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 65310474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 65410474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 65510037SARM gem5 Developers } 65610037SARM gem5 Developers 65710037SARM gem5 Developers } 65810037SARM gem5 Developers 65910037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 66010037SARM gem5 Developers if (start_lookup_level == L1) { 66110037SARM gem5 Developers n = 5 - tsz; 66210037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 66310037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 66410037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 66510037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 66610037SARM gem5 Developers } else { 66710037SARM gem5 Developers // Skip first-level lookup 66810037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 66910037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 67010037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 67110037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67210037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67310037SARM gem5 Developers } 67410037SARM gem5 Developers 67510037SARM gem5 Developers // Trickbox address check 67611395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 67711395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 67810037SARM gem5 Developers if (f) { 67910037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 68010037SARM gem5 Developers if (currState->timing) { 68110037SARM gem5 Developers pending = false; 68210037SARM gem5 Developers nextWalk(currState->tc); 68310037SARM gem5 Developers currState = NULL; 68410037SARM gem5 Developers } else { 68510037SARM gem5 Developers currState->tc = NULL; 68610037SARM gem5 Developers currState->req = NULL; 68710037SARM gem5 Developers } 68810037SARM gem5 Developers return f; 68910037SARM gem5 Developers } 69010037SARM gem5 Developers 69110037SARM gem5 Developers if (currState->sctlr.c == 0) { 69210836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 69310037SARM gem5 Developers } 69410037SARM gem5 Developers 69510037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 69610037SARM gem5 Developers currState->longDesc.aarch64 = false; 69710324SCurtis.Dunham@arm.com currState->longDesc.grainSize = Grain4KB; 69810037SARM gem5 Developers 69910037SARM gem5 Developers Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent 70010037SARM gem5 Developers : (Event *) &doL2LongDescEvent; 70110037SARM gem5 Developers 70210037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70310037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 70410037SARM gem5 Developers event, &TableWalker::doLongDescriptor); 70510037SARM gem5 Developers if (!delayed) { 70610037SARM gem5 Developers f = currState->fault; 70710037SARM gem5 Developers } 70810037SARM gem5 Developers 70910037SARM gem5 Developers return f; 71010037SARM gem5 Developers} 71110037SARM gem5 Developers 71210037SARM gem5 Developersunsigned 71310037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 71410037SARM gem5 Developers{ 71510037SARM gem5 Developers if (tsz < 25) 71610037SARM gem5 Developers return 25; 71710037SARM gem5 Developers if (tsz > 48) 71810037SARM gem5 Developers return 48; 71910037SARM gem5 Developers return tsz; 72010037SARM gem5 Developers} 72110037SARM gem5 Developers 72210037SARM gem5 Developersbool 72310037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 72410037SARM gem5 Developers{ 72510037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 72610037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 72710037SARM gem5 Developers} 72810037SARM gem5 Developers 72910037SARM gem5 DevelopersFault 73010037SARM gem5 DevelopersTableWalker::processWalkAArch64() 73110037SARM gem5 Developers{ 73210037SARM gem5 Developers assert(currState->aarch64); 73310037SARM gem5 Developers 73410324SCurtis.Dunham@arm.com DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 73510324SCurtis.Dunham@arm.com currState->vaddr_tainted, currState->tcr); 73610324SCurtis.Dunham@arm.com 73710324SCurtis.Dunham@arm.com static const GrainSize GrainMapDefault[] = 73810324SCurtis.Dunham@arm.com { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 73910324SCurtis.Dunham@arm.com static const GrainSize GrainMap_EL1_tg1[] = 74010324SCurtis.Dunham@arm.com { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 74110037SARM gem5 Developers 74210621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 74310621SCurtis.Dunham@arm.com 74410037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 74510037SARM gem5 Developers Addr ttbr = 0; 74610037SARM gem5 Developers int tsz = 0, ps = 0; 74710324SCurtis.Dunham@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 74810037SARM gem5 Developers bool fault = false; 74911575SDylan.Johnson@ARM.com 75011575SDylan.Johnson@ARM.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 75111575SDylan.Johnson@ARM.com 75210037SARM gem5 Developers switch (currState->el) { 75310037SARM gem5 Developers case EL0: 75410037SARM gem5 Developers case EL1: 75511575SDylan.Johnson@ARM.com if (isStage2) { 75611575SDylan.Johnson@ARM.com DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n"); 75711575SDylan.Johnson@ARM.com ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); 75811575SDylan.Johnson@ARM.com tsz = 64 - currState->vtcr.t0sz64; 75911575SDylan.Johnson@ARM.com tg = GrainMapDefault[currState->vtcr.tg0]; 76011575SDylan.Johnson@ARM.com // ARM DDI 0487A.f D7-2148 76111575SDylan.Johnson@ARM.com // The starting level of stage 2 translation depends on 76211575SDylan.Johnson@ARM.com // VTCR_EL2.SL0 and VTCR_EL2.TG0 76311575SDylan.Johnson@ARM.com LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level 76411575SDylan.Johnson@ARM.com uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0; 76511575SDylan.Johnson@ARM.com static const LookupLevel SLL[] = { 76611575SDylan.Johnson@ARM.com L2, L3, L3, __, // sl0 == 0 76711575SDylan.Johnson@ARM.com L1, L2, L2, __, // sl0 == 1, etc. 76811575SDylan.Johnson@ARM.com L0, L1, L1, __, 76911575SDylan.Johnson@ARM.com __, __, __, __ 77011575SDylan.Johnson@ARM.com }; 77111575SDylan.Johnson@ARM.com start_lookup_level = SLL[sl_tg]; 77211575SDylan.Johnson@ARM.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 77311575SDylan.Johnson@ARM.com "Cannot discern lookup level from vtcr.{sl0,tg0}"); 77411575SDylan.Johnson@ARM.com } else switch (bits(currState->vaddr, 63,48)) { 77510037SARM gem5 Developers case 0: 77610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 77710037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 77810324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 77910324SCurtis.Dunham@arm.com tg = GrainMapDefault[currState->tcr.tg0]; 78010037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != 0x0 || 78110324SCurtis.Dunham@arm.com currState->tcr.epd0) 78210037SARM gem5 Developers fault = true; 78310037SARM gem5 Developers break; 78410037SARM gem5 Developers case 0xffff: 78510037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 78610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 78710324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 78810324SCurtis.Dunham@arm.com tg = GrainMap_EL1_tg1[currState->tcr.tg1]; 78910037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 79010324SCurtis.Dunham@arm.com currState->tcr.epd1) 79110037SARM gem5 Developers fault = true; 79210037SARM gem5 Developers break; 79310037SARM gem5 Developers default: 79410037SARM gem5 Developers // top two bytes must be all 0s or all 1s, else invalid addr 79510037SARM gem5 Developers fault = true; 79610037SARM gem5 Developers } 79710324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 79810037SARM gem5 Developers break; 79910037SARM gem5 Developers case EL2: 80010037SARM gem5 Developers case EL3: 80110037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 80210037SARM gem5 Developers case 0: 80310324SCurtis.Dunham@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 80410324SCurtis.Dunham@arm.com if (currState->el == EL2) 80510324SCurtis.Dunham@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 80610324SCurtis.Dunham@arm.com else 80710324SCurtis.Dunham@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 80810324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 80910324SCurtis.Dunham@arm.com tg = GrainMapDefault[currState->tcr.tg0]; 81010037SARM gem5 Developers break; 81110037SARM gem5 Developers default: 81210037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 81310324SCurtis.Dunham@arm.com fault = true; 81410037SARM gem5 Developers } 81510324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 81610037SARM gem5 Developers break; 81710037SARM gem5 Developers } 81810037SARM gem5 Developers 81910037SARM gem5 Developers if (fault) { 82010037SARM gem5 Developers Fault f; 82110037SARM gem5 Developers if (currState->isFetch) 82210474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 82310474Sandreas.hansson@arm.com currState->vaddr_tainted, 82410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 82510474Sandreas.hansson@arm.com ArmFault::LpaeTran); 82610037SARM gem5 Developers else 82710474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 82810474Sandreas.hansson@arm.com currState->vaddr_tainted, 82910474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 83010474Sandreas.hansson@arm.com currState->isWrite, 83110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, 83210474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 83310037SARM gem5 Developers 83410037SARM gem5 Developers if (currState->timing) { 83510037SARM gem5 Developers pending = false; 83610037SARM gem5 Developers nextWalk(currState->tc); 83710037SARM gem5 Developers currState = NULL; 83810037SARM gem5 Developers } else { 83910037SARM gem5 Developers currState->tc = NULL; 84010037SARM gem5 Developers currState->req = NULL; 84110037SARM gem5 Developers } 84210037SARM gem5 Developers return f; 84310037SARM gem5 Developers 84410037SARM gem5 Developers } 84510037SARM gem5 Developers 84610324SCurtis.Dunham@arm.com if (tg == ReservedGrain) { 84710324SCurtis.Dunham@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 84810324SCurtis.Dunham@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 84910324SCurtis.Dunham@arm.com tg = Grain4KB; 85010324SCurtis.Dunham@arm.com } 85110324SCurtis.Dunham@arm.com 85210037SARM gem5 Developers // Determine starting lookup level 85310324SCurtis.Dunham@arm.com // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 85410324SCurtis.Dunham@arm.com // in ARM DDI 0487A. These table values correspond to the cascading tests 85510324SCurtis.Dunham@arm.com // to compute the lookup level and are of the form 85610324SCurtis.Dunham@arm.com // (grain_size + N*stride), for N = {1, 2, 3}. 85710324SCurtis.Dunham@arm.com // A value of 64 will never succeed and a value of 0 will always succeed. 85811575SDylan.Johnson@ARM.com if (start_lookup_level == MAX_LOOKUP_LEVELS) { 85910324SCurtis.Dunham@arm.com struct GrainMap { 86010324SCurtis.Dunham@arm.com GrainSize grain_size; 86110324SCurtis.Dunham@arm.com unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 86210324SCurtis.Dunham@arm.com }; 86310324SCurtis.Dunham@arm.com static const GrainMap GM[] = { 86410324SCurtis.Dunham@arm.com { Grain4KB, { 39, 30, 0, 0 } }, 86510324SCurtis.Dunham@arm.com { Grain16KB, { 47, 36, 25, 0 } }, 86610324SCurtis.Dunham@arm.com { Grain64KB, { 64, 42, 29, 0 } } 86710324SCurtis.Dunham@arm.com }; 86810324SCurtis.Dunham@arm.com 86910324SCurtis.Dunham@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 87010324SCurtis.Dunham@arm.com 87110324SCurtis.Dunham@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 87210324SCurtis.Dunham@arm.com if (tg == GM[i].grain_size) { 87310324SCurtis.Dunham@arm.com lookup = GM[i].lookup_level_cutoff; 87410324SCurtis.Dunham@arm.com break; 87510324SCurtis.Dunham@arm.com } 87610324SCurtis.Dunham@arm.com } 87710324SCurtis.Dunham@arm.com assert(lookup); 87810324SCurtis.Dunham@arm.com 87910324SCurtis.Dunham@arm.com for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 88010324SCurtis.Dunham@arm.com if (tsz > lookup[L]) { 88110324SCurtis.Dunham@arm.com start_lookup_level = (LookupLevel) L; 88210324SCurtis.Dunham@arm.com break; 88310324SCurtis.Dunham@arm.com } 88410324SCurtis.Dunham@arm.com } 88510324SCurtis.Dunham@arm.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 88610324SCurtis.Dunham@arm.com "Table walker couldn't find lookup level\n"); 88710037SARM gem5 Developers } 88810037SARM gem5 Developers 88911575SDylan.Johnson@ARM.com int stride = tg - 3; 89011575SDylan.Johnson@ARM.com 89110037SARM gem5 Developers // Determine table base address 89210324SCurtis.Dunham@arm.com int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 89310037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 89410037SARM gem5 Developers 89510037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 89610037SARM gem5 Developers // necessary 89710037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 89810037SARM gem5 Developers // Clamp to lower limit 89910037SARM gem5 Developers if (pa_range > physAddrRange) 90010037SARM gem5 Developers currState->physAddrRange = physAddrRange; 90110037SARM gem5 Developers else 90210037SARM gem5 Developers currState->physAddrRange = pa_range; 90310037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 90410037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 90510037SARM gem5 Developers Fault f; 90610037SARM gem5 Developers if (currState->isFetch) 90710474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 90810474Sandreas.hansson@arm.com currState->vaddr_tainted, 90910474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 91010474Sandreas.hansson@arm.com isStage2, 91110474Sandreas.hansson@arm.com ArmFault::LpaeTran); 91210037SARM gem5 Developers else 91310474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 91410474Sandreas.hansson@arm.com currState->vaddr_tainted, 91510474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 91610474Sandreas.hansson@arm.com currState->isWrite, 91710474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 91810474Sandreas.hansson@arm.com isStage2, 91910474Sandreas.hansson@arm.com ArmFault::LpaeTran); 92010037SARM gem5 Developers 92110037SARM gem5 Developers 92210037SARM gem5 Developers if (currState->timing) { 92310037SARM gem5 Developers pending = false; 92410037SARM gem5 Developers nextWalk(currState->tc); 92510037SARM gem5 Developers currState = NULL; 92610037SARM gem5 Developers } else { 92710037SARM gem5 Developers currState->tc = NULL; 92810037SARM gem5 Developers currState->req = NULL; 92910037SARM gem5 Developers } 93010037SARM gem5 Developers return f; 93110037SARM gem5 Developers 93210037SARM gem5 Developers } 93310037SARM gem5 Developers 93410037SARM gem5 Developers // Determine descriptor address 93510037SARM gem5 Developers Addr desc_addr = base_addr | 93610037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 93710324SCurtis.Dunham@arm.com stride * (3 - start_lookup_level) + tg) << 3); 93810037SARM gem5 Developers 93910037SARM gem5 Developers // Trickbox address check 94011395Sandreas.sandberg@arm.com Fault f = testWalk(desc_addr, sizeof(uint64_t), 94111395Sandreas.sandberg@arm.com TlbEntry::DomainType::NoAccess, start_lookup_level); 94210037SARM gem5 Developers if (f) { 94310037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 94410037SARM gem5 Developers if (currState->timing) { 94510037SARM gem5 Developers pending = false; 94610037SARM gem5 Developers nextWalk(currState->tc); 94710037SARM gem5 Developers currState = NULL; 94810037SARM gem5 Developers } else { 94910037SARM gem5 Developers currState->tc = NULL; 95010037SARM gem5 Developers currState->req = NULL; 95110037SARM gem5 Developers } 95210037SARM gem5 Developers return f; 95310037SARM gem5 Developers } 95410037SARM gem5 Developers 95510836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 95610037SARM gem5 Developers if (currState->sctlr.c == 0) { 95710836Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 95810037SARM gem5 Developers } 95910037SARM gem5 Developers 96011181Snathananel.premillieu@arm.com if (currState->isSecure) { 96111181Snathananel.premillieu@arm.com flag.set(Request::SECURE); 96211181Snathananel.premillieu@arm.com } 96311181Snathananel.premillieu@arm.com 96410037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 96510037SARM gem5 Developers currState->longDesc.aarch64 = true; 96610324SCurtis.Dunham@arm.com currState->longDesc.grainSize = tg; 96710037SARM gem5 Developers 9687439Sdam.sunwoo@arm.com if (currState->timing) { 96910037SARM gem5 Developers Event *event; 97010037SARM gem5 Developers switch (start_lookup_level) { 97110037SARM gem5 Developers case L0: 97210037SARM gem5 Developers event = (Event *) &doL0LongDescEvent; 97310037SARM gem5 Developers break; 97410037SARM gem5 Developers case L1: 97510037SARM gem5 Developers event = (Event *) &doL1LongDescEvent; 97610037SARM gem5 Developers break; 97710037SARM gem5 Developers case L2: 97810037SARM gem5 Developers event = (Event *) &doL2LongDescEvent; 97910037SARM gem5 Developers break; 98010037SARM gem5 Developers case L3: 98110037SARM gem5 Developers event = (Event *) &doL3LongDescEvent; 98210037SARM gem5 Developers break; 98310037SARM gem5 Developers default: 98410037SARM gem5 Developers panic("Invalid table lookup level"); 98510037SARM gem5 Developers break; 98610037SARM gem5 Developers } 98710717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 98810621SCurtis.Dunham@arm.com event, (uint8_t*) &currState->longDesc.data, 9899180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 99010037SARM gem5 Developers DPRINTF(TLBVerbose, 99110037SARM gem5 Developers "Adding to walker fifo: queue size before adding: %d\n", 99210037SARM gem5 Developers stateQueues[start_lookup_level].size()); 99310037SARM gem5 Developers stateQueues[start_lookup_level].push_back(currState); 9947439Sdam.sunwoo@arm.com currState = NULL; 9958733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 99611575SDylan.Johnson@ARM.com fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 99711575SDylan.Johnson@ARM.com sizeof(uint64_t), flag, -1, NULL, 99811575SDylan.Johnson@ARM.com &TableWalker::doLongDescriptor); 9997439Sdam.sunwoo@arm.com f = currState->fault; 10008733Sgeoffrey.blake@arm.com } else { 100110037SARM gem5 Developers RequestPtr req = new Request(desc_addr, sizeof(uint64_t), flag, 100210037SARM gem5 Developers masterId); 10038949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 100410037SARM gem5 Developers pkt->dataStatic((uint8_t*) &currState->longDesc.data); 100510717Sandreas.hansson@arm.com port->sendFunctional(pkt); 100610037SARM gem5 Developers doLongDescriptor(); 10078733Sgeoffrey.blake@arm.com delete req; 10088733Sgeoffrey.blake@arm.com delete pkt; 10098733Sgeoffrey.blake@arm.com f = currState->fault; 10107404SAli.Saidi@ARM.com } 10117404SAli.Saidi@ARM.com 10127439Sdam.sunwoo@arm.com return f; 10137404SAli.Saidi@ARM.com} 10147404SAli.Saidi@ARM.com 10157404SAli.Saidi@ARM.comvoid 10167439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 10177439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 10187404SAli.Saidi@ARM.com{ 10197439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 10207439Sdam.sunwoo@arm.com // variables 10217436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 10227436Sdam.sunwoo@arm.com te.shareable = false; // default value 10237582SAli.Saidi@arm.com te.nonCacheable = false; 102410037SARM gem5 Developers te.outerShareable = false; 10257439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 10267404SAli.Saidi@ARM.com switch(texcb) { 10277436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 10287404SAli.Saidi@ARM.com te.nonCacheable = true; 102910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 10307436Sdam.sunwoo@arm.com te.shareable = true; 10317436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10337404SAli.Saidi@ARM.com break; 10347436Sdam.sunwoo@arm.com case 1: // Shareable Device 10357436Sdam.sunwoo@arm.com te.nonCacheable = true; 103610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10377436Sdam.sunwoo@arm.com te.shareable = true; 10387436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10397436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10407436Sdam.sunwoo@arm.com break; 10417436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 104210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10437436Sdam.sunwoo@arm.com te.shareable = s; 10447436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10457436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10467436Sdam.sunwoo@arm.com break; 10477436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 104810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10497436Sdam.sunwoo@arm.com te.shareable = s; 10507436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10517436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10527436Sdam.sunwoo@arm.com break; 10537436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 10547436Sdam.sunwoo@arm.com te.nonCacheable = true; 105510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10567436Sdam.sunwoo@arm.com te.shareable = s; 10577436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10587436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10597436Sdam.sunwoo@arm.com break; 10607436Sdam.sunwoo@arm.com case 5: // Reserved 10617439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10627436Sdam.sunwoo@arm.com break; 10637436Sdam.sunwoo@arm.com case 6: // Implementation Defined 10647439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 10657436Sdam.sunwoo@arm.com break; 10667436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 106710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10687436Sdam.sunwoo@arm.com te.shareable = s; 10697436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10707436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10717436Sdam.sunwoo@arm.com break; 10727436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 10737436Sdam.sunwoo@arm.com te.nonCacheable = true; 107410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10757436Sdam.sunwoo@arm.com te.shareable = false; 10767436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10777436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10787436Sdam.sunwoo@arm.com break; 10797436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 10807439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10817436Sdam.sunwoo@arm.com break; 10827436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 108310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10847436Sdam.sunwoo@arm.com te.shareable = s; 10857404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 10867404SAli.Saidi@ARM.com te.nonCacheable = true; 10877436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 10887436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 10897404SAli.Saidi@ARM.com break; 10907436Sdam.sunwoo@arm.com default: 10917436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 10927404SAli.Saidi@ARM.com } 10937404SAli.Saidi@ARM.com } else { 10947438SAli.Saidi@ARM.com assert(tc); 109510037SARM gem5 Developers PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 109610037SARM gem5 Developers currState->tc, !currState->isSecure)); 109710037SARM gem5 Developers NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 109810037SARM gem5 Developers currState->tc, !currState->isSecure)); 10997436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 11007582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 11017404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 11027404SAli.Saidi@ARM.com case 0: 11037436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 11047436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 11057436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 110610037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 11077404SAli.Saidi@ARM.com break; 11087404SAli.Saidi@ARM.com case 1: 11097436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 11107436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 11117436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 111210037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 11137404SAli.Saidi@ARM.com break; 11147404SAli.Saidi@ARM.com case 2: 11157436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 11167436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 11177436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 111810037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 11197404SAli.Saidi@ARM.com break; 11207404SAli.Saidi@ARM.com case 3: 11217436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 11227436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 11237436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 112410037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 11257404SAli.Saidi@ARM.com break; 11267404SAli.Saidi@ARM.com case 4: 11277436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 11287436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 11297436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 113010037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 11317404SAli.Saidi@ARM.com break; 11327404SAli.Saidi@ARM.com case 5: 11337436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 11347436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 11357436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 113610037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 11377404SAli.Saidi@ARM.com break; 11387404SAli.Saidi@ARM.com case 6: 11397404SAli.Saidi@ARM.com panic("Imp defined type\n"); 11407404SAli.Saidi@ARM.com case 7: 11417436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 11427436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 11437436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 114410037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 11457404SAli.Saidi@ARM.com break; 11467404SAli.Saidi@ARM.com } 11477436Sdam.sunwoo@arm.com 11487436Sdam.sunwoo@arm.com switch(curr_tr) { 11497436Sdam.sunwoo@arm.com case 0: 11507436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 115110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 11527436Sdam.sunwoo@arm.com te.nonCacheable = true; 11537436Sdam.sunwoo@arm.com te.innerAttrs = 1; 11547436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11557436Sdam.sunwoo@arm.com te.shareable = true; 11567436Sdam.sunwoo@arm.com break; 11577436Sdam.sunwoo@arm.com case 1: 11587436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 11597436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 116010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 11617436Sdam.sunwoo@arm.com te.nonCacheable = true; 11627436Sdam.sunwoo@arm.com te.innerAttrs = 3; 11637436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11647436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 11657436Sdam.sunwoo@arm.com te.shareable = true; 11667436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 11677436Sdam.sunwoo@arm.com te.shareable = true; 11687436Sdam.sunwoo@arm.com break; 11697436Sdam.sunwoo@arm.com case 2: 11707436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 11717436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 117210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 11737436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 11747436Sdam.sunwoo@arm.com te.shareable = true; 11757436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 11767436Sdam.sunwoo@arm.com te.shareable = true; 11777436Sdam.sunwoo@arm.com break; 11787436Sdam.sunwoo@arm.com case 3: 11797436Sdam.sunwoo@arm.com panic("Reserved type"); 11807436Sdam.sunwoo@arm.com } 11817436Sdam.sunwoo@arm.com 118210037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 11837436Sdam.sunwoo@arm.com switch(curr_ir) { 11847436Sdam.sunwoo@arm.com case 0: 11857436Sdam.sunwoo@arm.com te.nonCacheable = true; 11867436Sdam.sunwoo@arm.com te.innerAttrs = 0; 11877436Sdam.sunwoo@arm.com break; 11887436Sdam.sunwoo@arm.com case 1: 11897436Sdam.sunwoo@arm.com te.innerAttrs = 5; 11907436Sdam.sunwoo@arm.com break; 11917436Sdam.sunwoo@arm.com case 2: 11927436Sdam.sunwoo@arm.com te.innerAttrs = 6; 11937436Sdam.sunwoo@arm.com break; 11947436Sdam.sunwoo@arm.com case 3: 11957436Sdam.sunwoo@arm.com te.innerAttrs = 7; 11967436Sdam.sunwoo@arm.com break; 11977436Sdam.sunwoo@arm.com } 11987436Sdam.sunwoo@arm.com 11997436Sdam.sunwoo@arm.com switch(curr_or) { 12007436Sdam.sunwoo@arm.com case 0: 12017436Sdam.sunwoo@arm.com te.nonCacheable = true; 12027436Sdam.sunwoo@arm.com te.outerAttrs = 0; 12037436Sdam.sunwoo@arm.com break; 12047436Sdam.sunwoo@arm.com case 1: 12057436Sdam.sunwoo@arm.com te.outerAttrs = 1; 12067436Sdam.sunwoo@arm.com break; 12077436Sdam.sunwoo@arm.com case 2: 12087436Sdam.sunwoo@arm.com te.outerAttrs = 2; 12097436Sdam.sunwoo@arm.com break; 12107436Sdam.sunwoo@arm.com case 3: 12117436Sdam.sunwoo@arm.com te.outerAttrs = 3; 12127436Sdam.sunwoo@arm.com break; 12137436Sdam.sunwoo@arm.com } 12147436Sdam.sunwoo@arm.com } 12157404SAli.Saidi@ARM.com } 121610367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 121710367SAndrew.Bardsley@arm.com "outerAttrs: %d\n", 12187439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 121910037SARM gem5 Developers te.setAttributes(false); 122010037SARM gem5 Developers} 12217436Sdam.sunwoo@arm.com 122210037SARM gem5 Developersvoid 122310037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 122410037SARM gem5 Developers LongDescriptor &lDescriptor) 122510037SARM gem5 Developers{ 122610037SARM gem5 Developers assert(_haveLPAE); 12277436Sdam.sunwoo@arm.com 122810037SARM gem5 Developers uint8_t attr; 122910037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 123010037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 123110037SARM gem5 Developers // translation 123210037SARM gem5 Developers if (isStage2) { 123310037SARM gem5 Developers attr = lDescriptor.memAttr(); 123410037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 123510037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 12367436Sdam.sunwoo@arm.com 123710037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 123810037SARM gem5 Developers 123910037SARM gem5 Developers if (attr_3_2 == 0) { 124010037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 124110037SARM gem5 Developers : TlbEntry::MemoryType::Device; 124210037SARM gem5 Developers te.outerAttrs = 0; 124310037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 124410037SARM gem5 Developers te.nonCacheable = true; 124510037SARM gem5 Developers } else { 124610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 124710037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 124810037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 124910037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 125010037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 125110037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 125210037SARM gem5 Developers } 125310037SARM gem5 Developers } else { 125410037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 125510037SARM gem5 Developers 125610037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 125710037SARM gem5 Developers // value of SCTLR.TRE 125810421Sandreas.hansson@arm.com MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 125910421Sandreas.hansson@arm.com int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, 126010421Sandreas.hansson@arm.com !currState->isSecure); 126110421Sandreas.hansson@arm.com uint32_t mair = currState->tc->readMiscReg(reg_as_int); 126210037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 126310037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 126410037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 126510037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 126610037SARM gem5 Developers 126710037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 126810037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 126910037SARM gem5 Developers // accordingly to provide the illusion of full support 127010037SARM gem5 Developers te.nonCacheable = false; 127110037SARM gem5 Developers 127210037SARM gem5 Developers switch (attr_7_4) { 127310037SARM gem5 Developers case 0x0: 127410037SARM gem5 Developers // Strongly-ordered or Device memory 127510037SARM gem5 Developers if (attr_3_0 == 0x0) 127610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 127710037SARM gem5 Developers else if (attr_3_0 == 0x4) 127810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 127910037SARM gem5 Developers else 128010037SARM gem5 Developers panic("Unpredictable behavior\n"); 128110037SARM gem5 Developers te.nonCacheable = true; 128210037SARM gem5 Developers te.outerAttrs = 0; 128310037SARM gem5 Developers break; 128410037SARM gem5 Developers case 0x4: 128510037SARM gem5 Developers // Normal memory, Outer Non-cacheable 128610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 128710037SARM gem5 Developers te.outerAttrs = 0; 128810037SARM gem5 Developers if (attr_3_0 == 0x4) 128910037SARM gem5 Developers // Inner Non-cacheable 129010037SARM gem5 Developers te.nonCacheable = true; 129110037SARM gem5 Developers else if (attr_3_0 < 0x8) 129210037SARM gem5 Developers panic("Unpredictable behavior\n"); 129310037SARM gem5 Developers break; 129410037SARM gem5 Developers case 0x8: 129510037SARM gem5 Developers case 0x9: 129610037SARM gem5 Developers case 0xa: 129710037SARM gem5 Developers case 0xb: 129810037SARM gem5 Developers case 0xc: 129910037SARM gem5 Developers case 0xd: 130010037SARM gem5 Developers case 0xe: 130110037SARM gem5 Developers case 0xf: 130210037SARM gem5 Developers if (attr_7_4 & 0x4) { 130310037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 130410037SARM gem5 Developers } else { 130510037SARM gem5 Developers te.outerAttrs = 0x2; 130610037SARM gem5 Developers } 130710037SARM gem5 Developers // Normal memory, Outer Cacheable 130810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 130910037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 131010037SARM gem5 Developers panic("Unpredictable behavior\n"); 131110037SARM gem5 Developers break; 131210037SARM gem5 Developers default: 131310037SARM gem5 Developers panic("Unpredictable behavior\n"); 131410037SARM gem5 Developers break; 131510037SARM gem5 Developers } 131610037SARM gem5 Developers 131710037SARM gem5 Developers switch (attr_3_0) { 131810037SARM gem5 Developers case 0x0: 131910037SARM gem5 Developers te.innerAttrs = 0x1; 132010037SARM gem5 Developers break; 132110037SARM gem5 Developers case 0x4: 132210037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 132310037SARM gem5 Developers break; 132410037SARM gem5 Developers case 0x8: 132510037SARM gem5 Developers case 0x9: 132610037SARM gem5 Developers case 0xA: 132710037SARM gem5 Developers case 0xB: 132810037SARM gem5 Developers te.innerAttrs = 6; 132910037SARM gem5 Developers break; 133010037SARM gem5 Developers case 0xC: 133110037SARM gem5 Developers case 0xD: 133210037SARM gem5 Developers case 0xE: 133310037SARM gem5 Developers case 0xF: 133410037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 133510037SARM gem5 Developers break; 133610037SARM gem5 Developers default: 133710037SARM gem5 Developers panic("Unpredictable behavior\n"); 133810037SARM gem5 Developers break; 133910037SARM gem5 Developers } 134010037SARM gem5 Developers } 134110037SARM gem5 Developers 134210037SARM gem5 Developers te.outerShareable = sh == 2; 134310037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 134410037SARM gem5 Developers te.setAttributes(true); 134510037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 134610037SARM gem5 Developers} 134710037SARM gem5 Developers 134810037SARM gem5 Developersvoid 134910037SARM gem5 DevelopersTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 135010037SARM gem5 Developers uint8_t sh) 135110037SARM gem5 Developers{ 135210037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 135310037SARM gem5 Developers 135410037SARM gem5 Developers // Select MAIR 135510037SARM gem5 Developers uint64_t mair; 135610037SARM gem5 Developers switch (currState->el) { 135710037SARM gem5 Developers case EL0: 135810037SARM gem5 Developers case EL1: 135910037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL1); 136010037SARM gem5 Developers break; 136110037SARM gem5 Developers case EL2: 136210037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL2); 136310037SARM gem5 Developers break; 136410037SARM gem5 Developers case EL3: 136510037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL3); 136610037SARM gem5 Developers break; 136710037SARM gem5 Developers default: 136810037SARM gem5 Developers panic("Invalid exception level"); 136910037SARM gem5 Developers break; 137010037SARM gem5 Developers } 137110037SARM gem5 Developers 137210037SARM gem5 Developers // Select attributes 137310037SARM gem5 Developers uint8_t attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 137410037SARM gem5 Developers uint8_t attr_lo = bits(attr, 3, 0); 137510037SARM gem5 Developers uint8_t attr_hi = bits(attr, 7, 4); 137610037SARM gem5 Developers 137710037SARM gem5 Developers // Memory type 137810037SARM gem5 Developers te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 137910037SARM gem5 Developers 138010037SARM gem5 Developers // Cacheability 138110037SARM gem5 Developers te.nonCacheable = false; 138210037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Device || // Device memory 138310037SARM gem5 Developers attr_hi == 0x8 || // Normal memory, Outer Non-cacheable 138410037SARM gem5 Developers attr_lo == 0x8) { // Normal memory, Inner Non-cacheable 138510037SARM gem5 Developers te.nonCacheable = true; 138610037SARM gem5 Developers } 138710037SARM gem5 Developers 138810037SARM gem5 Developers te.shareable = sh == 2; 138910037SARM gem5 Developers te.outerShareable = (sh & 0x2) ? true : false; 139010037SARM gem5 Developers // Attributes formatted according to the 64-bit PAR 139110037SARM gem5 Developers te.attributes = ((uint64_t) attr << 56) | 139210037SARM gem5 Developers (1 << 11) | // LPAE bit 139310037SARM gem5 Developers (te.ns << 9) | // NS bit 139410037SARM gem5 Developers (sh << 7); 13957404SAli.Saidi@ARM.com} 13967404SAli.Saidi@ARM.com 13977404SAli.Saidi@ARM.comvoid 13987404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 13997404SAli.Saidi@ARM.com{ 140010037SARM gem5 Developers if (currState->fault != NoFault) { 140110037SARM gem5 Developers return; 140210037SARM gem5 Developers } 140310037SARM gem5 Developers 14047439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 140510037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 14067404SAli.Saidi@ARM.com TlbEntry te; 14077404SAli.Saidi@ARM.com 14087439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 14097404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 14107404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 14117946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 14127439Sdam.sunwoo@arm.com currState->tc = NULL; 14137439Sdam.sunwoo@arm.com currState->req = NULL; 14147437Sdam.sunwoo@arm.com } 14157406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 14167439Sdam.sunwoo@arm.com if (currState->isFetch) 14177439Sdam.sunwoo@arm.com currState->fault = 141810474Sandreas.hansson@arm.com std::make_shared<PrefetchAbort>( 141910474Sandreas.hansson@arm.com currState->vaddr_tainted, 142010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 142110474Sandreas.hansson@arm.com isStage2, 142210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14237406SAli.Saidi@ARM.com else 14247439Sdam.sunwoo@arm.com currState->fault = 142510474Sandreas.hansson@arm.com std::make_shared<DataAbort>( 142610474Sandreas.hansson@arm.com currState->vaddr_tainted, 142710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 142810474Sandreas.hansson@arm.com currState->isWrite, 142910474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 143010474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14317404SAli.Saidi@ARM.com return; 14327404SAli.Saidi@ARM.com case L1Descriptor::Section: 14337439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 14347436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 14357436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 14367436Sdam.sunwoo@arm.com * AccessFlag0 14377436Sdam.sunwoo@arm.com */ 14387436Sdam.sunwoo@arm.com 143910474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 144010474Sandreas.hansson@arm.com currState->vaddr_tainted, 144110474Sandreas.hansson@arm.com currState->l1Desc.domain(), 144210474Sandreas.hansson@arm.com currState->isWrite, 144310474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L1, 144410474Sandreas.hansson@arm.com isStage2, 144510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14467436Sdam.sunwoo@arm.com } 14477439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 14487404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 14497404SAli.Saidi@ARM.com } 145010037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 145110037SARM gem5 Developers return; 145210037SARM gem5 Developers case L1Descriptor::PageTable: 145310037SARM gem5 Developers { 145410037SARM gem5 Developers Addr l2desc_addr; 145510037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 145610037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 145710037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 145810037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 14597404SAli.Saidi@ARM.com 146010037SARM gem5 Developers // Trickbox address check 146111395Sandreas.sandberg@arm.com currState->fault = testWalk(l2desc_addr, sizeof(uint32_t), 146211395Sandreas.sandberg@arm.com currState->l1Desc.domain(), L2); 14637404SAli.Saidi@ARM.com 146410037SARM gem5 Developers if (currState->fault) { 146510037SARM gem5 Developers if (!currState->timing) { 146610037SARM gem5 Developers currState->tc = NULL; 146710037SARM gem5 Developers currState->req = NULL; 146810037SARM gem5 Developers } 146910037SARM gem5 Developers return; 147010037SARM gem5 Developers } 147110037SARM gem5 Developers 147210836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 147310037SARM gem5 Developers if (currState->isSecure) 147410037SARM gem5 Developers flag.set(Request::SECURE); 147510037SARM gem5 Developers 147610037SARM gem5 Developers bool delayed; 147710037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 147810037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 147910037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 148010037SARM gem5 Developers &TableWalker::doL2Descriptor); 148110037SARM gem5 Developers if (delayed) { 148210037SARM gem5 Developers currState->delayed = true; 148310037SARM gem5 Developers } 148410037SARM gem5 Developers 148510037SARM gem5 Developers return; 148610037SARM gem5 Developers } 148710037SARM gem5 Developers default: 148810037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 148910037SARM gem5 Developers } 149010037SARM gem5 Developers} 149110037SARM gem5 Developers 149210037SARM gem5 Developersvoid 149310037SARM gem5 DevelopersTableWalker::doLongDescriptor() 149410037SARM gem5 Developers{ 149510037SARM gem5 Developers if (currState->fault != NoFault) { 149610037SARM gem5 Developers return; 149710037SARM gem5 Developers } 149810037SARM gem5 Developers 149910037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 150010037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 150110037SARM gem5 Developers currState->longDesc.data, 150210037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 150310037SARM gem5 Developers 150410037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 150510037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 150610037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 150710037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 150810037SARM gem5 Developers currState->longDesc.lookupLevel, 150910037SARM gem5 Developers currState->longDesc.data, 151010037SARM gem5 Developers currState->longDesc.pxn(), 151110037SARM gem5 Developers currState->longDesc.xn(), 151210037SARM gem5 Developers currState->longDesc.ap(), 151310037SARM gem5 Developers currState->longDesc.af(), 151410037SARM gem5 Developers currState->longDesc.type()); 151510037SARM gem5 Developers } else { 151610037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 151710037SARM gem5 Developers currState->longDesc.lookupLevel, 151810037SARM gem5 Developers currState->longDesc.data, 151910037SARM gem5 Developers currState->longDesc.type()); 152010037SARM gem5 Developers } 152110037SARM gem5 Developers 152210037SARM gem5 Developers TlbEntry te; 152310037SARM gem5 Developers 152410037SARM gem5 Developers switch (currState->longDesc.type()) { 152510037SARM gem5 Developers case LongDescriptor::Invalid: 15267439Sdam.sunwoo@arm.com if (!currState->timing) { 15277439Sdam.sunwoo@arm.com currState->tc = NULL; 15287439Sdam.sunwoo@arm.com currState->req = NULL; 15297437Sdam.sunwoo@arm.com } 15307404SAli.Saidi@ARM.com 153110037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 153210037SARM gem5 Developers currState->longDesc.lookupLevel, 153310037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 153410037SARM gem5 Developers if (currState->isFetch) 153510474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 153610037SARM gem5 Developers currState->vaddr_tainted, 153710037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 153810037SARM gem5 Developers isStage2, 153910037SARM gem5 Developers ArmFault::LpaeTran); 154010037SARM gem5 Developers else 154110474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 154210037SARM gem5 Developers currState->vaddr_tainted, 154310037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 154410037SARM gem5 Developers currState->isWrite, 154510037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 154610037SARM gem5 Developers isStage2, 154710037SARM gem5 Developers ArmFault::LpaeTran); 15487404SAli.Saidi@ARM.com return; 154910037SARM gem5 Developers case LongDescriptor::Block: 155010037SARM gem5 Developers case LongDescriptor::Page: 155110037SARM gem5 Developers { 155210037SARM gem5 Developers bool fault = false; 155310037SARM gem5 Developers bool aff = false; 155410037SARM gem5 Developers // Check for address size fault 155510037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 155610037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 155710037SARM gem5 Developers currState->longDesc.offsetBits()), 155810037SARM gem5 Developers currState->physAddrRange)) { 155910037SARM gem5 Developers fault = true; 156010037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 156110037SARM gem5 Developers currState->longDesc.lookupLevel); 156210037SARM gem5 Developers // Check for access fault 156310037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 156410037SARM gem5 Developers fault = true; 156510037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 156610037SARM gem5 Developers currState->longDesc.lookupLevel); 156710037SARM gem5 Developers aff = true; 156810037SARM gem5 Developers } 156910037SARM gem5 Developers if (fault) { 157010037SARM gem5 Developers if (currState->isFetch) 157110474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 157210037SARM gem5 Developers currState->vaddr_tainted, 157310037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 157410037SARM gem5 Developers currState->longDesc.lookupLevel, 157510037SARM gem5 Developers isStage2, 157610037SARM gem5 Developers ArmFault::LpaeTran); 157710037SARM gem5 Developers else 157810474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 157910037SARM gem5 Developers currState->vaddr_tainted, 158010037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 158110037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 158210037SARM gem5 Developers currState->longDesc.lookupLevel, 158310037SARM gem5 Developers isStage2, 158410037SARM gem5 Developers ArmFault::LpaeTran); 158510037SARM gem5 Developers } else { 158610037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 158710037SARM gem5 Developers } 158810037SARM gem5 Developers } 158910037SARM gem5 Developers return; 159010037SARM gem5 Developers case LongDescriptor::Table: 159110037SARM gem5 Developers { 159210037SARM gem5 Developers // Set hierarchical permission flags 159310037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 159410037SARM gem5 Developers currState->longDesc.secureTable(); 159510037SARM gem5 Developers currState->rwTable = currState->rwTable && 159610037SARM gem5 Developers currState->longDesc.rwTable(); 159710037SARM gem5 Developers currState->userTable = currState->userTable && 159810037SARM gem5 Developers currState->longDesc.userTable(); 159910037SARM gem5 Developers currState->xnTable = currState->xnTable || 160010037SARM gem5 Developers currState->longDesc.xnTable(); 160110037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 160210037SARM gem5 Developers currState->longDesc.pxnTable(); 16037404SAli.Saidi@ARM.com 160410037SARM gem5 Developers // Set up next level lookup 160510037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 160610037SARM gem5 Developers currState->vaddr); 16077439Sdam.sunwoo@arm.com 160810037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 160910037SARM gem5 Developers currState->longDesc.lookupLevel, 161010037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 161110037SARM gem5 Developers next_desc_addr, 161210037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 161310037SARM gem5 Developers 161410037SARM gem5 Developers // Check for address size fault 161510037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 161610037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 161710037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 161810037SARM gem5 Developers currState->longDesc.lookupLevel); 161910037SARM gem5 Developers if (currState->isFetch) 162010474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 162110037SARM gem5 Developers currState->vaddr_tainted, 162210037SARM gem5 Developers ArmFault::AddressSizeLL 162310037SARM gem5 Developers + currState->longDesc.lookupLevel, 162410037SARM gem5 Developers isStage2, 162510037SARM gem5 Developers ArmFault::LpaeTran); 162610037SARM gem5 Developers else 162710474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 162810037SARM gem5 Developers currState->vaddr_tainted, 162910037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 163010037SARM gem5 Developers ArmFault::AddressSizeLL 163110037SARM gem5 Developers + currState->longDesc.lookupLevel, 163210037SARM gem5 Developers isStage2, 163310037SARM gem5 Developers ArmFault::LpaeTran); 163410037SARM gem5 Developers return; 16357437Sdam.sunwoo@arm.com } 16367404SAli.Saidi@ARM.com 163710037SARM gem5 Developers // Trickbox address check 163811395Sandreas.sandberg@arm.com currState->fault = testWalk( 163911395Sandreas.sandberg@arm.com next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client, 164011395Sandreas.sandberg@arm.com toLookupLevel(currState->longDesc.lookupLevel +1)); 16417404SAli.Saidi@ARM.com 164210037SARM gem5 Developers if (currState->fault) { 164310037SARM gem5 Developers if (!currState->timing) { 164410037SARM gem5 Developers currState->tc = NULL; 164510037SARM gem5 Developers currState->req = NULL; 164610037SARM gem5 Developers } 164710037SARM gem5 Developers return; 164810037SARM gem5 Developers } 164910037SARM gem5 Developers 165010836Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 165110037SARM gem5 Developers if (currState->secureLookup) 165210037SARM gem5 Developers flag.set(Request::SECURE); 165310037SARM gem5 Developers 165410037SARM gem5 Developers currState->longDesc.lookupLevel = 165510037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 165610037SARM gem5 Developers Event *event = NULL; 165710037SARM gem5 Developers switch (currState->longDesc.lookupLevel) { 165810037SARM gem5 Developers case L1: 165910037SARM gem5 Developers assert(currState->aarch64); 166010037SARM gem5 Developers event = &doL1LongDescEvent; 166110037SARM gem5 Developers break; 166210037SARM gem5 Developers case L2: 166310037SARM gem5 Developers event = &doL2LongDescEvent; 166410037SARM gem5 Developers break; 166510037SARM gem5 Developers case L3: 166610037SARM gem5 Developers event = &doL3LongDescEvent; 166710037SARM gem5 Developers break; 166810037SARM gem5 Developers default: 166910037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 167010037SARM gem5 Developers break; 167110037SARM gem5 Developers } 167210037SARM gem5 Developers 167310037SARM gem5 Developers bool delayed; 167410037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 167510037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 167610037SARM gem5 Developers &TableWalker::doLongDescriptor); 167710037SARM gem5 Developers if (delayed) { 167810037SARM gem5 Developers currState->delayed = true; 167910037SARM gem5 Developers } 16807404SAli.Saidi@ARM.com } 16817404SAli.Saidi@ARM.com return; 16827404SAli.Saidi@ARM.com default: 16837404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 16847404SAli.Saidi@ARM.com } 16857404SAli.Saidi@ARM.com} 16867404SAli.Saidi@ARM.com 16877404SAli.Saidi@ARM.comvoid 16887404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 16897404SAli.Saidi@ARM.com{ 169010037SARM gem5 Developers if (currState->fault != NoFault) { 169110037SARM gem5 Developers return; 169210037SARM gem5 Developers } 169310037SARM gem5 Developers 16947439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 169510037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 16967404SAli.Saidi@ARM.com TlbEntry te; 16977404SAli.Saidi@ARM.com 16987439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 16997404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 17007946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 17017439Sdam.sunwoo@arm.com currState->tc = NULL; 17027439Sdam.sunwoo@arm.com currState->req = NULL; 17037437Sdam.sunwoo@arm.com } 17047439Sdam.sunwoo@arm.com if (currState->isFetch) 170510474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 170610474Sandreas.hansson@arm.com currState->vaddr_tainted, 170710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L2, 170810474Sandreas.hansson@arm.com isStage2, 170910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17107406SAli.Saidi@ARM.com else 171110474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 171210474Sandreas.hansson@arm.com currState->vaddr_tainted, currState->l1Desc.domain(), 171310474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L2, 171410474Sandreas.hansson@arm.com isStage2, 171510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17167404SAli.Saidi@ARM.com return; 17177404SAli.Saidi@ARM.com } 17187404SAli.Saidi@ARM.com 17197439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 17207436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 17217436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 17227436Sdam.sunwoo@arm.com */ 172310037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 172410037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 17257436Sdam.sunwoo@arm.com 172610474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 172710474Sandreas.hansson@arm.com currState->vaddr_tainted, 172810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 172910474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L2, isStage2, 173010474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17317436Sdam.sunwoo@arm.com } 17327436Sdam.sunwoo@arm.com 173310037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 17347437Sdam.sunwoo@arm.com} 17357437Sdam.sunwoo@arm.com 17367437Sdam.sunwoo@arm.comvoid 17377437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 17387437Sdam.sunwoo@arm.com{ 173910037SARM gem5 Developers currState = stateQueues[L1].front(); 17407439Sdam.sunwoo@arm.com currState->delayed = false; 174110037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 174210037SARM gem5 Developers if (currState->stage2Tran) { 174310037SARM gem5 Developers delete currState->stage2Tran; 174410037SARM gem5 Developers currState->stage2Tran = NULL; 174510037SARM gem5 Developers } 174610037SARM gem5 Developers 17477437Sdam.sunwoo@arm.com 17487578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 17497578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 17507578Sdam.sunwoo@arm.com 175110037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 17527437Sdam.sunwoo@arm.com doL1Descriptor(); 17537437Sdam.sunwoo@arm.com 175410037SARM gem5 Developers stateQueues[L1].pop_front(); 17557437Sdam.sunwoo@arm.com // Check if fault was generated 17567439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 17577439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 17587439Sdam.sunwoo@arm.com currState->tc, currState->mode); 175910621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 17607437Sdam.sunwoo@arm.com 17617728SAli.Saidi@ARM.com pending = false; 17627728SAli.Saidi@ARM.com nextWalk(currState->tc); 17637728SAli.Saidi@ARM.com 17647439Sdam.sunwoo@arm.com currState->req = NULL; 17657439Sdam.sunwoo@arm.com currState->tc = NULL; 17667439Sdam.sunwoo@arm.com currState->delayed = false; 17678510SAli.Saidi@ARM.com delete currState; 17687437Sdam.sunwoo@arm.com } 17697439Sdam.sunwoo@arm.com else if (!currState->delayed) { 17707653Sgene.wu@arm.com // delay is not set so there is no L2 to do 177110037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 177210037SARM gem5 Developers if (!currState->doingStage2) { 177310621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 177410037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 177510037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 177610037SARM gem5 Developers currState->transState, currState->mode); 177710621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 177810037SARM gem5 Developers } 17797437Sdam.sunwoo@arm.com 17807728SAli.Saidi@ARM.com pending = false; 17817728SAli.Saidi@ARM.com nextWalk(currState->tc); 17827728SAli.Saidi@ARM.com 17837439Sdam.sunwoo@arm.com currState->req = NULL; 17847439Sdam.sunwoo@arm.com currState->tc = NULL; 17857439Sdam.sunwoo@arm.com currState->delayed = false; 17867653Sgene.wu@arm.com delete currState; 17877653Sgene.wu@arm.com } else { 17887653Sgene.wu@arm.com // need to do L2 descriptor 178910037SARM gem5 Developers stateQueues[L2].push_back(currState); 17907437Sdam.sunwoo@arm.com } 17917439Sdam.sunwoo@arm.com currState = NULL; 17927437Sdam.sunwoo@arm.com} 17937437Sdam.sunwoo@arm.com 17947437Sdam.sunwoo@arm.comvoid 17957437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 17967437Sdam.sunwoo@arm.com{ 179710037SARM gem5 Developers currState = stateQueues[L2].front(); 17987439Sdam.sunwoo@arm.com assert(currState->delayed); 179910037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 180010037SARM gem5 Developers if (currState->stage2Tran) { 180110037SARM gem5 Developers delete currState->stage2Tran; 180210037SARM gem5 Developers currState->stage2Tran = NULL; 180310037SARM gem5 Developers } 18047437Sdam.sunwoo@arm.com 18057439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 180610037SARM gem5 Developers currState->vaddr_tainted); 18077437Sdam.sunwoo@arm.com doL2Descriptor(); 18087437Sdam.sunwoo@arm.com 18097437Sdam.sunwoo@arm.com // Check if fault was generated 18107439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 18117439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 18127439Sdam.sunwoo@arm.com currState->tc, currState->mode); 181310621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 18147437Sdam.sunwoo@arm.com } 18157437Sdam.sunwoo@arm.com else { 181610037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 181710037SARM gem5 Developers if (!currState->doingStage2) { 181810621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 181910037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 182010037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, 182110037SARM gem5 Developers currState->tc, currState->transState, currState->mode); 182210621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 182310037SARM gem5 Developers } 18247437Sdam.sunwoo@arm.com } 18257437Sdam.sunwoo@arm.com 18267728SAli.Saidi@ARM.com 182710037SARM gem5 Developers stateQueues[L2].pop_front(); 18287728SAli.Saidi@ARM.com pending = false; 18297728SAli.Saidi@ARM.com nextWalk(currState->tc); 18307728SAli.Saidi@ARM.com 18317439Sdam.sunwoo@arm.com currState->req = NULL; 18327439Sdam.sunwoo@arm.com currState->tc = NULL; 18337439Sdam.sunwoo@arm.com currState->delayed = false; 18347439Sdam.sunwoo@arm.com 18357653Sgene.wu@arm.com delete currState; 18367439Sdam.sunwoo@arm.com currState = NULL; 18377404SAli.Saidi@ARM.com} 18387404SAli.Saidi@ARM.com 18397728SAli.Saidi@ARM.comvoid 184010037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 184110037SARM gem5 Developers{ 184210037SARM gem5 Developers doLongDescriptorWrapper(L0); 184310037SARM gem5 Developers} 184410037SARM gem5 Developers 184510037SARM gem5 Developersvoid 184610037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 184710037SARM gem5 Developers{ 184810037SARM gem5 Developers doLongDescriptorWrapper(L1); 184910037SARM gem5 Developers} 185010037SARM gem5 Developers 185110037SARM gem5 Developersvoid 185210037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 185310037SARM gem5 Developers{ 185410037SARM gem5 Developers doLongDescriptorWrapper(L2); 185510037SARM gem5 Developers} 185610037SARM gem5 Developers 185710037SARM gem5 Developersvoid 185810037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 185910037SARM gem5 Developers{ 186010037SARM gem5 Developers doLongDescriptorWrapper(L3); 186110037SARM gem5 Developers} 186210037SARM gem5 Developers 186310037SARM gem5 Developersvoid 186410037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 186510037SARM gem5 Developers{ 186610037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 186710037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 186810037SARM gem5 Developers currState->delayed = false; 186910037SARM gem5 Developers 187010037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 187110037SARM gem5 Developers if (currState->stage2Tran) { 187210037SARM gem5 Developers delete currState->stage2Tran; 187310037SARM gem5 Developers currState->stage2Tran = NULL; 187410037SARM gem5 Developers } 187510037SARM gem5 Developers 187610037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 187710037SARM gem5 Developers currState->vaddr_tainted); 187810037SARM gem5 Developers doLongDescriptor(); 187910037SARM gem5 Developers 188010037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 188110037SARM gem5 Developers 188210037SARM gem5 Developers if (currState->fault != NoFault) { 188310037SARM gem5 Developers // A fault was generated 188410037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 188510037SARM gem5 Developers currState->tc, currState->mode); 188610037SARM gem5 Developers 188710037SARM gem5 Developers pending = false; 188810037SARM gem5 Developers nextWalk(currState->tc); 188910037SARM gem5 Developers 189010037SARM gem5 Developers currState->req = NULL; 189110037SARM gem5 Developers currState->tc = NULL; 189210037SARM gem5 Developers currState->delayed = false; 189310037SARM gem5 Developers delete currState; 189410037SARM gem5 Developers } else if (!currState->delayed) { 189510037SARM gem5 Developers // No additional lookups required 189610037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 189710037SARM gem5 Developers if (!currState->doingStage2) { 189810037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 189910621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 190010037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 190110037SARM gem5 Developers currState->transState, 190210037SARM gem5 Developers currState->mode); 190310621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 190410037SARM gem5 Developers } 190510037SARM gem5 Developers 190610037SARM gem5 Developers pending = false; 190710037SARM gem5 Developers nextWalk(currState->tc); 190810037SARM gem5 Developers 190910037SARM gem5 Developers currState->req = NULL; 191010037SARM gem5 Developers currState->tc = NULL; 191110037SARM gem5 Developers currState->delayed = false; 191210037SARM gem5 Developers delete currState; 191310037SARM gem5 Developers } else { 191410037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 191510037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 191610037SARM gem5 Developers // Need to perform additional lookups 191710037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 191810037SARM gem5 Developers } 191910037SARM gem5 Developers currState = NULL; 192010037SARM gem5 Developers} 192110037SARM gem5 Developers 192210037SARM gem5 Developers 192310037SARM gem5 Developersvoid 19247728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 19257728SAli.Saidi@ARM.com{ 19267728SAli.Saidi@ARM.com if (pendingQueue.size()) 19279309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 192810509SAli.Saidi@ARM.com else 192910509SAli.Saidi@ARM.com completeDrain(); 19307728SAli.Saidi@ARM.com} 19317728SAli.Saidi@ARM.com 193210037SARM gem5 Developersbool 193310037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 193410037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 193510037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 193610037SARM gem5 Developers{ 193710037SARM gem5 Developers bool isTiming = currState->timing; 19387728SAli.Saidi@ARM.com 193911575SDylan.Johnson@ARM.com DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n", 194011575SDylan.Johnson@ARM.com descAddr, currState->stage2Req); 194111575SDylan.Johnson@ARM.com 194211575SDylan.Johnson@ARM.com // If this translation has a stage 2 then we know descAddr is an IPA and 194311575SDylan.Johnson@ARM.com // needs to be translated before we can access the page table. Do that 194411575SDylan.Johnson@ARM.com // check here. 194510037SARM gem5 Developers if (currState->stage2Req) { 194610037SARM gem5 Developers Fault fault; 194710037SARM gem5 Developers flags = flags | TLB::MustBeOne; 194810037SARM gem5 Developers 194910037SARM gem5 Developers if (isTiming) { 195010037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 195110037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 195210037SARM gem5 Developers currState->vaddr); 195310037SARM gem5 Developers currState->stage2Tran = tran; 195410037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 195510717Sandreas.hansson@arm.com flags); 195610037SARM gem5 Developers fault = tran->fault; 195710037SARM gem5 Developers } else { 195810037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 195910717Sandreas.hansson@arm.com currState->vaddr, descAddr, data, numBytes, flags, 196010037SARM gem5 Developers currState->functional); 196110037SARM gem5 Developers } 196210037SARM gem5 Developers 196310037SARM gem5 Developers if (fault != NoFault) { 196410037SARM gem5 Developers currState->fault = fault; 196510037SARM gem5 Developers } 196610037SARM gem5 Developers if (isTiming) { 196710037SARM gem5 Developers if (queueIndex >= 0) { 196810037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 196910037SARM gem5 Developers stateQueues[queueIndex].size()); 197010037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 197110037SARM gem5 Developers currState = NULL; 197210037SARM gem5 Developers } 197310037SARM gem5 Developers } else { 197410037SARM gem5 Developers (this->*doDescriptor)(); 197510037SARM gem5 Developers } 197610037SARM gem5 Developers } else { 197710037SARM gem5 Developers if (isTiming) { 197810717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 197910621SCurtis.Dunham@arm.com currState->tc->getCpuPtr()->clockPeriod(),flags); 198010037SARM gem5 Developers if (queueIndex >= 0) { 198110037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 198210037SARM gem5 Developers stateQueues[queueIndex].size()); 198310037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 198410037SARM gem5 Developers currState = NULL; 198510037SARM gem5 Developers } 198610037SARM gem5 Developers } else if (!currState->functional) { 198710717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 198810037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 198910037SARM gem5 Developers (this->*doDescriptor)(); 199010037SARM gem5 Developers } else { 199110037SARM gem5 Developers RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 199210037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 199310037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 199410037SARM gem5 Developers pkt->dataStatic(data); 199510717Sandreas.hansson@arm.com port->sendFunctional(pkt); 199610037SARM gem5 Developers (this->*doDescriptor)(); 199710037SARM gem5 Developers delete req; 199810037SARM gem5 Developers delete pkt; 199910037SARM gem5 Developers } 200010037SARM gem5 Developers } 200110037SARM gem5 Developers return (isTiming); 200210037SARM gem5 Developers} 200310037SARM gem5 Developers 200410037SARM gem5 Developersvoid 200510037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 200610037SARM gem5 Developers{ 200710037SARM gem5 Developers TlbEntry te; 200810037SARM gem5 Developers 200910037SARM gem5 Developers // Create and fill a new page table entry 201010037SARM gem5 Developers te.valid = true; 201110037SARM gem5 Developers te.longDescFormat = longDescriptor; 201210037SARM gem5 Developers te.isHyp = currState->isHyp; 201310037SARM gem5 Developers te.asid = currState->asid; 201410037SARM gem5 Developers te.vmid = currState->vmid; 201510037SARM gem5 Developers te.N = descriptor.offsetBits(); 201610037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 201710037SARM gem5 Developers te.size = (1<<te.N) - 1; 201810037SARM gem5 Developers te.pfn = descriptor.pfn(); 201910037SARM gem5 Developers te.domain = descriptor.domain(); 202010037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 202110037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 202210037SARM gem5 Developers te.nstid = !currState->isSecure; 202310037SARM gem5 Developers te.xn = descriptor.xn(); 202410037SARM gem5 Developers if (currState->aarch64) 202510037SARM gem5 Developers te.el = currState->el; 202610037SARM gem5 Developers else 202710037SARM gem5 Developers te.el = 1; 202810037SARM gem5 Developers 202910621SCurtis.Dunham@arm.com statPageSizes[pageSizeNtoStatBin(te.N)]++; 203010621SCurtis.Dunham@arm.com statRequestOrigin[COMPLETED][currState->isFetch]++; 203110621SCurtis.Dunham@arm.com 203210037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 203310037SARM gem5 Developers // as global 203410037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 203510037SARM gem5 Developers if (longDescriptor) { 203610037SARM gem5 Developers LongDescriptor lDescriptor = 203710037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 203810037SARM gem5 Developers 203910037SARM gem5 Developers te.xn |= currState->xnTable; 204010037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 204110037SARM gem5 Developers if (isStage2) { 204210037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 204310037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 204410037SARM gem5 Developers te.hap = lDescriptor.ap(); 204510037SARM gem5 Developers } else { 204610037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 204710037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 204810037SARM gem5 Developers } 204910037SARM gem5 Developers if (currState->aarch64) 205010037SARM gem5 Developers memAttrsAArch64(currState->tc, te, currState->longDesc.attrIndx(), 205110037SARM gem5 Developers currState->longDesc.sh()); 205210037SARM gem5 Developers else 205310037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 205410037SARM gem5 Developers } else { 205510037SARM gem5 Developers te.ap = descriptor.ap(); 205610037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 205710037SARM gem5 Developers descriptor.shareable()); 205810037SARM gem5 Developers } 205910037SARM gem5 Developers 206010037SARM gem5 Developers // Debug output 206110037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 206210037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 206310037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 206410037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 206510037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 206610037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 206710037SARM gem5 Developers te.nonCacheable, te.ns); 206810037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 206910037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 207010037SARM gem5 Developers descriptor.getRawData()); 207110037SARM gem5 Developers 207210037SARM gem5 Developers // Insert the entry into the TLB 207310037SARM gem5 Developers tlb->insert(currState->vaddr, te); 207410037SARM gem5 Developers if (!currState->timing) { 207510037SARM gem5 Developers currState->tc = NULL; 207610037SARM gem5 Developers currState->req = NULL; 207710037SARM gem5 Developers } 207810037SARM gem5 Developers} 20797728SAli.Saidi@ARM.com 20807404SAli.Saidi@ARM.comArmISA::TableWalker * 20817404SAli.Saidi@ARM.comArmTableWalkerParams::create() 20827404SAli.Saidi@ARM.com{ 20837404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 20847404SAli.Saidi@ARM.com} 20857404SAli.Saidi@ARM.com 208610037SARM gem5 DevelopersLookupLevel 208710037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 208810037SARM gem5 Developers{ 208910037SARM gem5 Developers switch (lookup_level_as_int) { 209010037SARM gem5 Developers case L1: 209110037SARM gem5 Developers return L1; 209210037SARM gem5 Developers case L2: 209310037SARM gem5 Developers return L2; 209410037SARM gem5 Developers case L3: 209510037SARM gem5 Developers return L3; 209610037SARM gem5 Developers default: 209710037SARM gem5 Developers panic("Invalid lookup level conversion"); 209810037SARM gem5 Developers } 209910037SARM gem5 Developers} 210010621SCurtis.Dunham@arm.com 210110621SCurtis.Dunham@arm.com/* this method keeps track of the table walker queue's residency, so 210210621SCurtis.Dunham@arm.com * needs to be called whenever requests start and complete. */ 210310621SCurtis.Dunham@arm.comvoid 210410621SCurtis.Dunham@arm.comTableWalker::pendingChange() 210510621SCurtis.Dunham@arm.com{ 210610621SCurtis.Dunham@arm.com unsigned n = pendingQueue.size(); 210710621SCurtis.Dunham@arm.com if ((currState != NULL) && (currState != pendingQueue.front())) { 210810621SCurtis.Dunham@arm.com ++n; 210910621SCurtis.Dunham@arm.com } 211010621SCurtis.Dunham@arm.com 211110621SCurtis.Dunham@arm.com if (n != pendingReqs) { 211210621SCurtis.Dunham@arm.com Tick now = curTick(); 211310621SCurtis.Dunham@arm.com statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 211410621SCurtis.Dunham@arm.com pendingReqs = n; 211510621SCurtis.Dunham@arm.com pendingChangeTick = now; 211610621SCurtis.Dunham@arm.com } 211710621SCurtis.Dunham@arm.com} 211810621SCurtis.Dunham@arm.com 211911395Sandreas.sandberg@arm.comFault 212011395Sandreas.sandberg@arm.comTableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, 212111395Sandreas.sandberg@arm.com LookupLevel lookup_level) 212211395Sandreas.sandberg@arm.com{ 212311395Sandreas.sandberg@arm.com return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure, 212411395Sandreas.sandberg@arm.com currState->mode, domain, lookup_level); 212511395Sandreas.sandberg@arm.com} 212611395Sandreas.sandberg@arm.com 212711395Sandreas.sandberg@arm.com 212810621SCurtis.Dunham@arm.comuint8_t 212910621SCurtis.Dunham@arm.comTableWalker::pageSizeNtoStatBin(uint8_t N) 213010621SCurtis.Dunham@arm.com{ 213110621SCurtis.Dunham@arm.com /* for statPageSizes */ 213210621SCurtis.Dunham@arm.com switch(N) { 213310621SCurtis.Dunham@arm.com case 12: return 0; // 4K 213410621SCurtis.Dunham@arm.com case 14: return 1; // 16K (using 16K granule in v8-64) 213510621SCurtis.Dunham@arm.com case 16: return 2; // 64K 213610621SCurtis.Dunham@arm.com case 20: return 3; // 1M 213710621SCurtis.Dunham@arm.com case 21: return 4; // 2M-LPAE 213810621SCurtis.Dunham@arm.com case 24: return 5; // 16M 213910621SCurtis.Dunham@arm.com case 25: return 6; // 32M (using 16K granule in v8-64) 214010621SCurtis.Dunham@arm.com case 29: return 7; // 512M (using 64K granule in v8-64) 214110621SCurtis.Dunham@arm.com case 30: return 8; // 1G-LPAE 214210621SCurtis.Dunham@arm.com default: 214310621SCurtis.Dunham@arm.com panic("unknown page size"); 214410621SCurtis.Dunham@arm.com return 255; 214510621SCurtis.Dunham@arm.com } 214610621SCurtis.Dunham@arm.com} 214710621SCurtis.Dunham@arm.com 214810621SCurtis.Dunham@arm.comvoid 214910621SCurtis.Dunham@arm.comTableWalker::regStats() 215010621SCurtis.Dunham@arm.com{ 215111522Sstephan.diestelhorst@arm.com ClockedObject::regStats(); 215211522Sstephan.diestelhorst@arm.com 215310621SCurtis.Dunham@arm.com statWalks 215410621SCurtis.Dunham@arm.com .name(name() + ".walks") 215510621SCurtis.Dunham@arm.com .desc("Table walker walks requested") 215610621SCurtis.Dunham@arm.com ; 215710621SCurtis.Dunham@arm.com 215810621SCurtis.Dunham@arm.com statWalksShortDescriptor 215910621SCurtis.Dunham@arm.com .name(name() + ".walksShort") 216010621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with short descriptors") 216110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 216210621SCurtis.Dunham@arm.com ; 216310621SCurtis.Dunham@arm.com 216410621SCurtis.Dunham@arm.com statWalksLongDescriptor 216510621SCurtis.Dunham@arm.com .name(name() + ".walksLong") 216610621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with long descriptors") 216710621SCurtis.Dunham@arm.com .flags(Stats::nozero) 216810621SCurtis.Dunham@arm.com ; 216910621SCurtis.Dunham@arm.com 217010621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel 217110621SCurtis.Dunham@arm.com .init(2) 217210621SCurtis.Dunham@arm.com .name(name() + ".walksShortTerminationLevel") 217310621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 217410621SCurtis.Dunham@arm.com "with short descriptors terminate") 217510621SCurtis.Dunham@arm.com .flags(Stats::nozero) 217610621SCurtis.Dunham@arm.com ; 217710621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(0, "Level1"); 217810621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(1, "Level2"); 217910621SCurtis.Dunham@arm.com 218010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel 218110621SCurtis.Dunham@arm.com .init(4) 218210621SCurtis.Dunham@arm.com .name(name() + ".walksLongTerminationLevel") 218310621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 218410621SCurtis.Dunham@arm.com "with long descriptors terminate") 218510621SCurtis.Dunham@arm.com .flags(Stats::nozero) 218610621SCurtis.Dunham@arm.com ; 218710621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(0, "Level0"); 218810621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(1, "Level1"); 218910621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(2, "Level2"); 219010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(3, "Level3"); 219110621SCurtis.Dunham@arm.com 219210621SCurtis.Dunham@arm.com statSquashedBefore 219310621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedBefore") 219410621SCurtis.Dunham@arm.com .desc("Table walks squashed before starting") 219510621SCurtis.Dunham@arm.com .flags(Stats::nozero) 219610621SCurtis.Dunham@arm.com ; 219710621SCurtis.Dunham@arm.com 219810621SCurtis.Dunham@arm.com statSquashedAfter 219910621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedAfter") 220010621SCurtis.Dunham@arm.com .desc("Table walks squashed after completion") 220110621SCurtis.Dunham@arm.com .flags(Stats::nozero) 220210621SCurtis.Dunham@arm.com ; 220310621SCurtis.Dunham@arm.com 220410621SCurtis.Dunham@arm.com statWalkWaitTime 220510621SCurtis.Dunham@arm.com .init(16) 220610621SCurtis.Dunham@arm.com .name(name() + ".walkWaitTime") 220710621SCurtis.Dunham@arm.com .desc("Table walker wait (enqueue to first request) latency") 220810621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 220910621SCurtis.Dunham@arm.com ; 221010621SCurtis.Dunham@arm.com 221110621SCurtis.Dunham@arm.com statWalkServiceTime 221210621SCurtis.Dunham@arm.com .init(16) 221310621SCurtis.Dunham@arm.com .name(name() + ".walkCompletionTime") 221410621SCurtis.Dunham@arm.com .desc("Table walker service (enqueue to completion) latency") 221510621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 221610621SCurtis.Dunham@arm.com ; 221710621SCurtis.Dunham@arm.com 221810621SCurtis.Dunham@arm.com statPendingWalks 221910621SCurtis.Dunham@arm.com .init(16) 222010621SCurtis.Dunham@arm.com .name(name() + ".walksPending") 222110621SCurtis.Dunham@arm.com .desc("Table walker pending requests distribution") 222210621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 222310621SCurtis.Dunham@arm.com ; 222410621SCurtis.Dunham@arm.com 222510621SCurtis.Dunham@arm.com statPageSizes // see DDI 0487A D4-1661 222610621SCurtis.Dunham@arm.com .init(9) 222710621SCurtis.Dunham@arm.com .name(name() + ".walkPageSizes") 222810621SCurtis.Dunham@arm.com .desc("Table walker page sizes translated") 222910621SCurtis.Dunham@arm.com .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 223010621SCurtis.Dunham@arm.com ; 223110621SCurtis.Dunham@arm.com statPageSizes.subname(0, "4K"); 223210621SCurtis.Dunham@arm.com statPageSizes.subname(1, "16K"); 223310621SCurtis.Dunham@arm.com statPageSizes.subname(2, "64K"); 223410621SCurtis.Dunham@arm.com statPageSizes.subname(3, "1M"); 223510621SCurtis.Dunham@arm.com statPageSizes.subname(4, "2M"); 223610621SCurtis.Dunham@arm.com statPageSizes.subname(5, "16M"); 223710621SCurtis.Dunham@arm.com statPageSizes.subname(6, "32M"); 223810621SCurtis.Dunham@arm.com statPageSizes.subname(7, "512M"); 223910621SCurtis.Dunham@arm.com statPageSizes.subname(8, "1G"); 224010621SCurtis.Dunham@arm.com 224110621SCurtis.Dunham@arm.com statRequestOrigin 224210621SCurtis.Dunham@arm.com .init(2,2) // Instruction/Data, requests/completed 224310621SCurtis.Dunham@arm.com .name(name() + ".walkRequestOrigin") 224410621SCurtis.Dunham@arm.com .desc("Table walker requests started/completed, data/inst") 224510621SCurtis.Dunham@arm.com .flags(Stats::total) 224610621SCurtis.Dunham@arm.com ; 224710621SCurtis.Dunham@arm.com statRequestOrigin.subname(0,"Requested"); 224810621SCurtis.Dunham@arm.com statRequestOrigin.subname(1,"Completed"); 224910621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(0,"Data"); 225010621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(1,"Inst"); 225110621SCurtis.Dunham@arm.com} 2252