table_walker.cc revision 11181
12497SN/A/* 210719SMarco.Balboni@ARM.com * Copyright (c) 2010, 2012-2015 ARM Limited 38711SN/A * All rights reserved 48711SN/A * 58711SN/A * The license below extends only to copyright in the software and shall 68711SN/A * not be construed as granting a license to any other intellectual 78711SN/A * property including but not limited to intellectual property relating 88711SN/A * to a hardware implementation of the functionality of the software 98711SN/A * licensed hereunder. You may use the software subject to the license 108711SN/A * terms below provided that you ensure that this notice is replicated 118711SN/A * unmodified and in its entirety in all distributions of the software, 128711SN/A * modified or unmodified, in source code or in binary form. 138711SN/A * 142497SN/A * Redistribution and use in source and binary forms, with or without 152497SN/A * modification, are permitted provided that the following conditions are 162497SN/A * met: redistributions of source code must retain the above copyright 172497SN/A * notice, this list of conditions and the following disclaimer; 182497SN/A * redistributions in binary form must reproduce the above copyright 192497SN/A * notice, this list of conditions and the following disclaimer in the 202497SN/A * documentation and/or other materials provided with the distribution; 212497SN/A * neither the name of the copyright holders nor the names of its 222497SN/A * contributors may be used to endorse or promote products derived from 232497SN/A * this software without specific prior written permission. 242497SN/A * 252497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362497SN/A * 372497SN/A * Authors: Ali Saidi 382497SN/A * Giacomo Gabrielli 392665SN/A */ 402665SN/A#include "arch/arm/table_walker.hh" 418715SN/A 428922SN/A#include <memory> 432497SN/A 442497SN/A#include "arch/arm/faults.hh" 452497SN/A#include "arch/arm/stage2_mmu.hh" 462982SN/A#include "arch/arm/system.hh" 4710405Sandreas.hansson@arm.com#include "arch/arm/tlb.hh" 482497SN/A#include "cpu/base.hh" 492497SN/A#include "cpu/thread_context.hh" 502846SN/A#include "debug/Checkpoint.hh" 512548SN/A#include "debug/Drain.hh" 5210405Sandreas.hansson@arm.com#include "debug/TLB.hh" 5310405Sandreas.hansson@arm.com#include "debug/TLBVerbose.hh" 5410405Sandreas.hansson@arm.com#include "dev/dma_device.hh" 559524SN/A#include "sim/system.hh" 562497SN/A 5710405Sandreas.hansson@arm.comusing namespace ArmISA; 5810719SMarco.Balboni@ARM.com 5910719SMarco.Balboni@ARM.comTableWalker::TableWalker(const Params *p) 607523SN/A : MemObject(p), 618851SN/A stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 628948SN/A isStage2(p->is_stage2), tlb(NULL), 638948SN/A currState(NULL), pending(false), 648851SN/A numSquashable(p->num_squash_per_cycle), 659095SN/A pendingReqs(0), 6610405Sandreas.hansson@arm.com pendingChangeTick(curTick()), 678922SN/A doL1DescEvent(this), doL2DescEvent(this), 689715SN/A doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this), 699715SN/A doL3LongDescEvent(this), 7010713Sandreas.hansson@arm.com doProcessEvent(this) 7110713Sandreas.hansson@arm.com{ 728851SN/A sctlr = 0; 738851SN/A 748948SN/A // Cache system-level properties 758948SN/A if (FullSystem) { 768915SN/A ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 779031SN/A assert(armSys); 789095SN/A haveSecurity = armSys->haveSecurity(); 7910405Sandreas.hansson@arm.com _haveLPAE = armSys->haveLPAE(); 809036SN/A _haveVirtualization = armSys->haveVirtualization(); 818922SN/A physAddrRange = armSys->physAddrRange(); 829715SN/A _haveLargeAsid64 = armSys->haveLargeAsid64(); 839715SN/A } else { 8410713Sandreas.hansson@arm.com haveSecurity = _haveLPAE = _haveVirtualization = false; 8510713Sandreas.hansson@arm.com _haveLargeAsid64 = false; 8610713Sandreas.hansson@arm.com physAddrRange = 32; 878915SN/A } 888915SN/A 898948SN/A} 908851SN/A 919095SN/ATableWalker::~TableWalker() 9210888Sandreas.hansson@arm.com{ 938922SN/A ; 949715SN/A} 959715SN/A 969716SN/Avoid 978851SN/ATableWalker::setMMU(Stage2MMU *m, MasterID master_id) 988851SN/A{ 997523SN/A stage2Mmu = m; 1007523SN/A port = &m->getPort(); 1017523SN/A masterId = master_id; 10210405Sandreas.hansson@arm.com} 1039715SN/A 10410405Sandreas.hansson@arm.comvoid 10510405Sandreas.hansson@arm.comTableWalker::init() 10610405Sandreas.hansson@arm.com{ 10710405Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 10810405Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 10910405Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 11010405Sandreas.hansson@arm.com} 11110405Sandreas.hansson@arm.com 1129715SN/ABaseMasterPort& 1139715SN/ATableWalker::getMasterPort(const std::string &if_name, PortID idx) 1142568SN/A{ 11510405Sandreas.hansson@arm.com if (if_name == "port") { 1162568SN/A if (!isStage2) { 1179278SN/A return *port; 11810405Sandreas.hansson@arm.com } else { 1199278SN/A fatal("Cannot access table walker port through stage-two walker\n"); 1208948SN/A } 1218948SN/A } 12210405Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 1239088SN/A} 12410405Sandreas.hansson@arm.com 12510405Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 12610405Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 12710405Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 1288711SN/A vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 1298711SN/A secureLookup(false), rwTable(false), userTable(false), xnTable(false), 1302568SN/A pxnTable(false), stage2Req(false), doingStage2(false), 1319036SN/A stage2Tran(nullptr), timing(false), functional(false), 13210405Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 13311133Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 13411133Sandreas.hansson@arm.com{ 13511133Sandreas.hansson@arm.com} 13611133Sandreas.hansson@arm.com 13711133Sandreas.hansson@arm.comvoid 1383244SN/ATableWalker::completeDrain() 1393244SN/A{ 1408948SN/A if (drainState() == DrainState::Draining && 14110405Sandreas.hansson@arm.com stateQueues[L1].empty() && stateQueues[L2].empty() && 1423244SN/A pendingQueue.empty()) { 1438975SN/A 1449032SN/A DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 1453244SN/A signalDrainDone(); 1469091SN/A } 1479091SN/A} 14811284Sandreas.hansson@arm.com 14910656Sandreas.hansson@arm.comDrainState 15011284Sandreas.hansson@arm.comTableWalker::drain() 15111284Sandreas.hansson@arm.com{ 1529091SN/A bool state_queues_not_empty = false; 1539612SN/A 1549712SN/A for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 1559612SN/A if (!stateQueues[i].empty()) { 15610405Sandreas.hansson@arm.com state_queues_not_empty = true; 1579033SN/A break; 1589715SN/A } 15910405Sandreas.hansson@arm.com } 1608949SN/A 1613244SN/A if (state_queues_not_empty || pendingQueue.size()) { 1623244SN/A DPRINTF(Drain, "TableWalker not drained\n"); 1633244SN/A return DrainState::Draining; 16410405Sandreas.hansson@arm.com } else { 1659091SN/A DPRINTF(Drain, "TableWalker free, no need to drain\n"); 1669091SN/A return DrainState::Drained; 1675197SN/A } 1689712SN/A} 1699712SN/A 1709712SN/Avoid 1719712SN/ATableWalker::drainResume() 1729712SN/A{ 17310719SMarco.Balboni@ARM.com if (params()->sys->isTimingMode() && currState) { 17410719SMarco.Balboni@ARM.com delete currState; 17510719SMarco.Balboni@ARM.com currState = NULL; 17610719SMarco.Balboni@ARM.com pendingChange(); 17710719SMarco.Balboni@ARM.com } 17810719SMarco.Balboni@ARM.com} 17910719SMarco.Balboni@ARM.com 18010719SMarco.Balboni@ARM.comFault 18110719SMarco.Balboni@ARM.comTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 18210719SMarco.Balboni@ARM.com uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 18310719SMarco.Balboni@ARM.com TLB::Translation *_trans, bool _timing, bool _functional, 1844912SN/A bool secure, TLB::ArmTranslationType tranType) 18510821Sandreas.hansson@arm.com{ 18611127Sandreas.hansson@arm.com assert(!(_functional && _timing)); 18711127Sandreas.hansson@arm.com ++statWalks; 1888979SN/A 1898979SN/A WalkerState *savedCurrState = NULL; 19010402SN/A 19110402SN/A if (!currState && !_functional) { 19210402SN/A // For atomic mode, a new WalkerState instance should be only created 19311126Sandreas.hansson@arm.com // once per TLB. For timing mode, a new instance is generated for every 19411126Sandreas.hansson@arm.com // TLB miss. 19511126Sandreas.hansson@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 19610719SMarco.Balboni@ARM.com 19710405Sandreas.hansson@arm.com currState = new WalkerState(); 19810402SN/A currState->tableWalker = this; 19910402SN/A } else if (_functional) { 20010402SN/A // If we are mixing functional mode with timing (or even 20111196Sali.jafri@arm.com // atomic), we need to to be careful and clean up after 20211199Sandreas.hansson@arm.com // ourselves to not risk getting into an inconsistent state. 20311196Sali.jafri@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 20411196Sali.jafri@arm.com savedCurrState = currState; 20511196Sali.jafri@arm.com currState = new WalkerState(); 20611196Sali.jafri@arm.com currState->tableWalker = this; 20711196Sali.jafri@arm.com } else if (_timing) { 20811196Sali.jafri@arm.com // This is a translation that was completed and then faulted again 20911196Sali.jafri@arm.com // because some underlying parameters that affect the translation 21011196Sali.jafri@arm.com // changed out from under us (e.g. asid). It will either be a 21111196Sali.jafri@arm.com // misprediction, in which case nothing will happen or we'll use 21211196Sali.jafri@arm.com // this fault to re-execute the faulting instruction which should clean 21310402SN/A // up everything. 21410402SN/A if (currState->vaddr_tainted == _req->getVaddr()) { 21510402SN/A ++statSquashedBefore; 21611127Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 21711127Sandreas.hansson@arm.com } 21811127Sandreas.hansson@arm.com } 21911127Sandreas.hansson@arm.com pendingChange(); 2208979SN/A 2218948SN/A currState->startTime = curTick(); 22210883Sali.jafri@arm.com currState->tc = _tc; 22311199Sandreas.hansson@arm.com currState->aarch64 = opModeIs64(currOpMode(_tc)); 22411199Sandreas.hansson@arm.com currState->el = currEL(_tc); 22511199Sandreas.hansson@arm.com currState->transState = _trans; 22611199Sandreas.hansson@arm.com currState->req = _req; 22711199Sandreas.hansson@arm.com currState->fault = NoFault; 22810883Sali.jafri@arm.com currState->asid = _asid; 22910883Sali.jafri@arm.com currState->vmid = _vmid; 23010883Sali.jafri@arm.com currState->isHyp = _isHyp; 23110883Sali.jafri@arm.com currState->timing = _timing; 23211190Sandreas.hansson@arm.com currState->functional = _functional; 23311190Sandreas.hansson@arm.com currState->mode = _mode; 23411190Sandreas.hansson@arm.com currState->tranType = tranType; 23511190Sandreas.hansson@arm.com currState->isSecure = secure; 23610883Sali.jafri@arm.com currState->physAddrRange = physAddrRange; 23710883Sali.jafri@arm.com 23810883Sali.jafri@arm.com /** @todo These should be cached or grabbed from cached copies in 23911284Sandreas.hansson@arm.com the TLB, all these miscreg reads are expensive */ 24011284Sandreas.hansson@arm.com currState->vaddr_tainted = currState->req->getVaddr(); 24111284Sandreas.hansson@arm.com if (currState->aarch64) 24211284Sandreas.hansson@arm.com currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 24310656Sandreas.hansson@arm.com currState->tc, currState->el); 24411284Sandreas.hansson@arm.com else 2458915SN/A currState->vaddr = currState->vaddr_tainted; 2469612SN/A 2479712SN/A if (currState->aarch64) { 2488948SN/A switch (currState->el) { 24910821Sandreas.hansson@arm.com case EL0: 25010402SN/A case EL1: 25111131Sandreas.hansson@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 25210402SN/A currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 25310402SN/A break; 25410656Sandreas.hansson@arm.com // @todo: uncomment this to enable Virtualization 25510656Sandreas.hansson@arm.com // case EL2: 25611284Sandreas.hansson@arm.com // assert(haveVirtualization); 25710656Sandreas.hansson@arm.com // currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 25810656Sandreas.hansson@arm.com // currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 25910719SMarco.Balboni@ARM.com // break; 26010719SMarco.Balboni@ARM.com case EL3: 26110656Sandreas.hansson@arm.com assert(haveSecurity); 26210656Sandreas.hansson@arm.com currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 26310656Sandreas.hansson@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 26410656Sandreas.hansson@arm.com break; 26510656Sandreas.hansson@arm.com default: 26610656Sandreas.hansson@arm.com panic("Invalid exception level"); 26710719SMarco.Balboni@ARM.com break; 2689091SN/A } 26910656Sandreas.hansson@arm.com } else { 27010656Sandreas.hansson@arm.com currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 27110656Sandreas.hansson@arm.com MISCREG_SCTLR, currState->tc, !currState->isSecure)); 27210656Sandreas.hansson@arm.com currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 27310656Sandreas.hansson@arm.com MISCREG_TTBCR, currState->tc, !currState->isSecure)); 27410656Sandreas.hansson@arm.com currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 27510656Sandreas.hansson@arm.com currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 27610656Sandreas.hansson@arm.com currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 27710656Sandreas.hansson@arm.com } 2788948SN/A sctlr = currState->sctlr; 27910656Sandreas.hansson@arm.com 28010656Sandreas.hansson@arm.com currState->isFetch = (currState->mode == TLB::Execute); 28110656Sandreas.hansson@arm.com currState->isWrite = (currState->mode == TLB::Write); 28210656Sandreas.hansson@arm.com 2838948SN/A statRequestOrigin[REQUESTED][currState->isFetch]++; 28410656Sandreas.hansson@arm.com 28510656Sandreas.hansson@arm.com // We only do a second stage of translation if we're not secure, or in 28610656Sandreas.hansson@arm.com // hyp mode, the second stage MMU is enabled, and this table walker 28710656Sandreas.hansson@arm.com // instance is the first stage. 2889549SN/A currState->doingStage2 = false; 28910656Sandreas.hansson@arm.com // @todo: for now disable this in AArch64 (HCR is not set) 29010656Sandreas.hansson@arm.com currState->stage2Req = !currState->aarch64 && currState->hcr.vm && 29110656Sandreas.hansson@arm.com !isStage2 && !currState->isSecure && !currState->isHyp; 2928948SN/A 29310405Sandreas.hansson@arm.com bool long_desc_format = currState->aarch64 || 2949715SN/A (_haveLPAE && currState->ttbcr.eae) || 2959091SN/A _isHyp || isStage2; 2968975SN/A 29710656Sandreas.hansson@arm.com if (long_desc_format) { 2989712SN/A // Helper variables used for hierarchical permissions 29910405Sandreas.hansson@arm.com currState->secureLookup = currState->isSecure; 3009712SN/A currState->rwTable = true; 30110656Sandreas.hansson@arm.com currState->userTable = true; 30210656Sandreas.hansson@arm.com currState->xnTable = false; 30310656Sandreas.hansson@arm.com currState->pxnTable = false; 3049712SN/A 3059712SN/A ++statWalksLongDescriptor; 3069091SN/A } else { 3078975SN/A ++statWalksShortDescriptor; 3088975SN/A } 3098975SN/A 31010405Sandreas.hansson@arm.com if (!currState->timing) { 3118975SN/A Fault fault = NoFault; 3128975SN/A if (currState->aarch64) 3139032SN/A fault = processWalkAArch64(); 3148975SN/A else if (long_desc_format) 31510656Sandreas.hansson@arm.com fault = processWalkLPAE(); 31610656Sandreas.hansson@arm.com else 31710656Sandreas.hansson@arm.com fault = processWalk(); 31810656Sandreas.hansson@arm.com 31910572Sandreas.hansson@arm.com // If this was a functional non-timing access restore state to 32010572Sandreas.hansson@arm.com // how we found it. 3219713SN/A if (currState->functional) { 32210405Sandreas.hansson@arm.com delete currState; 32310405Sandreas.hansson@arm.com currState = savedCurrState; 3249715SN/A } 32510405Sandreas.hansson@arm.com return fault; 3268975SN/A } 3278975SN/A 3288975SN/A if (pending || pendingQueue.size()) { 3298975SN/A pendingQueue.push_back(currState); 33010405Sandreas.hansson@arm.com currState = NULL; 3318975SN/A pendingChange(); 3328975SN/A } else { 3339712SN/A pending = true; 3349712SN/A pendingChange(); 3359712SN/A if (currState->aarch64) 3369712SN/A return processWalkAArch64(); 3379712SN/A else if (long_desc_format) 33810719SMarco.Balboni@ARM.com return processWalkLPAE(); 33910719SMarco.Balboni@ARM.com else 34010719SMarco.Balboni@ARM.com return processWalk(); 34110719SMarco.Balboni@ARM.com } 34210719SMarco.Balboni@ARM.com 34310719SMarco.Balboni@ARM.com return NoFault; 34410719SMarco.Balboni@ARM.com} 34510719SMarco.Balboni@ARM.com 3468975SN/Avoid 34710821Sandreas.hansson@arm.comTableWalker::processWalkWrapper() 34810402SN/A{ 34910402SN/A assert(!currState); 35010402SN/A assert(pendingQueue.size()); 35110402SN/A pendingChange(); 35210888Sandreas.hansson@arm.com currState = pendingQueue.front(); 35310888Sandreas.hansson@arm.com 35410888Sandreas.hansson@arm.com ExceptionLevel target_el = EL0; 35510888Sandreas.hansson@arm.com if (currState->aarch64) 35610888Sandreas.hansson@arm.com target_el = currEL(currState->tc); 3578975SN/A else 35810656Sandreas.hansson@arm.com target_el = EL1; 35910656Sandreas.hansson@arm.com 36010656Sandreas.hansson@arm.com // Check if a previous walk filled this request already 3619715SN/A // @TODO Should this always be the TLB or should we look in the stage2 TLB? 3628975SN/A TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 3639712SN/A currState->vmid, currState->isHyp, currState->isSecure, true, false, 3649712SN/A target_el); 36510405Sandreas.hansson@arm.com 3669712SN/A // Check if we still need to have a walk for this request. If the requesting 3679712SN/A // instruction has been squashed, or a previous walk has filled the TLB with 3688975SN/A // a match, we just want to get rid of the walk. The latter could happen 3698975SN/A // when there are multiple outstanding misses to a single page and a 3708975SN/A // previous request has been successfully translated. 3718975SN/A if (!currState->transState->squashed() && !te) { 37210405Sandreas.hansson@arm.com // We've got a valid request, lets process it 3738975SN/A pending = true; 37410405Sandreas.hansson@arm.com pendingQueue.pop_front(); 3759032SN/A // Keep currState in case one of the processWalk... calls NULLs it 3768975SN/A WalkerState *curr_state_copy = currState; 3778975SN/A Fault f; 3789712SN/A if (currState->aarch64) 3799712SN/A f = processWalkAArch64(); 38010405Sandreas.hansson@arm.com else if ((_haveLPAE && currState->ttbcr.eae) || currState->isHyp || isStage2) 3819712SN/A f = processWalkLPAE(); 3828975SN/A else 3838975SN/A f = processWalk(); 3848975SN/A 38511127Sandreas.hansson@arm.com if (f != NoFault) { 38611127Sandreas.hansson@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 38711127Sandreas.hansson@arm.com curr_state_copy->tc, curr_state_copy->mode); 38811127Sandreas.hansson@arm.com 38911284Sandreas.hansson@arm.com delete curr_state_copy; 39011284Sandreas.hansson@arm.com } 39111284Sandreas.hansson@arm.com return; 3929032SN/A } 39311127Sandreas.hansson@arm.com 39411127Sandreas.hansson@arm.com 39510402SN/A // If the instruction that we were translating for has been 39610402SN/A // squashed we shouldn't bother. 39710402SN/A unsigned num_squashed = 0; 39811126Sandreas.hansson@arm.com ThreadContext *tc = currState->tc; 39911126Sandreas.hansson@arm.com while ((num_squashed < numSquashable) && currState && 40011126Sandreas.hansson@arm.com (currState->transState->squashed() || te)) { 40111126Sandreas.hansson@arm.com pendingQueue.pop_front(); 40210405Sandreas.hansson@arm.com num_squashed++; 40310402SN/A statSquashedBefore++; 40410402SN/A 40510402SN/A DPRINTF(TLB, "Squashing table walk for address %#x\n", 40610402SN/A currState->vaddr_tainted); 40710402SN/A 40810402SN/A if (currState->transState->squashed()) { 40910402SN/A // finish the translation which will delete the translation object 41010402SN/A currState->transState->finish( 41110402SN/A std::make_shared<UnimpFault>("Squashed Inst"), 4128975SN/A currState->req, currState->tc, currState->mode); 41311127Sandreas.hansson@arm.com } else { 41411127Sandreas.hansson@arm.com // translate the request now that we know it will work 41511127Sandreas.hansson@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 41611127Sandreas.hansson@arm.com tlb->translateTiming(currState->req, currState->tc, 41710656Sandreas.hansson@arm.com currState->transState, currState->mode); 41811284Sandreas.hansson@arm.com 41910656Sandreas.hansson@arm.com } 42010656Sandreas.hansson@arm.com 42110656Sandreas.hansson@arm.com // delete the current request 42210656Sandreas.hansson@arm.com delete currState; 4238975SN/A 4248975SN/A // peak at the next one 4258975SN/A if (pendingQueue.size()) { 4268975SN/A currState = pendingQueue.front(); 4278975SN/A te = tlb->lookup(currState->vaddr, currState->asid, 4289032SN/A currState->vmid, currState->isHyp, currState->isSecure, true, 4298975SN/A false, target_el); 4308975SN/A } else { 4318975SN/A // Terminate the loop, nothing more to do 43210405Sandreas.hansson@arm.com currState = NULL; 4338975SN/A } 4348975SN/A } 4359032SN/A pendingChange(); 4368975SN/A 43710656Sandreas.hansson@arm.com // if we still have pending translations, schedule more work 43810656Sandreas.hansson@arm.com nextWalk(tc); 43910656Sandreas.hansson@arm.com currState = NULL; 44010656Sandreas.hansson@arm.com} 44110572Sandreas.hansson@arm.com 4429714SN/AFault 4439714SN/ATableWalker::processWalk() 4449714SN/A{ 44510656Sandreas.hansson@arm.com Addr ttbr = 0; 4469714SN/A 44710656Sandreas.hansson@arm.com // If translation isn't enabled, we shouldn't be here 44810656Sandreas.hansson@arm.com assert(currState->sctlr.m || isStage2); 4499714SN/A 45010405Sandreas.hansson@arm.com DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 45110405Sandreas.hansson@arm.com currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 45210405Sandreas.hansson@arm.com 32 - currState->ttbcr.n)); 45310405Sandreas.hansson@arm.com 4549715SN/A statWalkWaitTime.sample(curTick() - currState->startTime); 45510572Sandreas.hansson@arm.com 4569715SN/A if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 45710405Sandreas.hansson@arm.com 32 - currState->ttbcr.n)) { 4589715SN/A DPRINTF(TLB, " - Selecting TTBR0\n"); 4599715SN/A // Check if table walk is allowed when Security Extensions are enabled 4609715SN/A if (haveSecurity && currState->ttbcr.pd0) { 4619716SN/A if (currState->isFetch) 4629716SN/A return std::make_shared<PrefetchAbort>( 4639716SN/A currState->vaddr_tainted, 46410572Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 4659716SN/A isStage2, 46610405Sandreas.hansson@arm.com ArmFault::VmsaTran); 4679716SN/A else 4689716SN/A return std::make_shared<DataAbort>( 4699716SN/A currState->vaddr_tainted, 4708975SN/A TlbEntry::DomainType::NoAccess, currState->isWrite, 4718975SN/A ArmFault::TranslationLL + L1, isStage2, 47210405Sandreas.hansson@arm.com ArmFault::VmsaTran); 4738975SN/A } 4748975SN/A ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 4759712SN/A MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4769712SN/A } else { 4779712SN/A DPRINTF(TLB, " - Selecting TTBR1\n"); 4789712SN/A // Check if table walk is allowed when Security Extensions are enabled 4799712SN/A if (haveSecurity && currState->ttbcr.pd1) { 4808975SN/A if (currState->isFetch) 4818975SN/A return std::make_shared<PrefetchAbort>( 4828975SN/A currState->vaddr_tainted, 48310719SMarco.Balboni@ARM.com ArmFault::TranslationLL + L1, 48410719SMarco.Balboni@ARM.com isStage2, 48510719SMarco.Balboni@ARM.com ArmFault::VmsaTran); 48610719SMarco.Balboni@ARM.com else 48710719SMarco.Balboni@ARM.com return std::make_shared<DataAbort>( 48810719SMarco.Balboni@ARM.com currState->vaddr_tainted, 48910719SMarco.Balboni@ARM.com TlbEntry::DomainType::NoAccess, currState->isWrite, 49010719SMarco.Balboni@ARM.com ArmFault::TranslationLL + L1, isStage2, 49110719SMarco.Balboni@ARM.com ArmFault::VmsaTran); 49210719SMarco.Balboni@ARM.com } 49310719SMarco.Balboni@ARM.com ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 4948975SN/A MISCREG_TTBR1, currState->tc, !currState->isSecure)); 4959714SN/A currState->ttbcr.n = 0; 4969714SN/A } 4979714SN/A 4989714SN/A Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 4999714SN/A (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 50010402SN/A DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 50110402SN/A currState->isSecure ? "s" : "ns"); 50210402SN/A 50310402SN/A // Trickbox address check 50410402SN/A Fault f; 50510402SN/A f = tlb->walkTrickBoxCheck(l1desc_addr, currState->isSecure, 50610402SN/A currState->vaddr, sizeof(uint32_t), currState->isFetch, 5079712SN/A currState->isWrite, TlbEntry::DomainType::NoAccess, L1); 5089712SN/A if (f) { 5099712SN/A DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 51010405Sandreas.hansson@arm.com if (currState->timing) { 5118975SN/A pending = false; 5129714SN/A nextWalk(currState->tc); 5139715SN/A currState = NULL; 5143244SN/A } else { 5158975SN/A currState->tc = NULL; 51610405Sandreas.hansson@arm.com currState->req = NULL; 51710405Sandreas.hansson@arm.com } 51810405Sandreas.hansson@arm.com return f; 51910656Sandreas.hansson@arm.com } 5208948SN/A 52110656Sandreas.hansson@arm.com Request::Flags flag = Request::PT_WALK; 52210656Sandreas.hansson@arm.com if (currState->sctlr.c == 0) { 52310656Sandreas.hansson@arm.com flag.set(Request::UNCACHEABLE); 5249712SN/A } 5258948SN/A 52610402SN/A if (currState->isSecure) { 52710402SN/A flag.set(Request::SECURE); 52810402SN/A } 52910402SN/A 53010402SN/A bool delayed; 53110402SN/A delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 53210405Sandreas.hansson@arm.com sizeof(uint32_t), flag, L1, &doL1DescEvent, 53310402SN/A &TableWalker::doL1Descriptor); 53410402SN/A if (!delayed) { 53510402SN/A f = currState->fault; 5369714SN/A } 53710888Sandreas.hansson@arm.com 53810888Sandreas.hansson@arm.com return f; 53910888Sandreas.hansson@arm.com} 54010888Sandreas.hansson@arm.com 54110888Sandreas.hansson@arm.comFault 5429716SN/ATableWalker::processWalkLPAE() 5439716SN/A{ 5443244SN/A Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 5453244SN/A int tsz, n; 54610656Sandreas.hansson@arm.com LookupLevel start_lookup_level = L1; 54710656Sandreas.hansson@arm.com 54810656Sandreas.hansson@arm.com DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 5499712SN/A currState->vaddr_tainted, currState->ttbcr); 5509712SN/A 55110405Sandreas.hansson@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 5529712SN/A 5538948SN/A Request::Flags flag = Request::PT_WALK; 5548948SN/A if (currState->isSecure) 5558948SN/A flag.set(Request::SECURE); 5563210SN/A 5578948SN/A // work out which base address register to use, if in hyp mode we always 55810405Sandreas.hansson@arm.com // use HTTBR 55910888Sandreas.hansson@arm.com if (isStage2) { 5608948SN/A DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 56110405Sandreas.hansson@arm.com ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 5629663SN/A tsz = sext<4>(currState->vtcr.t0sz); 5639663SN/A start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 5649524SN/A } else if (currState->isHyp) { 5659524SN/A DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 5669524SN/A ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 56710401SN/A tsz = currState->htcr.t0sz; 56810401SN/A } else { 56910405Sandreas.hansson@arm.com assert(_haveLPAE && currState->ttbcr.eae); 5708948SN/A 5718948SN/A // Determine boundaries of TTBR0/1 regions 5728948SN/A if (currState->ttbcr.t0sz) 5738948SN/A ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 5749031SN/A else if (currState->ttbcr.t1sz) 5758948SN/A ttbr0_max = (1ULL << 32) - 5768948SN/A (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 5778975SN/A else 57810401SN/A ttbr0_max = (1ULL << 32) - 1; 5798948SN/A if (currState->ttbcr.t1sz) 5808948SN/A ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 58110401SN/A else 58210401SN/A ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 58310401SN/A 5842497SN/A // The following code snippet selects the appropriate translation table base 5852497SN/A // address (TTBR0 or TTBR1) and the appropriate starting lookup level 5869092SN/A // depending on the address range supported by the translation table (ARM 58710713Sandreas.hansson@arm.com // ARM issue C B3.6.4) 5889092SN/A if (currState->vaddr <= ttbr0_max) { 5899093SN/A DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 5909093SN/A // Check if table walk is allowed 5919093SN/A if (currState->ttbcr.epd0) { 5929715SN/A if (currState->isFetch) 5939092SN/A return std::make_shared<PrefetchAbort>( 5949092SN/A currState->vaddr_tainted, 5959036SN/A ArmFault::TranslationLL + L1, 59610405Sandreas.hansson@arm.com isStage2, 5972657SN/A ArmFault::LpaeTran); 59810405Sandreas.hansson@arm.com else 5999032SN/A return std::make_shared<DataAbort>( 6008949SN/A currState->vaddr_tainted, 6018915SN/A TlbEntry::DomainType::NoAccess, 60210405Sandreas.hansson@arm.com currState->isWrite, 60310405Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 6049712SN/A isStage2, 6058979SN/A ArmFault::LpaeTran); 6068979SN/A } 6078979SN/A ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 60810821Sandreas.hansson@arm.com MISCREG_TTBR0, currState->tc, !currState->isSecure)); 6098979SN/A tsz = currState->ttbcr.t0sz; 61010402SN/A if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 61110402SN/A start_lookup_level = L2; 61210402SN/A } else if (currState->vaddr >= ttbr1_min) { 61310402SN/A DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 61410402SN/A // Check if table walk is allowed 61510402SN/A if (currState->ttbcr.epd1) { 61610405Sandreas.hansson@arm.com if (currState->isFetch) 61710402SN/A return std::make_shared<PrefetchAbort>( 61810402SN/A currState->vaddr_tainted, 61910402SN/A ArmFault::TranslationLL + L1, 62011130Sali.jafri@arm.com isStage2, 62111130Sali.jafri@arm.com ArmFault::LpaeTran); 62211130Sali.jafri@arm.com else 62311130Sali.jafri@arm.com return std::make_shared<DataAbort>( 62411130Sali.jafri@arm.com currState->vaddr_tainted, 62511131Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 62611130Sali.jafri@arm.com currState->isWrite, 62710402SN/A ArmFault::TranslationLL + L1, 62810402SN/A isStage2, 62910402SN/A ArmFault::LpaeTran); 63010402SN/A } 63110402SN/A ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 6328979SN/A MISCREG_TTBR1, currState->tc, !currState->isSecure)); 63310402SN/A tsz = currState->ttbcr.t1sz; 6348979SN/A if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 6358915SN/A start_lookup_level = L2; 63611130Sali.jafri@arm.com } else { 63711130Sali.jafri@arm.com // Out of boundaries -> translation fault 63811130Sali.jafri@arm.com if (currState->isFetch) 63911199Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64011199Sandreas.hansson@arm.com currState->vaddr_tainted, 64111199Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 64211130Sali.jafri@arm.com isStage2, 64311130Sali.jafri@arm.com ArmFault::LpaeTran); 64411130Sali.jafri@arm.com else 64511130Sali.jafri@arm.com return std::make_shared<DataAbort>( 6468948SN/A currState->vaddr_tainted, 6478948SN/A TlbEntry::DomainType::NoAccess, 64810405Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 64910405Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 65010405Sandreas.hansson@arm.com } 65110405Sandreas.hansson@arm.com 65210405Sandreas.hansson@arm.com } 65310405Sandreas.hansson@arm.com 6548948SN/A // Perform lookup (ARM ARM issue C B3.6.6) 6558948SN/A if (start_lookup_level == L1) { 65610405Sandreas.hansson@arm.com n = 5 - tsz; 6578948SN/A desc_addr = mbits(ttbr, 39, n) | 65811130Sali.jafri@arm.com (bits(currState->vaddr, n + 26, 30) << 3); 65911130Sali.jafri@arm.com DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 66010402SN/A desc_addr, currState->isSecure ? "s" : "ns"); 66110402SN/A } else { 66210402SN/A // Skip first-level lookup 6638948SN/A n = (tsz >= 2 ? 14 - tsz : 12); 6648948SN/A desc_addr = mbits(ttbr, 39, n) | 6658948SN/A (bits(currState->vaddr, n + 17, 21) << 3); 6668948SN/A DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 6678948SN/A desc_addr, currState->isSecure ? "s" : "ns"); 6688948SN/A } 6698948SN/A 6708948SN/A // Trickbox address check 6719712SN/A Fault f = tlb->walkTrickBoxCheck(desc_addr, currState->isSecure, 67210405Sandreas.hansson@arm.com currState->vaddr, sizeof(uint64_t), currState->isFetch, 67310405Sandreas.hansson@arm.com currState->isWrite, TlbEntry::DomainType::NoAccess, 67410405Sandreas.hansson@arm.com start_lookup_level); 67510405Sandreas.hansson@arm.com if (f) { 67610405Sandreas.hansson@arm.com DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 67710405Sandreas.hansson@arm.com if (currState->timing) { 67810405Sandreas.hansson@arm.com pending = false; 67910405Sandreas.hansson@arm.com nextWalk(currState->tc); 68010405Sandreas.hansson@arm.com currState = NULL; 6819712SN/A } else { 68210694SMarco.Balboni@ARM.com currState->tc = NULL; 68310694SMarco.Balboni@ARM.com currState->req = NULL; 6848948SN/A } 6858948SN/A return f; 6868948SN/A } 6878948SN/A 68810405Sandreas.hansson@arm.com if (currState->sctlr.c == 0) { 6898948SN/A flag.set(Request::UNCACHEABLE); 69010405Sandreas.hansson@arm.com } 6919032SN/A 6928949SN/A currState->longDesc.lookupLevel = start_lookup_level; 6938948SN/A currState->longDesc.aarch64 = false; 6949712SN/A currState->longDesc.grainSize = Grain4KB; 69510405Sandreas.hansson@arm.com 6969712SN/A Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent 6978948SN/A : (Event *) &doL2LongDescEvent; 69810402SN/A 69910402SN/A bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70010402SN/A sizeof(uint64_t), flag, start_lookup_level, 70110402SN/A event, &TableWalker::doLongDescriptor); 70210402SN/A if (!delayed) { 70310405Sandreas.hansson@arm.com f = currState->fault; 70410402SN/A } 70510402SN/A 70610402SN/A return f; 70710402SN/A} 70810402SN/A 70910402SN/Aunsigned 71010402SN/ATableWalker::adjustTableSizeAArch64(unsigned tsz) 7118948SN/A{ 71210402SN/A if (tsz < 25) 7138948SN/A return 25; 7148948SN/A if (tsz > 48) 7158948SN/A return 48; 7168948SN/A return tsz; 7179712SN/A} 71810401SN/A 71910405Sandreas.hansson@arm.combool 72010401SN/ATableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 7219712SN/A{ 72210694SMarco.Balboni@ARM.com return (currPhysAddrRange != MaxPhysAddrRange && 72310694SMarco.Balboni@ARM.com bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 7248948SN/A} 7258948SN/A 7268948SN/AFault 7278948SN/ATableWalker::processWalkAArch64() 72810405Sandreas.hansson@arm.com{ 72910402SN/A assert(currState->aarch64); 73010888Sandreas.hansson@arm.com 7318948SN/A DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 7329032SN/A currState->vaddr_tainted, currState->tcr); 7339032SN/A 7348948SN/A static const GrainSize GrainMapDefault[] = 7354626SN/A { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 7364879SN/A static const GrainSize GrainMap_EL1_tg1[] = 7374879SN/A { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 7383662SN/A 7399524SN/A statWalkWaitTime.sample(curTick() - currState->startTime); 7409524SN/A 7419524SN/A // Determine TTBR, table size, granule size and phys. address range 74210401SN/A Addr ttbr = 0; 74310401SN/A int tsz = 0, ps = 0; 74410405Sandreas.hansson@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 7458915SN/A bool fault = false; 7468915SN/A switch (currState->el) { 7478915SN/A case EL0: 7488915SN/A case EL1: 74910402SN/A switch (bits(currState->vaddr, 63,48)) { 75010402SN/A case 0: 75110402SN/A DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 75210401SN/A ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 75310402SN/A tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 75410402SN/A tg = GrainMapDefault[currState->tcr.tg0]; 75510402SN/A if (bits(currState->vaddr, 63, tsz) != 0x0 || 75610402SN/A currState->tcr.epd0) 75710402SN/A fault = true; 75810402SN/A break; 75910402SN/A case 0xffff: 76010402SN/A DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 76110402SN/A ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 76210402SN/A tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 76310402SN/A tg = GrainMap_EL1_tg1[currState->tcr.tg1]; 76411284Sandreas.hansson@arm.com if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 76510402SN/A currState->tcr.epd1) 76610402SN/A fault = true; 76710402SN/A break; 76810402SN/A default: 76910402SN/A // top two bytes must be all 0s or all 1s, else invalid addr 77010402SN/A fault = true; 77110402SN/A } 77210402SN/A ps = currState->tcr.ips; 77310402SN/A break; 77410402SN/A case EL2: 77510402SN/A case EL3: 77610402SN/A switch(bits(currState->vaddr, 63,48)) { 77710402SN/A case 0: 77810402SN/A DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 77910402SN/A if (currState->el == EL2) 78010402SN/A ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 78110402SN/A else 78210402SN/A ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 78310402SN/A tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 7844626SN/A tg = GrainMapDefault[currState->tcr.tg0]; 7854626SN/A break; 78610402SN/A default: 78710402SN/A // invalid addr if top two bytes are not all 0s 7884626SN/A fault = true; 7894626SN/A } 79010401SN/A ps = currState->tcr.ips; 79110401SN/A break; 79210401SN/A } 7938948SN/A 7948948SN/A if (fault) { 7958948SN/A Fault f; 7962497SN/A if (currState->isFetch) 7972497SN/A f = std::make_shared<PrefetchAbort>( 7982497SN/A currState->vaddr_tainted, 79910405Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 8002497SN/A ArmFault::LpaeTran); 8018663SN/A else 8028663SN/A f = std::make_shared<DataAbort>( 80310405Sandreas.hansson@arm.com currState->vaddr_tainted, 8048949SN/A TlbEntry::DomainType::NoAccess, 8059032SN/A currState->isWrite, 8068663SN/A ArmFault::TranslationLL + L0, 8078663SN/A isStage2, ArmFault::LpaeTran); 8088663SN/A 80910821Sandreas.hansson@arm.com if (currState->timing) { 8108979SN/A pending = false; 8119032SN/A nextWalk(currState->tc); 8128979SN/A currState = NULL; 8134912SN/A } else { 8148948SN/A currState->tc = NULL; 8158948SN/A currState->req = NULL; 8168948SN/A } 81710888Sandreas.hansson@arm.com return f; 81810888Sandreas.hansson@arm.com 81910888Sandreas.hansson@arm.com } 82010888Sandreas.hansson@arm.com 82110888Sandreas.hansson@arm.com if (tg == ReservedGrain) { 82210888Sandreas.hansson@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 82310888Sandreas.hansson@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 82410888Sandreas.hansson@arm.com tg = Grain4KB; 82510888Sandreas.hansson@arm.com } 82610888Sandreas.hansson@arm.com 82710888Sandreas.hansson@arm.com int stride = tg - 3; 82810888Sandreas.hansson@arm.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 8299031SN/A 8308948SN/A // Determine starting lookup level 8318948SN/A // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 8328948SN/A // in ARM DDI 0487A. These table values correspond to the cascading tests 8338948SN/A // to compute the lookup level and are of the form 8348948SN/A // (grain_size + N*stride), for N = {1, 2, 3}. 8358948SN/A // A value of 64 will never succeed and a value of 0 will always succeed. 83610405Sandreas.hansson@arm.com { 8378948SN/A struct GrainMap { 8388948SN/A GrainSize grain_size; 8398948SN/A unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 84010405Sandreas.hansson@arm.com }; 8418949SN/A static const GrainMap GM[] = { 8429032SN/A { Grain4KB, { 39, 30, 0, 0 } }, 8438948SN/A { Grain16KB, { 47, 36, 25, 0 } }, 8448948SN/A { Grain64KB, { 64, 42, 29, 0 } } 8458948SN/A }; 84611188Sandreas.sandberg@arm.com 84711188Sandreas.sandberg@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 84811188Sandreas.sandberg@arm.com 84911188Sandreas.sandberg@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 85011188Sandreas.sandberg@arm.com if (tg == GM[i].grain_size) { 85111188Sandreas.sandberg@arm.com lookup = GM[i].lookup_level_cutoff; 85211188Sandreas.sandberg@arm.com break; 85311188Sandreas.sandberg@arm.com } 8548948SN/A } 8559031SN/A assert(lookup); 8568948SN/A 8578948SN/A for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 8588948SN/A if (tsz > lookup[L]) { 85910405Sandreas.hansson@arm.com start_lookup_level = (LookupLevel) L; 8608948SN/A break; 8619524SN/A } 8629524SN/A } 8639524SN/A panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 86410405Sandreas.hansson@arm.com "Table walker couldn't find lookup level\n"); 8658915SN/A } 8668915SN/A 8678915SN/A // Determine table base address 8688915SN/A int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 8699031SN/A Addr base_addr = mbits(ttbr, 47, base_addr_lo); 8708948SN/A 8718948SN/A // Determine physical address size and raise an Address Size Fault if 8728915SN/A // necessary 8738948SN/A int pa_range = decodePhysAddrRange64(ps); 8748948SN/A // Clamp to lower limit 8758948SN/A if (pa_range > physAddrRange) 8768915SN/A currState->physAddrRange = physAddrRange; 8773650SN/A else 8782497SN/A currState->physAddrRange = pa_range; 8792497SN/A if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 8809712SN/A DPRINTF(TLB, "Address size fault before any lookup\n"); 88110405Sandreas.hansson@arm.com Fault f; 8829712SN/A if (currState->isFetch) 88310405Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 88410405Sandreas.hansson@arm.com currState->vaddr_tainted, 88510405Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 88610405Sandreas.hansson@arm.com isStage2, 88710405Sandreas.hansson@arm.com ArmFault::LpaeTran); 88810405Sandreas.hansson@arm.com else 88910405Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 89010405Sandreas.hansson@arm.com currState->vaddr_tainted, 8919712SN/A TlbEntry::DomainType::NoAccess, 89210405Sandreas.hansson@arm.com currState->isWrite, 89310405Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 89410401SN/A isStage2, 89510401SN/A ArmFault::LpaeTran); 89610401SN/A 89710401SN/A 89810401SN/A if (currState->timing) { 89910401SN/A pending = false; 90010401SN/A nextWalk(currState->tc); 90110401SN/A currState = NULL; 9029712SN/A } else { 9039712SN/A currState->tc = NULL; 90410405Sandreas.hansson@arm.com currState->req = NULL; 90510405Sandreas.hansson@arm.com } 9062497SN/A return f; 90710405Sandreas.hansson@arm.com 9082497SN/A } 909 910 // Determine descriptor address 911 Addr desc_addr = base_addr | 912 (bits(currState->vaddr, tsz - 1, 913 stride * (3 - start_lookup_level) + tg) << 3); 914 915 // Trickbox address check 916 Fault f = tlb->walkTrickBoxCheck(desc_addr, currState->isSecure, 917 currState->vaddr, sizeof(uint64_t), currState->isFetch, 918 currState->isWrite, TlbEntry::DomainType::NoAccess, 919 start_lookup_level); 920 if (f) { 921 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 922 if (currState->timing) { 923 pending = false; 924 nextWalk(currState->tc); 925 currState = NULL; 926 } else { 927 currState->tc = NULL; 928 currState->req = NULL; 929 } 930 return f; 931 } 932 933 Request::Flags flag = Request::PT_WALK; 934 if (currState->sctlr.c == 0) { 935 flag.set(Request::UNCACHEABLE); 936 } 937 938 if (currState->isSecure) { 939 flag.set(Request::SECURE); 940 } 941 942 currState->longDesc.lookupLevel = start_lookup_level; 943 currState->longDesc.aarch64 = true; 944 currState->longDesc.grainSize = tg; 945 946 if (currState->timing) { 947 Event *event; 948 switch (start_lookup_level) { 949 case L0: 950 event = (Event *) &doL0LongDescEvent; 951 break; 952 case L1: 953 event = (Event *) &doL1LongDescEvent; 954 break; 955 case L2: 956 event = (Event *) &doL2LongDescEvent; 957 break; 958 case L3: 959 event = (Event *) &doL3LongDescEvent; 960 break; 961 default: 962 panic("Invalid table lookup level"); 963 break; 964 } 965 port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 966 event, (uint8_t*) &currState->longDesc.data, 967 currState->tc->getCpuPtr()->clockPeriod(), flag); 968 DPRINTF(TLBVerbose, 969 "Adding to walker fifo: queue size before adding: %d\n", 970 stateQueues[start_lookup_level].size()); 971 stateQueues[start_lookup_level].push_back(currState); 972 currState = NULL; 973 } else if (!currState->functional) { 974 port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 975 NULL, (uint8_t*) &currState->longDesc.data, 976 currState->tc->getCpuPtr()->clockPeriod(), flag); 977 doLongDescriptor(); 978 f = currState->fault; 979 } else { 980 RequestPtr req = new Request(desc_addr, sizeof(uint64_t), flag, 981 masterId); 982 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 983 pkt->dataStatic((uint8_t*) &currState->longDesc.data); 984 port->sendFunctional(pkt); 985 doLongDescriptor(); 986 delete req; 987 delete pkt; 988 f = currState->fault; 989 } 990 991 return f; 992} 993 994void 995TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 996 uint8_t texcb, bool s) 997{ 998 // Note: tc and sctlr local variables are hiding tc and sctrl class 999 // variables 1000 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 1001 te.shareable = false; // default value 1002 te.nonCacheable = false; 1003 te.outerShareable = false; 1004 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 1005 switch(texcb) { 1006 case 0: // Stongly-ordered 1007 te.nonCacheable = true; 1008 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1009 te.shareable = true; 1010 te.innerAttrs = 1; 1011 te.outerAttrs = 0; 1012 break; 1013 case 1: // Shareable Device 1014 te.nonCacheable = true; 1015 te.mtype = TlbEntry::MemoryType::Device; 1016 te.shareable = true; 1017 te.innerAttrs = 3; 1018 te.outerAttrs = 0; 1019 break; 1020 case 2: // Outer and Inner Write-Through, no Write-Allocate 1021 te.mtype = TlbEntry::MemoryType::Normal; 1022 te.shareable = s; 1023 te.innerAttrs = 6; 1024 te.outerAttrs = bits(texcb, 1, 0); 1025 break; 1026 case 3: // Outer and Inner Write-Back, no Write-Allocate 1027 te.mtype = TlbEntry::MemoryType::Normal; 1028 te.shareable = s; 1029 te.innerAttrs = 7; 1030 te.outerAttrs = bits(texcb, 1, 0); 1031 break; 1032 case 4: // Outer and Inner Non-cacheable 1033 te.nonCacheable = true; 1034 te.mtype = TlbEntry::MemoryType::Normal; 1035 te.shareable = s; 1036 te.innerAttrs = 0; 1037 te.outerAttrs = bits(texcb, 1, 0); 1038 break; 1039 case 5: // Reserved 1040 panic("Reserved texcb value!\n"); 1041 break; 1042 case 6: // Implementation Defined 1043 panic("Implementation-defined texcb value!\n"); 1044 break; 1045 case 7: // Outer and Inner Write-Back, Write-Allocate 1046 te.mtype = TlbEntry::MemoryType::Normal; 1047 te.shareable = s; 1048 te.innerAttrs = 5; 1049 te.outerAttrs = 1; 1050 break; 1051 case 8: // Non-shareable Device 1052 te.nonCacheable = true; 1053 te.mtype = TlbEntry::MemoryType::Device; 1054 te.shareable = false; 1055 te.innerAttrs = 3; 1056 te.outerAttrs = 0; 1057 break; 1058 case 9 ... 15: // Reserved 1059 panic("Reserved texcb value!\n"); 1060 break; 1061 case 16 ... 31: // Cacheable Memory 1062 te.mtype = TlbEntry::MemoryType::Normal; 1063 te.shareable = s; 1064 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 1065 te.nonCacheable = true; 1066 te.innerAttrs = bits(texcb, 1, 0); 1067 te.outerAttrs = bits(texcb, 3, 2); 1068 break; 1069 default: 1070 panic("More than 32 states for 5 bits?\n"); 1071 } 1072 } else { 1073 assert(tc); 1074 PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 1075 currState->tc, !currState->isSecure)); 1076 NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 1077 currState->tc, !currState->isSecure)); 1078 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 1079 uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 1080 switch(bits(texcb, 2,0)) { 1081 case 0: 1082 curr_tr = prrr.tr0; 1083 curr_ir = nmrr.ir0; 1084 curr_or = nmrr.or0; 1085 te.outerShareable = (prrr.nos0 == 0); 1086 break; 1087 case 1: 1088 curr_tr = prrr.tr1; 1089 curr_ir = nmrr.ir1; 1090 curr_or = nmrr.or1; 1091 te.outerShareable = (prrr.nos1 == 0); 1092 break; 1093 case 2: 1094 curr_tr = prrr.tr2; 1095 curr_ir = nmrr.ir2; 1096 curr_or = nmrr.or2; 1097 te.outerShareable = (prrr.nos2 == 0); 1098 break; 1099 case 3: 1100 curr_tr = prrr.tr3; 1101 curr_ir = nmrr.ir3; 1102 curr_or = nmrr.or3; 1103 te.outerShareable = (prrr.nos3 == 0); 1104 break; 1105 case 4: 1106 curr_tr = prrr.tr4; 1107 curr_ir = nmrr.ir4; 1108 curr_or = nmrr.or4; 1109 te.outerShareable = (prrr.nos4 == 0); 1110 break; 1111 case 5: 1112 curr_tr = prrr.tr5; 1113 curr_ir = nmrr.ir5; 1114 curr_or = nmrr.or5; 1115 te.outerShareable = (prrr.nos5 == 0); 1116 break; 1117 case 6: 1118 panic("Imp defined type\n"); 1119 case 7: 1120 curr_tr = prrr.tr7; 1121 curr_ir = nmrr.ir7; 1122 curr_or = nmrr.or7; 1123 te.outerShareable = (prrr.nos7 == 0); 1124 break; 1125 } 1126 1127 switch(curr_tr) { 1128 case 0: 1129 DPRINTF(TLBVerbose, "StronglyOrdered\n"); 1130 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1131 te.nonCacheable = true; 1132 te.innerAttrs = 1; 1133 te.outerAttrs = 0; 1134 te.shareable = true; 1135 break; 1136 case 1: 1137 DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 1138 prrr.ds1, prrr.ds0, s); 1139 te.mtype = TlbEntry::MemoryType::Device; 1140 te.nonCacheable = true; 1141 te.innerAttrs = 3; 1142 te.outerAttrs = 0; 1143 if (prrr.ds1 && s) 1144 te.shareable = true; 1145 if (prrr.ds0 && !s) 1146 te.shareable = true; 1147 break; 1148 case 2: 1149 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 1150 prrr.ns1, prrr.ns0, s); 1151 te.mtype = TlbEntry::MemoryType::Normal; 1152 if (prrr.ns1 && s) 1153 te.shareable = true; 1154 if (prrr.ns0 && !s) 1155 te.shareable = true; 1156 break; 1157 case 3: 1158 panic("Reserved type"); 1159 } 1160 1161 if (te.mtype == TlbEntry::MemoryType::Normal){ 1162 switch(curr_ir) { 1163 case 0: 1164 te.nonCacheable = true; 1165 te.innerAttrs = 0; 1166 break; 1167 case 1: 1168 te.innerAttrs = 5; 1169 break; 1170 case 2: 1171 te.innerAttrs = 6; 1172 break; 1173 case 3: 1174 te.innerAttrs = 7; 1175 break; 1176 } 1177 1178 switch(curr_or) { 1179 case 0: 1180 te.nonCacheable = true; 1181 te.outerAttrs = 0; 1182 break; 1183 case 1: 1184 te.outerAttrs = 1; 1185 break; 1186 case 2: 1187 te.outerAttrs = 2; 1188 break; 1189 case 3: 1190 te.outerAttrs = 3; 1191 break; 1192 } 1193 } 1194 } 1195 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 1196 "outerAttrs: %d\n", 1197 te.shareable, te.innerAttrs, te.outerAttrs); 1198 te.setAttributes(false); 1199} 1200 1201void 1202TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 1203 LongDescriptor &lDescriptor) 1204{ 1205 assert(_haveLPAE); 1206 1207 uint8_t attr; 1208 uint8_t sh = lDescriptor.sh(); 1209 // Different format and source of attributes if this is a stage 2 1210 // translation 1211 if (isStage2) { 1212 attr = lDescriptor.memAttr(); 1213 uint8_t attr_3_2 = (attr >> 2) & 0x3; 1214 uint8_t attr_1_0 = attr & 0x3; 1215 1216 DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 1217 1218 if (attr_3_2 == 0) { 1219 te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 1220 : TlbEntry::MemoryType::Device; 1221 te.outerAttrs = 0; 1222 te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 1223 te.nonCacheable = true; 1224 } else { 1225 te.mtype = TlbEntry::MemoryType::Normal; 1226 te.outerAttrs = attr_3_2 == 1 ? 0 : 1227 attr_3_2 == 2 ? 2 : 1; 1228 te.innerAttrs = attr_1_0 == 1 ? 0 : 1229 attr_1_0 == 2 ? 6 : 5; 1230 te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 1231 } 1232 } else { 1233 uint8_t attrIndx = lDescriptor.attrIndx(); 1234 1235 // LPAE always uses remapping of memory attributes, irrespective of the 1236 // value of SCTLR.TRE 1237 MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 1238 int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, 1239 !currState->isSecure); 1240 uint32_t mair = currState->tc->readMiscReg(reg_as_int); 1241 attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 1242 uint8_t attr_7_4 = bits(attr, 7, 4); 1243 uint8_t attr_3_0 = bits(attr, 3, 0); 1244 DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 1245 1246 // Note: the memory subsystem only cares about the 'cacheable' memory 1247 // attribute. The other attributes are only used to fill the PAR register 1248 // accordingly to provide the illusion of full support 1249 te.nonCacheable = false; 1250 1251 switch (attr_7_4) { 1252 case 0x0: 1253 // Strongly-ordered or Device memory 1254 if (attr_3_0 == 0x0) 1255 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1256 else if (attr_3_0 == 0x4) 1257 te.mtype = TlbEntry::MemoryType::Device; 1258 else 1259 panic("Unpredictable behavior\n"); 1260 te.nonCacheable = true; 1261 te.outerAttrs = 0; 1262 break; 1263 case 0x4: 1264 // Normal memory, Outer Non-cacheable 1265 te.mtype = TlbEntry::MemoryType::Normal; 1266 te.outerAttrs = 0; 1267 if (attr_3_0 == 0x4) 1268 // Inner Non-cacheable 1269 te.nonCacheable = true; 1270 else if (attr_3_0 < 0x8) 1271 panic("Unpredictable behavior\n"); 1272 break; 1273 case 0x8: 1274 case 0x9: 1275 case 0xa: 1276 case 0xb: 1277 case 0xc: 1278 case 0xd: 1279 case 0xe: 1280 case 0xf: 1281 if (attr_7_4 & 0x4) { 1282 te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 1283 } else { 1284 te.outerAttrs = 0x2; 1285 } 1286 // Normal memory, Outer Cacheable 1287 te.mtype = TlbEntry::MemoryType::Normal; 1288 if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 1289 panic("Unpredictable behavior\n"); 1290 break; 1291 default: 1292 panic("Unpredictable behavior\n"); 1293 break; 1294 } 1295 1296 switch (attr_3_0) { 1297 case 0x0: 1298 te.innerAttrs = 0x1; 1299 break; 1300 case 0x4: 1301 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 1302 break; 1303 case 0x8: 1304 case 0x9: 1305 case 0xA: 1306 case 0xB: 1307 te.innerAttrs = 6; 1308 break; 1309 case 0xC: 1310 case 0xD: 1311 case 0xE: 1312 case 0xF: 1313 te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 1314 break; 1315 default: 1316 panic("Unpredictable behavior\n"); 1317 break; 1318 } 1319 } 1320 1321 te.outerShareable = sh == 2; 1322 te.shareable = (sh & 0x2) ? true : false; 1323 te.setAttributes(true); 1324 te.attributes |= (uint64_t) attr << 56; 1325} 1326 1327void 1328TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 1329 uint8_t sh) 1330{ 1331 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 1332 1333 // Select MAIR 1334 uint64_t mair; 1335 switch (currState->el) { 1336 case EL0: 1337 case EL1: 1338 mair = tc->readMiscReg(MISCREG_MAIR_EL1); 1339 break; 1340 case EL2: 1341 mair = tc->readMiscReg(MISCREG_MAIR_EL2); 1342 break; 1343 case EL3: 1344 mair = tc->readMiscReg(MISCREG_MAIR_EL3); 1345 break; 1346 default: 1347 panic("Invalid exception level"); 1348 break; 1349 } 1350 1351 // Select attributes 1352 uint8_t attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 1353 uint8_t attr_lo = bits(attr, 3, 0); 1354 uint8_t attr_hi = bits(attr, 7, 4); 1355 1356 // Memory type 1357 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 1358 1359 // Cacheability 1360 te.nonCacheable = false; 1361 if (te.mtype == TlbEntry::MemoryType::Device || // Device memory 1362 attr_hi == 0x8 || // Normal memory, Outer Non-cacheable 1363 attr_lo == 0x8) { // Normal memory, Inner Non-cacheable 1364 te.nonCacheable = true; 1365 } 1366 1367 te.shareable = sh == 2; 1368 te.outerShareable = (sh & 0x2) ? true : false; 1369 // Attributes formatted according to the 64-bit PAR 1370 te.attributes = ((uint64_t) attr << 56) | 1371 (1 << 11) | // LPAE bit 1372 (te.ns << 9) | // NS bit 1373 (sh << 7); 1374} 1375 1376void 1377TableWalker::doL1Descriptor() 1378{ 1379 if (currState->fault != NoFault) { 1380 return; 1381 } 1382 1383 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 1384 currState->vaddr_tainted, currState->l1Desc.data); 1385 TlbEntry te; 1386 1387 switch (currState->l1Desc.type()) { 1388 case L1Descriptor::Ignore: 1389 case L1Descriptor::Reserved: 1390 if (!currState->timing) { 1391 currState->tc = NULL; 1392 currState->req = NULL; 1393 } 1394 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 1395 if (currState->isFetch) 1396 currState->fault = 1397 std::make_shared<PrefetchAbort>( 1398 currState->vaddr_tainted, 1399 ArmFault::TranslationLL + L1, 1400 isStage2, 1401 ArmFault::VmsaTran); 1402 else 1403 currState->fault = 1404 std::make_shared<DataAbort>( 1405 currState->vaddr_tainted, 1406 TlbEntry::DomainType::NoAccess, 1407 currState->isWrite, 1408 ArmFault::TranslationLL + L1, isStage2, 1409 ArmFault::VmsaTran); 1410 return; 1411 case L1Descriptor::Section: 1412 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 1413 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 1414 * enabled if set, do l1.Desc.setAp0() instead of generating 1415 * AccessFlag0 1416 */ 1417 1418 currState->fault = std::make_shared<DataAbort>( 1419 currState->vaddr_tainted, 1420 currState->l1Desc.domain(), 1421 currState->isWrite, 1422 ArmFault::AccessFlagLL + L1, 1423 isStage2, 1424 ArmFault::VmsaTran); 1425 } 1426 if (currState->l1Desc.supersection()) { 1427 panic("Haven't implemented supersections\n"); 1428 } 1429 insertTableEntry(currState->l1Desc, false); 1430 return; 1431 case L1Descriptor::PageTable: 1432 { 1433 Addr l2desc_addr; 1434 l2desc_addr = currState->l1Desc.l2Addr() | 1435 (bits(currState->vaddr, 19, 12) << 2); 1436 DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 1437 l2desc_addr, currState->isSecure ? "s" : "ns"); 1438 1439 // Trickbox address check 1440 currState->fault = tlb->walkTrickBoxCheck( 1441 l2desc_addr, currState->isSecure, currState->vaddr, 1442 sizeof(uint32_t), currState->isFetch, currState->isWrite, 1443 currState->l1Desc.domain(), L2); 1444 1445 if (currState->fault) { 1446 if (!currState->timing) { 1447 currState->tc = NULL; 1448 currState->req = NULL; 1449 } 1450 return; 1451 } 1452 1453 Request::Flags flag = Request::PT_WALK; 1454 if (currState->isSecure) 1455 flag.set(Request::SECURE); 1456 1457 bool delayed; 1458 delayed = fetchDescriptor(l2desc_addr, 1459 (uint8_t*)&currState->l2Desc.data, 1460 sizeof(uint32_t), flag, -1, &doL2DescEvent, 1461 &TableWalker::doL2Descriptor); 1462 if (delayed) { 1463 currState->delayed = true; 1464 } 1465 1466 return; 1467 } 1468 default: 1469 panic("A new type in a 2 bit field?\n"); 1470 } 1471} 1472 1473void 1474TableWalker::doLongDescriptor() 1475{ 1476 if (currState->fault != NoFault) { 1477 return; 1478 } 1479 1480 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 1481 currState->longDesc.lookupLevel, currState->vaddr_tainted, 1482 currState->longDesc.data, 1483 currState->aarch64 ? "AArch64" : "long-desc."); 1484 1485 if ((currState->longDesc.type() == LongDescriptor::Block) || 1486 (currState->longDesc.type() == LongDescriptor::Page)) { 1487 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 1488 "xn: %d, ap: %d, af: %d, type: %d\n", 1489 currState->longDesc.lookupLevel, 1490 currState->longDesc.data, 1491 currState->longDesc.pxn(), 1492 currState->longDesc.xn(), 1493 currState->longDesc.ap(), 1494 currState->longDesc.af(), 1495 currState->longDesc.type()); 1496 } else { 1497 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 1498 currState->longDesc.lookupLevel, 1499 currState->longDesc.data, 1500 currState->longDesc.type()); 1501 } 1502 1503 TlbEntry te; 1504 1505 switch (currState->longDesc.type()) { 1506 case LongDescriptor::Invalid: 1507 if (!currState->timing) { 1508 currState->tc = NULL; 1509 currState->req = NULL; 1510 } 1511 1512 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 1513 currState->longDesc.lookupLevel, 1514 ArmFault::TranslationLL + currState->longDesc.lookupLevel); 1515 if (currState->isFetch) 1516 currState->fault = std::make_shared<PrefetchAbort>( 1517 currState->vaddr_tainted, 1518 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1519 isStage2, 1520 ArmFault::LpaeTran); 1521 else 1522 currState->fault = std::make_shared<DataAbort>( 1523 currState->vaddr_tainted, 1524 TlbEntry::DomainType::NoAccess, 1525 currState->isWrite, 1526 ArmFault::TranslationLL + currState->longDesc.lookupLevel, 1527 isStage2, 1528 ArmFault::LpaeTran); 1529 return; 1530 case LongDescriptor::Block: 1531 case LongDescriptor::Page: 1532 { 1533 bool fault = false; 1534 bool aff = false; 1535 // Check for address size fault 1536 if (checkAddrSizeFaultAArch64( 1537 mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 1538 currState->longDesc.offsetBits()), 1539 currState->physAddrRange)) { 1540 fault = true; 1541 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1542 currState->longDesc.lookupLevel); 1543 // Check for access fault 1544 } else if (currState->longDesc.af() == 0) { 1545 fault = true; 1546 DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 1547 currState->longDesc.lookupLevel); 1548 aff = true; 1549 } 1550 if (fault) { 1551 if (currState->isFetch) 1552 currState->fault = std::make_shared<PrefetchAbort>( 1553 currState->vaddr_tainted, 1554 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1555 currState->longDesc.lookupLevel, 1556 isStage2, 1557 ArmFault::LpaeTran); 1558 else 1559 currState->fault = std::make_shared<DataAbort>( 1560 currState->vaddr_tainted, 1561 TlbEntry::DomainType::NoAccess, currState->isWrite, 1562 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 1563 currState->longDesc.lookupLevel, 1564 isStage2, 1565 ArmFault::LpaeTran); 1566 } else { 1567 insertTableEntry(currState->longDesc, true); 1568 } 1569 } 1570 return; 1571 case LongDescriptor::Table: 1572 { 1573 // Set hierarchical permission flags 1574 currState->secureLookup = currState->secureLookup && 1575 currState->longDesc.secureTable(); 1576 currState->rwTable = currState->rwTable && 1577 currState->longDesc.rwTable(); 1578 currState->userTable = currState->userTable && 1579 currState->longDesc.userTable(); 1580 currState->xnTable = currState->xnTable || 1581 currState->longDesc.xnTable(); 1582 currState->pxnTable = currState->pxnTable || 1583 currState->longDesc.pxnTable(); 1584 1585 // Set up next level lookup 1586 Addr next_desc_addr = currState->longDesc.nextDescAddr( 1587 currState->vaddr); 1588 1589 DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 1590 currState->longDesc.lookupLevel, 1591 currState->longDesc.lookupLevel + 1, 1592 next_desc_addr, 1593 currState->secureLookup ? "s" : "ns"); 1594 1595 // Check for address size fault 1596 if (currState->aarch64 && checkAddrSizeFaultAArch64( 1597 next_desc_addr, currState->physAddrRange)) { 1598 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 1599 currState->longDesc.lookupLevel); 1600 if (currState->isFetch) 1601 currState->fault = std::make_shared<PrefetchAbort>( 1602 currState->vaddr_tainted, 1603 ArmFault::AddressSizeLL 1604 + currState->longDesc.lookupLevel, 1605 isStage2, 1606 ArmFault::LpaeTran); 1607 else 1608 currState->fault = std::make_shared<DataAbort>( 1609 currState->vaddr_tainted, 1610 TlbEntry::DomainType::NoAccess, currState->isWrite, 1611 ArmFault::AddressSizeLL 1612 + currState->longDesc.lookupLevel, 1613 isStage2, 1614 ArmFault::LpaeTran); 1615 return; 1616 } 1617 1618 // Trickbox address check 1619 currState->fault = tlb->walkTrickBoxCheck( 1620 next_desc_addr, currState->vaddr, 1621 currState->vaddr, sizeof(uint64_t), 1622 currState->isFetch, currState->isWrite, 1623 TlbEntry::DomainType::Client, 1624 toLookupLevel(currState->longDesc.lookupLevel +1)); 1625 1626 if (currState->fault) { 1627 if (!currState->timing) { 1628 currState->tc = NULL; 1629 currState->req = NULL; 1630 } 1631 return; 1632 } 1633 1634 Request::Flags flag = Request::PT_WALK; 1635 if (currState->secureLookup) 1636 flag.set(Request::SECURE); 1637 1638 currState->longDesc.lookupLevel = 1639 (LookupLevel) (currState->longDesc.lookupLevel + 1); 1640 Event *event = NULL; 1641 switch (currState->longDesc.lookupLevel) { 1642 case L1: 1643 assert(currState->aarch64); 1644 event = &doL1LongDescEvent; 1645 break; 1646 case L2: 1647 event = &doL2LongDescEvent; 1648 break; 1649 case L3: 1650 event = &doL3LongDescEvent; 1651 break; 1652 default: 1653 panic("Wrong lookup level in table walk\n"); 1654 break; 1655 } 1656 1657 bool delayed; 1658 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 1659 sizeof(uint64_t), flag, -1, event, 1660 &TableWalker::doLongDescriptor); 1661 if (delayed) { 1662 currState->delayed = true; 1663 } 1664 } 1665 return; 1666 default: 1667 panic("A new type in a 2 bit field?\n"); 1668 } 1669} 1670 1671void 1672TableWalker::doL2Descriptor() 1673{ 1674 if (currState->fault != NoFault) { 1675 return; 1676 } 1677 1678 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 1679 currState->vaddr_tainted, currState->l2Desc.data); 1680 TlbEntry te; 1681 1682 if (currState->l2Desc.invalid()) { 1683 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 1684 if (!currState->timing) { 1685 currState->tc = NULL; 1686 currState->req = NULL; 1687 } 1688 if (currState->isFetch) 1689 currState->fault = std::make_shared<PrefetchAbort>( 1690 currState->vaddr_tainted, 1691 ArmFault::TranslationLL + L2, 1692 isStage2, 1693 ArmFault::VmsaTran); 1694 else 1695 currState->fault = std::make_shared<DataAbort>( 1696 currState->vaddr_tainted, currState->l1Desc.domain(), 1697 currState->isWrite, ArmFault::TranslationLL + L2, 1698 isStage2, 1699 ArmFault::VmsaTran); 1700 return; 1701 } 1702 1703 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 1704 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 1705 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 1706 */ 1707 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 1708 currState->sctlr.afe, currState->l2Desc.ap()); 1709 1710 currState->fault = std::make_shared<DataAbort>( 1711 currState->vaddr_tainted, 1712 TlbEntry::DomainType::NoAccess, currState->isWrite, 1713 ArmFault::AccessFlagLL + L2, isStage2, 1714 ArmFault::VmsaTran); 1715 } 1716 1717 insertTableEntry(currState->l2Desc, false); 1718} 1719 1720void 1721TableWalker::doL1DescriptorWrapper() 1722{ 1723 currState = stateQueues[L1].front(); 1724 currState->delayed = false; 1725 // if there's a stage2 translation object we don't need it any more 1726 if (currState->stage2Tran) { 1727 delete currState->stage2Tran; 1728 currState->stage2Tran = NULL; 1729 } 1730 1731 1732 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 1733 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 1734 1735 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 1736 doL1Descriptor(); 1737 1738 stateQueues[L1].pop_front(); 1739 // Check if fault was generated 1740 if (currState->fault != NoFault) { 1741 currState->transState->finish(currState->fault, currState->req, 1742 currState->tc, currState->mode); 1743 statWalksShortTerminatedAtLevel[0]++; 1744 1745 pending = false; 1746 nextWalk(currState->tc); 1747 1748 currState->req = NULL; 1749 currState->tc = NULL; 1750 currState->delayed = false; 1751 delete currState; 1752 } 1753 else if (!currState->delayed) { 1754 // delay is not set so there is no L2 to do 1755 // Don't finish the translation if a stage 2 look up is underway 1756 if (!currState->doingStage2) { 1757 statWalkServiceTime.sample(curTick() - currState->startTime); 1758 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1759 currState->fault = tlb->translateTiming(currState->req, currState->tc, 1760 currState->transState, currState->mode); 1761 statWalksShortTerminatedAtLevel[0]++; 1762 } 1763 1764 pending = false; 1765 nextWalk(currState->tc); 1766 1767 currState->req = NULL; 1768 currState->tc = NULL; 1769 currState->delayed = false; 1770 delete currState; 1771 } else { 1772 // need to do L2 descriptor 1773 stateQueues[L2].push_back(currState); 1774 } 1775 currState = NULL; 1776} 1777 1778void 1779TableWalker::doL2DescriptorWrapper() 1780{ 1781 currState = stateQueues[L2].front(); 1782 assert(currState->delayed); 1783 // if there's a stage2 translation object we don't need it any more 1784 if (currState->stage2Tran) { 1785 delete currState->stage2Tran; 1786 currState->stage2Tran = NULL; 1787 } 1788 1789 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 1790 currState->vaddr_tainted); 1791 doL2Descriptor(); 1792 1793 // Check if fault was generated 1794 if (currState->fault != NoFault) { 1795 currState->transState->finish(currState->fault, currState->req, 1796 currState->tc, currState->mode); 1797 statWalksShortTerminatedAtLevel[1]++; 1798 } 1799 else { 1800 // Don't finish the translation if a stage 2 look up is underway 1801 if (!currState->doingStage2) { 1802 statWalkServiceTime.sample(curTick() - currState->startTime); 1803 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1804 currState->fault = tlb->translateTiming(currState->req, 1805 currState->tc, currState->transState, currState->mode); 1806 statWalksShortTerminatedAtLevel[1]++; 1807 } 1808 } 1809 1810 1811 stateQueues[L2].pop_front(); 1812 pending = false; 1813 nextWalk(currState->tc); 1814 1815 currState->req = NULL; 1816 currState->tc = NULL; 1817 currState->delayed = false; 1818 1819 delete currState; 1820 currState = NULL; 1821} 1822 1823void 1824TableWalker::doL0LongDescriptorWrapper() 1825{ 1826 doLongDescriptorWrapper(L0); 1827} 1828 1829void 1830TableWalker::doL1LongDescriptorWrapper() 1831{ 1832 doLongDescriptorWrapper(L1); 1833} 1834 1835void 1836TableWalker::doL2LongDescriptorWrapper() 1837{ 1838 doLongDescriptorWrapper(L2); 1839} 1840 1841void 1842TableWalker::doL3LongDescriptorWrapper() 1843{ 1844 doLongDescriptorWrapper(L3); 1845} 1846 1847void 1848TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 1849{ 1850 currState = stateQueues[curr_lookup_level].front(); 1851 assert(curr_lookup_level == currState->longDesc.lookupLevel); 1852 currState->delayed = false; 1853 1854 // if there's a stage2 translation object we don't need it any more 1855 if (currState->stage2Tran) { 1856 delete currState->stage2Tran; 1857 currState->stage2Tran = NULL; 1858 } 1859 1860 DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 1861 currState->vaddr_tainted); 1862 doLongDescriptor(); 1863 1864 stateQueues[curr_lookup_level].pop_front(); 1865 1866 if (currState->fault != NoFault) { 1867 // A fault was generated 1868 currState->transState->finish(currState->fault, currState->req, 1869 currState->tc, currState->mode); 1870 1871 pending = false; 1872 nextWalk(currState->tc); 1873 1874 currState->req = NULL; 1875 currState->tc = NULL; 1876 currState->delayed = false; 1877 delete currState; 1878 } else if (!currState->delayed) { 1879 // No additional lookups required 1880 // Don't finish the translation if a stage 2 look up is underway 1881 if (!currState->doingStage2) { 1882 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 1883 statWalkServiceTime.sample(curTick() - currState->startTime); 1884 currState->fault = tlb->translateTiming(currState->req, currState->tc, 1885 currState->transState, 1886 currState->mode); 1887 statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 1888 } 1889 1890 pending = false; 1891 nextWalk(currState->tc); 1892 1893 currState->req = NULL; 1894 currState->tc = NULL; 1895 currState->delayed = false; 1896 delete currState; 1897 } else { 1898 if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 1899 panic("Max. number of lookups already reached in table walk\n"); 1900 // Need to perform additional lookups 1901 stateQueues[currState->longDesc.lookupLevel].push_back(currState); 1902 } 1903 currState = NULL; 1904} 1905 1906 1907void 1908TableWalker::nextWalk(ThreadContext *tc) 1909{ 1910 if (pendingQueue.size()) 1911 schedule(doProcessEvent, clockEdge(Cycles(1))); 1912 else 1913 completeDrain(); 1914} 1915 1916bool 1917TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 1918 Request::Flags flags, int queueIndex, Event *event, 1919 void (TableWalker::*doDescriptor)()) 1920{ 1921 bool isTiming = currState->timing; 1922 1923 // do the requests for the page table descriptors have to go through the 1924 // second stage MMU 1925 if (currState->stage2Req) { 1926 Fault fault; 1927 flags = flags | TLB::MustBeOne; 1928 1929 if (isTiming) { 1930 Stage2MMU::Stage2Translation *tran = new 1931 Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 1932 currState->vaddr); 1933 currState->stage2Tran = tran; 1934 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 1935 flags); 1936 fault = tran->fault; 1937 } else { 1938 fault = stage2Mmu->readDataUntimed(currState->tc, 1939 currState->vaddr, descAddr, data, numBytes, flags, 1940 currState->functional); 1941 } 1942 1943 if (fault != NoFault) { 1944 currState->fault = fault; 1945 } 1946 if (isTiming) { 1947 if (queueIndex >= 0) { 1948 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1949 stateQueues[queueIndex].size()); 1950 stateQueues[queueIndex].push_back(currState); 1951 currState = NULL; 1952 } 1953 } else { 1954 (this->*doDescriptor)(); 1955 } 1956 } else { 1957 if (isTiming) { 1958 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 1959 currState->tc->getCpuPtr()->clockPeriod(),flags); 1960 if (queueIndex >= 0) { 1961 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 1962 stateQueues[queueIndex].size()); 1963 stateQueues[queueIndex].push_back(currState); 1964 currState = NULL; 1965 } 1966 } else if (!currState->functional) { 1967 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 1968 currState->tc->getCpuPtr()->clockPeriod(), flags); 1969 (this->*doDescriptor)(); 1970 } else { 1971 RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 1972 req->taskId(ContextSwitchTaskId::DMA); 1973 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 1974 pkt->dataStatic(data); 1975 port->sendFunctional(pkt); 1976 (this->*doDescriptor)(); 1977 delete req; 1978 delete pkt; 1979 } 1980 } 1981 return (isTiming); 1982} 1983 1984void 1985TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 1986{ 1987 TlbEntry te; 1988 1989 // Create and fill a new page table entry 1990 te.valid = true; 1991 te.longDescFormat = longDescriptor; 1992 te.isHyp = currState->isHyp; 1993 te.asid = currState->asid; 1994 te.vmid = currState->vmid; 1995 te.N = descriptor.offsetBits(); 1996 te.vpn = currState->vaddr >> te.N; 1997 te.size = (1<<te.N) - 1; 1998 te.pfn = descriptor.pfn(); 1999 te.domain = descriptor.domain(); 2000 te.lookupLevel = descriptor.lookupLevel; 2001 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 2002 te.nstid = !currState->isSecure; 2003 te.xn = descriptor.xn(); 2004 if (currState->aarch64) 2005 te.el = currState->el; 2006 else 2007 te.el = 1; 2008 2009 statPageSizes[pageSizeNtoStatBin(te.N)]++; 2010 statRequestOrigin[COMPLETED][currState->isFetch]++; 2011 2012 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 2013 // as global 2014 te.global = descriptor.global(currState) || isStage2; 2015 if (longDescriptor) { 2016 LongDescriptor lDescriptor = 2017 dynamic_cast<LongDescriptor &>(descriptor); 2018 2019 te.xn |= currState->xnTable; 2020 te.pxn = currState->pxnTable || lDescriptor.pxn(); 2021 if (isStage2) { 2022 // this is actually the HAP field, but its stored in the same bit 2023 // possitions as the AP field in a stage 1 translation. 2024 te.hap = lDescriptor.ap(); 2025 } else { 2026 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 2027 (currState->userTable && (descriptor.ap() & 0x1)); 2028 } 2029 if (currState->aarch64) 2030 memAttrsAArch64(currState->tc, te, currState->longDesc.attrIndx(), 2031 currState->longDesc.sh()); 2032 else 2033 memAttrsLPAE(currState->tc, te, lDescriptor); 2034 } else { 2035 te.ap = descriptor.ap(); 2036 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 2037 descriptor.shareable()); 2038 } 2039 2040 // Debug output 2041 DPRINTF(TLB, descriptor.dbgHeader().c_str()); 2042 DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 2043 te.N, te.pfn, te.size, te.global, te.valid); 2044 DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 2045 "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 2046 te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 2047 te.nonCacheable, te.ns); 2048 DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 2049 descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 2050 descriptor.getRawData()); 2051 2052 // Insert the entry into the TLB 2053 tlb->insert(currState->vaddr, te); 2054 if (!currState->timing) { 2055 currState->tc = NULL; 2056 currState->req = NULL; 2057 } 2058} 2059 2060ArmISA::TableWalker * 2061ArmTableWalkerParams::create() 2062{ 2063 return new ArmISA::TableWalker(this); 2064} 2065 2066LookupLevel 2067TableWalker::toLookupLevel(uint8_t lookup_level_as_int) 2068{ 2069 switch (lookup_level_as_int) { 2070 case L1: 2071 return L1; 2072 case L2: 2073 return L2; 2074 case L3: 2075 return L3; 2076 default: 2077 panic("Invalid lookup level conversion"); 2078 } 2079} 2080 2081/* this method keeps track of the table walker queue's residency, so 2082 * needs to be called whenever requests start and complete. */ 2083void 2084TableWalker::pendingChange() 2085{ 2086 unsigned n = pendingQueue.size(); 2087 if ((currState != NULL) && (currState != pendingQueue.front())) { 2088 ++n; 2089 } 2090 2091 if (n != pendingReqs) { 2092 Tick now = curTick(); 2093 statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 2094 pendingReqs = n; 2095 pendingChangeTick = now; 2096 } 2097} 2098 2099uint8_t 2100TableWalker::pageSizeNtoStatBin(uint8_t N) 2101{ 2102 /* for statPageSizes */ 2103 switch(N) { 2104 case 12: return 0; // 4K 2105 case 14: return 1; // 16K (using 16K granule in v8-64) 2106 case 16: return 2; // 64K 2107 case 20: return 3; // 1M 2108 case 21: return 4; // 2M-LPAE 2109 case 24: return 5; // 16M 2110 case 25: return 6; // 32M (using 16K granule in v8-64) 2111 case 29: return 7; // 512M (using 64K granule in v8-64) 2112 case 30: return 8; // 1G-LPAE 2113 default: 2114 panic("unknown page size"); 2115 return 255; 2116 } 2117} 2118 2119void 2120TableWalker::regStats() 2121{ 2122 statWalks 2123 .name(name() + ".walks") 2124 .desc("Table walker walks requested") 2125 ; 2126 2127 statWalksShortDescriptor 2128 .name(name() + ".walksShort") 2129 .desc("Table walker walks initiated with short descriptors") 2130 .flags(Stats::nozero) 2131 ; 2132 2133 statWalksLongDescriptor 2134 .name(name() + ".walksLong") 2135 .desc("Table walker walks initiated with long descriptors") 2136 .flags(Stats::nozero) 2137 ; 2138 2139 statWalksShortTerminatedAtLevel 2140 .init(2) 2141 .name(name() + ".walksShortTerminationLevel") 2142 .desc("Level at which table walker walks " 2143 "with short descriptors terminate") 2144 .flags(Stats::nozero) 2145 ; 2146 statWalksShortTerminatedAtLevel.subname(0, "Level1"); 2147 statWalksShortTerminatedAtLevel.subname(1, "Level2"); 2148 2149 statWalksLongTerminatedAtLevel 2150 .init(4) 2151 .name(name() + ".walksLongTerminationLevel") 2152 .desc("Level at which table walker walks " 2153 "with long descriptors terminate") 2154 .flags(Stats::nozero) 2155 ; 2156 statWalksLongTerminatedAtLevel.subname(0, "Level0"); 2157 statWalksLongTerminatedAtLevel.subname(1, "Level1"); 2158 statWalksLongTerminatedAtLevel.subname(2, "Level2"); 2159 statWalksLongTerminatedAtLevel.subname(3, "Level3"); 2160 2161 statSquashedBefore 2162 .name(name() + ".walksSquashedBefore") 2163 .desc("Table walks squashed before starting") 2164 .flags(Stats::nozero) 2165 ; 2166 2167 statSquashedAfter 2168 .name(name() + ".walksSquashedAfter") 2169 .desc("Table walks squashed after completion") 2170 .flags(Stats::nozero) 2171 ; 2172 2173 statWalkWaitTime 2174 .init(16) 2175 .name(name() + ".walkWaitTime") 2176 .desc("Table walker wait (enqueue to first request) latency") 2177 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2178 ; 2179 2180 statWalkServiceTime 2181 .init(16) 2182 .name(name() + ".walkCompletionTime") 2183 .desc("Table walker service (enqueue to completion) latency") 2184 .flags(Stats::pdf | Stats::nozero | Stats::nonan) 2185 ; 2186 2187 statPendingWalks 2188 .init(16) 2189 .name(name() + ".walksPending") 2190 .desc("Table walker pending requests distribution") 2191 .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 2192 ; 2193 2194 statPageSizes // see DDI 0487A D4-1661 2195 .init(9) 2196 .name(name() + ".walkPageSizes") 2197 .desc("Table walker page sizes translated") 2198 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 2199 ; 2200 statPageSizes.subname(0, "4K"); 2201 statPageSizes.subname(1, "16K"); 2202 statPageSizes.subname(2, "64K"); 2203 statPageSizes.subname(3, "1M"); 2204 statPageSizes.subname(4, "2M"); 2205 statPageSizes.subname(5, "16M"); 2206 statPageSizes.subname(6, "32M"); 2207 statPageSizes.subname(7, "512M"); 2208 statPageSizes.subname(8, "1G"); 2209 2210 statRequestOrigin 2211 .init(2,2) // Instruction/Data, requests/completed 2212 .name(name() + ".walkRequestOrigin") 2213 .desc("Table walker requests started/completed, data/inst") 2214 .flags(Stats::total) 2215 ; 2216 statRequestOrigin.subname(0,"Requested"); 2217 statRequestOrigin.subname(1,"Completed"); 2218 statRequestOrigin.ysubname(0,"Data"); 2219 statRequestOrigin.ysubname(1,"Inst"); 2220} 2221