table_walker.cc revision 10717
17404SAli.Saidi@ARM.com/* 210717Sandreas.hansson@arm.com * Copyright (c) 2010, 2012-2015 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 407404SAli.Saidi@ARM.com 4110474Sandreas.hansson@arm.com#include <memory> 4210474Sandreas.hansson@arm.com 437404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4410037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4510037SARM gem5 Developers#include "arch/arm/system.hh" 467404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 487728SAli.Saidi@ARM.com#include "cpu/base.hh" 497404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 508245Snate@binkert.org#include "debug/Checkpoint.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528245Snate@binkert.org#include "debug/TLB.hh" 538245Snate@binkert.org#include "debug/TLBVerbose.hh" 547748SAli.Saidi@ARM.com#include "sim/system.hh" 557404SAli.Saidi@ARM.com 567404SAli.Saidi@ARM.comusing namespace ArmISA; 577404SAli.Saidi@ARM.com 587404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 5910717Sandreas.hansson@arm.com : MemObject(p), drainManager(NULL), 6010717Sandreas.hansson@arm.com stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 6110717Sandreas.hansson@arm.com isStage2(p->is_stage2), tlb(NULL), 6210717Sandreas.hansson@arm.com currState(NULL), pending(false), 639258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6410621SCurtis.Dunham@arm.com pendingReqs(0), 6510621SCurtis.Dunham@arm.com pendingChangeTick(curTick()), 6610037SARM gem5 Developers doL1DescEvent(this), doL2DescEvent(this), 6710037SARM gem5 Developers doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this), 6810037SARM gem5 Developers doL3LongDescEvent(this), 6910037SARM gem5 Developers doProcessEvent(this) 707439Sdam.sunwoo@arm.com{ 717576SAli.Saidi@ARM.com sctlr = 0; 7210037SARM gem5 Developers 7310037SARM gem5 Developers // Cache system-level properties 7410037SARM gem5 Developers if (FullSystem) { 7510717Sandreas.hansson@arm.com ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys); 7610037SARM gem5 Developers assert(armSys); 7710037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 7810037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 7910037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 8010037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 8110037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 8210037SARM gem5 Developers } else { 8310037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 8410037SARM gem5 Developers _haveLargeAsid64 = false; 8510037SARM gem5 Developers physAddrRange = 32; 8610037SARM gem5 Developers } 8710037SARM gem5 Developers 887439Sdam.sunwoo@arm.com} 897404SAli.Saidi@ARM.com 907404SAli.Saidi@ARM.comTableWalker::~TableWalker() 917404SAli.Saidi@ARM.com{ 927404SAli.Saidi@ARM.com ; 937404SAli.Saidi@ARM.com} 947404SAli.Saidi@ARM.com 9510717Sandreas.hansson@arm.comvoid 9610717Sandreas.hansson@arm.comTableWalker::setMMU(Stage2MMU *m, MasterID master_id) 9710717Sandreas.hansson@arm.com{ 9810717Sandreas.hansson@arm.com stage2Mmu = m; 9910717Sandreas.hansson@arm.com port = &m->getPort(); 10010717Sandreas.hansson@arm.com masterId = master_id; 10110717Sandreas.hansson@arm.com} 10210717Sandreas.hansson@arm.com 10310717Sandreas.hansson@arm.comvoid 10410717Sandreas.hansson@arm.comTableWalker::init() 10510717Sandreas.hansson@arm.com{ 10610717Sandreas.hansson@arm.com fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n"); 10710717Sandreas.hansson@arm.com fatal_if(!port, "Table walker must have a valid port\n"); 10810717Sandreas.hansson@arm.com fatal_if(!tlb, "Table walker must have a valid TLB\n"); 10910717Sandreas.hansson@arm.com} 11010717Sandreas.hansson@arm.com 11110717Sandreas.hansson@arm.comBaseMasterPort& 11210717Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 11310717Sandreas.hansson@arm.com{ 11410717Sandreas.hansson@arm.com if (if_name == "port") { 11510717Sandreas.hansson@arm.com if (!isStage2) { 11610717Sandreas.hansson@arm.com return *port; 11710717Sandreas.hansson@arm.com } else { 11810717Sandreas.hansson@arm.com fatal("Cannot access table walker port through stage-two walker\n"); 11910717Sandreas.hansson@arm.com } 12010717Sandreas.hansson@arm.com } 12110717Sandreas.hansson@arm.com return MemObject::getMasterPort(if_name, idx); 12210717Sandreas.hansson@arm.com} 12310717Sandreas.hansson@arm.com 12410537Sandreas.hansson@arm.comTableWalker::WalkerState::WalkerState() : 12510537Sandreas.hansson@arm.com tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr), 12610537Sandreas.hansson@arm.com asid(0), vmid(0), isHyp(false), transState(nullptr), 12710537Sandreas.hansson@arm.com vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false), 12810537Sandreas.hansson@arm.com secureLookup(false), rwTable(false), userTable(false), xnTable(false), 12910537Sandreas.hansson@arm.com pxnTable(false), stage2Req(false), doingStage2(false), 13010537Sandreas.hansson@arm.com stage2Tran(nullptr), timing(false), functional(false), 13110537Sandreas.hansson@arm.com mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc), 13210537Sandreas.hansson@arm.com delayed(false), tableWalker(nullptr) 13310037SARM gem5 Developers{ 13410037SARM gem5 Developers} 13510037SARM gem5 Developers 1369152Satgutier@umich.eduvoid 1379152Satgutier@umich.eduTableWalker::completeDrain() 1389152Satgutier@umich.edu{ 13910037SARM gem5 Developers if (drainManager && stateQueues[L1].empty() && stateQueues[L2].empty() && 1409152Satgutier@umich.edu pendingQueue.empty()) { 1419342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1429152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 1439342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 1449342SAndreas.Sandberg@arm.com drainManager = NULL; 1459152Satgutier@umich.edu } 1469152Satgutier@umich.edu} 1479152Satgutier@umich.edu 1487748SAli.Saidi@ARM.comunsigned int 1499342SAndreas.Sandberg@arm.comTableWalker::drain(DrainManager *dm) 1507404SAli.Saidi@ARM.com{ 15110037SARM gem5 Developers bool state_queues_not_empty = false; 1529152Satgutier@umich.edu 15310037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 15410037SARM gem5 Developers if (!stateQueues[i].empty()) { 15510037SARM gem5 Developers state_queues_not_empty = true; 15610037SARM gem5 Developers break; 15710037SARM gem5 Developers } 15810037SARM gem5 Developers } 15910037SARM gem5 Developers 16010037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1619342SAndreas.Sandberg@arm.com drainManager = dm; 1629342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 1639152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 1649152Satgutier@umich.edu 1659152Satgutier@umich.edu // return port drain count plus the table walker itself needs to drain 16610717Sandreas.hansson@arm.com return 1; 16710037SARM gem5 Developers } else { 16810037SARM gem5 Developers setDrainState(Drainable::Drained); 16910037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 1709152Satgutier@umich.edu 17110037SARM gem5 Developers // table walker is drained, but its ports may still need to be drained 17210717Sandreas.hansson@arm.com return 0; 1737733SAli.Saidi@ARM.com } 1747404SAli.Saidi@ARM.com} 1757404SAli.Saidi@ARM.com 1767748SAli.Saidi@ARM.comvoid 1779342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1787748SAli.Saidi@ARM.com{ 1799342SAndreas.Sandberg@arm.com Drainable::drainResume(); 1809524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1819152Satgutier@umich.edu delete currState; 1829152Satgutier@umich.edu currState = NULL; 18310621SCurtis.Dunham@arm.com pendingChange(); 1847748SAli.Saidi@ARM.com } 1857748SAli.Saidi@ARM.com} 1867748SAli.Saidi@ARM.com 1877404SAli.Saidi@ARM.comFault 18810037SARM gem5 DevelopersTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 18910037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 19010037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 19110037SARM gem5 Developers bool secure, TLB::ArmTranslationType tranType) 1927404SAli.Saidi@ARM.com{ 1938733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 19410621SCurtis.Dunham@arm.com ++statWalks; 19510621SCurtis.Dunham@arm.com 19610109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 19710037SARM gem5 Developers 19810109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 1997439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 2007439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 2017439Sdam.sunwoo@arm.com // TLB miss. 2027439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 2037404SAli.Saidi@ARM.com 2047439Sdam.sunwoo@arm.com currState = new WalkerState(); 2057439Sdam.sunwoo@arm.com currState->tableWalker = this; 20610109SGeoffrey.Blake@arm.com } else if (_functional) { 20710109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 20810109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 20910109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 21010109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 21110109SGeoffrey.Blake@arm.com savedCurrState = currState; 21210109SGeoffrey.Blake@arm.com currState = new WalkerState(); 21310109SGeoffrey.Blake@arm.com currState->tableWalker = this; 2148202SAli.Saidi@ARM.com } else if (_timing) { 2158202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 2168202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 2178202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 2188202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 2198202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 2208202SAli.Saidi@ARM.com // up everything. 22110037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 22210621SCurtis.Dunham@arm.com ++statSquashedBefore; 22310474Sandreas.hansson@arm.com return std::make_shared<ReExec>(); 2248202SAli.Saidi@ARM.com } 2257439Sdam.sunwoo@arm.com } 22610621SCurtis.Dunham@arm.com pendingChange(); 2277439Sdam.sunwoo@arm.com 22810621SCurtis.Dunham@arm.com currState->startTime = curTick(); 2297439Sdam.sunwoo@arm.com currState->tc = _tc; 23010037SARM gem5 Developers currState->aarch64 = opModeIs64(currOpMode(_tc)); 23110037SARM gem5 Developers currState->el = currEL(_tc); 2327439Sdam.sunwoo@arm.com currState->transState = _trans; 2337439Sdam.sunwoo@arm.com currState->req = _req; 2347439Sdam.sunwoo@arm.com currState->fault = NoFault; 23510037SARM gem5 Developers currState->asid = _asid; 23610037SARM gem5 Developers currState->vmid = _vmid; 23710037SARM gem5 Developers currState->isHyp = _isHyp; 2387439Sdam.sunwoo@arm.com currState->timing = _timing; 2398733Sgeoffrey.blake@arm.com currState->functional = _functional; 2407439Sdam.sunwoo@arm.com currState->mode = _mode; 24110037SARM gem5 Developers currState->tranType = tranType; 24210037SARM gem5 Developers currState->isSecure = secure; 24310037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2447404SAli.Saidi@ARM.com 2457436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2467436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 24710037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 24810037SARM gem5 Developers if (currState->aarch64) 24910037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 25010037SARM gem5 Developers currState->tc, currState->el); 25110037SARM gem5 Developers else 25210037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 25310037SARM gem5 Developers 25410037SARM gem5 Developers if (currState->aarch64) { 25510037SARM gem5 Developers switch (currState->el) { 25610037SARM gem5 Developers case EL0: 25710037SARM gem5 Developers case EL1: 25810037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 25910324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 26010037SARM gem5 Developers break; 26110037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 26210037SARM gem5 Developers // case EL2: 26310037SARM gem5 Developers // assert(haveVirtualization); 26410037SARM gem5 Developers // currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 26510324SCurtis.Dunham@arm.com // currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 26610037SARM gem5 Developers // break; 26710037SARM gem5 Developers case EL3: 26810037SARM gem5 Developers assert(haveSecurity); 26910037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 27010324SCurtis.Dunham@arm.com currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 27110037SARM gem5 Developers break; 27210037SARM gem5 Developers default: 27310037SARM gem5 Developers panic("Invalid exception level"); 27410037SARM gem5 Developers break; 27510037SARM gem5 Developers } 27610037SARM gem5 Developers } else { 27710037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 27810037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 27910037SARM gem5 Developers currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 28010037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 28110037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 28210037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 28310037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 28410037SARM gem5 Developers } 2857439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 2867439Sdam.sunwoo@arm.com 2877439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 2887439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 2897439Sdam.sunwoo@arm.com 29010621SCurtis.Dunham@arm.com statRequestOrigin[REQUESTED][currState->isFetch]++; 29110621SCurtis.Dunham@arm.com 29210037SARM gem5 Developers // We only do a second stage of translation if we're not secure, or in 29310037SARM gem5 Developers // hyp mode, the second stage MMU is enabled, and this table walker 29410037SARM gem5 Developers // instance is the first stage. 29510037SARM gem5 Developers currState->doingStage2 = false; 29610037SARM gem5 Developers // @todo: for now disable this in AArch64 (HCR is not set) 29710037SARM gem5 Developers currState->stage2Req = !currState->aarch64 && currState->hcr.vm && 29810037SARM gem5 Developers !isStage2 && !currState->isSecure && !currState->isHyp; 2997728SAli.Saidi@ARM.com 30010037SARM gem5 Developers bool long_desc_format = currState->aarch64 || 30110037SARM gem5 Developers (_haveLPAE && currState->ttbcr.eae) || 30210037SARM gem5 Developers _isHyp || isStage2; 30310037SARM gem5 Developers 30410037SARM gem5 Developers if (long_desc_format) { 30510037SARM gem5 Developers // Helper variables used for hierarchical permissions 30610037SARM gem5 Developers currState->secureLookup = currState->isSecure; 30710037SARM gem5 Developers currState->rwTable = true; 30810037SARM gem5 Developers currState->userTable = true; 30910037SARM gem5 Developers currState->xnTable = false; 31010037SARM gem5 Developers currState->pxnTable = false; 31110621SCurtis.Dunham@arm.com 31210621SCurtis.Dunham@arm.com ++statWalksLongDescriptor; 31310621SCurtis.Dunham@arm.com } else { 31410621SCurtis.Dunham@arm.com ++statWalksShortDescriptor; 31510037SARM gem5 Developers } 31610037SARM gem5 Developers 31710037SARM gem5 Developers if (!currState->timing) { 31810109SGeoffrey.Blake@arm.com Fault fault = NoFault; 31910037SARM gem5 Developers if (currState->aarch64) 32010109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 32110037SARM gem5 Developers else if (long_desc_format) 32210109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 32310037SARM gem5 Developers else 32410109SGeoffrey.Blake@arm.com fault = processWalk(); 32510109SGeoffrey.Blake@arm.com 32610109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 32710109SGeoffrey.Blake@arm.com // how we found it. 32810109SGeoffrey.Blake@arm.com if (currState->functional) { 32910109SGeoffrey.Blake@arm.com delete currState; 33010109SGeoffrey.Blake@arm.com currState = savedCurrState; 33110109SGeoffrey.Blake@arm.com } 33210109SGeoffrey.Blake@arm.com return fault; 33310037SARM gem5 Developers } 3347728SAli.Saidi@ARM.com 3358067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 3367728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 3377728SAli.Saidi@ARM.com currState = NULL; 33810621SCurtis.Dunham@arm.com pendingChange(); 3397728SAli.Saidi@ARM.com } else { 3407728SAli.Saidi@ARM.com pending = true; 34110621SCurtis.Dunham@arm.com pendingChange(); 34210037SARM gem5 Developers if (currState->aarch64) 34310037SARM gem5 Developers return processWalkAArch64(); 34410037SARM gem5 Developers else if (long_desc_format) 34510037SARM gem5 Developers return processWalkLPAE(); 34610037SARM gem5 Developers else 34710037SARM gem5 Developers return processWalk(); 3487728SAli.Saidi@ARM.com } 3497728SAli.Saidi@ARM.com 3507728SAli.Saidi@ARM.com return NoFault; 3517728SAli.Saidi@ARM.com} 3527728SAli.Saidi@ARM.com 3537728SAli.Saidi@ARM.comvoid 3547728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3557728SAli.Saidi@ARM.com{ 3567728SAli.Saidi@ARM.com assert(!currState); 3577728SAli.Saidi@ARM.com assert(pendingQueue.size()); 35810621SCurtis.Dunham@arm.com pendingChange(); 3597728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3609258SAli.Saidi@ARM.com 36110037SARM gem5 Developers ExceptionLevel target_el = EL0; 36210037SARM gem5 Developers if (currState->aarch64) 36310037SARM gem5 Developers target_el = currEL(currState->tc); 36410037SARM gem5 Developers else 36510037SARM gem5 Developers target_el = EL1; 36610037SARM gem5 Developers 3679535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 36810037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 36910037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 37010037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 37110037SARM gem5 Developers target_el); 3729258SAli.Saidi@ARM.com 3739535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3749535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3759535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3769535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3779535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3789535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3799258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3809258SAli.Saidi@ARM.com pending = true; 3819258SAli.Saidi@ARM.com pendingQueue.pop_front(); 38210579SAndrew.Bardsley@arm.com // Keep currState in case one of the processWalk... calls NULLs it 38310579SAndrew.Bardsley@arm.com WalkerState *curr_state_copy = currState; 38410579SAndrew.Bardsley@arm.com Fault f; 38510037SARM gem5 Developers if (currState->aarch64) 38610579SAndrew.Bardsley@arm.com f = processWalkAArch64(); 38710037SARM gem5 Developers else if ((_haveLPAE && currState->ttbcr.eae) || currState->isHyp || isStage2) 38810579SAndrew.Bardsley@arm.com f = processWalkLPAE(); 38910037SARM gem5 Developers else 39010579SAndrew.Bardsley@arm.com f = processWalk(); 39110579SAndrew.Bardsley@arm.com 39210579SAndrew.Bardsley@arm.com if (f != NoFault) { 39310579SAndrew.Bardsley@arm.com curr_state_copy->transState->finish(f, curr_state_copy->req, 39410579SAndrew.Bardsley@arm.com curr_state_copy->tc, curr_state_copy->mode); 39510579SAndrew.Bardsley@arm.com 39610579SAndrew.Bardsley@arm.com delete curr_state_copy; 39710579SAndrew.Bardsley@arm.com } 3989258SAli.Saidi@ARM.com return; 3999258SAli.Saidi@ARM.com } 4009258SAli.Saidi@ARM.com 4019258SAli.Saidi@ARM.com 4029258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 4039258SAli.Saidi@ARM.com // squashed we shouldn't bother. 4049258SAli.Saidi@ARM.com unsigned num_squashed = 0; 4059258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 4069258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 4079535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 4089258SAli.Saidi@ARM.com pendingQueue.pop_front(); 4099258SAli.Saidi@ARM.com num_squashed++; 41010621SCurtis.Dunham@arm.com statSquashedBefore++; 4119258SAli.Saidi@ARM.com 41210037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 41310037SARM gem5 Developers currState->vaddr_tainted); 4149258SAli.Saidi@ARM.com 4159535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 4169535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 41710474Sandreas.hansson@arm.com currState->transState->finish( 41810474Sandreas.hansson@arm.com std::make_shared<UnimpFault>("Squashed Inst"), 41910474Sandreas.hansson@arm.com currState->req, currState->tc, currState->mode); 4209535Smrinmoy.ghosh@arm.com } else { 4219535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 42210621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 42310037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 42410037SARM gem5 Developers currState->transState, currState->mode); 42510037SARM gem5 Developers 4269535Smrinmoy.ghosh@arm.com } 4279258SAli.Saidi@ARM.com 4289258SAli.Saidi@ARM.com // delete the current request 4299258SAli.Saidi@ARM.com delete currState; 4309258SAli.Saidi@ARM.com 4319258SAli.Saidi@ARM.com // peak at the next one 4329535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 4339258SAli.Saidi@ARM.com currState = pendingQueue.front(); 43410037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 43510037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 43610037SARM gem5 Developers false, target_el); 4379535Smrinmoy.ghosh@arm.com } else { 4389535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 4399258SAli.Saidi@ARM.com currState = NULL; 4409535Smrinmoy.ghosh@arm.com } 4419258SAli.Saidi@ARM.com } 44210621SCurtis.Dunham@arm.com pendingChange(); 4439258SAli.Saidi@ARM.com 44410621SCurtis.Dunham@arm.com // if we still have pending translations, schedule more work 4459258SAli.Saidi@ARM.com nextWalk(tc); 4469258SAli.Saidi@ARM.com currState = NULL; 4477728SAli.Saidi@ARM.com} 4487728SAli.Saidi@ARM.com 4497728SAli.Saidi@ARM.comFault 4507728SAli.Saidi@ARM.comTableWalker::processWalk() 4517728SAli.Saidi@ARM.com{ 4527404SAli.Saidi@ARM.com Addr ttbr = 0; 4537404SAli.Saidi@ARM.com 4547404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 45510037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 4567404SAli.Saidi@ARM.com 45710037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 45810037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 45910037SARM gem5 Developers 32 - currState->ttbcr.n)); 4607406SAli.Saidi@ARM.com 46110621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 46210621SCurtis.Dunham@arm.com 46310037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 46410037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4657406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 46610037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 46710037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 46810037SARM gem5 Developers if (currState->isFetch) 46910474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 47010474Sandreas.hansson@arm.com currState->vaddr_tainted, 47110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 47210474Sandreas.hansson@arm.com isStage2, 47310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 47410037SARM gem5 Developers else 47510474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 47610474Sandreas.hansson@arm.com currState->vaddr_tainted, 47710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 47810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 47910474Sandreas.hansson@arm.com ArmFault::VmsaTran); 48010037SARM gem5 Developers } 48110037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 48210037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4837404SAli.Saidi@ARM.com } else { 4847406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 48510037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 48610037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 48710037SARM gem5 Developers if (currState->isFetch) 48810474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 48910474Sandreas.hansson@arm.com currState->vaddr_tainted, 49010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 49110474Sandreas.hansson@arm.com isStage2, 49210474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49310037SARM gem5 Developers else 49410474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 49510474Sandreas.hansson@arm.com currState->vaddr_tainted, 49610474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 49710474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 49810474Sandreas.hansson@arm.com ArmFault::VmsaTran); 49910037SARM gem5 Developers } 50010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 50110037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 50210037SARM gem5 Developers currState->ttbcr.n = 0; 5037404SAli.Saidi@ARM.com } 5047404SAli.Saidi@ARM.com 50510037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 50610037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 50710037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 50810037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 5097404SAli.Saidi@ARM.com 5107404SAli.Saidi@ARM.com // Trickbox address check 5117439Sdam.sunwoo@arm.com Fault f; 51210037SARM gem5 Developers f = tlb->walkTrickBoxCheck(l1desc_addr, currState->isSecure, 51310037SARM gem5 Developers currState->vaddr, sizeof(uint32_t), currState->isFetch, 51410037SARM gem5 Developers currState->isWrite, TlbEntry::DomainType::NoAccess, L1); 5157439Sdam.sunwoo@arm.com if (f) { 51610037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 5177579Sminkyu.jeong@arm.com if (currState->timing) { 5187728SAli.Saidi@ARM.com pending = false; 5197728SAli.Saidi@ARM.com nextWalk(currState->tc); 5207579Sminkyu.jeong@arm.com currState = NULL; 5217579Sminkyu.jeong@arm.com } else { 5227579Sminkyu.jeong@arm.com currState->tc = NULL; 5237579Sminkyu.jeong@arm.com currState->req = NULL; 5247579Sminkyu.jeong@arm.com } 5257579Sminkyu.jeong@arm.com return f; 5267404SAli.Saidi@ARM.com } 5277404SAli.Saidi@ARM.com 5287946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 5297946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 5307946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 5317946SGiacomo.Gabrielli@arm.com } 5327946SGiacomo.Gabrielli@arm.com 53310037SARM gem5 Developers bool delayed; 53410037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 53510037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 53610037SARM gem5 Developers &TableWalker::doL1Descriptor); 53710037SARM gem5 Developers if (!delayed) { 53810037SARM gem5 Developers f = currState->fault; 53910037SARM gem5 Developers } 54010037SARM gem5 Developers 54110037SARM gem5 Developers return f; 54210037SARM gem5 Developers} 54310037SARM gem5 Developers 54410037SARM gem5 DevelopersFault 54510037SARM gem5 DevelopersTableWalker::processWalkLPAE() 54610037SARM gem5 Developers{ 54710037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 54810037SARM gem5 Developers int tsz, n; 54910037SARM gem5 Developers LookupLevel start_lookup_level = L1; 55010037SARM gem5 Developers 55110037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 55210037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 55310037SARM gem5 Developers 55410621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 55510621SCurtis.Dunham@arm.com 55610037SARM gem5 Developers Request::Flags flag = 0; 55710037SARM gem5 Developers if (currState->isSecure) 55810037SARM gem5 Developers flag.set(Request::SECURE); 55910037SARM gem5 Developers 56010037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 56110037SARM gem5 Developers // use HTTBR 56210037SARM gem5 Developers if (isStage2) { 56310037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 56410037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 56510037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 56610037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 56710037SARM gem5 Developers } else if (currState->isHyp) { 56810037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 56910037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 57010037SARM gem5 Developers tsz = currState->htcr.t0sz; 57110037SARM gem5 Developers } else { 57210037SARM gem5 Developers assert(_haveLPAE && currState->ttbcr.eae); 57310037SARM gem5 Developers 57410037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 57510037SARM gem5 Developers if (currState->ttbcr.t0sz) 57610037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 57710037SARM gem5 Developers else if (currState->ttbcr.t1sz) 57810037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 57910037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 58010037SARM gem5 Developers else 58110037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 58210037SARM gem5 Developers if (currState->ttbcr.t1sz) 58310037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 58410037SARM gem5 Developers else 58510037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 58610037SARM gem5 Developers 58710037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 58810037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 58910037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 59010037SARM gem5 Developers // ARM issue C B3.6.4) 59110037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 59210037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 59310037SARM gem5 Developers // Check if table walk is allowed 59410037SARM gem5 Developers if (currState->ttbcr.epd0) { 59510037SARM gem5 Developers if (currState->isFetch) 59610474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 59710474Sandreas.hansson@arm.com currState->vaddr_tainted, 59810474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 59910474Sandreas.hansson@arm.com isStage2, 60010474Sandreas.hansson@arm.com ArmFault::LpaeTran); 60110037SARM gem5 Developers else 60210474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 60310474Sandreas.hansson@arm.com currState->vaddr_tainted, 60410474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 60510474Sandreas.hansson@arm.com currState->isWrite, 60610474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 60710474Sandreas.hansson@arm.com isStage2, 60810474Sandreas.hansson@arm.com ArmFault::LpaeTran); 60910037SARM gem5 Developers } 61010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 61110037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 61210037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 61310037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 61410037SARM gem5 Developers start_lookup_level = L2; 61510037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 61610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 61710037SARM gem5 Developers // Check if table walk is allowed 61810037SARM gem5 Developers if (currState->ttbcr.epd1) { 61910037SARM gem5 Developers if (currState->isFetch) 62010474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 62110474Sandreas.hansson@arm.com currState->vaddr_tainted, 62210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 62310474Sandreas.hansson@arm.com isStage2, 62410474Sandreas.hansson@arm.com ArmFault::LpaeTran); 62510037SARM gem5 Developers else 62610474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 62710474Sandreas.hansson@arm.com currState->vaddr_tainted, 62810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 62910474Sandreas.hansson@arm.com currState->isWrite, 63010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 63110474Sandreas.hansson@arm.com isStage2, 63210474Sandreas.hansson@arm.com ArmFault::LpaeTran); 63310037SARM gem5 Developers } 63410037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 63510037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 63610037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 63710037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 63810037SARM gem5 Developers start_lookup_level = L2; 63910037SARM gem5 Developers } else { 64010037SARM gem5 Developers // Out of boundaries -> translation fault 64110037SARM gem5 Developers if (currState->isFetch) 64210474Sandreas.hansson@arm.com return std::make_shared<PrefetchAbort>( 64310474Sandreas.hansson@arm.com currState->vaddr_tainted, 64410474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 64510474Sandreas.hansson@arm.com isStage2, 64610474Sandreas.hansson@arm.com ArmFault::LpaeTran); 64710037SARM gem5 Developers else 64810474Sandreas.hansson@arm.com return std::make_shared<DataAbort>( 64910474Sandreas.hansson@arm.com currState->vaddr_tainted, 65010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 65110474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L1, 65210474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 65310037SARM gem5 Developers } 65410037SARM gem5 Developers 65510037SARM gem5 Developers } 65610037SARM gem5 Developers 65710037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 65810037SARM gem5 Developers if (start_lookup_level == L1) { 65910037SARM gem5 Developers n = 5 - tsz; 66010037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 66110037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 66210037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 66310037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 66410037SARM gem5 Developers } else { 66510037SARM gem5 Developers // Skip first-level lookup 66610037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 66710037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 66810037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 66910037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 67010037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 67110037SARM gem5 Developers } 67210037SARM gem5 Developers 67310037SARM gem5 Developers // Trickbox address check 67410037SARM gem5 Developers Fault f = tlb->walkTrickBoxCheck(desc_addr, currState->isSecure, 67510037SARM gem5 Developers currState->vaddr, sizeof(uint64_t), currState->isFetch, 67610037SARM gem5 Developers currState->isWrite, TlbEntry::DomainType::NoAccess, 67710037SARM gem5 Developers start_lookup_level); 67810037SARM gem5 Developers if (f) { 67910037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 68010037SARM gem5 Developers if (currState->timing) { 68110037SARM gem5 Developers pending = false; 68210037SARM gem5 Developers nextWalk(currState->tc); 68310037SARM gem5 Developers currState = NULL; 68410037SARM gem5 Developers } else { 68510037SARM gem5 Developers currState->tc = NULL; 68610037SARM gem5 Developers currState->req = NULL; 68710037SARM gem5 Developers } 68810037SARM gem5 Developers return f; 68910037SARM gem5 Developers } 69010037SARM gem5 Developers 69110037SARM gem5 Developers if (currState->sctlr.c == 0) { 69210037SARM gem5 Developers flag = Request::UNCACHEABLE; 69310037SARM gem5 Developers } 69410037SARM gem5 Developers 69510037SARM gem5 Developers if (currState->isSecure) 69610037SARM gem5 Developers flag.set(Request::SECURE); 69710037SARM gem5 Developers 69810037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 69910037SARM gem5 Developers currState->longDesc.aarch64 = false; 70010324SCurtis.Dunham@arm.com currState->longDesc.grainSize = Grain4KB; 70110037SARM gem5 Developers 70210037SARM gem5 Developers Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent 70310037SARM gem5 Developers : (Event *) &doL2LongDescEvent; 70410037SARM gem5 Developers 70510037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 70610037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 70710037SARM gem5 Developers event, &TableWalker::doLongDescriptor); 70810037SARM gem5 Developers if (!delayed) { 70910037SARM gem5 Developers f = currState->fault; 71010037SARM gem5 Developers } 71110037SARM gem5 Developers 71210037SARM gem5 Developers return f; 71310037SARM gem5 Developers} 71410037SARM gem5 Developers 71510037SARM gem5 Developersunsigned 71610037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 71710037SARM gem5 Developers{ 71810037SARM gem5 Developers if (tsz < 25) 71910037SARM gem5 Developers return 25; 72010037SARM gem5 Developers if (tsz > 48) 72110037SARM gem5 Developers return 48; 72210037SARM gem5 Developers return tsz; 72310037SARM gem5 Developers} 72410037SARM gem5 Developers 72510037SARM gem5 Developersbool 72610037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 72710037SARM gem5 Developers{ 72810037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 72910037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 73010037SARM gem5 Developers} 73110037SARM gem5 Developers 73210037SARM gem5 DevelopersFault 73310037SARM gem5 DevelopersTableWalker::processWalkAArch64() 73410037SARM gem5 Developers{ 73510037SARM gem5 Developers assert(currState->aarch64); 73610037SARM gem5 Developers 73710324SCurtis.Dunham@arm.com DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n", 73810324SCurtis.Dunham@arm.com currState->vaddr_tainted, currState->tcr); 73910324SCurtis.Dunham@arm.com 74010324SCurtis.Dunham@arm.com static const GrainSize GrainMapDefault[] = 74110324SCurtis.Dunham@arm.com { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }; 74210324SCurtis.Dunham@arm.com static const GrainSize GrainMap_EL1_tg1[] = 74310324SCurtis.Dunham@arm.com { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }; 74410037SARM gem5 Developers 74510621SCurtis.Dunham@arm.com statWalkWaitTime.sample(curTick() - currState->startTime); 74610621SCurtis.Dunham@arm.com 74710037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 74810037SARM gem5 Developers Addr ttbr = 0; 74910037SARM gem5 Developers int tsz = 0, ps = 0; 75010324SCurtis.Dunham@arm.com GrainSize tg = Grain4KB; // grain size computed from tg* field 75110037SARM gem5 Developers bool fault = false; 75210037SARM gem5 Developers switch (currState->el) { 75310037SARM gem5 Developers case EL0: 75410037SARM gem5 Developers case EL1: 75510037SARM gem5 Developers switch (bits(currState->vaddr, 63,48)) { 75610037SARM gem5 Developers case 0: 75710037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 75810037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 75910324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 76010324SCurtis.Dunham@arm.com tg = GrainMapDefault[currState->tcr.tg0]; 76110037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != 0x0 || 76210324SCurtis.Dunham@arm.com currState->tcr.epd0) 76310037SARM gem5 Developers fault = true; 76410037SARM gem5 Developers break; 76510037SARM gem5 Developers case 0xffff: 76610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 76710037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 76810324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); 76910324SCurtis.Dunham@arm.com tg = GrainMap_EL1_tg1[currState->tcr.tg1]; 77010037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 77110324SCurtis.Dunham@arm.com currState->tcr.epd1) 77210037SARM gem5 Developers fault = true; 77310037SARM gem5 Developers break; 77410037SARM gem5 Developers default: 77510037SARM gem5 Developers // top two bytes must be all 0s or all 1s, else invalid addr 77610037SARM gem5 Developers fault = true; 77710037SARM gem5 Developers } 77810324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 77910037SARM gem5 Developers break; 78010037SARM gem5 Developers case EL2: 78110037SARM gem5 Developers case EL3: 78210037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 78310037SARM gem5 Developers case 0: 78410324SCurtis.Dunham@arm.com DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 78510324SCurtis.Dunham@arm.com if (currState->el == EL2) 78610324SCurtis.Dunham@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 78710324SCurtis.Dunham@arm.com else 78810324SCurtis.Dunham@arm.com ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 78910324SCurtis.Dunham@arm.com tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 79010324SCurtis.Dunham@arm.com tg = GrainMapDefault[currState->tcr.tg0]; 79110037SARM gem5 Developers break; 79210037SARM gem5 Developers default: 79310037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 79410324SCurtis.Dunham@arm.com fault = true; 79510037SARM gem5 Developers } 79610324SCurtis.Dunham@arm.com ps = currState->tcr.ips; 79710037SARM gem5 Developers break; 79810037SARM gem5 Developers } 79910037SARM gem5 Developers 80010037SARM gem5 Developers if (fault) { 80110037SARM gem5 Developers Fault f; 80210037SARM gem5 Developers if (currState->isFetch) 80310474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 80410474Sandreas.hansson@arm.com currState->vaddr_tainted, 80510474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, isStage2, 80610474Sandreas.hansson@arm.com ArmFault::LpaeTran); 80710037SARM gem5 Developers else 80810474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 80910474Sandreas.hansson@arm.com currState->vaddr_tainted, 81010474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 81110474Sandreas.hansson@arm.com currState->isWrite, 81210474Sandreas.hansson@arm.com ArmFault::TranslationLL + L0, 81310474Sandreas.hansson@arm.com isStage2, ArmFault::LpaeTran); 81410037SARM gem5 Developers 81510037SARM gem5 Developers if (currState->timing) { 81610037SARM gem5 Developers pending = false; 81710037SARM gem5 Developers nextWalk(currState->tc); 81810037SARM gem5 Developers currState = NULL; 81910037SARM gem5 Developers } else { 82010037SARM gem5 Developers currState->tc = NULL; 82110037SARM gem5 Developers currState->req = NULL; 82210037SARM gem5 Developers } 82310037SARM gem5 Developers return f; 82410037SARM gem5 Developers 82510037SARM gem5 Developers } 82610037SARM gem5 Developers 82710324SCurtis.Dunham@arm.com if (tg == ReservedGrain) { 82810324SCurtis.Dunham@arm.com warn_once("Reserved granule size requested; gem5's IMPLEMENTATION " 82910324SCurtis.Dunham@arm.com "DEFINED behavior takes this to mean 4KB granules\n"); 83010324SCurtis.Dunham@arm.com tg = Grain4KB; 83110324SCurtis.Dunham@arm.com } 83210324SCurtis.Dunham@arm.com 83310324SCurtis.Dunham@arm.com int stride = tg - 3; 83410324SCurtis.Dunham@arm.com LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS; 83510324SCurtis.Dunham@arm.com 83610037SARM gem5 Developers // Determine starting lookup level 83710324SCurtis.Dunham@arm.com // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library 83810324SCurtis.Dunham@arm.com // in ARM DDI 0487A. These table values correspond to the cascading tests 83910324SCurtis.Dunham@arm.com // to compute the lookup level and are of the form 84010324SCurtis.Dunham@arm.com // (grain_size + N*stride), for N = {1, 2, 3}. 84110324SCurtis.Dunham@arm.com // A value of 64 will never succeed and a value of 0 will always succeed. 84210324SCurtis.Dunham@arm.com { 84310324SCurtis.Dunham@arm.com struct GrainMap { 84410324SCurtis.Dunham@arm.com GrainSize grain_size; 84510324SCurtis.Dunham@arm.com unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS]; 84610324SCurtis.Dunham@arm.com }; 84710324SCurtis.Dunham@arm.com static const GrainMap GM[] = { 84810324SCurtis.Dunham@arm.com { Grain4KB, { 39, 30, 0, 0 } }, 84910324SCurtis.Dunham@arm.com { Grain16KB, { 47, 36, 25, 0 } }, 85010324SCurtis.Dunham@arm.com { Grain64KB, { 64, 42, 29, 0 } } 85110324SCurtis.Dunham@arm.com }; 85210324SCurtis.Dunham@arm.com 85310324SCurtis.Dunham@arm.com const unsigned *lookup = NULL; // points to a lookup_level_cutoff 85410324SCurtis.Dunham@arm.com 85510324SCurtis.Dunham@arm.com for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[] 85610324SCurtis.Dunham@arm.com if (tg == GM[i].grain_size) { 85710324SCurtis.Dunham@arm.com lookup = GM[i].lookup_level_cutoff; 85810324SCurtis.Dunham@arm.com break; 85910324SCurtis.Dunham@arm.com } 86010324SCurtis.Dunham@arm.com } 86110324SCurtis.Dunham@arm.com assert(lookup); 86210324SCurtis.Dunham@arm.com 86310324SCurtis.Dunham@arm.com for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) { 86410324SCurtis.Dunham@arm.com if (tsz > lookup[L]) { 86510324SCurtis.Dunham@arm.com start_lookup_level = (LookupLevel) L; 86610324SCurtis.Dunham@arm.com break; 86710324SCurtis.Dunham@arm.com } 86810324SCurtis.Dunham@arm.com } 86910324SCurtis.Dunham@arm.com panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, 87010324SCurtis.Dunham@arm.com "Table walker couldn't find lookup level\n"); 87110037SARM gem5 Developers } 87210037SARM gem5 Developers 87310037SARM gem5 Developers // Determine table base address 87410324SCurtis.Dunham@arm.com int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg; 87510037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 87610037SARM gem5 Developers 87710037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 87810037SARM gem5 Developers // necessary 87910037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 88010037SARM gem5 Developers // Clamp to lower limit 88110037SARM gem5 Developers if (pa_range > physAddrRange) 88210037SARM gem5 Developers currState->physAddrRange = physAddrRange; 88310037SARM gem5 Developers else 88410037SARM gem5 Developers currState->physAddrRange = pa_range; 88510037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 88610037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 88710037SARM gem5 Developers Fault f; 88810037SARM gem5 Developers if (currState->isFetch) 88910474Sandreas.hansson@arm.com f = std::make_shared<PrefetchAbort>( 89010474Sandreas.hansson@arm.com currState->vaddr_tainted, 89110474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 89210474Sandreas.hansson@arm.com isStage2, 89310474Sandreas.hansson@arm.com ArmFault::LpaeTran); 89410037SARM gem5 Developers else 89510474Sandreas.hansson@arm.com f = std::make_shared<DataAbort>( 89610474Sandreas.hansson@arm.com currState->vaddr_tainted, 89710474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 89810474Sandreas.hansson@arm.com currState->isWrite, 89910474Sandreas.hansson@arm.com ArmFault::AddressSizeLL + start_lookup_level, 90010474Sandreas.hansson@arm.com isStage2, 90110474Sandreas.hansson@arm.com ArmFault::LpaeTran); 90210037SARM gem5 Developers 90310037SARM gem5 Developers 90410037SARM gem5 Developers if (currState->timing) { 90510037SARM gem5 Developers pending = false; 90610037SARM gem5 Developers nextWalk(currState->tc); 90710037SARM gem5 Developers currState = NULL; 90810037SARM gem5 Developers } else { 90910037SARM gem5 Developers currState->tc = NULL; 91010037SARM gem5 Developers currState->req = NULL; 91110037SARM gem5 Developers } 91210037SARM gem5 Developers return f; 91310037SARM gem5 Developers 91410037SARM gem5 Developers } 91510037SARM gem5 Developers 91610037SARM gem5 Developers // Determine descriptor address 91710037SARM gem5 Developers Addr desc_addr = base_addr | 91810037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 91910324SCurtis.Dunham@arm.com stride * (3 - start_lookup_level) + tg) << 3); 92010037SARM gem5 Developers 92110037SARM gem5 Developers // Trickbox address check 92210037SARM gem5 Developers Fault f = tlb->walkTrickBoxCheck(desc_addr, currState->isSecure, 92310037SARM gem5 Developers currState->vaddr, sizeof(uint64_t), currState->isFetch, 92410037SARM gem5 Developers currState->isWrite, TlbEntry::DomainType::NoAccess, 92510037SARM gem5 Developers start_lookup_level); 92610037SARM gem5 Developers if (f) { 92710037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 92810037SARM gem5 Developers if (currState->timing) { 92910037SARM gem5 Developers pending = false; 93010037SARM gem5 Developers nextWalk(currState->tc); 93110037SARM gem5 Developers currState = NULL; 93210037SARM gem5 Developers } else { 93310037SARM gem5 Developers currState->tc = NULL; 93410037SARM gem5 Developers currState->req = NULL; 93510037SARM gem5 Developers } 93610037SARM gem5 Developers return f; 93710037SARM gem5 Developers } 93810037SARM gem5 Developers 93910037SARM gem5 Developers Request::Flags flag = 0; 94010037SARM gem5 Developers if (currState->sctlr.c == 0) { 94110037SARM gem5 Developers flag = Request::UNCACHEABLE; 94210037SARM gem5 Developers } 94310037SARM gem5 Developers 94410037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 94510037SARM gem5 Developers currState->longDesc.aarch64 = true; 94610324SCurtis.Dunham@arm.com currState->longDesc.grainSize = tg; 94710037SARM gem5 Developers 9487439Sdam.sunwoo@arm.com if (currState->timing) { 94910037SARM gem5 Developers Event *event; 95010037SARM gem5 Developers switch (start_lookup_level) { 95110037SARM gem5 Developers case L0: 95210037SARM gem5 Developers event = (Event *) &doL0LongDescEvent; 95310037SARM gem5 Developers break; 95410037SARM gem5 Developers case L1: 95510037SARM gem5 Developers event = (Event *) &doL1LongDescEvent; 95610037SARM gem5 Developers break; 95710037SARM gem5 Developers case L2: 95810037SARM gem5 Developers event = (Event *) &doL2LongDescEvent; 95910037SARM gem5 Developers break; 96010037SARM gem5 Developers case L3: 96110037SARM gem5 Developers event = (Event *) &doL3LongDescEvent; 96210037SARM gem5 Developers break; 96310037SARM gem5 Developers default: 96410037SARM gem5 Developers panic("Invalid table lookup level"); 96510037SARM gem5 Developers break; 96610037SARM gem5 Developers } 96710717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 96810621SCurtis.Dunham@arm.com event, (uint8_t*) &currState->longDesc.data, 9699180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 97010037SARM gem5 Developers DPRINTF(TLBVerbose, 97110037SARM gem5 Developers "Adding to walker fifo: queue size before adding: %d\n", 97210037SARM gem5 Developers stateQueues[start_lookup_level].size()); 97310037SARM gem5 Developers stateQueues[start_lookup_level].push_back(currState); 9747439Sdam.sunwoo@arm.com currState = NULL; 9758733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 97610717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 97710037SARM gem5 Developers NULL, (uint8_t*) &currState->longDesc.data, 9789180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 97910037SARM gem5 Developers doLongDescriptor(); 9807439Sdam.sunwoo@arm.com f = currState->fault; 9818733Sgeoffrey.blake@arm.com } else { 98210037SARM gem5 Developers RequestPtr req = new Request(desc_addr, sizeof(uint64_t), flag, 98310037SARM gem5 Developers masterId); 9848949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 98510037SARM gem5 Developers pkt->dataStatic((uint8_t*) &currState->longDesc.data); 98610717Sandreas.hansson@arm.com port->sendFunctional(pkt); 98710037SARM gem5 Developers doLongDescriptor(); 9888733Sgeoffrey.blake@arm.com delete req; 9898733Sgeoffrey.blake@arm.com delete pkt; 9908733Sgeoffrey.blake@arm.com f = currState->fault; 9917404SAli.Saidi@ARM.com } 9927404SAli.Saidi@ARM.com 9937439Sdam.sunwoo@arm.com return f; 9947404SAli.Saidi@ARM.com} 9957404SAli.Saidi@ARM.com 9967404SAli.Saidi@ARM.comvoid 9977439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 9987439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 9997404SAli.Saidi@ARM.com{ 10007439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 10017439Sdam.sunwoo@arm.com // variables 10027436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 10037436Sdam.sunwoo@arm.com te.shareable = false; // default value 10047582SAli.Saidi@arm.com te.nonCacheable = false; 100510037SARM gem5 Developers te.outerShareable = false; 10067439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 10077404SAli.Saidi@ARM.com switch(texcb) { 10087436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 10097404SAli.Saidi@ARM.com te.nonCacheable = true; 101010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 10117436Sdam.sunwoo@arm.com te.shareable = true; 10127436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10137436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10147404SAli.Saidi@ARM.com break; 10157436Sdam.sunwoo@arm.com case 1: // Shareable Device 10167436Sdam.sunwoo@arm.com te.nonCacheable = true; 101710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10187436Sdam.sunwoo@arm.com te.shareable = true; 10197436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10207436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10217436Sdam.sunwoo@arm.com break; 10227436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 102310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10247436Sdam.sunwoo@arm.com te.shareable = s; 10257436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10267436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10277436Sdam.sunwoo@arm.com break; 10287436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 102910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10307436Sdam.sunwoo@arm.com te.shareable = s; 10317436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10327436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10337436Sdam.sunwoo@arm.com break; 10347436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 10357436Sdam.sunwoo@arm.com te.nonCacheable = true; 103610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10377436Sdam.sunwoo@arm.com te.shareable = s; 10387436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10397436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 10407436Sdam.sunwoo@arm.com break; 10417436Sdam.sunwoo@arm.com case 5: // Reserved 10427439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10437436Sdam.sunwoo@arm.com break; 10447436Sdam.sunwoo@arm.com case 6: // Implementation Defined 10457439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 10467436Sdam.sunwoo@arm.com break; 10477436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 104810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10497436Sdam.sunwoo@arm.com te.shareable = s; 10507436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10517436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10527436Sdam.sunwoo@arm.com break; 10537436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 10547436Sdam.sunwoo@arm.com te.nonCacheable = true; 105510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10567436Sdam.sunwoo@arm.com te.shareable = false; 10577436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10587436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10597436Sdam.sunwoo@arm.com break; 10607436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 10617439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 10627436Sdam.sunwoo@arm.com break; 10637436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 106410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10657436Sdam.sunwoo@arm.com te.shareable = s; 10667404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 10677404SAli.Saidi@ARM.com te.nonCacheable = true; 10687436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 10697436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 10707404SAli.Saidi@ARM.com break; 10717436Sdam.sunwoo@arm.com default: 10727436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 10737404SAli.Saidi@ARM.com } 10747404SAli.Saidi@ARM.com } else { 10757438SAli.Saidi@ARM.com assert(tc); 107610037SARM gem5 Developers PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 107710037SARM gem5 Developers currState->tc, !currState->isSecure)); 107810037SARM gem5 Developers NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 107910037SARM gem5 Developers currState->tc, !currState->isSecure)); 10807436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 10817582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 10827404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 10837404SAli.Saidi@ARM.com case 0: 10847436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 10857436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 10867436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 108710037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 10887404SAli.Saidi@ARM.com break; 10897404SAli.Saidi@ARM.com case 1: 10907436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 10917436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 10927436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 109310037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 10947404SAli.Saidi@ARM.com break; 10957404SAli.Saidi@ARM.com case 2: 10967436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 10977436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 10987436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 109910037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 11007404SAli.Saidi@ARM.com break; 11017404SAli.Saidi@ARM.com case 3: 11027436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 11037436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 11047436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 110510037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 11067404SAli.Saidi@ARM.com break; 11077404SAli.Saidi@ARM.com case 4: 11087436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 11097436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 11107436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 111110037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 11127404SAli.Saidi@ARM.com break; 11137404SAli.Saidi@ARM.com case 5: 11147436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 11157436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 11167436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 111710037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 11187404SAli.Saidi@ARM.com break; 11197404SAli.Saidi@ARM.com case 6: 11207404SAli.Saidi@ARM.com panic("Imp defined type\n"); 11217404SAli.Saidi@ARM.com case 7: 11227436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 11237436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 11247436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 112510037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 11267404SAli.Saidi@ARM.com break; 11277404SAli.Saidi@ARM.com } 11287436Sdam.sunwoo@arm.com 11297436Sdam.sunwoo@arm.com switch(curr_tr) { 11307436Sdam.sunwoo@arm.com case 0: 11317436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 113210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 11337436Sdam.sunwoo@arm.com te.nonCacheable = true; 11347436Sdam.sunwoo@arm.com te.innerAttrs = 1; 11357436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11367436Sdam.sunwoo@arm.com te.shareable = true; 11377436Sdam.sunwoo@arm.com break; 11387436Sdam.sunwoo@arm.com case 1: 11397436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 11407436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 114110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 11427436Sdam.sunwoo@arm.com te.nonCacheable = true; 11437436Sdam.sunwoo@arm.com te.innerAttrs = 3; 11447436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11457436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 11467436Sdam.sunwoo@arm.com te.shareable = true; 11477436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 11487436Sdam.sunwoo@arm.com te.shareable = true; 11497436Sdam.sunwoo@arm.com break; 11507436Sdam.sunwoo@arm.com case 2: 11517436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 11527436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 115310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 11547436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 11557436Sdam.sunwoo@arm.com te.shareable = true; 11567436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 11577436Sdam.sunwoo@arm.com te.shareable = true; 11587436Sdam.sunwoo@arm.com break; 11597436Sdam.sunwoo@arm.com case 3: 11607436Sdam.sunwoo@arm.com panic("Reserved type"); 11617436Sdam.sunwoo@arm.com } 11627436Sdam.sunwoo@arm.com 116310037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 11647436Sdam.sunwoo@arm.com switch(curr_ir) { 11657436Sdam.sunwoo@arm.com case 0: 11667436Sdam.sunwoo@arm.com te.nonCacheable = true; 11677436Sdam.sunwoo@arm.com te.innerAttrs = 0; 11687436Sdam.sunwoo@arm.com break; 11697436Sdam.sunwoo@arm.com case 1: 11707436Sdam.sunwoo@arm.com te.innerAttrs = 5; 11717436Sdam.sunwoo@arm.com break; 11727436Sdam.sunwoo@arm.com case 2: 11737436Sdam.sunwoo@arm.com te.innerAttrs = 6; 11747436Sdam.sunwoo@arm.com break; 11757436Sdam.sunwoo@arm.com case 3: 11767436Sdam.sunwoo@arm.com te.innerAttrs = 7; 11777436Sdam.sunwoo@arm.com break; 11787436Sdam.sunwoo@arm.com } 11797436Sdam.sunwoo@arm.com 11807436Sdam.sunwoo@arm.com switch(curr_or) { 11817436Sdam.sunwoo@arm.com case 0: 11827436Sdam.sunwoo@arm.com te.nonCacheable = true; 11837436Sdam.sunwoo@arm.com te.outerAttrs = 0; 11847436Sdam.sunwoo@arm.com break; 11857436Sdam.sunwoo@arm.com case 1: 11867436Sdam.sunwoo@arm.com te.outerAttrs = 1; 11877436Sdam.sunwoo@arm.com break; 11887436Sdam.sunwoo@arm.com case 2: 11897436Sdam.sunwoo@arm.com te.outerAttrs = 2; 11907436Sdam.sunwoo@arm.com break; 11917436Sdam.sunwoo@arm.com case 3: 11927436Sdam.sunwoo@arm.com te.outerAttrs = 3; 11937436Sdam.sunwoo@arm.com break; 11947436Sdam.sunwoo@arm.com } 11957436Sdam.sunwoo@arm.com } 11967404SAli.Saidi@ARM.com } 119710367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " 119810367SAndrew.Bardsley@arm.com "outerAttrs: %d\n", 11997439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 120010037SARM gem5 Developers te.setAttributes(false); 120110037SARM gem5 Developers} 12027436Sdam.sunwoo@arm.com 120310037SARM gem5 Developersvoid 120410037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 120510037SARM gem5 Developers LongDescriptor &lDescriptor) 120610037SARM gem5 Developers{ 120710037SARM gem5 Developers assert(_haveLPAE); 12087436Sdam.sunwoo@arm.com 120910037SARM gem5 Developers uint8_t attr; 121010037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 121110037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 121210037SARM gem5 Developers // translation 121310037SARM gem5 Developers if (isStage2) { 121410037SARM gem5 Developers attr = lDescriptor.memAttr(); 121510037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 121610037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 12177436Sdam.sunwoo@arm.com 121810037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 121910037SARM gem5 Developers 122010037SARM gem5 Developers if (attr_3_2 == 0) { 122110037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 122210037SARM gem5 Developers : TlbEntry::MemoryType::Device; 122310037SARM gem5 Developers te.outerAttrs = 0; 122410037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 122510037SARM gem5 Developers te.nonCacheable = true; 122610037SARM gem5 Developers } else { 122710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 122810037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 122910037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 123010037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 123110037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 123210037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 123310037SARM gem5 Developers } 123410037SARM gem5 Developers } else { 123510037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 123610037SARM gem5 Developers 123710037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 123810037SARM gem5 Developers // value of SCTLR.TRE 123910421Sandreas.hansson@arm.com MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 124010421Sandreas.hansson@arm.com int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, 124110421Sandreas.hansson@arm.com !currState->isSecure); 124210421Sandreas.hansson@arm.com uint32_t mair = currState->tc->readMiscReg(reg_as_int); 124310037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 124410037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 124510037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 124610037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 124710037SARM gem5 Developers 124810037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 124910037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 125010037SARM gem5 Developers // accordingly to provide the illusion of full support 125110037SARM gem5 Developers te.nonCacheable = false; 125210037SARM gem5 Developers 125310037SARM gem5 Developers switch (attr_7_4) { 125410037SARM gem5 Developers case 0x0: 125510037SARM gem5 Developers // Strongly-ordered or Device memory 125610037SARM gem5 Developers if (attr_3_0 == 0x0) 125710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 125810037SARM gem5 Developers else if (attr_3_0 == 0x4) 125910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 126010037SARM gem5 Developers else 126110037SARM gem5 Developers panic("Unpredictable behavior\n"); 126210037SARM gem5 Developers te.nonCacheable = true; 126310037SARM gem5 Developers te.outerAttrs = 0; 126410037SARM gem5 Developers break; 126510037SARM gem5 Developers case 0x4: 126610037SARM gem5 Developers // Normal memory, Outer Non-cacheable 126710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 126810037SARM gem5 Developers te.outerAttrs = 0; 126910037SARM gem5 Developers if (attr_3_0 == 0x4) 127010037SARM gem5 Developers // Inner Non-cacheable 127110037SARM gem5 Developers te.nonCacheable = true; 127210037SARM gem5 Developers else if (attr_3_0 < 0x8) 127310037SARM gem5 Developers panic("Unpredictable behavior\n"); 127410037SARM gem5 Developers break; 127510037SARM gem5 Developers case 0x8: 127610037SARM gem5 Developers case 0x9: 127710037SARM gem5 Developers case 0xa: 127810037SARM gem5 Developers case 0xb: 127910037SARM gem5 Developers case 0xc: 128010037SARM gem5 Developers case 0xd: 128110037SARM gem5 Developers case 0xe: 128210037SARM gem5 Developers case 0xf: 128310037SARM gem5 Developers if (attr_7_4 & 0x4) { 128410037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 128510037SARM gem5 Developers } else { 128610037SARM gem5 Developers te.outerAttrs = 0x2; 128710037SARM gem5 Developers } 128810037SARM gem5 Developers // Normal memory, Outer Cacheable 128910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 129010037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 129110037SARM gem5 Developers panic("Unpredictable behavior\n"); 129210037SARM gem5 Developers break; 129310037SARM gem5 Developers default: 129410037SARM gem5 Developers panic("Unpredictable behavior\n"); 129510037SARM gem5 Developers break; 129610037SARM gem5 Developers } 129710037SARM gem5 Developers 129810037SARM gem5 Developers switch (attr_3_0) { 129910037SARM gem5 Developers case 0x0: 130010037SARM gem5 Developers te.innerAttrs = 0x1; 130110037SARM gem5 Developers break; 130210037SARM gem5 Developers case 0x4: 130310037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 130410037SARM gem5 Developers break; 130510037SARM gem5 Developers case 0x8: 130610037SARM gem5 Developers case 0x9: 130710037SARM gem5 Developers case 0xA: 130810037SARM gem5 Developers case 0xB: 130910037SARM gem5 Developers te.innerAttrs = 6; 131010037SARM gem5 Developers break; 131110037SARM gem5 Developers case 0xC: 131210037SARM gem5 Developers case 0xD: 131310037SARM gem5 Developers case 0xE: 131410037SARM gem5 Developers case 0xF: 131510037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 131610037SARM gem5 Developers break; 131710037SARM gem5 Developers default: 131810037SARM gem5 Developers panic("Unpredictable behavior\n"); 131910037SARM gem5 Developers break; 132010037SARM gem5 Developers } 132110037SARM gem5 Developers } 132210037SARM gem5 Developers 132310037SARM gem5 Developers te.outerShareable = sh == 2; 132410037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 132510037SARM gem5 Developers te.setAttributes(true); 132610037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 132710037SARM gem5 Developers} 132810037SARM gem5 Developers 132910037SARM gem5 Developersvoid 133010037SARM gem5 DevelopersTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 133110037SARM gem5 Developers uint8_t sh) 133210037SARM gem5 Developers{ 133310037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 133410037SARM gem5 Developers 133510037SARM gem5 Developers // Select MAIR 133610037SARM gem5 Developers uint64_t mair; 133710037SARM gem5 Developers switch (currState->el) { 133810037SARM gem5 Developers case EL0: 133910037SARM gem5 Developers case EL1: 134010037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL1); 134110037SARM gem5 Developers break; 134210037SARM gem5 Developers case EL2: 134310037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL2); 134410037SARM gem5 Developers break; 134510037SARM gem5 Developers case EL3: 134610037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL3); 134710037SARM gem5 Developers break; 134810037SARM gem5 Developers default: 134910037SARM gem5 Developers panic("Invalid exception level"); 135010037SARM gem5 Developers break; 135110037SARM gem5 Developers } 135210037SARM gem5 Developers 135310037SARM gem5 Developers // Select attributes 135410037SARM gem5 Developers uint8_t attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 135510037SARM gem5 Developers uint8_t attr_lo = bits(attr, 3, 0); 135610037SARM gem5 Developers uint8_t attr_hi = bits(attr, 7, 4); 135710037SARM gem5 Developers 135810037SARM gem5 Developers // Memory type 135910037SARM gem5 Developers te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 136010037SARM gem5 Developers 136110037SARM gem5 Developers // Cacheability 136210037SARM gem5 Developers te.nonCacheable = false; 136310037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Device || // Device memory 136410037SARM gem5 Developers attr_hi == 0x8 || // Normal memory, Outer Non-cacheable 136510037SARM gem5 Developers attr_lo == 0x8) { // Normal memory, Inner Non-cacheable 136610037SARM gem5 Developers te.nonCacheable = true; 136710037SARM gem5 Developers } 136810037SARM gem5 Developers 136910037SARM gem5 Developers te.shareable = sh == 2; 137010037SARM gem5 Developers te.outerShareable = (sh & 0x2) ? true : false; 137110037SARM gem5 Developers // Attributes formatted according to the 64-bit PAR 137210037SARM gem5 Developers te.attributes = ((uint64_t) attr << 56) | 137310037SARM gem5 Developers (1 << 11) | // LPAE bit 137410037SARM gem5 Developers (te.ns << 9) | // NS bit 137510037SARM gem5 Developers (sh << 7); 13767404SAli.Saidi@ARM.com} 13777404SAli.Saidi@ARM.com 13787404SAli.Saidi@ARM.comvoid 13797404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 13807404SAli.Saidi@ARM.com{ 138110037SARM gem5 Developers if (currState->fault != NoFault) { 138210037SARM gem5 Developers return; 138310037SARM gem5 Developers } 138410037SARM gem5 Developers 13857439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 138610037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 13877404SAli.Saidi@ARM.com TlbEntry te; 13887404SAli.Saidi@ARM.com 13897439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 13907404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 13917404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 13927946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 13937439Sdam.sunwoo@arm.com currState->tc = NULL; 13947439Sdam.sunwoo@arm.com currState->req = NULL; 13957437Sdam.sunwoo@arm.com } 13967406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 13977439Sdam.sunwoo@arm.com if (currState->isFetch) 13987439Sdam.sunwoo@arm.com currState->fault = 139910474Sandreas.hansson@arm.com std::make_shared<PrefetchAbort>( 140010474Sandreas.hansson@arm.com currState->vaddr_tainted, 140110474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, 140210474Sandreas.hansson@arm.com isStage2, 140310474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14047406SAli.Saidi@ARM.com else 14057439Sdam.sunwoo@arm.com currState->fault = 140610474Sandreas.hansson@arm.com std::make_shared<DataAbort>( 140710474Sandreas.hansson@arm.com currState->vaddr_tainted, 140810474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, 140910474Sandreas.hansson@arm.com currState->isWrite, 141010474Sandreas.hansson@arm.com ArmFault::TranslationLL + L1, isStage2, 141110474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14127404SAli.Saidi@ARM.com return; 14137404SAli.Saidi@ARM.com case L1Descriptor::Section: 14147439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 14157436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 14167436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 14177436Sdam.sunwoo@arm.com * AccessFlag0 14187436Sdam.sunwoo@arm.com */ 14197436Sdam.sunwoo@arm.com 142010474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 142110474Sandreas.hansson@arm.com currState->vaddr_tainted, 142210474Sandreas.hansson@arm.com currState->l1Desc.domain(), 142310474Sandreas.hansson@arm.com currState->isWrite, 142410474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L1, 142510474Sandreas.hansson@arm.com isStage2, 142610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 14277436Sdam.sunwoo@arm.com } 14287439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 14297404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 14307404SAli.Saidi@ARM.com } 143110037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 143210037SARM gem5 Developers return; 143310037SARM gem5 Developers case L1Descriptor::PageTable: 143410037SARM gem5 Developers { 143510037SARM gem5 Developers Addr l2desc_addr; 143610037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 143710037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 143810037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 143910037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 14407404SAli.Saidi@ARM.com 144110037SARM gem5 Developers // Trickbox address check 144210037SARM gem5 Developers currState->fault = tlb->walkTrickBoxCheck( 144310037SARM gem5 Developers l2desc_addr, currState->isSecure, currState->vaddr, 144410037SARM gem5 Developers sizeof(uint32_t), currState->isFetch, currState->isWrite, 144510037SARM gem5 Developers currState->l1Desc.domain(), L2); 14467404SAli.Saidi@ARM.com 144710037SARM gem5 Developers if (currState->fault) { 144810037SARM gem5 Developers if (!currState->timing) { 144910037SARM gem5 Developers currState->tc = NULL; 145010037SARM gem5 Developers currState->req = NULL; 145110037SARM gem5 Developers } 145210037SARM gem5 Developers return; 145310037SARM gem5 Developers } 145410037SARM gem5 Developers 145510037SARM gem5 Developers Request::Flags flag = 0; 145610037SARM gem5 Developers if (currState->isSecure) 145710037SARM gem5 Developers flag.set(Request::SECURE); 145810037SARM gem5 Developers 145910037SARM gem5 Developers bool delayed; 146010037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 146110037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 146210037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 146310037SARM gem5 Developers &TableWalker::doL2Descriptor); 146410037SARM gem5 Developers if (delayed) { 146510037SARM gem5 Developers currState->delayed = true; 146610037SARM gem5 Developers } 146710037SARM gem5 Developers 146810037SARM gem5 Developers return; 146910037SARM gem5 Developers } 147010037SARM gem5 Developers default: 147110037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 147210037SARM gem5 Developers } 147310037SARM gem5 Developers} 147410037SARM gem5 Developers 147510037SARM gem5 Developersvoid 147610037SARM gem5 DevelopersTableWalker::doLongDescriptor() 147710037SARM gem5 Developers{ 147810037SARM gem5 Developers if (currState->fault != NoFault) { 147910037SARM gem5 Developers return; 148010037SARM gem5 Developers } 148110037SARM gem5 Developers 148210037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 148310037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 148410037SARM gem5 Developers currState->longDesc.data, 148510037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 148610037SARM gem5 Developers 148710037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 148810037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 148910037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 149010037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 149110037SARM gem5 Developers currState->longDesc.lookupLevel, 149210037SARM gem5 Developers currState->longDesc.data, 149310037SARM gem5 Developers currState->longDesc.pxn(), 149410037SARM gem5 Developers currState->longDesc.xn(), 149510037SARM gem5 Developers currState->longDesc.ap(), 149610037SARM gem5 Developers currState->longDesc.af(), 149710037SARM gem5 Developers currState->longDesc.type()); 149810037SARM gem5 Developers } else { 149910037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 150010037SARM gem5 Developers currState->longDesc.lookupLevel, 150110037SARM gem5 Developers currState->longDesc.data, 150210037SARM gem5 Developers currState->longDesc.type()); 150310037SARM gem5 Developers } 150410037SARM gem5 Developers 150510037SARM gem5 Developers TlbEntry te; 150610037SARM gem5 Developers 150710037SARM gem5 Developers switch (currState->longDesc.type()) { 150810037SARM gem5 Developers case LongDescriptor::Invalid: 15097439Sdam.sunwoo@arm.com if (!currState->timing) { 15107439Sdam.sunwoo@arm.com currState->tc = NULL; 15117439Sdam.sunwoo@arm.com currState->req = NULL; 15127437Sdam.sunwoo@arm.com } 15137404SAli.Saidi@ARM.com 151410037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 151510037SARM gem5 Developers currState->longDesc.lookupLevel, 151610037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 151710037SARM gem5 Developers if (currState->isFetch) 151810474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 151910037SARM gem5 Developers currState->vaddr_tainted, 152010037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 152110037SARM gem5 Developers isStage2, 152210037SARM gem5 Developers ArmFault::LpaeTran); 152310037SARM gem5 Developers else 152410474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 152510037SARM gem5 Developers currState->vaddr_tainted, 152610037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 152710037SARM gem5 Developers currState->isWrite, 152810037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 152910037SARM gem5 Developers isStage2, 153010037SARM gem5 Developers ArmFault::LpaeTran); 15317404SAli.Saidi@ARM.com return; 153210037SARM gem5 Developers case LongDescriptor::Block: 153310037SARM gem5 Developers case LongDescriptor::Page: 153410037SARM gem5 Developers { 153510037SARM gem5 Developers bool fault = false; 153610037SARM gem5 Developers bool aff = false; 153710037SARM gem5 Developers // Check for address size fault 153810037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 153910037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 154010037SARM gem5 Developers currState->longDesc.offsetBits()), 154110037SARM gem5 Developers currState->physAddrRange)) { 154210037SARM gem5 Developers fault = true; 154310037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 154410037SARM gem5 Developers currState->longDesc.lookupLevel); 154510037SARM gem5 Developers // Check for access fault 154610037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 154710037SARM gem5 Developers fault = true; 154810037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 154910037SARM gem5 Developers currState->longDesc.lookupLevel); 155010037SARM gem5 Developers aff = true; 155110037SARM gem5 Developers } 155210037SARM gem5 Developers if (fault) { 155310037SARM gem5 Developers if (currState->isFetch) 155410474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 155510037SARM gem5 Developers currState->vaddr_tainted, 155610037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 155710037SARM gem5 Developers currState->longDesc.lookupLevel, 155810037SARM gem5 Developers isStage2, 155910037SARM gem5 Developers ArmFault::LpaeTran); 156010037SARM gem5 Developers else 156110474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 156210037SARM gem5 Developers currState->vaddr_tainted, 156310037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 156410037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 156510037SARM gem5 Developers currState->longDesc.lookupLevel, 156610037SARM gem5 Developers isStage2, 156710037SARM gem5 Developers ArmFault::LpaeTran); 156810037SARM gem5 Developers } else { 156910037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 157010037SARM gem5 Developers } 157110037SARM gem5 Developers } 157210037SARM gem5 Developers return; 157310037SARM gem5 Developers case LongDescriptor::Table: 157410037SARM gem5 Developers { 157510037SARM gem5 Developers // Set hierarchical permission flags 157610037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 157710037SARM gem5 Developers currState->longDesc.secureTable(); 157810037SARM gem5 Developers currState->rwTable = currState->rwTable && 157910037SARM gem5 Developers currState->longDesc.rwTable(); 158010037SARM gem5 Developers currState->userTable = currState->userTable && 158110037SARM gem5 Developers currState->longDesc.userTable(); 158210037SARM gem5 Developers currState->xnTable = currState->xnTable || 158310037SARM gem5 Developers currState->longDesc.xnTable(); 158410037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 158510037SARM gem5 Developers currState->longDesc.pxnTable(); 15867404SAli.Saidi@ARM.com 158710037SARM gem5 Developers // Set up next level lookup 158810037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 158910037SARM gem5 Developers currState->vaddr); 15907439Sdam.sunwoo@arm.com 159110037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 159210037SARM gem5 Developers currState->longDesc.lookupLevel, 159310037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 159410037SARM gem5 Developers next_desc_addr, 159510037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 159610037SARM gem5 Developers 159710037SARM gem5 Developers // Check for address size fault 159810037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 159910037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 160010037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 160110037SARM gem5 Developers currState->longDesc.lookupLevel); 160210037SARM gem5 Developers if (currState->isFetch) 160310474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 160410037SARM gem5 Developers currState->vaddr_tainted, 160510037SARM gem5 Developers ArmFault::AddressSizeLL 160610037SARM gem5 Developers + currState->longDesc.lookupLevel, 160710037SARM gem5 Developers isStage2, 160810037SARM gem5 Developers ArmFault::LpaeTran); 160910037SARM gem5 Developers else 161010474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 161110037SARM gem5 Developers currState->vaddr_tainted, 161210037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 161310037SARM gem5 Developers ArmFault::AddressSizeLL 161410037SARM gem5 Developers + currState->longDesc.lookupLevel, 161510037SARM gem5 Developers isStage2, 161610037SARM gem5 Developers ArmFault::LpaeTran); 161710037SARM gem5 Developers return; 16187437Sdam.sunwoo@arm.com } 16197404SAli.Saidi@ARM.com 162010037SARM gem5 Developers // Trickbox address check 162110037SARM gem5 Developers currState->fault = tlb->walkTrickBoxCheck( 162210037SARM gem5 Developers next_desc_addr, currState->vaddr, 162310037SARM gem5 Developers currState->vaddr, sizeof(uint64_t), 162410037SARM gem5 Developers currState->isFetch, currState->isWrite, 162510037SARM gem5 Developers TlbEntry::DomainType::Client, 162610037SARM gem5 Developers toLookupLevel(currState->longDesc.lookupLevel +1)); 16277404SAli.Saidi@ARM.com 162810037SARM gem5 Developers if (currState->fault) { 162910037SARM gem5 Developers if (!currState->timing) { 163010037SARM gem5 Developers currState->tc = NULL; 163110037SARM gem5 Developers currState->req = NULL; 163210037SARM gem5 Developers } 163310037SARM gem5 Developers return; 163410037SARM gem5 Developers } 163510037SARM gem5 Developers 163610037SARM gem5 Developers Request::Flags flag = 0; 163710037SARM gem5 Developers if (currState->secureLookup) 163810037SARM gem5 Developers flag.set(Request::SECURE); 163910037SARM gem5 Developers 164010037SARM gem5 Developers currState->longDesc.lookupLevel = 164110037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 164210037SARM gem5 Developers Event *event = NULL; 164310037SARM gem5 Developers switch (currState->longDesc.lookupLevel) { 164410037SARM gem5 Developers case L1: 164510037SARM gem5 Developers assert(currState->aarch64); 164610037SARM gem5 Developers event = &doL1LongDescEvent; 164710037SARM gem5 Developers break; 164810037SARM gem5 Developers case L2: 164910037SARM gem5 Developers event = &doL2LongDescEvent; 165010037SARM gem5 Developers break; 165110037SARM gem5 Developers case L3: 165210037SARM gem5 Developers event = &doL3LongDescEvent; 165310037SARM gem5 Developers break; 165410037SARM gem5 Developers default: 165510037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 165610037SARM gem5 Developers break; 165710037SARM gem5 Developers } 165810037SARM gem5 Developers 165910037SARM gem5 Developers bool delayed; 166010037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 166110037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 166210037SARM gem5 Developers &TableWalker::doLongDescriptor); 166310037SARM gem5 Developers if (delayed) { 166410037SARM gem5 Developers currState->delayed = true; 166510037SARM gem5 Developers } 16667404SAli.Saidi@ARM.com } 16677404SAli.Saidi@ARM.com return; 16687404SAli.Saidi@ARM.com default: 16697404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 16707404SAli.Saidi@ARM.com } 16717404SAli.Saidi@ARM.com} 16727404SAli.Saidi@ARM.com 16737404SAli.Saidi@ARM.comvoid 16747404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 16757404SAli.Saidi@ARM.com{ 167610037SARM gem5 Developers if (currState->fault != NoFault) { 167710037SARM gem5 Developers return; 167810037SARM gem5 Developers } 167910037SARM gem5 Developers 16807439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 168110037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 16827404SAli.Saidi@ARM.com TlbEntry te; 16837404SAli.Saidi@ARM.com 16847439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 16857404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 16867946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 16877439Sdam.sunwoo@arm.com currState->tc = NULL; 16887439Sdam.sunwoo@arm.com currState->req = NULL; 16897437Sdam.sunwoo@arm.com } 16907439Sdam.sunwoo@arm.com if (currState->isFetch) 169110474Sandreas.hansson@arm.com currState->fault = std::make_shared<PrefetchAbort>( 169210474Sandreas.hansson@arm.com currState->vaddr_tainted, 169310474Sandreas.hansson@arm.com ArmFault::TranslationLL + L2, 169410474Sandreas.hansson@arm.com isStage2, 169510474Sandreas.hansson@arm.com ArmFault::VmsaTran); 16967406SAli.Saidi@ARM.com else 169710474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 169810474Sandreas.hansson@arm.com currState->vaddr_tainted, currState->l1Desc.domain(), 169910474Sandreas.hansson@arm.com currState->isWrite, ArmFault::TranslationLL + L2, 170010474Sandreas.hansson@arm.com isStage2, 170110474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17027404SAli.Saidi@ARM.com return; 17037404SAli.Saidi@ARM.com } 17047404SAli.Saidi@ARM.com 17057439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 17067436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 17077436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 17087436Sdam.sunwoo@arm.com */ 170910037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 171010037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 17117436Sdam.sunwoo@arm.com 171210474Sandreas.hansson@arm.com currState->fault = std::make_shared<DataAbort>( 171310474Sandreas.hansson@arm.com currState->vaddr_tainted, 171410474Sandreas.hansson@arm.com TlbEntry::DomainType::NoAccess, currState->isWrite, 171510474Sandreas.hansson@arm.com ArmFault::AccessFlagLL + L2, isStage2, 171610474Sandreas.hansson@arm.com ArmFault::VmsaTran); 17177436Sdam.sunwoo@arm.com } 17187436Sdam.sunwoo@arm.com 171910037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 17207437Sdam.sunwoo@arm.com} 17217437Sdam.sunwoo@arm.com 17227437Sdam.sunwoo@arm.comvoid 17237437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 17247437Sdam.sunwoo@arm.com{ 172510037SARM gem5 Developers currState = stateQueues[L1].front(); 17267439Sdam.sunwoo@arm.com currState->delayed = false; 172710037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 172810037SARM gem5 Developers if (currState->stage2Tran) { 172910037SARM gem5 Developers delete currState->stage2Tran; 173010037SARM gem5 Developers currState->stage2Tran = NULL; 173110037SARM gem5 Developers } 173210037SARM gem5 Developers 17337437Sdam.sunwoo@arm.com 17347578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 17357578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 17367578Sdam.sunwoo@arm.com 173710037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 17387437Sdam.sunwoo@arm.com doL1Descriptor(); 17397437Sdam.sunwoo@arm.com 174010037SARM gem5 Developers stateQueues[L1].pop_front(); 17417437Sdam.sunwoo@arm.com // Check if fault was generated 17427439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 17437439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 17447439Sdam.sunwoo@arm.com currState->tc, currState->mode); 174510621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 17467437Sdam.sunwoo@arm.com 17477728SAli.Saidi@ARM.com pending = false; 17487728SAli.Saidi@ARM.com nextWalk(currState->tc); 17497728SAli.Saidi@ARM.com 17507439Sdam.sunwoo@arm.com currState->req = NULL; 17517439Sdam.sunwoo@arm.com currState->tc = NULL; 17527439Sdam.sunwoo@arm.com currState->delayed = false; 17538510SAli.Saidi@ARM.com delete currState; 17547437Sdam.sunwoo@arm.com } 17557439Sdam.sunwoo@arm.com else if (!currState->delayed) { 17567653Sgene.wu@arm.com // delay is not set so there is no L2 to do 175710037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 175810037SARM gem5 Developers if (!currState->doingStage2) { 175910621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 176010037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 176110037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 176210037SARM gem5 Developers currState->transState, currState->mode); 176310621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[0]++; 176410037SARM gem5 Developers } 17657437Sdam.sunwoo@arm.com 17667728SAli.Saidi@ARM.com pending = false; 17677728SAli.Saidi@ARM.com nextWalk(currState->tc); 17687728SAli.Saidi@ARM.com 17697439Sdam.sunwoo@arm.com currState->req = NULL; 17707439Sdam.sunwoo@arm.com currState->tc = NULL; 17717439Sdam.sunwoo@arm.com currState->delayed = false; 17727653Sgene.wu@arm.com delete currState; 17737653Sgene.wu@arm.com } else { 17747653Sgene.wu@arm.com // need to do L2 descriptor 177510037SARM gem5 Developers stateQueues[L2].push_back(currState); 17767437Sdam.sunwoo@arm.com } 17777439Sdam.sunwoo@arm.com currState = NULL; 17787437Sdam.sunwoo@arm.com} 17797437Sdam.sunwoo@arm.com 17807437Sdam.sunwoo@arm.comvoid 17817437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 17827437Sdam.sunwoo@arm.com{ 178310037SARM gem5 Developers currState = stateQueues[L2].front(); 17847439Sdam.sunwoo@arm.com assert(currState->delayed); 178510037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 178610037SARM gem5 Developers if (currState->stage2Tran) { 178710037SARM gem5 Developers delete currState->stage2Tran; 178810037SARM gem5 Developers currState->stage2Tran = NULL; 178910037SARM gem5 Developers } 17907437Sdam.sunwoo@arm.com 17917439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 179210037SARM gem5 Developers currState->vaddr_tainted); 17937437Sdam.sunwoo@arm.com doL2Descriptor(); 17947437Sdam.sunwoo@arm.com 17957437Sdam.sunwoo@arm.com // Check if fault was generated 17967439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 17977439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 17987439Sdam.sunwoo@arm.com currState->tc, currState->mode); 179910621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 18007437Sdam.sunwoo@arm.com } 18017437Sdam.sunwoo@arm.com else { 180210037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 180310037SARM gem5 Developers if (!currState->doingStage2) { 180410621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 180510037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 180610037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, 180710037SARM gem5 Developers currState->tc, currState->transState, currState->mode); 180810621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel[1]++; 180910037SARM gem5 Developers } 18107437Sdam.sunwoo@arm.com } 18117437Sdam.sunwoo@arm.com 18127728SAli.Saidi@ARM.com 181310037SARM gem5 Developers stateQueues[L2].pop_front(); 18147728SAli.Saidi@ARM.com pending = false; 18157728SAli.Saidi@ARM.com nextWalk(currState->tc); 18167728SAli.Saidi@ARM.com 18177439Sdam.sunwoo@arm.com currState->req = NULL; 18187439Sdam.sunwoo@arm.com currState->tc = NULL; 18197439Sdam.sunwoo@arm.com currState->delayed = false; 18207439Sdam.sunwoo@arm.com 18217653Sgene.wu@arm.com delete currState; 18227439Sdam.sunwoo@arm.com currState = NULL; 18237404SAli.Saidi@ARM.com} 18247404SAli.Saidi@ARM.com 18257728SAli.Saidi@ARM.comvoid 182610037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 182710037SARM gem5 Developers{ 182810037SARM gem5 Developers doLongDescriptorWrapper(L0); 182910037SARM gem5 Developers} 183010037SARM gem5 Developers 183110037SARM gem5 Developersvoid 183210037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 183310037SARM gem5 Developers{ 183410037SARM gem5 Developers doLongDescriptorWrapper(L1); 183510037SARM gem5 Developers} 183610037SARM gem5 Developers 183710037SARM gem5 Developersvoid 183810037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 183910037SARM gem5 Developers{ 184010037SARM gem5 Developers doLongDescriptorWrapper(L2); 184110037SARM gem5 Developers} 184210037SARM gem5 Developers 184310037SARM gem5 Developersvoid 184410037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 184510037SARM gem5 Developers{ 184610037SARM gem5 Developers doLongDescriptorWrapper(L3); 184710037SARM gem5 Developers} 184810037SARM gem5 Developers 184910037SARM gem5 Developersvoid 185010037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 185110037SARM gem5 Developers{ 185210037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 185310037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 185410037SARM gem5 Developers currState->delayed = false; 185510037SARM gem5 Developers 185610037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 185710037SARM gem5 Developers if (currState->stage2Tran) { 185810037SARM gem5 Developers delete currState->stage2Tran; 185910037SARM gem5 Developers currState->stage2Tran = NULL; 186010037SARM gem5 Developers } 186110037SARM gem5 Developers 186210037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 186310037SARM gem5 Developers currState->vaddr_tainted); 186410037SARM gem5 Developers doLongDescriptor(); 186510037SARM gem5 Developers 186610037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 186710037SARM gem5 Developers 186810037SARM gem5 Developers if (currState->fault != NoFault) { 186910037SARM gem5 Developers // A fault was generated 187010037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 187110037SARM gem5 Developers currState->tc, currState->mode); 187210037SARM gem5 Developers 187310037SARM gem5 Developers pending = false; 187410037SARM gem5 Developers nextWalk(currState->tc); 187510037SARM gem5 Developers 187610037SARM gem5 Developers currState->req = NULL; 187710037SARM gem5 Developers currState->tc = NULL; 187810037SARM gem5 Developers currState->delayed = false; 187910037SARM gem5 Developers delete currState; 188010037SARM gem5 Developers } else if (!currState->delayed) { 188110037SARM gem5 Developers // No additional lookups required 188210037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 188310037SARM gem5 Developers if (!currState->doingStage2) { 188410037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 188510621SCurtis.Dunham@arm.com statWalkServiceTime.sample(curTick() - currState->startTime); 188610037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 188710037SARM gem5 Developers currState->transState, 188810037SARM gem5 Developers currState->mode); 188910621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++; 189010037SARM gem5 Developers } 189110037SARM gem5 Developers 189210037SARM gem5 Developers pending = false; 189310037SARM gem5 Developers nextWalk(currState->tc); 189410037SARM gem5 Developers 189510037SARM gem5 Developers currState->req = NULL; 189610037SARM gem5 Developers currState->tc = NULL; 189710037SARM gem5 Developers currState->delayed = false; 189810037SARM gem5 Developers delete currState; 189910037SARM gem5 Developers } else { 190010037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 190110037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 190210037SARM gem5 Developers // Need to perform additional lookups 190310037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 190410037SARM gem5 Developers } 190510037SARM gem5 Developers currState = NULL; 190610037SARM gem5 Developers} 190710037SARM gem5 Developers 190810037SARM gem5 Developers 190910037SARM gem5 Developersvoid 19107728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 19117728SAli.Saidi@ARM.com{ 19127728SAli.Saidi@ARM.com if (pendingQueue.size()) 19139309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 191410509SAli.Saidi@ARM.com else 191510509SAli.Saidi@ARM.com completeDrain(); 19167728SAli.Saidi@ARM.com} 19177728SAli.Saidi@ARM.com 191810037SARM gem5 Developersbool 191910037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 192010037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 192110037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 192210037SARM gem5 Developers{ 192310037SARM gem5 Developers bool isTiming = currState->timing; 19247728SAli.Saidi@ARM.com 192510037SARM gem5 Developers // do the requests for the page table descriptors have to go through the 192610037SARM gem5 Developers // second stage MMU 192710037SARM gem5 Developers if (currState->stage2Req) { 192810037SARM gem5 Developers Fault fault; 192910037SARM gem5 Developers flags = flags | TLB::MustBeOne; 193010037SARM gem5 Developers 193110037SARM gem5 Developers if (isTiming) { 193210037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 193310037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 193410037SARM gem5 Developers currState->vaddr); 193510037SARM gem5 Developers currState->stage2Tran = tran; 193610037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 193710717Sandreas.hansson@arm.com flags); 193810037SARM gem5 Developers fault = tran->fault; 193910037SARM gem5 Developers } else { 194010037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 194110717Sandreas.hansson@arm.com currState->vaddr, descAddr, data, numBytes, flags, 194210037SARM gem5 Developers currState->functional); 194310037SARM gem5 Developers } 194410037SARM gem5 Developers 194510037SARM gem5 Developers if (fault != NoFault) { 194610037SARM gem5 Developers currState->fault = fault; 194710037SARM gem5 Developers } 194810037SARM gem5 Developers if (isTiming) { 194910037SARM gem5 Developers if (queueIndex >= 0) { 195010037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 195110037SARM gem5 Developers stateQueues[queueIndex].size()); 195210037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 195310037SARM gem5 Developers currState = NULL; 195410037SARM gem5 Developers } 195510037SARM gem5 Developers } else { 195610037SARM gem5 Developers (this->*doDescriptor)(); 195710037SARM gem5 Developers } 195810037SARM gem5 Developers } else { 195910037SARM gem5 Developers if (isTiming) { 196010717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 196110621SCurtis.Dunham@arm.com currState->tc->getCpuPtr()->clockPeriod(),flags); 196210037SARM gem5 Developers if (queueIndex >= 0) { 196310037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 196410037SARM gem5 Developers stateQueues[queueIndex].size()); 196510037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 196610037SARM gem5 Developers currState = NULL; 196710037SARM gem5 Developers } 196810037SARM gem5 Developers } else if (!currState->functional) { 196910717Sandreas.hansson@arm.com port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 197010037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 197110037SARM gem5 Developers (this->*doDescriptor)(); 197210037SARM gem5 Developers } else { 197310037SARM gem5 Developers RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 197410037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 197510037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 197610037SARM gem5 Developers pkt->dataStatic(data); 197710717Sandreas.hansson@arm.com port->sendFunctional(pkt); 197810037SARM gem5 Developers (this->*doDescriptor)(); 197910037SARM gem5 Developers delete req; 198010037SARM gem5 Developers delete pkt; 198110037SARM gem5 Developers } 198210037SARM gem5 Developers } 198310037SARM gem5 Developers return (isTiming); 198410037SARM gem5 Developers} 198510037SARM gem5 Developers 198610037SARM gem5 Developersvoid 198710037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 198810037SARM gem5 Developers{ 198910037SARM gem5 Developers TlbEntry te; 199010037SARM gem5 Developers 199110037SARM gem5 Developers // Create and fill a new page table entry 199210037SARM gem5 Developers te.valid = true; 199310037SARM gem5 Developers te.longDescFormat = longDescriptor; 199410037SARM gem5 Developers te.isHyp = currState->isHyp; 199510037SARM gem5 Developers te.asid = currState->asid; 199610037SARM gem5 Developers te.vmid = currState->vmid; 199710037SARM gem5 Developers te.N = descriptor.offsetBits(); 199810037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 199910037SARM gem5 Developers te.size = (1<<te.N) - 1; 200010037SARM gem5 Developers te.pfn = descriptor.pfn(); 200110037SARM gem5 Developers te.domain = descriptor.domain(); 200210037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 200310037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 200410037SARM gem5 Developers te.nstid = !currState->isSecure; 200510037SARM gem5 Developers te.xn = descriptor.xn(); 200610037SARM gem5 Developers if (currState->aarch64) 200710037SARM gem5 Developers te.el = currState->el; 200810037SARM gem5 Developers else 200910037SARM gem5 Developers te.el = 1; 201010037SARM gem5 Developers 201110621SCurtis.Dunham@arm.com statPageSizes[pageSizeNtoStatBin(te.N)]++; 201210621SCurtis.Dunham@arm.com statRequestOrigin[COMPLETED][currState->isFetch]++; 201310621SCurtis.Dunham@arm.com 201410037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 201510037SARM gem5 Developers // as global 201610037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 201710037SARM gem5 Developers if (longDescriptor) { 201810037SARM gem5 Developers LongDescriptor lDescriptor = 201910037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 202010037SARM gem5 Developers 202110037SARM gem5 Developers te.xn |= currState->xnTable; 202210037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 202310037SARM gem5 Developers if (isStage2) { 202410037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 202510037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 202610037SARM gem5 Developers te.hap = lDescriptor.ap(); 202710037SARM gem5 Developers } else { 202810037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 202910037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 203010037SARM gem5 Developers } 203110037SARM gem5 Developers if (currState->aarch64) 203210037SARM gem5 Developers memAttrsAArch64(currState->tc, te, currState->longDesc.attrIndx(), 203310037SARM gem5 Developers currState->longDesc.sh()); 203410037SARM gem5 Developers else 203510037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 203610037SARM gem5 Developers } else { 203710037SARM gem5 Developers te.ap = descriptor.ap(); 203810037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 203910037SARM gem5 Developers descriptor.shareable()); 204010037SARM gem5 Developers } 204110037SARM gem5 Developers 204210037SARM gem5 Developers // Debug output 204310037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 204410037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 204510037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 204610037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 204710037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 204810037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 204910037SARM gem5 Developers te.nonCacheable, te.ns); 205010037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 205110037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 205210037SARM gem5 Developers descriptor.getRawData()); 205310037SARM gem5 Developers 205410037SARM gem5 Developers // Insert the entry into the TLB 205510037SARM gem5 Developers tlb->insert(currState->vaddr, te); 205610037SARM gem5 Developers if (!currState->timing) { 205710037SARM gem5 Developers currState->tc = NULL; 205810037SARM gem5 Developers currState->req = NULL; 205910037SARM gem5 Developers } 206010037SARM gem5 Developers} 20617728SAli.Saidi@ARM.com 20627404SAli.Saidi@ARM.comArmISA::TableWalker * 20637404SAli.Saidi@ARM.comArmTableWalkerParams::create() 20647404SAli.Saidi@ARM.com{ 20657404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 20667404SAli.Saidi@ARM.com} 20677404SAli.Saidi@ARM.com 206810037SARM gem5 DevelopersLookupLevel 206910037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 207010037SARM gem5 Developers{ 207110037SARM gem5 Developers switch (lookup_level_as_int) { 207210037SARM gem5 Developers case L1: 207310037SARM gem5 Developers return L1; 207410037SARM gem5 Developers case L2: 207510037SARM gem5 Developers return L2; 207610037SARM gem5 Developers case L3: 207710037SARM gem5 Developers return L3; 207810037SARM gem5 Developers default: 207910037SARM gem5 Developers panic("Invalid lookup level conversion"); 208010037SARM gem5 Developers } 208110037SARM gem5 Developers} 208210621SCurtis.Dunham@arm.com 208310621SCurtis.Dunham@arm.com/* this method keeps track of the table walker queue's residency, so 208410621SCurtis.Dunham@arm.com * needs to be called whenever requests start and complete. */ 208510621SCurtis.Dunham@arm.comvoid 208610621SCurtis.Dunham@arm.comTableWalker::pendingChange() 208710621SCurtis.Dunham@arm.com{ 208810621SCurtis.Dunham@arm.com unsigned n = pendingQueue.size(); 208910621SCurtis.Dunham@arm.com if ((currState != NULL) && (currState != pendingQueue.front())) { 209010621SCurtis.Dunham@arm.com ++n; 209110621SCurtis.Dunham@arm.com } 209210621SCurtis.Dunham@arm.com 209310621SCurtis.Dunham@arm.com if (n != pendingReqs) { 209410621SCurtis.Dunham@arm.com Tick now = curTick(); 209510621SCurtis.Dunham@arm.com statPendingWalks.sample(pendingReqs, now - pendingChangeTick); 209610621SCurtis.Dunham@arm.com pendingReqs = n; 209710621SCurtis.Dunham@arm.com pendingChangeTick = now; 209810621SCurtis.Dunham@arm.com } 209910621SCurtis.Dunham@arm.com} 210010621SCurtis.Dunham@arm.com 210110621SCurtis.Dunham@arm.comuint8_t 210210621SCurtis.Dunham@arm.comTableWalker::pageSizeNtoStatBin(uint8_t N) 210310621SCurtis.Dunham@arm.com{ 210410621SCurtis.Dunham@arm.com /* for statPageSizes */ 210510621SCurtis.Dunham@arm.com switch(N) { 210610621SCurtis.Dunham@arm.com case 12: return 0; // 4K 210710621SCurtis.Dunham@arm.com case 14: return 1; // 16K (using 16K granule in v8-64) 210810621SCurtis.Dunham@arm.com case 16: return 2; // 64K 210910621SCurtis.Dunham@arm.com case 20: return 3; // 1M 211010621SCurtis.Dunham@arm.com case 21: return 4; // 2M-LPAE 211110621SCurtis.Dunham@arm.com case 24: return 5; // 16M 211210621SCurtis.Dunham@arm.com case 25: return 6; // 32M (using 16K granule in v8-64) 211310621SCurtis.Dunham@arm.com case 29: return 7; // 512M (using 64K granule in v8-64) 211410621SCurtis.Dunham@arm.com case 30: return 8; // 1G-LPAE 211510621SCurtis.Dunham@arm.com default: 211610621SCurtis.Dunham@arm.com panic("unknown page size"); 211710621SCurtis.Dunham@arm.com return 255; 211810621SCurtis.Dunham@arm.com } 211910621SCurtis.Dunham@arm.com} 212010621SCurtis.Dunham@arm.com 212110621SCurtis.Dunham@arm.comvoid 212210621SCurtis.Dunham@arm.comTableWalker::regStats() 212310621SCurtis.Dunham@arm.com{ 212410621SCurtis.Dunham@arm.com statWalks 212510621SCurtis.Dunham@arm.com .name(name() + ".walks") 212610621SCurtis.Dunham@arm.com .desc("Table walker walks requested") 212710621SCurtis.Dunham@arm.com ; 212810621SCurtis.Dunham@arm.com 212910621SCurtis.Dunham@arm.com statWalksShortDescriptor 213010621SCurtis.Dunham@arm.com .name(name() + ".walksShort") 213110621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with short descriptors") 213210621SCurtis.Dunham@arm.com .flags(Stats::nozero) 213310621SCurtis.Dunham@arm.com ; 213410621SCurtis.Dunham@arm.com 213510621SCurtis.Dunham@arm.com statWalksLongDescriptor 213610621SCurtis.Dunham@arm.com .name(name() + ".walksLong") 213710621SCurtis.Dunham@arm.com .desc("Table walker walks initiated with long descriptors") 213810621SCurtis.Dunham@arm.com .flags(Stats::nozero) 213910621SCurtis.Dunham@arm.com ; 214010621SCurtis.Dunham@arm.com 214110621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel 214210621SCurtis.Dunham@arm.com .init(2) 214310621SCurtis.Dunham@arm.com .name(name() + ".walksShortTerminationLevel") 214410621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 214510621SCurtis.Dunham@arm.com "with short descriptors terminate") 214610621SCurtis.Dunham@arm.com .flags(Stats::nozero) 214710621SCurtis.Dunham@arm.com ; 214810621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(0, "Level1"); 214910621SCurtis.Dunham@arm.com statWalksShortTerminatedAtLevel.subname(1, "Level2"); 215010621SCurtis.Dunham@arm.com 215110621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel 215210621SCurtis.Dunham@arm.com .init(4) 215310621SCurtis.Dunham@arm.com .name(name() + ".walksLongTerminationLevel") 215410621SCurtis.Dunham@arm.com .desc("Level at which table walker walks " 215510621SCurtis.Dunham@arm.com "with long descriptors terminate") 215610621SCurtis.Dunham@arm.com .flags(Stats::nozero) 215710621SCurtis.Dunham@arm.com ; 215810621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(0, "Level0"); 215910621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(1, "Level1"); 216010621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(2, "Level2"); 216110621SCurtis.Dunham@arm.com statWalksLongTerminatedAtLevel.subname(3, "Level3"); 216210621SCurtis.Dunham@arm.com 216310621SCurtis.Dunham@arm.com statSquashedBefore 216410621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedBefore") 216510621SCurtis.Dunham@arm.com .desc("Table walks squashed before starting") 216610621SCurtis.Dunham@arm.com .flags(Stats::nozero) 216710621SCurtis.Dunham@arm.com ; 216810621SCurtis.Dunham@arm.com 216910621SCurtis.Dunham@arm.com statSquashedAfter 217010621SCurtis.Dunham@arm.com .name(name() + ".walksSquashedAfter") 217110621SCurtis.Dunham@arm.com .desc("Table walks squashed after completion") 217210621SCurtis.Dunham@arm.com .flags(Stats::nozero) 217310621SCurtis.Dunham@arm.com ; 217410621SCurtis.Dunham@arm.com 217510621SCurtis.Dunham@arm.com statWalkWaitTime 217610621SCurtis.Dunham@arm.com .init(16) 217710621SCurtis.Dunham@arm.com .name(name() + ".walkWaitTime") 217810621SCurtis.Dunham@arm.com .desc("Table walker wait (enqueue to first request) latency") 217910621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 218010621SCurtis.Dunham@arm.com ; 218110621SCurtis.Dunham@arm.com 218210621SCurtis.Dunham@arm.com statWalkServiceTime 218310621SCurtis.Dunham@arm.com .init(16) 218410621SCurtis.Dunham@arm.com .name(name() + ".walkCompletionTime") 218510621SCurtis.Dunham@arm.com .desc("Table walker service (enqueue to completion) latency") 218610621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::nozero | Stats::nonan) 218710621SCurtis.Dunham@arm.com ; 218810621SCurtis.Dunham@arm.com 218910621SCurtis.Dunham@arm.com statPendingWalks 219010621SCurtis.Dunham@arm.com .init(16) 219110621SCurtis.Dunham@arm.com .name(name() + ".walksPending") 219210621SCurtis.Dunham@arm.com .desc("Table walker pending requests distribution") 219310621SCurtis.Dunham@arm.com .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan) 219410621SCurtis.Dunham@arm.com ; 219510621SCurtis.Dunham@arm.com 219610621SCurtis.Dunham@arm.com statPageSizes // see DDI 0487A D4-1661 219710621SCurtis.Dunham@arm.com .init(9) 219810621SCurtis.Dunham@arm.com .name(name() + ".walkPageSizes") 219910621SCurtis.Dunham@arm.com .desc("Table walker page sizes translated") 220010621SCurtis.Dunham@arm.com .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero) 220110621SCurtis.Dunham@arm.com ; 220210621SCurtis.Dunham@arm.com statPageSizes.subname(0, "4K"); 220310621SCurtis.Dunham@arm.com statPageSizes.subname(1, "16K"); 220410621SCurtis.Dunham@arm.com statPageSizes.subname(2, "64K"); 220510621SCurtis.Dunham@arm.com statPageSizes.subname(3, "1M"); 220610621SCurtis.Dunham@arm.com statPageSizes.subname(4, "2M"); 220710621SCurtis.Dunham@arm.com statPageSizes.subname(5, "16M"); 220810621SCurtis.Dunham@arm.com statPageSizes.subname(6, "32M"); 220910621SCurtis.Dunham@arm.com statPageSizes.subname(7, "512M"); 221010621SCurtis.Dunham@arm.com statPageSizes.subname(8, "1G"); 221110621SCurtis.Dunham@arm.com 221210621SCurtis.Dunham@arm.com statRequestOrigin 221310621SCurtis.Dunham@arm.com .init(2,2) // Instruction/Data, requests/completed 221410621SCurtis.Dunham@arm.com .name(name() + ".walkRequestOrigin") 221510621SCurtis.Dunham@arm.com .desc("Table walker requests started/completed, data/inst") 221610621SCurtis.Dunham@arm.com .flags(Stats::total) 221710621SCurtis.Dunham@arm.com ; 221810621SCurtis.Dunham@arm.com statRequestOrigin.subname(0,"Requested"); 221910621SCurtis.Dunham@arm.com statRequestOrigin.subname(1,"Completed"); 222010621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(0,"Data"); 222110621SCurtis.Dunham@arm.com statRequestOrigin.ysubname(1,"Inst"); 222210621SCurtis.Dunham@arm.com} 2223