table_walker.cc revision 10109
17404SAli.Saidi@ARM.com/* 210037SARM gem5 Developers * Copyright (c) 2010, 2012-2013 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 407404SAli.Saidi@ARM.com 417404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 4210037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 4310037SARM gem5 Developers#include "arch/arm/system.hh" 447404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 457404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 467728SAli.Saidi@ARM.com#include "cpu/base.hh" 477404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 488245Snate@binkert.org#include "debug/Checkpoint.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 508245Snate@binkert.org#include "debug/TLB.hh" 518245Snate@binkert.org#include "debug/TLBVerbose.hh" 527748SAli.Saidi@ARM.com#include "sim/system.hh" 537404SAli.Saidi@ARM.com 547404SAli.Saidi@ARM.comusing namespace ArmISA; 557404SAli.Saidi@ARM.com 567404SAli.Saidi@ARM.comTableWalker::TableWalker(const Params *p) 5710037SARM gem5 Developers : MemObject(p), port(this, p->sys), drainManager(NULL), 5810037SARM gem5 Developers stage2Mmu(NULL), isStage2(p->is_stage2), tlb(NULL), 5910037SARM gem5 Developers currState(NULL), pending(false), masterId(p->sys->getMasterId(name())), 609258SAli.Saidi@ARM.com numSquashable(p->num_squash_per_cycle), 6110037SARM gem5 Developers doL1DescEvent(this), doL2DescEvent(this), 6210037SARM gem5 Developers doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this), 6310037SARM gem5 Developers doL3LongDescEvent(this), 6410037SARM gem5 Developers doProcessEvent(this) 657439Sdam.sunwoo@arm.com{ 667576SAli.Saidi@ARM.com sctlr = 0; 6710037SARM gem5 Developers 6810037SARM gem5 Developers // Cache system-level properties 6910037SARM gem5 Developers if (FullSystem) { 7010037SARM gem5 Developers armSys = dynamic_cast<ArmSystem *>(p->sys); 7110037SARM gem5 Developers assert(armSys); 7210037SARM gem5 Developers haveSecurity = armSys->haveSecurity(); 7310037SARM gem5 Developers _haveLPAE = armSys->haveLPAE(); 7410037SARM gem5 Developers _haveVirtualization = armSys->haveVirtualization(); 7510037SARM gem5 Developers physAddrRange = armSys->physAddrRange(); 7610037SARM gem5 Developers _haveLargeAsid64 = armSys->haveLargeAsid64(); 7710037SARM gem5 Developers } else { 7810037SARM gem5 Developers armSys = NULL; 7910037SARM gem5 Developers haveSecurity = _haveLPAE = _haveVirtualization = false; 8010037SARM gem5 Developers _haveLargeAsid64 = false; 8110037SARM gem5 Developers physAddrRange = 32; 8210037SARM gem5 Developers } 8310037SARM gem5 Developers 847439Sdam.sunwoo@arm.com} 857404SAli.Saidi@ARM.com 867404SAli.Saidi@ARM.comTableWalker::~TableWalker() 877404SAli.Saidi@ARM.com{ 887404SAli.Saidi@ARM.com ; 897404SAli.Saidi@ARM.com} 907404SAli.Saidi@ARM.com 9110037SARM gem5 DevelopersTableWalker::WalkerState::WalkerState() : stage2Tran(NULL), l2Desc(l1Desc) 9210037SARM gem5 Developers{ 9310037SARM gem5 Developers} 9410037SARM gem5 Developers 959152Satgutier@umich.eduvoid 969152Satgutier@umich.eduTableWalker::completeDrain() 979152Satgutier@umich.edu{ 9810037SARM gem5 Developers if (drainManager && stateQueues[L1].empty() && stateQueues[L2].empty() && 999152Satgutier@umich.edu pendingQueue.empty()) { 1009342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1019152Satgutier@umich.edu DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 1029342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 1039342SAndreas.Sandberg@arm.com drainManager = NULL; 1049152Satgutier@umich.edu } 1059152Satgutier@umich.edu} 1069152Satgutier@umich.edu 1077748SAli.Saidi@ARM.comunsigned int 1089342SAndreas.Sandberg@arm.comTableWalker::drain(DrainManager *dm) 1097404SAli.Saidi@ARM.com{ 1109342SAndreas.Sandberg@arm.com unsigned int count = port.drain(dm); 1119152Satgutier@umich.edu 11210037SARM gem5 Developers bool state_queues_not_empty = false; 1139152Satgutier@umich.edu 11410037SARM gem5 Developers for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) { 11510037SARM gem5 Developers if (!stateQueues[i].empty()) { 11610037SARM gem5 Developers state_queues_not_empty = true; 11710037SARM gem5 Developers break; 11810037SARM gem5 Developers } 11910037SARM gem5 Developers } 12010037SARM gem5 Developers 12110037SARM gem5 Developers if (state_queues_not_empty || pendingQueue.size()) { 1229342SAndreas.Sandberg@arm.com drainManager = dm; 1239342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 1249152Satgutier@umich.edu DPRINTF(Drain, "TableWalker not drained\n"); 1259152Satgutier@umich.edu 1269152Satgutier@umich.edu // return port drain count plus the table walker itself needs to drain 1279152Satgutier@umich.edu return count + 1; 12810037SARM gem5 Developers } else { 12910037SARM gem5 Developers setDrainState(Drainable::Drained); 13010037SARM gem5 Developers DPRINTF(Drain, "TableWalker free, no need to drain\n"); 1319152Satgutier@umich.edu 13210037SARM gem5 Developers // table walker is drained, but its ports may still need to be drained 13310037SARM gem5 Developers return count; 1347733SAli.Saidi@ARM.com } 1357404SAli.Saidi@ARM.com} 1367404SAli.Saidi@ARM.com 1377748SAli.Saidi@ARM.comvoid 1389342SAndreas.Sandberg@arm.comTableWalker::drainResume() 1397748SAli.Saidi@ARM.com{ 1409342SAndreas.Sandberg@arm.com Drainable::drainResume(); 1419524SAndreas.Sandberg@ARM.com if (params()->sys->isTimingMode() && currState) { 1429152Satgutier@umich.edu delete currState; 1439152Satgutier@umich.edu currState = NULL; 1447748SAli.Saidi@ARM.com } 1457748SAli.Saidi@ARM.com} 1467748SAli.Saidi@ARM.com 1479294Sandreas.hansson@arm.comBaseMasterPort& 1489294Sandreas.hansson@arm.comTableWalker::getMasterPort(const std::string &if_name, PortID idx) 1497404SAli.Saidi@ARM.com{ 1507404SAli.Saidi@ARM.com if (if_name == "port") { 1518922Swilliam.wang@arm.com return port; 1527404SAli.Saidi@ARM.com } 1538922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1547404SAli.Saidi@ARM.com} 1557404SAli.Saidi@ARM.com 1567404SAli.Saidi@ARM.comFault 15710037SARM gem5 DevelopersTableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, 15810037SARM gem5 Developers uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 15910037SARM gem5 Developers TLB::Translation *_trans, bool _timing, bool _functional, 16010037SARM gem5 Developers bool secure, TLB::ArmTranslationType tranType) 1617404SAli.Saidi@ARM.com{ 1628733Sgeoffrey.blake@arm.com assert(!(_functional && _timing)); 16310109SGeoffrey.Blake@arm.com WalkerState *savedCurrState = NULL; 16410037SARM gem5 Developers 16510109SGeoffrey.Blake@arm.com if (!currState && !_functional) { 1667439Sdam.sunwoo@arm.com // For atomic mode, a new WalkerState instance should be only created 1677439Sdam.sunwoo@arm.com // once per TLB. For timing mode, a new instance is generated for every 1687439Sdam.sunwoo@arm.com // TLB miss. 1697439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 1707404SAli.Saidi@ARM.com 1717439Sdam.sunwoo@arm.com currState = new WalkerState(); 1727439Sdam.sunwoo@arm.com currState->tableWalker = this; 17310109SGeoffrey.Blake@arm.com } else if (_functional) { 17410109SGeoffrey.Blake@arm.com // If we are mixing functional mode with timing (or even 17510109SGeoffrey.Blake@arm.com // atomic), we need to to be careful and clean up after 17610109SGeoffrey.Blake@arm.com // ourselves to not risk getting into an inconsistent state. 17710109SGeoffrey.Blake@arm.com DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n"); 17810109SGeoffrey.Blake@arm.com savedCurrState = currState; 17910109SGeoffrey.Blake@arm.com currState = new WalkerState(); 18010109SGeoffrey.Blake@arm.com currState->tableWalker = this; 1818202SAli.Saidi@ARM.com } else if (_timing) { 1828202SAli.Saidi@ARM.com // This is a translation that was completed and then faulted again 1838202SAli.Saidi@ARM.com // because some underlying parameters that affect the translation 1848202SAli.Saidi@ARM.com // changed out from under us (e.g. asid). It will either be a 1858202SAli.Saidi@ARM.com // misprediction, in which case nothing will happen or we'll use 1868202SAli.Saidi@ARM.com // this fault to re-execute the faulting instruction which should clean 1878202SAli.Saidi@ARM.com // up everything. 18810037SARM gem5 Developers if (currState->vaddr_tainted == _req->getVaddr()) { 1898202SAli.Saidi@ARM.com return new ReExec; 1908202SAli.Saidi@ARM.com } 1917439Sdam.sunwoo@arm.com } 1927439Sdam.sunwoo@arm.com 1937439Sdam.sunwoo@arm.com currState->tc = _tc; 19410037SARM gem5 Developers currState->aarch64 = opModeIs64(currOpMode(_tc)); 19510037SARM gem5 Developers currState->el = currEL(_tc); 1967439Sdam.sunwoo@arm.com currState->transState = _trans; 1977439Sdam.sunwoo@arm.com currState->req = _req; 1987439Sdam.sunwoo@arm.com currState->fault = NoFault; 19910037SARM gem5 Developers currState->asid = _asid; 20010037SARM gem5 Developers currState->vmid = _vmid; 20110037SARM gem5 Developers currState->isHyp = _isHyp; 2027439Sdam.sunwoo@arm.com currState->timing = _timing; 2038733Sgeoffrey.blake@arm.com currState->functional = _functional; 2047439Sdam.sunwoo@arm.com currState->mode = _mode; 20510037SARM gem5 Developers currState->tranType = tranType; 20610037SARM gem5 Developers currState->isSecure = secure; 20710037SARM gem5 Developers currState->physAddrRange = physAddrRange; 2087404SAli.Saidi@ARM.com 2097436Sdam.sunwoo@arm.com /** @todo These should be cached or grabbed from cached copies in 2107436Sdam.sunwoo@arm.com the TLB, all these miscreg reads are expensive */ 21110037SARM gem5 Developers currState->vaddr_tainted = currState->req->getVaddr(); 21210037SARM gem5 Developers if (currState->aarch64) 21310037SARM gem5 Developers currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted, 21410037SARM gem5 Developers currState->tc, currState->el); 21510037SARM gem5 Developers else 21610037SARM gem5 Developers currState->vaddr = currState->vaddr_tainted; 21710037SARM gem5 Developers 21810037SARM gem5 Developers if (currState->aarch64) { 21910037SARM gem5 Developers switch (currState->el) { 22010037SARM gem5 Developers case EL0: 22110037SARM gem5 Developers case EL1: 22210037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); 22310037SARM gem5 Developers currState->ttbcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 22410037SARM gem5 Developers break; 22510037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 22610037SARM gem5 Developers // case EL2: 22710037SARM gem5 Developers // assert(haveVirtualization); 22810037SARM gem5 Developers // currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); 22910037SARM gem5 Developers // currState->ttbcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 23010037SARM gem5 Developers // break; 23110037SARM gem5 Developers case EL3: 23210037SARM gem5 Developers assert(haveSecurity); 23310037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); 23410037SARM gem5 Developers currState->ttbcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 23510037SARM gem5 Developers break; 23610037SARM gem5 Developers default: 23710037SARM gem5 Developers panic("Invalid exception level"); 23810037SARM gem5 Developers break; 23910037SARM gem5 Developers } 24010037SARM gem5 Developers } else { 24110037SARM gem5 Developers currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 24210037SARM gem5 Developers MISCREG_SCTLR, currState->tc, !currState->isSecure)); 24310037SARM gem5 Developers currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 24410037SARM gem5 Developers MISCREG_TTBCR, currState->tc, !currState->isSecure)); 24510037SARM gem5 Developers currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); 24610037SARM gem5 Developers currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); 24710037SARM gem5 Developers currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); 24810037SARM gem5 Developers } 2497439Sdam.sunwoo@arm.com sctlr = currState->sctlr; 2507439Sdam.sunwoo@arm.com 2517439Sdam.sunwoo@arm.com currState->isFetch = (currState->mode == TLB::Execute); 2527439Sdam.sunwoo@arm.com currState->isWrite = (currState->mode == TLB::Write); 2537439Sdam.sunwoo@arm.com 25410037SARM gem5 Developers // We only do a second stage of translation if we're not secure, or in 25510037SARM gem5 Developers // hyp mode, the second stage MMU is enabled, and this table walker 25610037SARM gem5 Developers // instance is the first stage. 25710037SARM gem5 Developers currState->doingStage2 = false; 25810037SARM gem5 Developers // @todo: for now disable this in AArch64 (HCR is not set) 25910037SARM gem5 Developers currState->stage2Req = !currState->aarch64 && currState->hcr.vm && 26010037SARM gem5 Developers !isStage2 && !currState->isSecure && !currState->isHyp; 2617728SAli.Saidi@ARM.com 26210037SARM gem5 Developers bool long_desc_format = currState->aarch64 || 26310037SARM gem5 Developers (_haveLPAE && currState->ttbcr.eae) || 26410037SARM gem5 Developers _isHyp || isStage2; 26510037SARM gem5 Developers 26610037SARM gem5 Developers if (long_desc_format) { 26710037SARM gem5 Developers // Helper variables used for hierarchical permissions 26810037SARM gem5 Developers currState->secureLookup = currState->isSecure; 26910037SARM gem5 Developers currState->rwTable = true; 27010037SARM gem5 Developers currState->userTable = true; 27110037SARM gem5 Developers currState->xnTable = false; 27210037SARM gem5 Developers currState->pxnTable = false; 27310037SARM gem5 Developers } 27410037SARM gem5 Developers 27510037SARM gem5 Developers if (!currState->timing) { 27610109SGeoffrey.Blake@arm.com Fault fault = NoFault; 27710037SARM gem5 Developers if (currState->aarch64) 27810109SGeoffrey.Blake@arm.com fault = processWalkAArch64(); 27910037SARM gem5 Developers else if (long_desc_format) 28010109SGeoffrey.Blake@arm.com fault = processWalkLPAE(); 28110037SARM gem5 Developers else 28210109SGeoffrey.Blake@arm.com fault = processWalk(); 28310109SGeoffrey.Blake@arm.com 28410109SGeoffrey.Blake@arm.com // If this was a functional non-timing access restore state to 28510109SGeoffrey.Blake@arm.com // how we found it. 28610109SGeoffrey.Blake@arm.com if (currState->functional) { 28710109SGeoffrey.Blake@arm.com delete currState; 28810109SGeoffrey.Blake@arm.com currState = savedCurrState; 28910109SGeoffrey.Blake@arm.com } 29010109SGeoffrey.Blake@arm.com return fault; 29110037SARM gem5 Developers } 2927728SAli.Saidi@ARM.com 2938067SAli.Saidi@ARM.com if (pending || pendingQueue.size()) { 2947728SAli.Saidi@ARM.com pendingQueue.push_back(currState); 2957728SAli.Saidi@ARM.com currState = NULL; 2967728SAli.Saidi@ARM.com } else { 2977728SAli.Saidi@ARM.com pending = true; 29810037SARM gem5 Developers if (currState->aarch64) 29910037SARM gem5 Developers return processWalkAArch64(); 30010037SARM gem5 Developers else if (long_desc_format) 30110037SARM gem5 Developers return processWalkLPAE(); 30210037SARM gem5 Developers else 30310037SARM gem5 Developers return processWalk(); 3047728SAli.Saidi@ARM.com } 3057728SAli.Saidi@ARM.com 3067728SAli.Saidi@ARM.com return NoFault; 3077728SAli.Saidi@ARM.com} 3087728SAli.Saidi@ARM.com 3097728SAli.Saidi@ARM.comvoid 3107728SAli.Saidi@ARM.comTableWalker::processWalkWrapper() 3117728SAli.Saidi@ARM.com{ 3127728SAli.Saidi@ARM.com assert(!currState); 3137728SAli.Saidi@ARM.com assert(pendingQueue.size()); 3147728SAli.Saidi@ARM.com currState = pendingQueue.front(); 3159258SAli.Saidi@ARM.com 31610037SARM gem5 Developers ExceptionLevel target_el = EL0; 31710037SARM gem5 Developers if (currState->aarch64) 31810037SARM gem5 Developers target_el = currEL(currState->tc); 31910037SARM gem5 Developers else 32010037SARM gem5 Developers target_el = EL1; 32110037SARM gem5 Developers 3229535Smrinmoy.ghosh@arm.com // Check if a previous walk filled this request already 32310037SARM gem5 Developers // @TODO Should this always be the TLB or should we look in the stage2 TLB? 32410037SARM gem5 Developers TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 32510037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, false, 32610037SARM gem5 Developers target_el); 3279258SAli.Saidi@ARM.com 3289535Smrinmoy.ghosh@arm.com // Check if we still need to have a walk for this request. If the requesting 3299535Smrinmoy.ghosh@arm.com // instruction has been squashed, or a previous walk has filled the TLB with 3309535Smrinmoy.ghosh@arm.com // a match, we just want to get rid of the walk. The latter could happen 3319535Smrinmoy.ghosh@arm.com // when there are multiple outstanding misses to a single page and a 3329535Smrinmoy.ghosh@arm.com // previous request has been successfully translated. 3339535Smrinmoy.ghosh@arm.com if (!currState->transState->squashed() && !te) { 3349258SAli.Saidi@ARM.com // We've got a valid request, lets process it 3359258SAli.Saidi@ARM.com pending = true; 3369258SAli.Saidi@ARM.com pendingQueue.pop_front(); 33710037SARM gem5 Developers if (currState->aarch64) 33810037SARM gem5 Developers processWalkAArch64(); 33910037SARM gem5 Developers else if ((_haveLPAE && currState->ttbcr.eae) || currState->isHyp || isStage2) 34010037SARM gem5 Developers processWalkLPAE(); 34110037SARM gem5 Developers else 34210037SARM gem5 Developers processWalk(); 3439258SAli.Saidi@ARM.com return; 3449258SAli.Saidi@ARM.com } 3459258SAli.Saidi@ARM.com 3469258SAli.Saidi@ARM.com 3479258SAli.Saidi@ARM.com // If the instruction that we were translating for has been 3489258SAli.Saidi@ARM.com // squashed we shouldn't bother. 3499258SAli.Saidi@ARM.com unsigned num_squashed = 0; 3509258SAli.Saidi@ARM.com ThreadContext *tc = currState->tc; 3519258SAli.Saidi@ARM.com while ((num_squashed < numSquashable) && currState && 3529535Smrinmoy.ghosh@arm.com (currState->transState->squashed() || te)) { 3539258SAli.Saidi@ARM.com pendingQueue.pop_front(); 3549258SAli.Saidi@ARM.com num_squashed++; 3559258SAli.Saidi@ARM.com 35610037SARM gem5 Developers DPRINTF(TLB, "Squashing table walk for address %#x\n", 35710037SARM gem5 Developers currState->vaddr_tainted); 3589258SAli.Saidi@ARM.com 3599535Smrinmoy.ghosh@arm.com if (currState->transState->squashed()) { 3609535Smrinmoy.ghosh@arm.com // finish the translation which will delete the translation object 3619535Smrinmoy.ghosh@arm.com currState->transState->finish(new UnimpFault("Squashed Inst"), 3629535Smrinmoy.ghosh@arm.com currState->req, currState->tc, currState->mode); 3639535Smrinmoy.ghosh@arm.com } else { 3649535Smrinmoy.ghosh@arm.com // translate the request now that we know it will work 36510037SARM gem5 Developers tlb->translateTiming(currState->req, currState->tc, 36610037SARM gem5 Developers currState->transState, currState->mode); 36710037SARM gem5 Developers 3689535Smrinmoy.ghosh@arm.com } 3699258SAli.Saidi@ARM.com 3709258SAli.Saidi@ARM.com // delete the current request 3719258SAli.Saidi@ARM.com delete currState; 3729258SAli.Saidi@ARM.com 3739258SAli.Saidi@ARM.com // peak at the next one 3749535Smrinmoy.ghosh@arm.com if (pendingQueue.size()) { 3759258SAli.Saidi@ARM.com currState = pendingQueue.front(); 37610037SARM gem5 Developers te = tlb->lookup(currState->vaddr, currState->asid, 37710037SARM gem5 Developers currState->vmid, currState->isHyp, currState->isSecure, true, 37810037SARM gem5 Developers false, target_el); 3799535Smrinmoy.ghosh@arm.com } else { 3809535Smrinmoy.ghosh@arm.com // Terminate the loop, nothing more to do 3819258SAli.Saidi@ARM.com currState = NULL; 3829535Smrinmoy.ghosh@arm.com } 3839258SAli.Saidi@ARM.com } 3849258SAli.Saidi@ARM.com 3859258SAli.Saidi@ARM.com // if we've still got pending translations schedule more work 3869258SAli.Saidi@ARM.com nextWalk(tc); 3879258SAli.Saidi@ARM.com currState = NULL; 3889438SAndreas.Sandberg@ARM.com completeDrain(); 3897728SAli.Saidi@ARM.com} 3907728SAli.Saidi@ARM.com 3917728SAli.Saidi@ARM.comFault 3927728SAli.Saidi@ARM.comTableWalker::processWalk() 3937728SAli.Saidi@ARM.com{ 3947404SAli.Saidi@ARM.com Addr ttbr = 0; 3957404SAli.Saidi@ARM.com 3967404SAli.Saidi@ARM.com // If translation isn't enabled, we shouldn't be here 39710037SARM gem5 Developers assert(currState->sctlr.m || isStage2); 3987404SAli.Saidi@ARM.com 39910037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 40010037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 40110037SARM gem5 Developers 32 - currState->ttbcr.n)); 4027406SAli.Saidi@ARM.com 40310037SARM gem5 Developers if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, 40410037SARM gem5 Developers 32 - currState->ttbcr.n)) { 4057406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR0\n"); 40610037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 40710037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd0) { 40810037SARM gem5 Developers if (currState->isFetch) 40910037SARM gem5 Developers return new PrefetchAbort(currState->vaddr_tainted, 41010037SARM gem5 Developers ArmFault::TranslationLL + L1, 41110037SARM gem5 Developers isStage2, 41210037SARM gem5 Developers ArmFault::VmsaTran); 41310037SARM gem5 Developers else 41410037SARM gem5 Developers return new DataAbort(currState->vaddr_tainted, 41510037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 41610037SARM gem5 Developers ArmFault::TranslationLL + L1, isStage2, 41710037SARM gem5 Developers ArmFault::VmsaTran); 41810037SARM gem5 Developers } 41910037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 42010037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 4217404SAli.Saidi@ARM.com } else { 4227406SAli.Saidi@ARM.com DPRINTF(TLB, " - Selecting TTBR1\n"); 42310037SARM gem5 Developers // Check if table walk is allowed when Security Extensions are enabled 42410037SARM gem5 Developers if (haveSecurity && currState->ttbcr.pd1) { 42510037SARM gem5 Developers if (currState->isFetch) 42610037SARM gem5 Developers return new PrefetchAbort(currState->vaddr_tainted, 42710037SARM gem5 Developers ArmFault::TranslationLL + L1, 42810037SARM gem5 Developers isStage2, 42910037SARM gem5 Developers ArmFault::VmsaTran); 43010037SARM gem5 Developers else 43110037SARM gem5 Developers return new DataAbort(currState->vaddr_tainted, 43210037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 43310037SARM gem5 Developers ArmFault::TranslationLL + L1, isStage2, 43410037SARM gem5 Developers ArmFault::VmsaTran); 43510037SARM gem5 Developers } 43610037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 43710037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 43810037SARM gem5 Developers currState->ttbcr.n = 0; 4397404SAli.Saidi@ARM.com } 4407404SAli.Saidi@ARM.com 44110037SARM gem5 Developers Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 44210037SARM gem5 Developers (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); 44310037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, 44410037SARM gem5 Developers currState->isSecure ? "s" : "ns"); 4457404SAli.Saidi@ARM.com 4467404SAli.Saidi@ARM.com // Trickbox address check 4477439Sdam.sunwoo@arm.com Fault f; 44810037SARM gem5 Developers f = tlb->walkTrickBoxCheck(l1desc_addr, currState->isSecure, 44910037SARM gem5 Developers currState->vaddr, sizeof(uint32_t), currState->isFetch, 45010037SARM gem5 Developers currState->isWrite, TlbEntry::DomainType::NoAccess, L1); 4517439Sdam.sunwoo@arm.com if (f) { 45210037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 4537579Sminkyu.jeong@arm.com if (currState->timing) { 4547728SAli.Saidi@ARM.com pending = false; 4557728SAli.Saidi@ARM.com nextWalk(currState->tc); 4567579Sminkyu.jeong@arm.com currState = NULL; 4577579Sminkyu.jeong@arm.com } else { 4587579Sminkyu.jeong@arm.com currState->tc = NULL; 4597579Sminkyu.jeong@arm.com currState->req = NULL; 4607579Sminkyu.jeong@arm.com } 4617579Sminkyu.jeong@arm.com return f; 4627404SAli.Saidi@ARM.com } 4637404SAli.Saidi@ARM.com 4647946SGiacomo.Gabrielli@arm.com Request::Flags flag = 0; 4657946SGiacomo.Gabrielli@arm.com if (currState->sctlr.c == 0) { 4667946SGiacomo.Gabrielli@arm.com flag = Request::UNCACHEABLE; 4677946SGiacomo.Gabrielli@arm.com } 4687946SGiacomo.Gabrielli@arm.com 46910037SARM gem5 Developers bool delayed; 47010037SARM gem5 Developers delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data, 47110037SARM gem5 Developers sizeof(uint32_t), flag, L1, &doL1DescEvent, 47210037SARM gem5 Developers &TableWalker::doL1Descriptor); 47310037SARM gem5 Developers if (!delayed) { 47410037SARM gem5 Developers f = currState->fault; 47510037SARM gem5 Developers } 47610037SARM gem5 Developers 47710037SARM gem5 Developers return f; 47810037SARM gem5 Developers} 47910037SARM gem5 Developers 48010037SARM gem5 DevelopersFault 48110037SARM gem5 DevelopersTableWalker::processWalkLPAE() 48210037SARM gem5 Developers{ 48310037SARM gem5 Developers Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 48410037SARM gem5 Developers int tsz, n; 48510037SARM gem5 Developers LookupLevel start_lookup_level = L1; 48610037SARM gem5 Developers 48710037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n", 48810037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 48910037SARM gem5 Developers 49010037SARM gem5 Developers Request::Flags flag = 0; 49110037SARM gem5 Developers if (currState->isSecure) 49210037SARM gem5 Developers flag.set(Request::SECURE); 49310037SARM gem5 Developers 49410037SARM gem5 Developers // work out which base address register to use, if in hyp mode we always 49510037SARM gem5 Developers // use HTTBR 49610037SARM gem5 Developers if (isStage2) { 49710037SARM gem5 Developers DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n"); 49810037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_VTTBR); 49910037SARM gem5 Developers tsz = sext<4>(currState->vtcr.t0sz); 50010037SARM gem5 Developers start_lookup_level = currState->vtcr.sl0 ? L1 : L2; 50110037SARM gem5 Developers } else if (currState->isHyp) { 50210037SARM gem5 Developers DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n"); 50310037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_HTTBR); 50410037SARM gem5 Developers tsz = currState->htcr.t0sz; 50510037SARM gem5 Developers } else { 50610037SARM gem5 Developers assert(_haveLPAE && currState->ttbcr.eae); 50710037SARM gem5 Developers 50810037SARM gem5 Developers // Determine boundaries of TTBR0/1 regions 50910037SARM gem5 Developers if (currState->ttbcr.t0sz) 51010037SARM gem5 Developers ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1; 51110037SARM gem5 Developers else if (currState->ttbcr.t1sz) 51210037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 51310037SARM gem5 Developers (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 51410037SARM gem5 Developers else 51510037SARM gem5 Developers ttbr0_max = (1ULL << 32) - 1; 51610037SARM gem5 Developers if (currState->ttbcr.t1sz) 51710037SARM gem5 Developers ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 51810037SARM gem5 Developers else 51910037SARM gem5 Developers ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 52010037SARM gem5 Developers 52110037SARM gem5 Developers // The following code snippet selects the appropriate translation table base 52210037SARM gem5 Developers // address (TTBR0 or TTBR1) and the appropriate starting lookup level 52310037SARM gem5 Developers // depending on the address range supported by the translation table (ARM 52410037SARM gem5 Developers // ARM issue C B3.6.4) 52510037SARM gem5 Developers if (currState->vaddr <= ttbr0_max) { 52610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 52710037SARM gem5 Developers // Check if table walk is allowed 52810037SARM gem5 Developers if (currState->ttbcr.epd0) { 52910037SARM gem5 Developers if (currState->isFetch) 53010037SARM gem5 Developers return new PrefetchAbort(currState->vaddr_tainted, 53110037SARM gem5 Developers ArmFault::TranslationLL + L1, 53210037SARM gem5 Developers isStage2, 53310037SARM gem5 Developers ArmFault::LpaeTran); 53410037SARM gem5 Developers else 53510037SARM gem5 Developers return new DataAbort(currState->vaddr_tainted, 53610037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 53710037SARM gem5 Developers currState->isWrite, 53810037SARM gem5 Developers ArmFault::TranslationLL + L1, 53910037SARM gem5 Developers isStage2, 54010037SARM gem5 Developers ArmFault::LpaeTran); 54110037SARM gem5 Developers } 54210037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 54310037SARM gem5 Developers MISCREG_TTBR0, currState->tc, !currState->isSecure)); 54410037SARM gem5 Developers tsz = currState->ttbcr.t0sz; 54510037SARM gem5 Developers if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB 54610037SARM gem5 Developers start_lookup_level = L2; 54710037SARM gem5 Developers } else if (currState->vaddr >= ttbr1_min) { 54810037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n"); 54910037SARM gem5 Developers // Check if table walk is allowed 55010037SARM gem5 Developers if (currState->ttbcr.epd1) { 55110037SARM gem5 Developers if (currState->isFetch) 55210037SARM gem5 Developers return new PrefetchAbort(currState->vaddr_tainted, 55310037SARM gem5 Developers ArmFault::TranslationLL + L1, 55410037SARM gem5 Developers isStage2, 55510037SARM gem5 Developers ArmFault::LpaeTran); 55610037SARM gem5 Developers else 55710037SARM gem5 Developers return new DataAbort(currState->vaddr_tainted, 55810037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 55910037SARM gem5 Developers currState->isWrite, 56010037SARM gem5 Developers ArmFault::TranslationLL + L1, 56110037SARM gem5 Developers isStage2, 56210037SARM gem5 Developers ArmFault::LpaeTran); 56310037SARM gem5 Developers } 56410037SARM gem5 Developers ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked( 56510037SARM gem5 Developers MISCREG_TTBR1, currState->tc, !currState->isSecure)); 56610037SARM gem5 Developers tsz = currState->ttbcr.t1sz; 56710037SARM gem5 Developers if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB 56810037SARM gem5 Developers start_lookup_level = L2; 56910037SARM gem5 Developers } else { 57010037SARM gem5 Developers // Out of boundaries -> translation fault 57110037SARM gem5 Developers if (currState->isFetch) 57210037SARM gem5 Developers return new PrefetchAbort(currState->vaddr_tainted, 57310037SARM gem5 Developers ArmFault::TranslationLL + L1, 57410037SARM gem5 Developers isStage2, 57510037SARM gem5 Developers ArmFault::LpaeTran); 57610037SARM gem5 Developers else 57710037SARM gem5 Developers return new DataAbort(currState->vaddr_tainted, 57810037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 57910037SARM gem5 Developers currState->isWrite, ArmFault::TranslationLL + L1, 58010037SARM gem5 Developers isStage2, ArmFault::LpaeTran); 58110037SARM gem5 Developers } 58210037SARM gem5 Developers 58310037SARM gem5 Developers } 58410037SARM gem5 Developers 58510037SARM gem5 Developers // Perform lookup (ARM ARM issue C B3.6.6) 58610037SARM gem5 Developers if (start_lookup_level == L1) { 58710037SARM gem5 Developers n = 5 - tsz; 58810037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 58910037SARM gem5 Developers (bits(currState->vaddr, n + 26, 30) << 3); 59010037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 59110037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 59210037SARM gem5 Developers } else { 59310037SARM gem5 Developers // Skip first-level lookup 59410037SARM gem5 Developers n = (tsz >= 2 ? 14 - tsz : 12); 59510037SARM gem5 Developers desc_addr = mbits(ttbr, 39, n) | 59610037SARM gem5 Developers (bits(currState->vaddr, n + 17, 21) << 3); 59710037SARM gem5 Developers DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", 59810037SARM gem5 Developers desc_addr, currState->isSecure ? "s" : "ns"); 59910037SARM gem5 Developers } 60010037SARM gem5 Developers 60110037SARM gem5 Developers // Trickbox address check 60210037SARM gem5 Developers Fault f = tlb->walkTrickBoxCheck(desc_addr, currState->isSecure, 60310037SARM gem5 Developers currState->vaddr, sizeof(uint64_t), currState->isFetch, 60410037SARM gem5 Developers currState->isWrite, TlbEntry::DomainType::NoAccess, 60510037SARM gem5 Developers start_lookup_level); 60610037SARM gem5 Developers if (f) { 60710037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 60810037SARM gem5 Developers if (currState->timing) { 60910037SARM gem5 Developers pending = false; 61010037SARM gem5 Developers nextWalk(currState->tc); 61110037SARM gem5 Developers currState = NULL; 61210037SARM gem5 Developers } else { 61310037SARM gem5 Developers currState->tc = NULL; 61410037SARM gem5 Developers currState->req = NULL; 61510037SARM gem5 Developers } 61610037SARM gem5 Developers return f; 61710037SARM gem5 Developers } 61810037SARM gem5 Developers 61910037SARM gem5 Developers if (currState->sctlr.c == 0) { 62010037SARM gem5 Developers flag = Request::UNCACHEABLE; 62110037SARM gem5 Developers } 62210037SARM gem5 Developers 62310037SARM gem5 Developers if (currState->isSecure) 62410037SARM gem5 Developers flag.set(Request::SECURE); 62510037SARM gem5 Developers 62610037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 62710037SARM gem5 Developers currState->longDesc.aarch64 = false; 62810037SARM gem5 Developers currState->longDesc.largeGrain = false; 62910037SARM gem5 Developers currState->longDesc.grainSize = 12; 63010037SARM gem5 Developers 63110037SARM gem5 Developers Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent 63210037SARM gem5 Developers : (Event *) &doL2LongDescEvent; 63310037SARM gem5 Developers 63410037SARM gem5 Developers bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data, 63510037SARM gem5 Developers sizeof(uint64_t), flag, start_lookup_level, 63610037SARM gem5 Developers event, &TableWalker::doLongDescriptor); 63710037SARM gem5 Developers if (!delayed) { 63810037SARM gem5 Developers f = currState->fault; 63910037SARM gem5 Developers } 64010037SARM gem5 Developers 64110037SARM gem5 Developers return f; 64210037SARM gem5 Developers} 64310037SARM gem5 Developers 64410037SARM gem5 Developersunsigned 64510037SARM gem5 DevelopersTableWalker::adjustTableSizeAArch64(unsigned tsz) 64610037SARM gem5 Developers{ 64710037SARM gem5 Developers if (tsz < 25) 64810037SARM gem5 Developers return 25; 64910037SARM gem5 Developers if (tsz > 48) 65010037SARM gem5 Developers return 48; 65110037SARM gem5 Developers return tsz; 65210037SARM gem5 Developers} 65310037SARM gem5 Developers 65410037SARM gem5 Developersbool 65510037SARM gem5 DevelopersTableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 65610037SARM gem5 Developers{ 65710037SARM gem5 Developers return (currPhysAddrRange != MaxPhysAddrRange && 65810037SARM gem5 Developers bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange)); 65910037SARM gem5 Developers} 66010037SARM gem5 Developers 66110037SARM gem5 DevelopersFault 66210037SARM gem5 DevelopersTableWalker::processWalkAArch64() 66310037SARM gem5 Developers{ 66410037SARM gem5 Developers assert(currState->aarch64); 66510037SARM gem5 Developers 66610037SARM gem5 Developers DPRINTF(TLB, "Beginning table walk for address %#llx, TTBCR: %#llx\n", 66710037SARM gem5 Developers currState->vaddr_tainted, currState->ttbcr); 66810037SARM gem5 Developers 66910037SARM gem5 Developers // Determine TTBR, table size, granule size and phys. address range 67010037SARM gem5 Developers Addr ttbr = 0; 67110037SARM gem5 Developers int tsz = 0, ps = 0; 67210037SARM gem5 Developers bool large_grain = false; 67310037SARM gem5 Developers bool fault = false; 67410037SARM gem5 Developers switch (currState->el) { 67510037SARM gem5 Developers case EL0: 67610037SARM gem5 Developers case EL1: 67710037SARM gem5 Developers switch (bits(currState->vaddr, 63,48)) { 67810037SARM gem5 Developers case 0: 67910037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 68010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); 68110037SARM gem5 Developers tsz = adjustTableSizeAArch64(64 - currState->ttbcr.t0sz); 68210037SARM gem5 Developers large_grain = currState->ttbcr.tg0; 68310037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != 0x0 || 68410037SARM gem5 Developers currState->ttbcr.epd0) 68510037SARM gem5 Developers fault = true; 68610037SARM gem5 Developers break; 68710037SARM gem5 Developers case 0xffff: 68810037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); 68910037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); 69010037SARM gem5 Developers tsz = adjustTableSizeAArch64(64 - currState->ttbcr.t1sz); 69110037SARM gem5 Developers large_grain = currState->ttbcr.tg1; 69210037SARM gem5 Developers if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 69310037SARM gem5 Developers currState->ttbcr.epd1) 69410037SARM gem5 Developers fault = true; 69510037SARM gem5 Developers break; 69610037SARM gem5 Developers default: 69710037SARM gem5 Developers // top two bytes must be all 0s or all 1s, else invalid addr 69810037SARM gem5 Developers fault = true; 69910037SARM gem5 Developers } 70010037SARM gem5 Developers ps = currState->ttbcr.ips; 70110037SARM gem5 Developers break; 70210037SARM gem5 Developers case EL2: 70310037SARM gem5 Developers case EL3: 70410037SARM gem5 Developers switch(bits(currState->vaddr, 63,48)) { 70510037SARM gem5 Developers case 0: 70610037SARM gem5 Developers DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); 70710037SARM gem5 Developers if (currState->el == EL2) 70810037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2); 70910037SARM gem5 Developers else 71010037SARM gem5 Developers ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3); 71110037SARM gem5 Developers tsz = adjustTableSizeAArch64(64 - currState->ttbcr.t0sz); 71210037SARM gem5 Developers large_grain = currState->ttbcr.tg0; 71310037SARM gem5 Developers break; 71410037SARM gem5 Developers default: 71510037SARM gem5 Developers // invalid addr if top two bytes are not all 0s 71610037SARM gem5 Developers fault = true; 71710037SARM gem5 Developers } 71810037SARM gem5 Developers ps = currState->ttbcr.ps; 71910037SARM gem5 Developers break; 72010037SARM gem5 Developers } 72110037SARM gem5 Developers 72210037SARM gem5 Developers if (fault) { 72310037SARM gem5 Developers Fault f; 72410037SARM gem5 Developers if (currState->isFetch) 72510037SARM gem5 Developers f = new PrefetchAbort(currState->vaddr_tainted, 72610037SARM gem5 Developers ArmFault::TranslationLL + L0, isStage2, 72710037SARM gem5 Developers ArmFault::LpaeTran); 72810037SARM gem5 Developers else 72910037SARM gem5 Developers f = new DataAbort(currState->vaddr_tainted, 73010037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 73110037SARM gem5 Developers currState->isWrite, 73210037SARM gem5 Developers ArmFault::TranslationLL + L0, 73310037SARM gem5 Developers isStage2, ArmFault::LpaeTran); 73410037SARM gem5 Developers 73510037SARM gem5 Developers if (currState->timing) { 73610037SARM gem5 Developers pending = false; 73710037SARM gem5 Developers nextWalk(currState->tc); 73810037SARM gem5 Developers currState = NULL; 73910037SARM gem5 Developers } else { 74010037SARM gem5 Developers currState->tc = NULL; 74110037SARM gem5 Developers currState->req = NULL; 74210037SARM gem5 Developers } 74310037SARM gem5 Developers return f; 74410037SARM gem5 Developers 74510037SARM gem5 Developers } 74610037SARM gem5 Developers 74710037SARM gem5 Developers // Determine starting lookup level 74810037SARM gem5 Developers LookupLevel start_lookup_level; 74910037SARM gem5 Developers int grain_size, stride; 75010037SARM gem5 Developers if (large_grain) { // 64 KB granule 75110037SARM gem5 Developers grain_size = 16; 75210037SARM gem5 Developers stride = grain_size - 3; 75310037SARM gem5 Developers if (tsz > grain_size + 2 * stride) 75410037SARM gem5 Developers start_lookup_level = L1; 75510037SARM gem5 Developers else if (tsz > grain_size + stride) 75610037SARM gem5 Developers start_lookup_level = L2; 75710037SARM gem5 Developers else 75810037SARM gem5 Developers start_lookup_level = L3; 75910037SARM gem5 Developers } else { // 4 KB granule 76010037SARM gem5 Developers grain_size = 12; 76110037SARM gem5 Developers stride = grain_size - 3; 76210037SARM gem5 Developers if (tsz > grain_size + 3 * stride) 76310037SARM gem5 Developers start_lookup_level = L0; 76410037SARM gem5 Developers else if (tsz > grain_size + 2 * stride) 76510037SARM gem5 Developers start_lookup_level = L1; 76610037SARM gem5 Developers else 76710037SARM gem5 Developers start_lookup_level = L2; 76810037SARM gem5 Developers } 76910037SARM gem5 Developers 77010037SARM gem5 Developers // Determine table base address 77110037SARM gem5 Developers int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - 77210037SARM gem5 Developers grain_size; 77310037SARM gem5 Developers Addr base_addr = mbits(ttbr, 47, base_addr_lo); 77410037SARM gem5 Developers 77510037SARM gem5 Developers // Determine physical address size and raise an Address Size Fault if 77610037SARM gem5 Developers // necessary 77710037SARM gem5 Developers int pa_range = decodePhysAddrRange64(ps); 77810037SARM gem5 Developers // Clamp to lower limit 77910037SARM gem5 Developers if (pa_range > physAddrRange) 78010037SARM gem5 Developers currState->physAddrRange = physAddrRange; 78110037SARM gem5 Developers else 78210037SARM gem5 Developers currState->physAddrRange = pa_range; 78310037SARM gem5 Developers if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) { 78410037SARM gem5 Developers DPRINTF(TLB, "Address size fault before any lookup\n"); 78510037SARM gem5 Developers Fault f; 78610037SARM gem5 Developers if (currState->isFetch) 78710037SARM gem5 Developers f = new PrefetchAbort(currState->vaddr_tainted, 78810037SARM gem5 Developers ArmFault::AddressSizeLL + start_lookup_level, 78910037SARM gem5 Developers isStage2, 79010037SARM gem5 Developers ArmFault::LpaeTran); 79110037SARM gem5 Developers else 79210037SARM gem5 Developers f = new DataAbort(currState->vaddr_tainted, 79310037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 79410037SARM gem5 Developers currState->isWrite, 79510037SARM gem5 Developers ArmFault::AddressSizeLL + start_lookup_level, 79610037SARM gem5 Developers isStage2, 79710037SARM gem5 Developers ArmFault::LpaeTran); 79810037SARM gem5 Developers 79910037SARM gem5 Developers 80010037SARM gem5 Developers if (currState->timing) { 80110037SARM gem5 Developers pending = false; 80210037SARM gem5 Developers nextWalk(currState->tc); 80310037SARM gem5 Developers currState = NULL; 80410037SARM gem5 Developers } else { 80510037SARM gem5 Developers currState->tc = NULL; 80610037SARM gem5 Developers currState->req = NULL; 80710037SARM gem5 Developers } 80810037SARM gem5 Developers return f; 80910037SARM gem5 Developers 81010037SARM gem5 Developers } 81110037SARM gem5 Developers 81210037SARM gem5 Developers // Determine descriptor address 81310037SARM gem5 Developers Addr desc_addr = base_addr | 81410037SARM gem5 Developers (bits(currState->vaddr, tsz - 1, 81510037SARM gem5 Developers stride * (3 - start_lookup_level) + grain_size) << 3); 81610037SARM gem5 Developers 81710037SARM gem5 Developers // Trickbox address check 81810037SARM gem5 Developers Fault f = tlb->walkTrickBoxCheck(desc_addr, currState->isSecure, 81910037SARM gem5 Developers currState->vaddr, sizeof(uint64_t), currState->isFetch, 82010037SARM gem5 Developers currState->isWrite, TlbEntry::DomainType::NoAccess, 82110037SARM gem5 Developers start_lookup_level); 82210037SARM gem5 Developers if (f) { 82310037SARM gem5 Developers DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted); 82410037SARM gem5 Developers if (currState->timing) { 82510037SARM gem5 Developers pending = false; 82610037SARM gem5 Developers nextWalk(currState->tc); 82710037SARM gem5 Developers currState = NULL; 82810037SARM gem5 Developers } else { 82910037SARM gem5 Developers currState->tc = NULL; 83010037SARM gem5 Developers currState->req = NULL; 83110037SARM gem5 Developers } 83210037SARM gem5 Developers return f; 83310037SARM gem5 Developers } 83410037SARM gem5 Developers 83510037SARM gem5 Developers Request::Flags flag = 0; 83610037SARM gem5 Developers if (currState->sctlr.c == 0) { 83710037SARM gem5 Developers flag = Request::UNCACHEABLE; 83810037SARM gem5 Developers } 83910037SARM gem5 Developers 84010037SARM gem5 Developers currState->longDesc.lookupLevel = start_lookup_level; 84110037SARM gem5 Developers currState->longDesc.aarch64 = true; 84210037SARM gem5 Developers currState->longDesc.largeGrain = large_grain; 84310037SARM gem5 Developers currState->longDesc.grainSize = grain_size; 84410037SARM gem5 Developers 8457439Sdam.sunwoo@arm.com if (currState->timing) { 84610037SARM gem5 Developers Event *event; 84710037SARM gem5 Developers switch (start_lookup_level) { 84810037SARM gem5 Developers case L0: 84910037SARM gem5 Developers event = (Event *) &doL0LongDescEvent; 85010037SARM gem5 Developers break; 85110037SARM gem5 Developers case L1: 85210037SARM gem5 Developers event = (Event *) &doL1LongDescEvent; 85310037SARM gem5 Developers break; 85410037SARM gem5 Developers case L2: 85510037SARM gem5 Developers event = (Event *) &doL2LongDescEvent; 85610037SARM gem5 Developers break; 85710037SARM gem5 Developers case L3: 85810037SARM gem5 Developers event = (Event *) &doL3LongDescEvent; 85910037SARM gem5 Developers break; 86010037SARM gem5 Developers default: 86110037SARM gem5 Developers panic("Invalid table lookup level"); 86210037SARM gem5 Developers break; 86310037SARM gem5 Developers } 86410037SARM gem5 Developers port.dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), event, 86510037SARM gem5 Developers (uint8_t*) &currState->longDesc.data, 8669180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 86710037SARM gem5 Developers DPRINTF(TLBVerbose, 86810037SARM gem5 Developers "Adding to walker fifo: queue size before adding: %d\n", 86910037SARM gem5 Developers stateQueues[start_lookup_level].size()); 87010037SARM gem5 Developers stateQueues[start_lookup_level].push_back(currState); 8717439Sdam.sunwoo@arm.com currState = NULL; 8728733Sgeoffrey.blake@arm.com } else if (!currState->functional) { 87310037SARM gem5 Developers port.dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t), 87410037SARM gem5 Developers NULL, (uint8_t*) &currState->longDesc.data, 8759180Sandreas.hansson@arm.com currState->tc->getCpuPtr()->clockPeriod(), flag); 87610037SARM gem5 Developers doLongDescriptor(); 8777439Sdam.sunwoo@arm.com f = currState->fault; 8788733Sgeoffrey.blake@arm.com } else { 87910037SARM gem5 Developers RequestPtr req = new Request(desc_addr, sizeof(uint64_t), flag, 88010037SARM gem5 Developers masterId); 8818949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 88210037SARM gem5 Developers pkt->dataStatic((uint8_t*) &currState->longDesc.data); 8838851Sandreas.hansson@arm.com port.sendFunctional(pkt); 88410037SARM gem5 Developers doLongDescriptor(); 8858733Sgeoffrey.blake@arm.com delete req; 8868733Sgeoffrey.blake@arm.com delete pkt; 8878733Sgeoffrey.blake@arm.com f = currState->fault; 8887404SAli.Saidi@ARM.com } 8897404SAli.Saidi@ARM.com 8907439Sdam.sunwoo@arm.com return f; 8917404SAli.Saidi@ARM.com} 8927404SAli.Saidi@ARM.com 8937404SAli.Saidi@ARM.comvoid 8947439Sdam.sunwoo@arm.comTableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 8957439Sdam.sunwoo@arm.com uint8_t texcb, bool s) 8967404SAli.Saidi@ARM.com{ 8977439Sdam.sunwoo@arm.com // Note: tc and sctlr local variables are hiding tc and sctrl class 8987439Sdam.sunwoo@arm.com // variables 8997436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 9007436Sdam.sunwoo@arm.com te.shareable = false; // default value 9017582SAli.Saidi@arm.com te.nonCacheable = false; 90210037SARM gem5 Developers te.outerShareable = false; 9037439Sdam.sunwoo@arm.com if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { 9047404SAli.Saidi@ARM.com switch(texcb) { 9057436Sdam.sunwoo@arm.com case 0: // Stongly-ordered 9067404SAli.Saidi@ARM.com te.nonCacheable = true; 90710037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 9087436Sdam.sunwoo@arm.com te.shareable = true; 9097436Sdam.sunwoo@arm.com te.innerAttrs = 1; 9107436Sdam.sunwoo@arm.com te.outerAttrs = 0; 9117404SAli.Saidi@ARM.com break; 9127436Sdam.sunwoo@arm.com case 1: // Shareable Device 9137436Sdam.sunwoo@arm.com te.nonCacheable = true; 91410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 9157436Sdam.sunwoo@arm.com te.shareable = true; 9167436Sdam.sunwoo@arm.com te.innerAttrs = 3; 9177436Sdam.sunwoo@arm.com te.outerAttrs = 0; 9187436Sdam.sunwoo@arm.com break; 9197436Sdam.sunwoo@arm.com case 2: // Outer and Inner Write-Through, no Write-Allocate 92010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 9217436Sdam.sunwoo@arm.com te.shareable = s; 9227436Sdam.sunwoo@arm.com te.innerAttrs = 6; 9237436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 9247436Sdam.sunwoo@arm.com break; 9257436Sdam.sunwoo@arm.com case 3: // Outer and Inner Write-Back, no Write-Allocate 92610037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 9277436Sdam.sunwoo@arm.com te.shareable = s; 9287436Sdam.sunwoo@arm.com te.innerAttrs = 7; 9297436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 9307436Sdam.sunwoo@arm.com break; 9317436Sdam.sunwoo@arm.com case 4: // Outer and Inner Non-cacheable 9327436Sdam.sunwoo@arm.com te.nonCacheable = true; 93310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 9347436Sdam.sunwoo@arm.com te.shareable = s; 9357436Sdam.sunwoo@arm.com te.innerAttrs = 0; 9367436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 1, 0); 9377436Sdam.sunwoo@arm.com break; 9387436Sdam.sunwoo@arm.com case 5: // Reserved 9397439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 9407436Sdam.sunwoo@arm.com break; 9417436Sdam.sunwoo@arm.com case 6: // Implementation Defined 9427439Sdam.sunwoo@arm.com panic("Implementation-defined texcb value!\n"); 9437436Sdam.sunwoo@arm.com break; 9447436Sdam.sunwoo@arm.com case 7: // Outer and Inner Write-Back, Write-Allocate 94510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 9467436Sdam.sunwoo@arm.com te.shareable = s; 9477436Sdam.sunwoo@arm.com te.innerAttrs = 5; 9487436Sdam.sunwoo@arm.com te.outerAttrs = 1; 9497436Sdam.sunwoo@arm.com break; 9507436Sdam.sunwoo@arm.com case 8: // Non-shareable Device 9517436Sdam.sunwoo@arm.com te.nonCacheable = true; 95210037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 9537436Sdam.sunwoo@arm.com te.shareable = false; 9547436Sdam.sunwoo@arm.com te.innerAttrs = 3; 9557436Sdam.sunwoo@arm.com te.outerAttrs = 0; 9567436Sdam.sunwoo@arm.com break; 9577436Sdam.sunwoo@arm.com case 9 ... 15: // Reserved 9587439Sdam.sunwoo@arm.com panic("Reserved texcb value!\n"); 9597436Sdam.sunwoo@arm.com break; 9607436Sdam.sunwoo@arm.com case 16 ... 31: // Cacheable Memory 96110037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 9627436Sdam.sunwoo@arm.com te.shareable = s; 9637404SAli.Saidi@ARM.com if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 9647404SAli.Saidi@ARM.com te.nonCacheable = true; 9657436Sdam.sunwoo@arm.com te.innerAttrs = bits(texcb, 1, 0); 9667436Sdam.sunwoo@arm.com te.outerAttrs = bits(texcb, 3, 2); 9677404SAli.Saidi@ARM.com break; 9687436Sdam.sunwoo@arm.com default: 9697436Sdam.sunwoo@arm.com panic("More than 32 states for 5 bits?\n"); 9707404SAli.Saidi@ARM.com } 9717404SAli.Saidi@ARM.com } else { 9727438SAli.Saidi@ARM.com assert(tc); 97310037SARM gem5 Developers PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, 97410037SARM gem5 Developers currState->tc, !currState->isSecure)); 97510037SARM gem5 Developers NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, 97610037SARM gem5 Developers currState->tc, !currState->isSecure)); 9777436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); 9787582SAli.Saidi@arm.com uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; 9797404SAli.Saidi@ARM.com switch(bits(texcb, 2,0)) { 9807404SAli.Saidi@ARM.com case 0: 9817436Sdam.sunwoo@arm.com curr_tr = prrr.tr0; 9827436Sdam.sunwoo@arm.com curr_ir = nmrr.ir0; 9837436Sdam.sunwoo@arm.com curr_or = nmrr.or0; 98410037SARM gem5 Developers te.outerShareable = (prrr.nos0 == 0); 9857404SAli.Saidi@ARM.com break; 9867404SAli.Saidi@ARM.com case 1: 9877436Sdam.sunwoo@arm.com curr_tr = prrr.tr1; 9887436Sdam.sunwoo@arm.com curr_ir = nmrr.ir1; 9897436Sdam.sunwoo@arm.com curr_or = nmrr.or1; 99010037SARM gem5 Developers te.outerShareable = (prrr.nos1 == 0); 9917404SAli.Saidi@ARM.com break; 9927404SAli.Saidi@ARM.com case 2: 9937436Sdam.sunwoo@arm.com curr_tr = prrr.tr2; 9947436Sdam.sunwoo@arm.com curr_ir = nmrr.ir2; 9957436Sdam.sunwoo@arm.com curr_or = nmrr.or2; 99610037SARM gem5 Developers te.outerShareable = (prrr.nos2 == 0); 9977404SAli.Saidi@ARM.com break; 9987404SAli.Saidi@ARM.com case 3: 9997436Sdam.sunwoo@arm.com curr_tr = prrr.tr3; 10007436Sdam.sunwoo@arm.com curr_ir = nmrr.ir3; 10017436Sdam.sunwoo@arm.com curr_or = nmrr.or3; 100210037SARM gem5 Developers te.outerShareable = (prrr.nos3 == 0); 10037404SAli.Saidi@ARM.com break; 10047404SAli.Saidi@ARM.com case 4: 10057436Sdam.sunwoo@arm.com curr_tr = prrr.tr4; 10067436Sdam.sunwoo@arm.com curr_ir = nmrr.ir4; 10077436Sdam.sunwoo@arm.com curr_or = nmrr.or4; 100810037SARM gem5 Developers te.outerShareable = (prrr.nos4 == 0); 10097404SAli.Saidi@ARM.com break; 10107404SAli.Saidi@ARM.com case 5: 10117436Sdam.sunwoo@arm.com curr_tr = prrr.tr5; 10127436Sdam.sunwoo@arm.com curr_ir = nmrr.ir5; 10137436Sdam.sunwoo@arm.com curr_or = nmrr.or5; 101410037SARM gem5 Developers te.outerShareable = (prrr.nos5 == 0); 10157404SAli.Saidi@ARM.com break; 10167404SAli.Saidi@ARM.com case 6: 10177404SAli.Saidi@ARM.com panic("Imp defined type\n"); 10187404SAli.Saidi@ARM.com case 7: 10197436Sdam.sunwoo@arm.com curr_tr = prrr.tr7; 10207436Sdam.sunwoo@arm.com curr_ir = nmrr.ir7; 10217436Sdam.sunwoo@arm.com curr_or = nmrr.or7; 102210037SARM gem5 Developers te.outerShareable = (prrr.nos7 == 0); 10237404SAli.Saidi@ARM.com break; 10247404SAli.Saidi@ARM.com } 10257436Sdam.sunwoo@arm.com 10267436Sdam.sunwoo@arm.com switch(curr_tr) { 10277436Sdam.sunwoo@arm.com case 0: 10287436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "StronglyOrdered\n"); 102910037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 10307436Sdam.sunwoo@arm.com te.nonCacheable = true; 10317436Sdam.sunwoo@arm.com te.innerAttrs = 1; 10327436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10337436Sdam.sunwoo@arm.com te.shareable = true; 10347436Sdam.sunwoo@arm.com break; 10357436Sdam.sunwoo@arm.com case 1: 10367436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n", 10377436Sdam.sunwoo@arm.com prrr.ds1, prrr.ds0, s); 103810037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 10397436Sdam.sunwoo@arm.com te.nonCacheable = true; 10407436Sdam.sunwoo@arm.com te.innerAttrs = 3; 10417436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10427436Sdam.sunwoo@arm.com if (prrr.ds1 && s) 10437436Sdam.sunwoo@arm.com te.shareable = true; 10447436Sdam.sunwoo@arm.com if (prrr.ds0 && !s) 10457436Sdam.sunwoo@arm.com te.shareable = true; 10467436Sdam.sunwoo@arm.com break; 10477436Sdam.sunwoo@arm.com case 2: 10487436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 10497436Sdam.sunwoo@arm.com prrr.ns1, prrr.ns0, s); 105010037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 10517436Sdam.sunwoo@arm.com if (prrr.ns1 && s) 10527436Sdam.sunwoo@arm.com te.shareable = true; 10537436Sdam.sunwoo@arm.com if (prrr.ns0 && !s) 10547436Sdam.sunwoo@arm.com te.shareable = true; 10557436Sdam.sunwoo@arm.com break; 10567436Sdam.sunwoo@arm.com case 3: 10577436Sdam.sunwoo@arm.com panic("Reserved type"); 10587436Sdam.sunwoo@arm.com } 10597436Sdam.sunwoo@arm.com 106010037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Normal){ 10617436Sdam.sunwoo@arm.com switch(curr_ir) { 10627436Sdam.sunwoo@arm.com case 0: 10637436Sdam.sunwoo@arm.com te.nonCacheable = true; 10647436Sdam.sunwoo@arm.com te.innerAttrs = 0; 10657436Sdam.sunwoo@arm.com break; 10667436Sdam.sunwoo@arm.com case 1: 10677436Sdam.sunwoo@arm.com te.innerAttrs = 5; 10687436Sdam.sunwoo@arm.com break; 10697436Sdam.sunwoo@arm.com case 2: 10707436Sdam.sunwoo@arm.com te.innerAttrs = 6; 10717436Sdam.sunwoo@arm.com break; 10727436Sdam.sunwoo@arm.com case 3: 10737436Sdam.sunwoo@arm.com te.innerAttrs = 7; 10747436Sdam.sunwoo@arm.com break; 10757436Sdam.sunwoo@arm.com } 10767436Sdam.sunwoo@arm.com 10777436Sdam.sunwoo@arm.com switch(curr_or) { 10787436Sdam.sunwoo@arm.com case 0: 10797436Sdam.sunwoo@arm.com te.nonCacheable = true; 10807436Sdam.sunwoo@arm.com te.outerAttrs = 0; 10817436Sdam.sunwoo@arm.com break; 10827436Sdam.sunwoo@arm.com case 1: 10837436Sdam.sunwoo@arm.com te.outerAttrs = 1; 10847436Sdam.sunwoo@arm.com break; 10857436Sdam.sunwoo@arm.com case 2: 10867436Sdam.sunwoo@arm.com te.outerAttrs = 2; 10877436Sdam.sunwoo@arm.com break; 10887436Sdam.sunwoo@arm.com case 3: 10897436Sdam.sunwoo@arm.com te.outerAttrs = 3; 10907436Sdam.sunwoo@arm.com break; 10917436Sdam.sunwoo@arm.com } 10927436Sdam.sunwoo@arm.com } 10937404SAli.Saidi@ARM.com } 10947439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 10957439Sdam.sunwoo@arm.com outerAttrs: %d\n", 10967439Sdam.sunwoo@arm.com te.shareable, te.innerAttrs, te.outerAttrs); 109710037SARM gem5 Developers te.setAttributes(false); 109810037SARM gem5 Developers} 10997436Sdam.sunwoo@arm.com 110010037SARM gem5 Developersvoid 110110037SARM gem5 DevelopersTableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 110210037SARM gem5 Developers LongDescriptor &lDescriptor) 110310037SARM gem5 Developers{ 110410037SARM gem5 Developers assert(_haveLPAE); 11057436Sdam.sunwoo@arm.com 110610037SARM gem5 Developers uint8_t attr; 110710037SARM gem5 Developers uint8_t sh = lDescriptor.sh(); 110810037SARM gem5 Developers // Different format and source of attributes if this is a stage 2 110910037SARM gem5 Developers // translation 111010037SARM gem5 Developers if (isStage2) { 111110037SARM gem5 Developers attr = lDescriptor.memAttr(); 111210037SARM gem5 Developers uint8_t attr_3_2 = (attr >> 2) & 0x3; 111310037SARM gem5 Developers uint8_t attr_1_0 = attr & 0x3; 11147436Sdam.sunwoo@arm.com 111510037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh); 111610037SARM gem5 Developers 111710037SARM gem5 Developers if (attr_3_2 == 0) { 111810037SARM gem5 Developers te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered 111910037SARM gem5 Developers : TlbEntry::MemoryType::Device; 112010037SARM gem5 Developers te.outerAttrs = 0; 112110037SARM gem5 Developers te.innerAttrs = attr_1_0 == 0 ? 1 : 3; 112210037SARM gem5 Developers te.nonCacheable = true; 112310037SARM gem5 Developers } else { 112410037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 112510037SARM gem5 Developers te.outerAttrs = attr_3_2 == 1 ? 0 : 112610037SARM gem5 Developers attr_3_2 == 2 ? 2 : 1; 112710037SARM gem5 Developers te.innerAttrs = attr_1_0 == 1 ? 0 : 112810037SARM gem5 Developers attr_1_0 == 2 ? 6 : 5; 112910037SARM gem5 Developers te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1); 113010037SARM gem5 Developers } 113110037SARM gem5 Developers } else { 113210037SARM gem5 Developers uint8_t attrIndx = lDescriptor.attrIndx(); 113310037SARM gem5 Developers 113410037SARM gem5 Developers // LPAE always uses remapping of memory attributes, irrespective of the 113510037SARM gem5 Developers // value of SCTLR.TRE 113610037SARM gem5 Developers int reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; 113710037SARM gem5 Developers reg = flattenMiscRegNsBanked(reg, currState->tc, !currState->isSecure); 113810037SARM gem5 Developers uint32_t mair = currState->tc->readMiscReg(reg); 113910037SARM gem5 Developers attr = (mair >> (8 * (attrIndx % 4))) & 0xff; 114010037SARM gem5 Developers uint8_t attr_7_4 = bits(attr, 7, 4); 114110037SARM gem5 Developers uint8_t attr_3_0 = bits(attr, 3, 0); 114210037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr); 114310037SARM gem5 Developers 114410037SARM gem5 Developers // Note: the memory subsystem only cares about the 'cacheable' memory 114510037SARM gem5 Developers // attribute. The other attributes are only used to fill the PAR register 114610037SARM gem5 Developers // accordingly to provide the illusion of full support 114710037SARM gem5 Developers te.nonCacheable = false; 114810037SARM gem5 Developers 114910037SARM gem5 Developers switch (attr_7_4) { 115010037SARM gem5 Developers case 0x0: 115110037SARM gem5 Developers // Strongly-ordered or Device memory 115210037SARM gem5 Developers if (attr_3_0 == 0x0) 115310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::StronglyOrdered; 115410037SARM gem5 Developers else if (attr_3_0 == 0x4) 115510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Device; 115610037SARM gem5 Developers else 115710037SARM gem5 Developers panic("Unpredictable behavior\n"); 115810037SARM gem5 Developers te.nonCacheable = true; 115910037SARM gem5 Developers te.outerAttrs = 0; 116010037SARM gem5 Developers break; 116110037SARM gem5 Developers case 0x4: 116210037SARM gem5 Developers // Normal memory, Outer Non-cacheable 116310037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 116410037SARM gem5 Developers te.outerAttrs = 0; 116510037SARM gem5 Developers if (attr_3_0 == 0x4) 116610037SARM gem5 Developers // Inner Non-cacheable 116710037SARM gem5 Developers te.nonCacheable = true; 116810037SARM gem5 Developers else if (attr_3_0 < 0x8) 116910037SARM gem5 Developers panic("Unpredictable behavior\n"); 117010037SARM gem5 Developers break; 117110037SARM gem5 Developers case 0x8: 117210037SARM gem5 Developers case 0x9: 117310037SARM gem5 Developers case 0xa: 117410037SARM gem5 Developers case 0xb: 117510037SARM gem5 Developers case 0xc: 117610037SARM gem5 Developers case 0xd: 117710037SARM gem5 Developers case 0xe: 117810037SARM gem5 Developers case 0xf: 117910037SARM gem5 Developers if (attr_7_4 & 0x4) { 118010037SARM gem5 Developers te.outerAttrs = (attr_7_4 & 1) ? 1 : 3; 118110037SARM gem5 Developers } else { 118210037SARM gem5 Developers te.outerAttrs = 0x2; 118310037SARM gem5 Developers } 118410037SARM gem5 Developers // Normal memory, Outer Cacheable 118510037SARM gem5 Developers te.mtype = TlbEntry::MemoryType::Normal; 118610037SARM gem5 Developers if (attr_3_0 != 0x4 && attr_3_0 < 0x8) 118710037SARM gem5 Developers panic("Unpredictable behavior\n"); 118810037SARM gem5 Developers break; 118910037SARM gem5 Developers default: 119010037SARM gem5 Developers panic("Unpredictable behavior\n"); 119110037SARM gem5 Developers break; 119210037SARM gem5 Developers } 119310037SARM gem5 Developers 119410037SARM gem5 Developers switch (attr_3_0) { 119510037SARM gem5 Developers case 0x0: 119610037SARM gem5 Developers te.innerAttrs = 0x1; 119710037SARM gem5 Developers break; 119810037SARM gem5 Developers case 0x4: 119910037SARM gem5 Developers te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 120010037SARM gem5 Developers break; 120110037SARM gem5 Developers case 0x8: 120210037SARM gem5 Developers case 0x9: 120310037SARM gem5 Developers case 0xA: 120410037SARM gem5 Developers case 0xB: 120510037SARM gem5 Developers te.innerAttrs = 6; 120610037SARM gem5 Developers break; 120710037SARM gem5 Developers case 0xC: 120810037SARM gem5 Developers case 0xD: 120910037SARM gem5 Developers case 0xE: 121010037SARM gem5 Developers case 0xF: 121110037SARM gem5 Developers te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7; 121210037SARM gem5 Developers break; 121310037SARM gem5 Developers default: 121410037SARM gem5 Developers panic("Unpredictable behavior\n"); 121510037SARM gem5 Developers break; 121610037SARM gem5 Developers } 121710037SARM gem5 Developers } 121810037SARM gem5 Developers 121910037SARM gem5 Developers te.outerShareable = sh == 2; 122010037SARM gem5 Developers te.shareable = (sh & 0x2) ? true : false; 122110037SARM gem5 Developers te.setAttributes(true); 122210037SARM gem5 Developers te.attributes |= (uint64_t) attr << 56; 122310037SARM gem5 Developers} 122410037SARM gem5 Developers 122510037SARM gem5 Developersvoid 122610037SARM gem5 DevelopersTableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 122710037SARM gem5 Developers uint8_t sh) 122810037SARM gem5 Developers{ 122910037SARM gem5 Developers DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 123010037SARM gem5 Developers 123110037SARM gem5 Developers // Select MAIR 123210037SARM gem5 Developers uint64_t mair; 123310037SARM gem5 Developers switch (currState->el) { 123410037SARM gem5 Developers case EL0: 123510037SARM gem5 Developers case EL1: 123610037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL1); 123710037SARM gem5 Developers break; 123810037SARM gem5 Developers case EL2: 123910037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL2); 124010037SARM gem5 Developers break; 124110037SARM gem5 Developers case EL3: 124210037SARM gem5 Developers mair = tc->readMiscReg(MISCREG_MAIR_EL3); 124310037SARM gem5 Developers break; 124410037SARM gem5 Developers default: 124510037SARM gem5 Developers panic("Invalid exception level"); 124610037SARM gem5 Developers break; 124710037SARM gem5 Developers } 124810037SARM gem5 Developers 124910037SARM gem5 Developers // Select attributes 125010037SARM gem5 Developers uint8_t attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx); 125110037SARM gem5 Developers uint8_t attr_lo = bits(attr, 3, 0); 125210037SARM gem5 Developers uint8_t attr_hi = bits(attr, 7, 4); 125310037SARM gem5 Developers 125410037SARM gem5 Developers // Memory type 125510037SARM gem5 Developers te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 125610037SARM gem5 Developers 125710037SARM gem5 Developers // Cacheability 125810037SARM gem5 Developers te.nonCacheable = false; 125910037SARM gem5 Developers if (te.mtype == TlbEntry::MemoryType::Device || // Device memory 126010037SARM gem5 Developers attr_hi == 0x8 || // Normal memory, Outer Non-cacheable 126110037SARM gem5 Developers attr_lo == 0x8) { // Normal memory, Inner Non-cacheable 126210037SARM gem5 Developers te.nonCacheable = true; 126310037SARM gem5 Developers } 126410037SARM gem5 Developers 126510037SARM gem5 Developers te.shareable = sh == 2; 126610037SARM gem5 Developers te.outerShareable = (sh & 0x2) ? true : false; 126710037SARM gem5 Developers // Attributes formatted according to the 64-bit PAR 126810037SARM gem5 Developers te.attributes = ((uint64_t) attr << 56) | 126910037SARM gem5 Developers (1 << 11) | // LPAE bit 127010037SARM gem5 Developers (te.ns << 9) | // NS bit 127110037SARM gem5 Developers (sh << 7); 12727404SAli.Saidi@ARM.com} 12737404SAli.Saidi@ARM.com 12747404SAli.Saidi@ARM.comvoid 12757404SAli.Saidi@ARM.comTableWalker::doL1Descriptor() 12767404SAli.Saidi@ARM.com{ 127710037SARM gem5 Developers if (currState->fault != NoFault) { 127810037SARM gem5 Developers return; 127910037SARM gem5 Developers } 128010037SARM gem5 Developers 12817439Sdam.sunwoo@arm.com DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 128210037SARM gem5 Developers currState->vaddr_tainted, currState->l1Desc.data); 12837404SAli.Saidi@ARM.com TlbEntry te; 12847404SAli.Saidi@ARM.com 12857439Sdam.sunwoo@arm.com switch (currState->l1Desc.type()) { 12867404SAli.Saidi@ARM.com case L1Descriptor::Ignore: 12877404SAli.Saidi@ARM.com case L1Descriptor::Reserved: 12887946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 12897439Sdam.sunwoo@arm.com currState->tc = NULL; 12907439Sdam.sunwoo@arm.com currState->req = NULL; 12917437Sdam.sunwoo@arm.com } 12927406SAli.Saidi@ARM.com DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 12937439Sdam.sunwoo@arm.com if (currState->isFetch) 12947439Sdam.sunwoo@arm.com currState->fault = 129510037SARM gem5 Developers new PrefetchAbort(currState->vaddr_tainted, 129610037SARM gem5 Developers ArmFault::TranslationLL + L1, 129710037SARM gem5 Developers isStage2, 129810037SARM gem5 Developers ArmFault::VmsaTran); 12997406SAli.Saidi@ARM.com else 13007439Sdam.sunwoo@arm.com currState->fault = 130110037SARM gem5 Developers new DataAbort(currState->vaddr_tainted, 130210037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 130310037SARM gem5 Developers currState->isWrite, 130410037SARM gem5 Developers ArmFault::TranslationLL + L1, isStage2, 130510037SARM gem5 Developers ArmFault::VmsaTran); 13067404SAli.Saidi@ARM.com return; 13077404SAli.Saidi@ARM.com case L1Descriptor::Section: 13087439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 13097436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 13107436Sdam.sunwoo@arm.com * enabled if set, do l1.Desc.setAp0() instead of generating 13117436Sdam.sunwoo@arm.com * AccessFlag0 13127436Sdam.sunwoo@arm.com */ 13137436Sdam.sunwoo@arm.com 131410037SARM gem5 Developers currState->fault = new DataAbort(currState->vaddr_tainted, 131510037SARM gem5 Developers currState->l1Desc.domain(), 131610037SARM gem5 Developers currState->isWrite, 131710037SARM gem5 Developers ArmFault::AccessFlagLL + L1, 131810037SARM gem5 Developers isStage2, 131910037SARM gem5 Developers ArmFault::VmsaTran); 13207436Sdam.sunwoo@arm.com } 13217439Sdam.sunwoo@arm.com if (currState->l1Desc.supersection()) { 13227404SAli.Saidi@ARM.com panic("Haven't implemented supersections\n"); 13237404SAli.Saidi@ARM.com } 132410037SARM gem5 Developers insertTableEntry(currState->l1Desc, false); 132510037SARM gem5 Developers return; 132610037SARM gem5 Developers case L1Descriptor::PageTable: 132710037SARM gem5 Developers { 132810037SARM gem5 Developers Addr l2desc_addr; 132910037SARM gem5 Developers l2desc_addr = currState->l1Desc.l2Addr() | 133010037SARM gem5 Developers (bits(currState->vaddr, 19, 12) << 2); 133110037SARM gem5 Developers DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", 133210037SARM gem5 Developers l2desc_addr, currState->isSecure ? "s" : "ns"); 13337404SAli.Saidi@ARM.com 133410037SARM gem5 Developers // Trickbox address check 133510037SARM gem5 Developers currState->fault = tlb->walkTrickBoxCheck( 133610037SARM gem5 Developers l2desc_addr, currState->isSecure, currState->vaddr, 133710037SARM gem5 Developers sizeof(uint32_t), currState->isFetch, currState->isWrite, 133810037SARM gem5 Developers currState->l1Desc.domain(), L2); 13397404SAli.Saidi@ARM.com 134010037SARM gem5 Developers if (currState->fault) { 134110037SARM gem5 Developers if (!currState->timing) { 134210037SARM gem5 Developers currState->tc = NULL; 134310037SARM gem5 Developers currState->req = NULL; 134410037SARM gem5 Developers } 134510037SARM gem5 Developers return; 134610037SARM gem5 Developers } 134710037SARM gem5 Developers 134810037SARM gem5 Developers Request::Flags flag = 0; 134910037SARM gem5 Developers if (currState->isSecure) 135010037SARM gem5 Developers flag.set(Request::SECURE); 135110037SARM gem5 Developers 135210037SARM gem5 Developers bool delayed; 135310037SARM gem5 Developers delayed = fetchDescriptor(l2desc_addr, 135410037SARM gem5 Developers (uint8_t*)&currState->l2Desc.data, 135510037SARM gem5 Developers sizeof(uint32_t), flag, -1, &doL2DescEvent, 135610037SARM gem5 Developers &TableWalker::doL2Descriptor); 135710037SARM gem5 Developers if (delayed) { 135810037SARM gem5 Developers currState->delayed = true; 135910037SARM gem5 Developers } 136010037SARM gem5 Developers 136110037SARM gem5 Developers return; 136210037SARM gem5 Developers } 136310037SARM gem5 Developers default: 136410037SARM gem5 Developers panic("A new type in a 2 bit field?\n"); 136510037SARM gem5 Developers } 136610037SARM gem5 Developers} 136710037SARM gem5 Developers 136810037SARM gem5 Developersvoid 136910037SARM gem5 DevelopersTableWalker::doLongDescriptor() 137010037SARM gem5 Developers{ 137110037SARM gem5 Developers if (currState->fault != NoFault) { 137210037SARM gem5 Developers return; 137310037SARM gem5 Developers } 137410037SARM gem5 Developers 137510037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n", 137610037SARM gem5 Developers currState->longDesc.lookupLevel, currState->vaddr_tainted, 137710037SARM gem5 Developers currState->longDesc.data, 137810037SARM gem5 Developers currState->aarch64 ? "AArch64" : "long-desc."); 137910037SARM gem5 Developers 138010037SARM gem5 Developers if ((currState->longDesc.type() == LongDescriptor::Block) || 138110037SARM gem5 Developers (currState->longDesc.type() == LongDescriptor::Page)) { 138210037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, " 138310037SARM gem5 Developers "xn: %d, ap: %d, af: %d, type: %d\n", 138410037SARM gem5 Developers currState->longDesc.lookupLevel, 138510037SARM gem5 Developers currState->longDesc.data, 138610037SARM gem5 Developers currState->longDesc.pxn(), 138710037SARM gem5 Developers currState->longDesc.xn(), 138810037SARM gem5 Developers currState->longDesc.ap(), 138910037SARM gem5 Developers currState->longDesc.af(), 139010037SARM gem5 Developers currState->longDesc.type()); 139110037SARM gem5 Developers } else { 139210037SARM gem5 Developers DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n", 139310037SARM gem5 Developers currState->longDesc.lookupLevel, 139410037SARM gem5 Developers currState->longDesc.data, 139510037SARM gem5 Developers currState->longDesc.type()); 139610037SARM gem5 Developers } 139710037SARM gem5 Developers 139810037SARM gem5 Developers TlbEntry te; 139910037SARM gem5 Developers 140010037SARM gem5 Developers switch (currState->longDesc.type()) { 140110037SARM gem5 Developers case LongDescriptor::Invalid: 14027439Sdam.sunwoo@arm.com if (!currState->timing) { 14037439Sdam.sunwoo@arm.com currState->tc = NULL; 14047439Sdam.sunwoo@arm.com currState->req = NULL; 14057437Sdam.sunwoo@arm.com } 14067404SAli.Saidi@ARM.com 140710037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 140810037SARM gem5 Developers currState->longDesc.lookupLevel, 140910037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel); 141010037SARM gem5 Developers if (currState->isFetch) 141110037SARM gem5 Developers currState->fault = new PrefetchAbort( 141210037SARM gem5 Developers currState->vaddr_tainted, 141310037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 141410037SARM gem5 Developers isStage2, 141510037SARM gem5 Developers ArmFault::LpaeTran); 141610037SARM gem5 Developers else 141710037SARM gem5 Developers currState->fault = new DataAbort( 141810037SARM gem5 Developers currState->vaddr_tainted, 141910037SARM gem5 Developers TlbEntry::DomainType::NoAccess, 142010037SARM gem5 Developers currState->isWrite, 142110037SARM gem5 Developers ArmFault::TranslationLL + currState->longDesc.lookupLevel, 142210037SARM gem5 Developers isStage2, 142310037SARM gem5 Developers ArmFault::LpaeTran); 14247404SAli.Saidi@ARM.com return; 142510037SARM gem5 Developers case LongDescriptor::Block: 142610037SARM gem5 Developers case LongDescriptor::Page: 142710037SARM gem5 Developers { 142810037SARM gem5 Developers bool fault = false; 142910037SARM gem5 Developers bool aff = false; 143010037SARM gem5 Developers // Check for address size fault 143110037SARM gem5 Developers if (checkAddrSizeFaultAArch64( 143210037SARM gem5 Developers mbits(currState->longDesc.data, MaxPhysAddrRange - 1, 143310037SARM gem5 Developers currState->longDesc.offsetBits()), 143410037SARM gem5 Developers currState->physAddrRange)) { 143510037SARM gem5 Developers fault = true; 143610037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 143710037SARM gem5 Developers currState->longDesc.lookupLevel); 143810037SARM gem5 Developers // Check for access fault 143910037SARM gem5 Developers } else if (currState->longDesc.af() == 0) { 144010037SARM gem5 Developers fault = true; 144110037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Access Fault\n", 144210037SARM gem5 Developers currState->longDesc.lookupLevel); 144310037SARM gem5 Developers aff = true; 144410037SARM gem5 Developers } 144510037SARM gem5 Developers if (fault) { 144610037SARM gem5 Developers if (currState->isFetch) 144710037SARM gem5 Developers currState->fault = new PrefetchAbort( 144810037SARM gem5 Developers currState->vaddr_tainted, 144910037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 145010037SARM gem5 Developers currState->longDesc.lookupLevel, 145110037SARM gem5 Developers isStage2, 145210037SARM gem5 Developers ArmFault::LpaeTran); 145310037SARM gem5 Developers else 145410037SARM gem5 Developers currState->fault = new DataAbort( 145510037SARM gem5 Developers currState->vaddr_tainted, 145610037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 145710037SARM gem5 Developers (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) + 145810037SARM gem5 Developers currState->longDesc.lookupLevel, 145910037SARM gem5 Developers isStage2, 146010037SARM gem5 Developers ArmFault::LpaeTran); 146110037SARM gem5 Developers } else { 146210037SARM gem5 Developers insertTableEntry(currState->longDesc, true); 146310037SARM gem5 Developers } 146410037SARM gem5 Developers } 146510037SARM gem5 Developers return; 146610037SARM gem5 Developers case LongDescriptor::Table: 146710037SARM gem5 Developers { 146810037SARM gem5 Developers // Set hierarchical permission flags 146910037SARM gem5 Developers currState->secureLookup = currState->secureLookup && 147010037SARM gem5 Developers currState->longDesc.secureTable(); 147110037SARM gem5 Developers currState->rwTable = currState->rwTable && 147210037SARM gem5 Developers currState->longDesc.rwTable(); 147310037SARM gem5 Developers currState->userTable = currState->userTable && 147410037SARM gem5 Developers currState->longDesc.userTable(); 147510037SARM gem5 Developers currState->xnTable = currState->xnTable || 147610037SARM gem5 Developers currState->longDesc.xnTable(); 147710037SARM gem5 Developers currState->pxnTable = currState->pxnTable || 147810037SARM gem5 Developers currState->longDesc.pxnTable(); 14797404SAli.Saidi@ARM.com 148010037SARM gem5 Developers // Set up next level lookup 148110037SARM gem5 Developers Addr next_desc_addr = currState->longDesc.nextDescAddr( 148210037SARM gem5 Developers currState->vaddr); 14837439Sdam.sunwoo@arm.com 148410037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n", 148510037SARM gem5 Developers currState->longDesc.lookupLevel, 148610037SARM gem5 Developers currState->longDesc.lookupLevel + 1, 148710037SARM gem5 Developers next_desc_addr, 148810037SARM gem5 Developers currState->secureLookup ? "s" : "ns"); 148910037SARM gem5 Developers 149010037SARM gem5 Developers // Check for address size fault 149110037SARM gem5 Developers if (currState->aarch64 && checkAddrSizeFaultAArch64( 149210037SARM gem5 Developers next_desc_addr, currState->physAddrRange)) { 149310037SARM gem5 Developers DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n", 149410037SARM gem5 Developers currState->longDesc.lookupLevel); 149510037SARM gem5 Developers if (currState->isFetch) 149610037SARM gem5 Developers currState->fault = new PrefetchAbort( 149710037SARM gem5 Developers currState->vaddr_tainted, 149810037SARM gem5 Developers ArmFault::AddressSizeLL 149910037SARM gem5 Developers + currState->longDesc.lookupLevel, 150010037SARM gem5 Developers isStage2, 150110037SARM gem5 Developers ArmFault::LpaeTran); 150210037SARM gem5 Developers else 150310037SARM gem5 Developers currState->fault = new DataAbort( 150410037SARM gem5 Developers currState->vaddr_tainted, 150510037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 150610037SARM gem5 Developers ArmFault::AddressSizeLL 150710037SARM gem5 Developers + currState->longDesc.lookupLevel, 150810037SARM gem5 Developers isStage2, 150910037SARM gem5 Developers ArmFault::LpaeTran); 151010037SARM gem5 Developers return; 15117437Sdam.sunwoo@arm.com } 15127404SAli.Saidi@ARM.com 151310037SARM gem5 Developers // Trickbox address check 151410037SARM gem5 Developers currState->fault = tlb->walkTrickBoxCheck( 151510037SARM gem5 Developers next_desc_addr, currState->vaddr, 151610037SARM gem5 Developers currState->vaddr, sizeof(uint64_t), 151710037SARM gem5 Developers currState->isFetch, currState->isWrite, 151810037SARM gem5 Developers TlbEntry::DomainType::Client, 151910037SARM gem5 Developers toLookupLevel(currState->longDesc.lookupLevel +1)); 15207404SAli.Saidi@ARM.com 152110037SARM gem5 Developers if (currState->fault) { 152210037SARM gem5 Developers if (!currState->timing) { 152310037SARM gem5 Developers currState->tc = NULL; 152410037SARM gem5 Developers currState->req = NULL; 152510037SARM gem5 Developers } 152610037SARM gem5 Developers return; 152710037SARM gem5 Developers } 152810037SARM gem5 Developers 152910037SARM gem5 Developers Request::Flags flag = 0; 153010037SARM gem5 Developers if (currState->secureLookup) 153110037SARM gem5 Developers flag.set(Request::SECURE); 153210037SARM gem5 Developers 153310037SARM gem5 Developers currState->longDesc.lookupLevel = 153410037SARM gem5 Developers (LookupLevel) (currState->longDesc.lookupLevel + 1); 153510037SARM gem5 Developers Event *event = NULL; 153610037SARM gem5 Developers switch (currState->longDesc.lookupLevel) { 153710037SARM gem5 Developers case L1: 153810037SARM gem5 Developers assert(currState->aarch64); 153910037SARM gem5 Developers event = &doL1LongDescEvent; 154010037SARM gem5 Developers break; 154110037SARM gem5 Developers case L2: 154210037SARM gem5 Developers event = &doL2LongDescEvent; 154310037SARM gem5 Developers break; 154410037SARM gem5 Developers case L3: 154510037SARM gem5 Developers event = &doL3LongDescEvent; 154610037SARM gem5 Developers break; 154710037SARM gem5 Developers default: 154810037SARM gem5 Developers panic("Wrong lookup level in table walk\n"); 154910037SARM gem5 Developers break; 155010037SARM gem5 Developers } 155110037SARM gem5 Developers 155210037SARM gem5 Developers bool delayed; 155310037SARM gem5 Developers delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data, 155410037SARM gem5 Developers sizeof(uint64_t), flag, -1, event, 155510037SARM gem5 Developers &TableWalker::doLongDescriptor); 155610037SARM gem5 Developers if (delayed) { 155710037SARM gem5 Developers currState->delayed = true; 155810037SARM gem5 Developers } 15597404SAli.Saidi@ARM.com } 15607404SAli.Saidi@ARM.com return; 15617404SAli.Saidi@ARM.com default: 15627404SAli.Saidi@ARM.com panic("A new type in a 2 bit field?\n"); 15637404SAli.Saidi@ARM.com } 15647404SAli.Saidi@ARM.com} 15657404SAli.Saidi@ARM.com 15667404SAli.Saidi@ARM.comvoid 15677404SAli.Saidi@ARM.comTableWalker::doL2Descriptor() 15687404SAli.Saidi@ARM.com{ 156910037SARM gem5 Developers if (currState->fault != NoFault) { 157010037SARM gem5 Developers return; 157110037SARM gem5 Developers } 157210037SARM gem5 Developers 15737439Sdam.sunwoo@arm.com DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 157410037SARM gem5 Developers currState->vaddr_tainted, currState->l2Desc.data); 15757404SAli.Saidi@ARM.com TlbEntry te; 15767404SAli.Saidi@ARM.com 15777439Sdam.sunwoo@arm.com if (currState->l2Desc.invalid()) { 15787404SAli.Saidi@ARM.com DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 15797946SGiacomo.Gabrielli@arm.com if (!currState->timing) { 15807439Sdam.sunwoo@arm.com currState->tc = NULL; 15817439Sdam.sunwoo@arm.com currState->req = NULL; 15827437Sdam.sunwoo@arm.com } 15837439Sdam.sunwoo@arm.com if (currState->isFetch) 15847439Sdam.sunwoo@arm.com currState->fault = 158510037SARM gem5 Developers new PrefetchAbort(currState->vaddr_tainted, 158610037SARM gem5 Developers ArmFault::TranslationLL + L2, 158710037SARM gem5 Developers isStage2, 158810037SARM gem5 Developers ArmFault::VmsaTran); 15897406SAli.Saidi@ARM.com else 15907439Sdam.sunwoo@arm.com currState->fault = 159110037SARM gem5 Developers new DataAbort(currState->vaddr_tainted, currState->l1Desc.domain(), 159210037SARM gem5 Developers currState->isWrite, ArmFault::TranslationLL + L2, 159310037SARM gem5 Developers isStage2, 159410037SARM gem5 Developers ArmFault::VmsaTran); 15957404SAli.Saidi@ARM.com return; 15967404SAli.Saidi@ARM.com } 15977404SAli.Saidi@ARM.com 15987439Sdam.sunwoo@arm.com if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 15997436Sdam.sunwoo@arm.com /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 16007436Sdam.sunwoo@arm.com * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 16017436Sdam.sunwoo@arm.com */ 160210037SARM gem5 Developers DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 160310037SARM gem5 Developers currState->sctlr.afe, currState->l2Desc.ap()); 16047436Sdam.sunwoo@arm.com 16057439Sdam.sunwoo@arm.com currState->fault = 160610037SARM gem5 Developers new DataAbort(currState->vaddr_tainted, 160710037SARM gem5 Developers TlbEntry::DomainType::NoAccess, currState->isWrite, 160810037SARM gem5 Developers ArmFault::AccessFlagLL + L2, isStage2, 160910037SARM gem5 Developers ArmFault::VmsaTran); 16107436Sdam.sunwoo@arm.com } 16117436Sdam.sunwoo@arm.com 161210037SARM gem5 Developers insertTableEntry(currState->l2Desc, false); 16137437Sdam.sunwoo@arm.com} 16147437Sdam.sunwoo@arm.com 16157437Sdam.sunwoo@arm.comvoid 16167437Sdam.sunwoo@arm.comTableWalker::doL1DescriptorWrapper() 16177437Sdam.sunwoo@arm.com{ 161810037SARM gem5 Developers currState = stateQueues[L1].front(); 16197439Sdam.sunwoo@arm.com currState->delayed = false; 162010037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 162110037SARM gem5 Developers if (currState->stage2Tran) { 162210037SARM gem5 Developers delete currState->stage2Tran; 162310037SARM gem5 Developers currState->stage2Tran = NULL; 162410037SARM gem5 Developers } 162510037SARM gem5 Developers 16267437Sdam.sunwoo@arm.com 16277578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 16287578Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 16297578Sdam.sunwoo@arm.com 163010037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted); 16317437Sdam.sunwoo@arm.com doL1Descriptor(); 16327437Sdam.sunwoo@arm.com 163310037SARM gem5 Developers stateQueues[L1].pop_front(); 16349152Satgutier@umich.edu completeDrain(); 16357437Sdam.sunwoo@arm.com // Check if fault was generated 16367439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 16377439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 16387439Sdam.sunwoo@arm.com currState->tc, currState->mode); 16397437Sdam.sunwoo@arm.com 16407728SAli.Saidi@ARM.com pending = false; 16417728SAli.Saidi@ARM.com nextWalk(currState->tc); 16427728SAli.Saidi@ARM.com 16437439Sdam.sunwoo@arm.com currState->req = NULL; 16447439Sdam.sunwoo@arm.com currState->tc = NULL; 16457439Sdam.sunwoo@arm.com currState->delayed = false; 16468510SAli.Saidi@ARM.com delete currState; 16477437Sdam.sunwoo@arm.com } 16487439Sdam.sunwoo@arm.com else if (!currState->delayed) { 16497653Sgene.wu@arm.com // delay is not set so there is no L2 to do 165010037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 165110037SARM gem5 Developers if (!currState->doingStage2) { 165210037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 165310037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 165410037SARM gem5 Developers currState->transState, currState->mode); 165510037SARM gem5 Developers } 16567437Sdam.sunwoo@arm.com 16577728SAli.Saidi@ARM.com pending = false; 16587728SAli.Saidi@ARM.com nextWalk(currState->tc); 16597728SAli.Saidi@ARM.com 16607439Sdam.sunwoo@arm.com currState->req = NULL; 16617439Sdam.sunwoo@arm.com currState->tc = NULL; 16627439Sdam.sunwoo@arm.com currState->delayed = false; 16637653Sgene.wu@arm.com delete currState; 16647653Sgene.wu@arm.com } else { 16657653Sgene.wu@arm.com // need to do L2 descriptor 166610037SARM gem5 Developers stateQueues[L2].push_back(currState); 16677437Sdam.sunwoo@arm.com } 16687439Sdam.sunwoo@arm.com currState = NULL; 16697437Sdam.sunwoo@arm.com} 16707437Sdam.sunwoo@arm.com 16717437Sdam.sunwoo@arm.comvoid 16727437Sdam.sunwoo@arm.comTableWalker::doL2DescriptorWrapper() 16737437Sdam.sunwoo@arm.com{ 167410037SARM gem5 Developers currState = stateQueues[L2].front(); 16757439Sdam.sunwoo@arm.com assert(currState->delayed); 167610037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 167710037SARM gem5 Developers if (currState->stage2Tran) { 167810037SARM gem5 Developers delete currState->stage2Tran; 167910037SARM gem5 Developers currState->stage2Tran = NULL; 168010037SARM gem5 Developers } 16817437Sdam.sunwoo@arm.com 16827439Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 168310037SARM gem5 Developers currState->vaddr_tainted); 16847437Sdam.sunwoo@arm.com doL2Descriptor(); 16857437Sdam.sunwoo@arm.com 16867437Sdam.sunwoo@arm.com // Check if fault was generated 16877439Sdam.sunwoo@arm.com if (currState->fault != NoFault) { 16887439Sdam.sunwoo@arm.com currState->transState->finish(currState->fault, currState->req, 16897439Sdam.sunwoo@arm.com currState->tc, currState->mode); 16907437Sdam.sunwoo@arm.com } 16917437Sdam.sunwoo@arm.com else { 169210037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 169310037SARM gem5 Developers if (!currState->doingStage2) { 169410037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 169510037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, 169610037SARM gem5 Developers currState->tc, currState->transState, currState->mode); 169710037SARM gem5 Developers } 16987437Sdam.sunwoo@arm.com } 16997437Sdam.sunwoo@arm.com 17007728SAli.Saidi@ARM.com 170110037SARM gem5 Developers stateQueues[L2].pop_front(); 17029152Satgutier@umich.edu completeDrain(); 17037728SAli.Saidi@ARM.com pending = false; 17047728SAli.Saidi@ARM.com nextWalk(currState->tc); 17057728SAli.Saidi@ARM.com 17067439Sdam.sunwoo@arm.com currState->req = NULL; 17077439Sdam.sunwoo@arm.com currState->tc = NULL; 17087439Sdam.sunwoo@arm.com currState->delayed = false; 17097439Sdam.sunwoo@arm.com 17107653Sgene.wu@arm.com delete currState; 17117439Sdam.sunwoo@arm.com currState = NULL; 17127404SAli.Saidi@ARM.com} 17137404SAli.Saidi@ARM.com 17147728SAli.Saidi@ARM.comvoid 171510037SARM gem5 DevelopersTableWalker::doL0LongDescriptorWrapper() 171610037SARM gem5 Developers{ 171710037SARM gem5 Developers doLongDescriptorWrapper(L0); 171810037SARM gem5 Developers} 171910037SARM gem5 Developers 172010037SARM gem5 Developersvoid 172110037SARM gem5 DevelopersTableWalker::doL1LongDescriptorWrapper() 172210037SARM gem5 Developers{ 172310037SARM gem5 Developers doLongDescriptorWrapper(L1); 172410037SARM gem5 Developers} 172510037SARM gem5 Developers 172610037SARM gem5 Developersvoid 172710037SARM gem5 DevelopersTableWalker::doL2LongDescriptorWrapper() 172810037SARM gem5 Developers{ 172910037SARM gem5 Developers doLongDescriptorWrapper(L2); 173010037SARM gem5 Developers} 173110037SARM gem5 Developers 173210037SARM gem5 Developersvoid 173310037SARM gem5 DevelopersTableWalker::doL3LongDescriptorWrapper() 173410037SARM gem5 Developers{ 173510037SARM gem5 Developers doLongDescriptorWrapper(L3); 173610037SARM gem5 Developers} 173710037SARM gem5 Developers 173810037SARM gem5 Developersvoid 173910037SARM gem5 DevelopersTableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level) 174010037SARM gem5 Developers{ 174110037SARM gem5 Developers currState = stateQueues[curr_lookup_level].front(); 174210037SARM gem5 Developers assert(curr_lookup_level == currState->longDesc.lookupLevel); 174310037SARM gem5 Developers currState->delayed = false; 174410037SARM gem5 Developers 174510037SARM gem5 Developers // if there's a stage2 translation object we don't need it any more 174610037SARM gem5 Developers if (currState->stage2Tran) { 174710037SARM gem5 Developers delete currState->stage2Tran; 174810037SARM gem5 Developers currState->stage2Tran = NULL; 174910037SARM gem5 Developers } 175010037SARM gem5 Developers 175110037SARM gem5 Developers DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n", 175210037SARM gem5 Developers currState->vaddr_tainted); 175310037SARM gem5 Developers doLongDescriptor(); 175410037SARM gem5 Developers 175510037SARM gem5 Developers stateQueues[curr_lookup_level].pop_front(); 175610037SARM gem5 Developers 175710037SARM gem5 Developers if (currState->fault != NoFault) { 175810037SARM gem5 Developers // A fault was generated 175910037SARM gem5 Developers currState->transState->finish(currState->fault, currState->req, 176010037SARM gem5 Developers currState->tc, currState->mode); 176110037SARM gem5 Developers 176210037SARM gem5 Developers pending = false; 176310037SARM gem5 Developers nextWalk(currState->tc); 176410037SARM gem5 Developers 176510037SARM gem5 Developers currState->req = NULL; 176610037SARM gem5 Developers currState->tc = NULL; 176710037SARM gem5 Developers currState->delayed = false; 176810037SARM gem5 Developers delete currState; 176910037SARM gem5 Developers } else if (!currState->delayed) { 177010037SARM gem5 Developers // No additional lookups required 177110037SARM gem5 Developers // Don't finish the translation if a stage 2 look up is underway 177210037SARM gem5 Developers if (!currState->doingStage2) { 177310037SARM gem5 Developers DPRINTF(TLBVerbose, "calling translateTiming again\n"); 177410037SARM gem5 Developers currState->fault = tlb->translateTiming(currState->req, currState->tc, 177510037SARM gem5 Developers currState->transState, 177610037SARM gem5 Developers currState->mode); 177710037SARM gem5 Developers } 177810037SARM gem5 Developers 177910037SARM gem5 Developers pending = false; 178010037SARM gem5 Developers nextWalk(currState->tc); 178110037SARM gem5 Developers 178210037SARM gem5 Developers currState->req = NULL; 178310037SARM gem5 Developers currState->tc = NULL; 178410037SARM gem5 Developers currState->delayed = false; 178510037SARM gem5 Developers delete currState; 178610037SARM gem5 Developers } else { 178710037SARM gem5 Developers if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1) 178810037SARM gem5 Developers panic("Max. number of lookups already reached in table walk\n"); 178910037SARM gem5 Developers // Need to perform additional lookups 179010037SARM gem5 Developers stateQueues[currState->longDesc.lookupLevel].push_back(currState); 179110037SARM gem5 Developers } 179210037SARM gem5 Developers currState = NULL; 179310037SARM gem5 Developers} 179410037SARM gem5 Developers 179510037SARM gem5 Developers 179610037SARM gem5 Developersvoid 17977728SAli.Saidi@ARM.comTableWalker::nextWalk(ThreadContext *tc) 17987728SAli.Saidi@ARM.com{ 17997728SAli.Saidi@ARM.com if (pendingQueue.size()) 18009309Sandreas.hansson@arm.com schedule(doProcessEvent, clockEdge(Cycles(1))); 18017728SAli.Saidi@ARM.com} 18027728SAli.Saidi@ARM.com 180310037SARM gem5 Developersbool 180410037SARM gem5 DevelopersTableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 180510037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 180610037SARM gem5 Developers void (TableWalker::*doDescriptor)()) 180710037SARM gem5 Developers{ 180810037SARM gem5 Developers bool isTiming = currState->timing; 18097728SAli.Saidi@ARM.com 181010037SARM gem5 Developers // do the requests for the page table descriptors have to go through the 181110037SARM gem5 Developers // second stage MMU 181210037SARM gem5 Developers if (currState->stage2Req) { 181310037SARM gem5 Developers Fault fault; 181410037SARM gem5 Developers flags = flags | TLB::MustBeOne; 181510037SARM gem5 Developers 181610037SARM gem5 Developers if (isTiming) { 181710037SARM gem5 Developers Stage2MMU::Stage2Translation *tran = new 181810037SARM gem5 Developers Stage2MMU::Stage2Translation(*stage2Mmu, data, event, 181910037SARM gem5 Developers currState->vaddr); 182010037SARM gem5 Developers currState->stage2Tran = tran; 182110037SARM gem5 Developers stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 182210037SARM gem5 Developers flags, masterId); 182310037SARM gem5 Developers fault = tran->fault; 182410037SARM gem5 Developers } else { 182510037SARM gem5 Developers fault = stage2Mmu->readDataUntimed(currState->tc, 182610037SARM gem5 Developers currState->vaddr, descAddr, data, numBytes, flags, masterId, 182710037SARM gem5 Developers currState->functional); 182810037SARM gem5 Developers } 182910037SARM gem5 Developers 183010037SARM gem5 Developers if (fault != NoFault) { 183110037SARM gem5 Developers currState->fault = fault; 183210037SARM gem5 Developers } 183310037SARM gem5 Developers if (isTiming) { 183410037SARM gem5 Developers if (queueIndex >= 0) { 183510037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 183610037SARM gem5 Developers stateQueues[queueIndex].size()); 183710037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 183810037SARM gem5 Developers currState = NULL; 183910037SARM gem5 Developers } 184010037SARM gem5 Developers } else { 184110037SARM gem5 Developers (this->*doDescriptor)(); 184210037SARM gem5 Developers } 184310037SARM gem5 Developers } else { 184410037SARM gem5 Developers if (isTiming) { 184510037SARM gem5 Developers port.dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 184610037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 184710037SARM gem5 Developers if (queueIndex >= 0) { 184810037SARM gem5 Developers DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 184910037SARM gem5 Developers stateQueues[queueIndex].size()); 185010037SARM gem5 Developers stateQueues[queueIndex].push_back(currState); 185110037SARM gem5 Developers currState = NULL; 185210037SARM gem5 Developers } 185310037SARM gem5 Developers } else if (!currState->functional) { 185410037SARM gem5 Developers port.dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 185510037SARM gem5 Developers currState->tc->getCpuPtr()->clockPeriod(), flags); 185610037SARM gem5 Developers (this->*doDescriptor)(); 185710037SARM gem5 Developers } else { 185810037SARM gem5 Developers RequestPtr req = new Request(descAddr, numBytes, flags, masterId); 185910037SARM gem5 Developers req->taskId(ContextSwitchTaskId::DMA); 186010037SARM gem5 Developers PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 186110037SARM gem5 Developers pkt->dataStatic(data); 186210037SARM gem5 Developers port.sendFunctional(pkt); 186310037SARM gem5 Developers (this->*doDescriptor)(); 186410037SARM gem5 Developers delete req; 186510037SARM gem5 Developers delete pkt; 186610037SARM gem5 Developers } 186710037SARM gem5 Developers } 186810037SARM gem5 Developers return (isTiming); 186910037SARM gem5 Developers} 187010037SARM gem5 Developers 187110037SARM gem5 Developersvoid 187210037SARM gem5 DevelopersTableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) 187310037SARM gem5 Developers{ 187410037SARM gem5 Developers TlbEntry te; 187510037SARM gem5 Developers 187610037SARM gem5 Developers // Create and fill a new page table entry 187710037SARM gem5 Developers te.valid = true; 187810037SARM gem5 Developers te.longDescFormat = longDescriptor; 187910037SARM gem5 Developers te.isHyp = currState->isHyp; 188010037SARM gem5 Developers te.asid = currState->asid; 188110037SARM gem5 Developers te.vmid = currState->vmid; 188210037SARM gem5 Developers te.N = descriptor.offsetBits(); 188310037SARM gem5 Developers te.vpn = currState->vaddr >> te.N; 188410037SARM gem5 Developers te.size = (1<<te.N) - 1; 188510037SARM gem5 Developers te.pfn = descriptor.pfn(); 188610037SARM gem5 Developers te.domain = descriptor.domain(); 188710037SARM gem5 Developers te.lookupLevel = descriptor.lookupLevel; 188810037SARM gem5 Developers te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 188910037SARM gem5 Developers te.nstid = !currState->isSecure; 189010037SARM gem5 Developers te.xn = descriptor.xn(); 189110037SARM gem5 Developers if (currState->aarch64) 189210037SARM gem5 Developers te.el = currState->el; 189310037SARM gem5 Developers else 189410037SARM gem5 Developers te.el = 1; 189510037SARM gem5 Developers 189610037SARM gem5 Developers // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries 189710037SARM gem5 Developers // as global 189810037SARM gem5 Developers te.global = descriptor.global(currState) || isStage2; 189910037SARM gem5 Developers if (longDescriptor) { 190010037SARM gem5 Developers LongDescriptor lDescriptor = 190110037SARM gem5 Developers dynamic_cast<LongDescriptor &>(descriptor); 190210037SARM gem5 Developers 190310037SARM gem5 Developers te.xn |= currState->xnTable; 190410037SARM gem5 Developers te.pxn = currState->pxnTable || lDescriptor.pxn(); 190510037SARM gem5 Developers if (isStage2) { 190610037SARM gem5 Developers // this is actually the HAP field, but its stored in the same bit 190710037SARM gem5 Developers // possitions as the AP field in a stage 1 translation. 190810037SARM gem5 Developers te.hap = lDescriptor.ap(); 190910037SARM gem5 Developers } else { 191010037SARM gem5 Developers te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) | 191110037SARM gem5 Developers (currState->userTable && (descriptor.ap() & 0x1)); 191210037SARM gem5 Developers } 191310037SARM gem5 Developers if (currState->aarch64) 191410037SARM gem5 Developers memAttrsAArch64(currState->tc, te, currState->longDesc.attrIndx(), 191510037SARM gem5 Developers currState->longDesc.sh()); 191610037SARM gem5 Developers else 191710037SARM gem5 Developers memAttrsLPAE(currState->tc, te, lDescriptor); 191810037SARM gem5 Developers } else { 191910037SARM gem5 Developers te.ap = descriptor.ap(); 192010037SARM gem5 Developers memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(), 192110037SARM gem5 Developers descriptor.shareable()); 192210037SARM gem5 Developers } 192310037SARM gem5 Developers 192410037SARM gem5 Developers // Debug output 192510037SARM gem5 Developers DPRINTF(TLB, descriptor.dbgHeader().c_str()); 192610037SARM gem5 Developers DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n", 192710037SARM gem5 Developers te.N, te.pfn, te.size, te.global, te.valid); 192810037SARM gem5 Developers DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d " 192910037SARM gem5 Developers "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn, 193010037SARM gem5 Developers te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp, 193110037SARM gem5 Developers te.nonCacheable, te.ns); 193210037SARM gem5 Developers DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n", 193310037SARM gem5 Developers descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()), 193410037SARM gem5 Developers descriptor.getRawData()); 193510037SARM gem5 Developers 193610037SARM gem5 Developers // Insert the entry into the TLB 193710037SARM gem5 Developers tlb->insert(currState->vaddr, te); 193810037SARM gem5 Developers if (!currState->timing) { 193910037SARM gem5 Developers currState->tc = NULL; 194010037SARM gem5 Developers currState->req = NULL; 194110037SARM gem5 Developers } 194210037SARM gem5 Developers} 19437728SAli.Saidi@ARM.com 19447404SAli.Saidi@ARM.comArmISA::TableWalker * 19457404SAli.Saidi@ARM.comArmTableWalkerParams::create() 19467404SAli.Saidi@ARM.com{ 19477404SAli.Saidi@ARM.com return new ArmISA::TableWalker(this); 19487404SAli.Saidi@ARM.com} 19497404SAli.Saidi@ARM.com 195010037SARM gem5 DevelopersLookupLevel 195110037SARM gem5 DevelopersTableWalker::toLookupLevel(uint8_t lookup_level_as_int) 195210037SARM gem5 Developers{ 195310037SARM gem5 Developers switch (lookup_level_as_int) { 195410037SARM gem5 Developers case L1: 195510037SARM gem5 Developers return L1; 195610037SARM gem5 Developers case L2: 195710037SARM gem5 Developers return L2; 195810037SARM gem5 Developers case L3: 195910037SARM gem5 Developers return L3; 196010037SARM gem5 Developers default: 196110037SARM gem5 Developers panic("Invalid lookup level conversion"); 196210037SARM gem5 Developers } 196310037SARM gem5 Developers} 1964