system.hh revision 13759:9941fca869a9 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class BaseGic;
58class ThreadContext;
59
60class ArmSystem : public System
61{
62  protected:
63    /**
64     * PC based event to skip the dprink() call and emulate its
65     * functionality
66     */
67    Linux::DebugPrintkEvent *debugPrintkEvent;
68
69    /** Bootloaders */
70    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
71
72    /**
73     * Pointer to the bootloader object
74     */
75    ObjectFile *bootldr;
76
77    /**
78     * True if this system implements the Security Extensions
79     */
80    const bool _haveSecurity;
81
82    /**
83     * True if this system implements the Large Physical Address Extension
84     */
85    const bool _haveLPAE;
86
87    /**
88     * True if this system implements the virtualization Extensions
89     */
90    const bool _haveVirtualization;
91
92    /**
93     * True if this system implements the Crypto Extension
94     */
95    const bool _haveCrypto;
96
97    /**
98     * Pointer to the Generic Timer wrapper.
99     */
100    GenericTimer *_genericTimer;
101    BaseGic *_gic;
102
103    /**
104     * Reset address (ARMv8)
105     */
106    const Addr _resetAddr;
107
108    /**
109     * True if the register width of the highest implemented exception level is
110     * 64 bits (ARMv8)
111     */
112    bool _highestELIs64;
113
114    /**
115     * Supported physical address range in bits if the highest implemented
116     * exception level is 64 bits (ARMv8)
117     */
118    const uint8_t _physAddrRange64;
119
120    /**
121     * True if ASID is 16 bits in AArch64 (ARMv8)
122     */
123    const bool _haveLargeAsid64;
124
125    /**
126     * True if SVE is implemented (ARMv8)
127     */
128    const bool _haveSVE;
129
130    /** SVE vector length at reset, in quadwords */
131    const unsigned _sveVL;
132
133    /**
134     * Range for memory-mapped m5 pseudo ops. The range will be
135     * invalid/empty if disabled.
136     */
137    const AddrRange _m5opRange;
138
139    /**
140     * True if the Semihosting interface is enabled.
141     */
142    ArmSemihosting *const semihosting;
143
144  protected:
145    /**
146     * Get a boot loader that matches the kernel.
147     *
148     * @param obj Kernel binary
149     * @return Pointer to boot loader ObjectFile or nullptr if there
150     *         is no matching boot loader.
151     */
152    ObjectFile *getBootLoader(ObjectFile *const obj);
153
154  public:
155    typedef ArmSystemParams Params;
156    const Params *
157    params() const
158    {
159        return dynamic_cast<const Params *>(_params);
160    }
161
162    ArmSystem(Params *p);
163    ~ArmSystem();
164
165    /**
166     * Initialise the system
167     */
168    virtual void initState();
169
170    virtual Addr fixFuncEventAddr(Addr addr)
171    {
172        // Remove the low bit that thumb symbols have set
173        // but that aren't actually odd aligned
174        if (addr & 0x1)
175            return addr & ~1;
176        return addr;
177    }
178
179    /** true if this a multiprocessor system */
180    bool multiProc;
181
182    /** Returns true if this system implements the Security Extensions */
183    bool haveSecurity() const { return _haveSecurity; }
184
185    /** Returns true if this system implements the Large Physical Address
186     * Extension */
187    bool haveLPAE() const { return _haveLPAE; }
188
189    /** Returns true if this system implements the virtualization
190      * Extensions
191      */
192    bool haveVirtualization() const { return _haveVirtualization; }
193
194    /** Returns true if this system implements the Crypto
195      * Extension
196      */
197    bool haveCrypto() const { return _haveCrypto; }
198
199    /** Sets the pointer to the Generic Timer. */
200    void setGenericTimer(GenericTimer *generic_timer)
201    {
202        _genericTimer = generic_timer;
203    }
204
205    /** Sets the pointer to the GIC. */
206    void setGIC(BaseGic *gic)
207    {
208        _gic = gic;
209    }
210
211    /** Get a pointer to the system's generic timer model */
212    GenericTimer *getGenericTimer() const { return _genericTimer; }
213
214    /** Get a pointer to the system's GIC */
215    BaseGic *getGIC() const { return _gic; }
216
217    /** Returns true if the register width of the highest implemented exception
218     * level is 64 bits (ARMv8) */
219    bool highestELIs64() const { return _highestELIs64; }
220
221    /** Returns the highest implemented exception level */
222    ExceptionLevel highestEL() const
223    {
224        if (_haveSecurity)
225            return EL3;
226        if (_haveVirtualization)
227            return EL2;
228        return EL1;
229    }
230
231    /** Returns the reset address if the highest implemented exception level is
232     * 64 bits (ARMv8) */
233    Addr resetAddr() const { return _resetAddr; }
234
235    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
236    bool haveLargeAsid64() const { return _haveLargeAsid64; }
237
238    /** Returns true if SVE is implemented (ARMv8) */
239    bool haveSVE() const { return _haveSVE; }
240
241    /** Returns the SVE vector length at reset, in quadwords */
242    unsigned sveVL() const { return _sveVL; }
243
244    /** Returns the supported physical address range in bits if the highest
245     * implemented exception level is 64 bits (ARMv8) */
246    uint8_t physAddrRange64() const { return _physAddrRange64; }
247
248    /** Returns the supported physical address range in bits */
249    uint8_t physAddrRange() const
250    {
251        if (_highestELIs64)
252            return _physAddrRange64;
253        if (_haveLPAE)
254            return 40;
255        return 32;
256    }
257
258    /** Returns the physical address mask */
259    Addr physAddrMask() const
260    {
261        return mask(physAddrRange());
262    }
263
264    /**
265     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
266     * an invalid/empty range if disabled.
267     */
268    const AddrRange &m5opRange() const { return _m5opRange; }
269
270    /** Is Arm Semihosting support enabled? */
271    bool haveSemihosting() const { return semihosting != nullptr; }
272
273    /**
274     * Returns a valid ArmSystem pointer if using ARM ISA, it fails
275     * otherwise.
276     */
277    static ArmSystem* getArmSystem(ThreadContext *tc);
278
279    /** Returns true if the system of a specific thread context implements the
280     * Security Extensions
281     */
282    static bool haveSecurity(ThreadContext *tc);
283
284    /** Returns true if the system of a specific thread context implements the
285     * virtualization Extensions
286     */
287    static bool haveVirtualization(ThreadContext *tc);
288
289    /** Returns true if the system of a specific thread context implements the
290     * Large Physical Address Extension
291     */
292    static bool haveLPAE(ThreadContext *tc);
293
294    /** Returns true if the register width of the highest implemented exception
295     * level for the system of a specific thread context is 64 bits (ARMv8)
296     */
297    static bool highestELIs64(ThreadContext *tc);
298
299    /** Returns the highest implemented exception level for the system of a
300     * specific thread context
301     */
302    static ExceptionLevel highestEL(ThreadContext *tc);
303
304    /** Return true if the system implements a specific exception level */
305    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
306
307    /** Returns the reset address if the highest implemented exception level
308     * for the system of a specific thread context is 64 bits (ARMv8)
309     */
310    static Addr resetAddr(ThreadContext *tc);
311
312    /** Returns the supported physical address range in bits for the system of a
313     * specific thread context
314     */
315    static uint8_t physAddrRange(ThreadContext *tc);
316
317    /** Returns the physical address mask for the system of a specific thread
318     * context
319     */
320    static Addr physAddrMask(ThreadContext *tc);
321
322    /** Returns true if ASID is 16 bits for the system of a specific thread
323     * context while in AArch64 (ARMv8) */
324    static bool haveLargeAsid64(ThreadContext *tc);
325
326    /** Is Arm Semihosting support enabled? */
327    static bool haveSemihosting(ThreadContext *tc);
328
329    /** Make a Semihosting call from aarch64 */
330    static uint64_t callSemihosting64(ThreadContext *tc,
331                                      uint32_t op, uint64_t param);
332
333    /** Make a Semihosting call from aarch32 */
334    static uint32_t callSemihosting32(ThreadContext *tc,
335                                      uint32_t op, uint32_t param);
336};
337
338class GenericArmSystem : public ArmSystem
339{
340  public:
341    typedef GenericArmSystemParams Params;
342    const Params *
343    params() const
344    {
345        return dynamic_cast<const Params *>(_params);
346    }
347
348    GenericArmSystem(Params *p) : ArmSystem(p) {};
349    virtual ~GenericArmSystem() {};
350
351    /**
352     * Initialise the system
353     */
354    virtual void initState();
355};
356
357#endif
358