system.hh revision 12531:3141027bd11a 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61  protected:
62    /**
63     * PC based event to skip the dprink() call and emulate its
64     * functionality
65     */
66    Linux::DebugPrintkEvent *debugPrintkEvent;
67
68    /** Bootloaders */
69    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71    /**
72     * Pointer to the bootloader object
73     */
74    ObjectFile *bootldr;
75
76    /**
77     * True if this system implements the Security Extensions
78     */
79    const bool _haveSecurity;
80
81    /**
82     * True if this system implements the Large Physical Address Extension
83     */
84    const bool _haveLPAE;
85
86    /**
87     * True if this system implements the virtualization Extensions
88     */
89    const bool _haveVirtualization;
90
91    /**
92     * Pointer to the Generic Timer wrapper.
93     */
94    GenericTimer *_genericTimer;
95
96    /**
97     * True if the register width of the highest implemented exception level is
98     * 64 bits (ARMv8)
99     */
100    bool _highestELIs64;
101
102    /**
103     * Reset address if the highest implemented exception level is 64 bits
104     * (ARMv8)
105     */
106    const Addr _resetAddr64;
107
108    /**
109     * Supported physical address range in bits if the highest implemented
110     * exception level is 64 bits (ARMv8)
111     */
112    const uint8_t _physAddrRange64;
113
114    /**
115     * True if ASID is 16 bits in AArch64 (ARMv8)
116     */
117    const bool _haveLargeAsid64;
118
119    /**
120     * Range for memory-mapped m5 pseudo ops. The range will be
121     * invalid/empty if disabled.
122     */
123    const AddrRange _m5opRange;
124
125    /**
126     * True if the Semihosting interface is enabled.
127     */
128    ArmSemihosting *const semihosting;
129
130  protected:
131    /**
132     * Get a boot loader that matches the kernel.
133     *
134     * @param obj Kernel binary
135     * @return Pointer to boot loader ObjectFile or nullptr if there
136     *         is no matching boot loader.
137     */
138    ObjectFile *getBootLoader(ObjectFile *const obj);
139
140  public:
141    typedef ArmSystemParams Params;
142    const Params *
143    params() const
144    {
145        return dynamic_cast<const Params *>(_params);
146    }
147
148    ArmSystem(Params *p);
149    ~ArmSystem();
150
151    /**
152     * Initialise the system
153     */
154    virtual void initState();
155
156    virtual Addr fixFuncEventAddr(Addr addr)
157    {
158        // Remove the low bit that thumb symbols have set
159        // but that aren't actually odd aligned
160        if (addr & 0x1)
161            return addr & ~1;
162        return addr;
163    }
164
165    /** true if this a multiprocessor system */
166    bool multiProc;
167
168    /** Returns true if this system implements the Security Extensions */
169    bool haveSecurity() const { return _haveSecurity; }
170
171    /** Returns true if this system implements the Large Physical Address
172     * Extension */
173    bool haveLPAE() const { return _haveLPAE; }
174
175    /** Returns true if this system implements the virtualization
176      * Extensions
177      */
178    bool haveVirtualization() const { return _haveVirtualization; }
179
180    /** Sets the pointer to the Generic Timer. */
181    void setGenericTimer(GenericTimer *generic_timer)
182    {
183        _genericTimer = generic_timer;
184    }
185
186    /** Get a pointer to the system's generic timer model */
187    GenericTimer *getGenericTimer() const { return _genericTimer; }
188
189    /** Returns true if the register width of the highest implemented exception
190     * level is 64 bits (ARMv8) */
191    bool highestELIs64() const { return _highestELIs64; }
192
193    /** Returns the highest implemented exception level */
194    ExceptionLevel highestEL() const
195    {
196        if (_haveSecurity)
197            return EL3;
198        if (_haveVirtualization)
199            return EL2;
200        return EL1;
201    }
202
203    /** Returns the reset address if the highest implemented exception level is
204     * 64 bits (ARMv8) */
205    Addr resetAddr64() const { return _resetAddr64; }
206
207    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
208    bool haveLargeAsid64() const { return _haveLargeAsid64; }
209
210    /** Returns the supported physical address range in bits if the highest
211     * implemented exception level is 64 bits (ARMv8) */
212    uint8_t physAddrRange64() const { return _physAddrRange64; }
213
214    /** Returns the supported physical address range in bits */
215    uint8_t physAddrRange() const
216    {
217        if (_highestELIs64)
218            return _physAddrRange64;
219        if (_haveLPAE)
220            return 40;
221        return 32;
222    }
223
224    /** Returns the physical address mask */
225    Addr physAddrMask() const
226    {
227        return mask(physAddrRange());
228    }
229
230    /**
231     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
232     * an invalid/empty range if disabled.
233     */
234    const AddrRange &m5opRange() const { return _m5opRange; }
235
236    /** Is Arm Semihosting support enabled? */
237    bool haveSemihosting() const { return semihosting != nullptr; }
238
239    /**
240     * Returns a valid ArmSystem pointer if using ARM ISA, it fails
241     * otherwise.
242     */
243    static ArmSystem* getArmSystem(ThreadContext *tc);
244
245    /** Returns true if the system of a specific thread context implements the
246     * Security Extensions
247     */
248    static bool haveSecurity(ThreadContext *tc);
249
250    /** Returns true if the system of a specific thread context implements the
251     * virtualization Extensions
252     */
253    static bool haveVirtualization(ThreadContext *tc);
254
255    /** Returns true if the system of a specific thread context implements the
256     * Large Physical Address Extension
257     */
258    static bool haveLPAE(ThreadContext *tc);
259
260    /** Returns true if the register width of the highest implemented exception
261     * level for the system of a specific thread context is 64 bits (ARMv8)
262     */
263    static bool highestELIs64(ThreadContext *tc);
264
265    /** Returns the highest implemented exception level for the system of a
266     * specific thread context
267     */
268    static ExceptionLevel highestEL(ThreadContext *tc);
269
270    /** Return true if the system implements a specific exception level */
271    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
272
273    /** Returns the reset address if the highest implemented exception level
274     * for the system of a specific thread context is 64 bits (ARMv8)
275     */
276    static Addr resetAddr64(ThreadContext *tc);
277
278    /** Returns the supported physical address range in bits for the system of a
279     * specific thread context
280     */
281    static uint8_t physAddrRange(ThreadContext *tc);
282
283    /** Returns the physical address mask for the system of a specific thread
284     * context
285     */
286    static Addr physAddrMask(ThreadContext *tc);
287
288    /** Returns true if ASID is 16 bits for the system of a specific thread
289     * context while in AArch64 (ARMv8) */
290    static bool haveLargeAsid64(ThreadContext *tc);
291
292    /** Is Arm Semihosting support enabled? */
293    static bool haveSemihosting(ThreadContext *tc);
294
295    /** Make a Semihosting call from aarch64 */
296    static uint64_t callSemihosting64(ThreadContext *tc,
297                                      uint32_t op, uint64_t param);
298
299    /** Make a Semihosting call from aarch32 */
300    static uint32_t callSemihosting32(ThreadContext *tc,
301                                      uint32_t op, uint32_t param);
302};
303
304class GenericArmSystem : public ArmSystem
305{
306  public:
307    typedef GenericArmSystemParams Params;
308    const Params *
309    params() const
310    {
311        return dynamic_cast<const Params *>(_params);
312    }
313
314    GenericArmSystem(Params *p) : ArmSystem(p) {};
315    virtual ~GenericArmSystem() {};
316
317    /**
318     * Initialise the system
319     */
320    virtual void initState();
321};
322
323#endif
324