system.hh revision 10822:d259f2bc2b31
1/* 2 * Copyright (c) 2010, 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_SYSTEM_HH__ 44#define __ARCH_ARM_SYSTEM_HH__ 45 46#include <string> 47#include <vector> 48 49#include "dev/arm/generic_timer.hh" 50#include "kern/linux/events.hh" 51#include "params/ArmSystem.hh" 52#include "params/GenericArmSystem.hh" 53#include "sim/sim_object.hh" 54#include "sim/system.hh" 55 56class ThreadContext; 57 58class ArmSystem : public System 59{ 60 protected: 61 /** 62 * PC based event to skip the dprink() call and emulate its 63 * functionality 64 */ 65 Linux::DebugPrintkEvent *debugPrintkEvent; 66 67 /** 68 * Pointer to the bootloader object 69 */ 70 ObjectFile *bootldr; 71 72 /** 73 * True if this system implements the Security Extensions 74 */ 75 const bool _haveSecurity; 76 77 /** 78 * True if this system implements the Large Physical Address Extension 79 */ 80 const bool _haveLPAE; 81 82 /** 83 * True if this system implements the virtualization Extensions 84 */ 85 const bool _haveVirtualization; 86 87 /** 88 * True if this system implements the Generic Timer extension 89 */ 90 const bool _haveGenericTimer; 91 92 /** 93 * Pointer to the Generic Timer wrapper. 94 */ 95 GenericTimer *_genericTimer; 96 97 /** 98 * True if the register width of the highest implemented exception level is 99 * 64 bits (ARMv8) 100 */ 101 bool _highestELIs64; 102 103 /** 104 * Reset address if the highest implemented exception level is 64 bits 105 * (ARMv8) 106 */ 107 const Addr _resetAddr64; 108 109 /** 110 * Supported physical address range in bits if the highest implemented 111 * exception level is 64 bits (ARMv8) 112 */ 113 const uint8_t _physAddrRange64; 114 115 /** 116 * True if ASID is 16 bits in AArch64 (ARMv8) 117 */ 118 const bool _haveLargeAsid64; 119 120 public: 121 typedef ArmSystemParams Params; 122 const Params * 123 params() const 124 { 125 return dynamic_cast<const Params *>(_params); 126 } 127 128 ArmSystem(Params *p); 129 ~ArmSystem(); 130 131 /** 132 * Initialise the system 133 */ 134 virtual void initState(); 135 136 virtual Addr fixFuncEventAddr(Addr addr) 137 { 138 // Remove the low bit that thumb symbols have set 139 // but that aren't actually odd aligned 140 if (addr & 0x1) 141 return addr & ~1; 142 return addr; 143 } 144 145 /** true if this a multiprocessor system */ 146 bool multiProc; 147 148 /** Returns true if this system implements the Security Extensions */ 149 bool haveSecurity() const { return _haveSecurity; } 150 151 /** Returns true if this system implements the Large Physical Address 152 * Extension */ 153 bool haveLPAE() const { return _haveLPAE; } 154 155 /** Returns true if this system implements the virtualization 156 * Extensions 157 */ 158 bool haveVirtualization() const { return _haveVirtualization; } 159 160 /** Returns true if this system implements the Generic Timer extension. */ 161 bool haveGenericTimer() const { return _haveGenericTimer; } 162 163 /** Sets the pointer to the Generic Timer. */ 164 void setGenericTimer(GenericTimer *generic_timer) 165 { 166 _genericTimer = generic_timer; 167 } 168 169 /** Returns a pointer to the system counter. */ 170 GenericTimer::SystemCounter *getSystemCounter() const; 171 172 /** Returns a pointer to the appropriate architected timer. */ 173 GenericTimer::ArchTimer *getArchTimer(int cpu_id) const; 174 175 /** Returns true if the register width of the highest implemented exception 176 * level is 64 bits (ARMv8) */ 177 bool highestELIs64() const { return _highestELIs64; } 178 179 /** Returns the highest implemented exception level */ 180 ExceptionLevel highestEL() const 181 { 182 if (_haveSecurity) 183 return EL3; 184 // @todo: uncomment this to enable Virtualization 185 // if (_haveVirtualization) 186 // return EL2; 187 return EL1; 188 } 189 190 /** Returns the reset address if the highest implemented exception level is 191 * 64 bits (ARMv8) */ 192 Addr resetAddr64() const { return _resetAddr64; } 193 194 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */ 195 bool haveLargeAsid64() const { return _haveLargeAsid64; } 196 197 /** Returns the supported physical address range in bits if the highest 198 * implemented exception level is 64 bits (ARMv8) */ 199 uint8_t physAddrRange64() const { return _physAddrRange64; } 200 201 /** Returns the supported physical address range in bits */ 202 uint8_t physAddrRange() const 203 { 204 if (_highestELIs64) 205 return _physAddrRange64; 206 if (_haveLPAE) 207 return 40; 208 return 32; 209 } 210 211 /** Returns the physical address mask */ 212 Addr physAddrMask() const 213 { 214 return mask(physAddrRange()); 215 } 216 217 /** Returns true if the system of a specific thread context implements the 218 * Security Extensions 219 */ 220 static bool haveSecurity(ThreadContext *tc); 221 222 /** Returns true if the system of a specific thread context implements the 223 * virtualization Extensions 224 */ 225 static bool haveVirtualization(ThreadContext *tc); 226 227 /** Returns true if the system of a specific thread context implements the 228 * Large Physical Address Extension 229 */ 230 static bool haveLPAE(ThreadContext *tc); 231 232 /** Returns true if the register width of the highest implemented exception 233 * level for the system of a specific thread context is 64 bits (ARMv8) 234 */ 235 static bool highestELIs64(ThreadContext *tc); 236 237 /** Returns the highest implemented exception level for the system of a 238 * specific thread context 239 */ 240 static ExceptionLevel highestEL(ThreadContext *tc); 241 242 /** Returns the reset address if the highest implemented exception level for 243 * the system of a specific thread context is 64 bits (ARMv8) 244 */ 245 static Addr resetAddr64(ThreadContext *tc); 246 247 /** Returns the supported physical address range in bits for the system of a 248 * specific thread context 249 */ 250 static uint8_t physAddrRange(ThreadContext *tc); 251 252 /** Returns the physical address mask for the system of a specific thread 253 * context 254 */ 255 static Addr physAddrMask(ThreadContext *tc); 256 257 /** Returns true if ASID is 16 bits for the system of a specific thread 258 * context while in AArch64 (ARMv8) */ 259 static bool haveLargeAsid64(ThreadContext *tc); 260}; 261 262class GenericArmSystem : public ArmSystem 263{ 264 public: 265 typedef GenericArmSystemParams Params; 266 const Params * 267 params() const 268 { 269 return dynamic_cast<const Params *>(_params); 270 } 271 272 GenericArmSystem(Params *p) : ArmSystem(p) {}; 273 virtual ~GenericArmSystem() {}; 274 275 /** 276 * Initialise the system 277 */ 278 virtual void initState(); 279}; 280 281#endif 282