system.hh revision 10810:683ab55819fd 
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <string>
47#include <vector>
48
49#include "dev/arm/generic_timer.hh"
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class ThreadContext;
57
58class ArmSystem : public System
59{
60  protected:
61    /**
62     * PC based event to skip the dprink() call and emulate its
63     * functionality
64     */
65    Linux::DebugPrintkEvent *debugPrintkEvent;
66
67    /**
68     * Pointer to the bootloader object
69     */
70    ObjectFile *bootldr;
71
72    /**
73     * True if this system implements the Security Extensions
74     */
75    const bool _haveSecurity;
76
77    /**
78     * True if this system implements the Large Physical Address Extension
79     */
80    const bool _haveLPAE;
81
82    /**
83     * True if this system implements the virtualization Extensions
84     */
85    const bool _haveVirtualization;
86
87    /**
88     * True if this system implements the Generic Timer extension
89     */
90    const bool _haveGenericTimer;
91
92    /**
93     * Pointer to the Generic Timer wrapper.
94     */
95    GenericTimer *_genericTimer;
96
97    /**
98     * True if the register width of the highest implemented exception level is
99     * 64 bits (ARMv8)
100     */
101    bool _highestELIs64;
102
103    /**
104     * Reset address if the highest implemented exception level is 64 bits
105     * (ARMv8)
106     */
107    const Addr _resetAddr64;
108
109    /**
110     * Supported physical address range in bits if the highest implemented
111     * exception level is 64 bits (ARMv8)
112     */
113    const uint8_t _physAddrRange64;
114
115    /**
116     * True if ASID is 16 bits in AArch64 (ARMv8)
117     */
118    const bool _haveLargeAsid64;
119
120  public:
121    typedef ArmSystemParams Params;
122    const Params *
123    params() const
124    {
125        return dynamic_cast<const Params *>(_params);
126    }
127
128    ArmSystem(Params *p);
129    ~ArmSystem();
130
131    /**
132     * Initialise the system
133     */
134    virtual void initState();
135
136    /** Check if an address should be uncacheable until all caches are enabled.
137     * This exits because coherence on some addresses at boot is maintained via
138     * sw coherence until the caches are enbaled. Since we don't support sw
139     * coherence operations in gem5, this is a method that allows a system
140     * type to designate certain addresses that should remain uncachebale
141     * for a while.
142     */
143    virtual bool adderBootUncacheable(Addr a) { return false; }
144
145    virtual Addr fixFuncEventAddr(Addr addr)
146    {
147        // Remove the low bit that thumb symbols have set
148        // but that aren't actually odd aligned
149        if (addr & 0x1)
150            return addr & ~1;
151        return addr;
152    }
153
154    /** true if this a multiprocessor system */
155    bool multiProc;
156
157    /** Returns true if this system implements the Security Extensions */
158    bool haveSecurity() const { return _haveSecurity; }
159
160    /** Returns true if this system implements the Large Physical Address
161     * Extension */
162    bool haveLPAE() const { return _haveLPAE; }
163
164    /** Returns true if this system implements the virtualization
165      * Extensions
166      */
167    bool haveVirtualization() const { return _haveVirtualization; }
168
169    /** Returns true if this system implements the Generic Timer extension. */
170    bool haveGenericTimer() const { return _haveGenericTimer; }
171
172    /** Sets the pointer to the Generic Timer. */
173    void setGenericTimer(GenericTimer *generic_timer)
174    {
175        _genericTimer = generic_timer;
176    }
177
178    /** Returns a pointer to the system counter. */
179    GenericTimer::SystemCounter *getSystemCounter() const;
180
181    /** Returns a pointer to the appropriate architected timer. */
182    GenericTimer::ArchTimer *getArchTimer(int cpu_id) const;
183
184    /** Returns true if the register width of the highest implemented exception
185     * level is 64 bits (ARMv8) */
186    bool highestELIs64() const { return _highestELIs64; }
187
188    /** Returns the highest implemented exception level */
189    ExceptionLevel highestEL() const
190    {
191        if (_haveSecurity)
192            return EL3;
193        // @todo: uncomment this to enable Virtualization
194        // if (_haveVirtualization)
195        //     return EL2;
196        return EL1;
197    }
198
199    /** Returns the reset address if the highest implemented exception level is
200     * 64 bits (ARMv8) */
201    Addr resetAddr64() const { return _resetAddr64; }
202
203    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
204    bool haveLargeAsid64() const { return _haveLargeAsid64; }
205
206    /** Returns the supported physical address range in bits if the highest
207     * implemented exception level is 64 bits (ARMv8) */
208    uint8_t physAddrRange64() const { return _physAddrRange64; }
209
210    /** Returns the supported physical address range in bits */
211    uint8_t physAddrRange() const
212    {
213        if (_highestELIs64)
214            return _physAddrRange64;
215        if (_haveLPAE)
216            return 40;
217        return 32;
218    }
219
220    /** Returns the physical address mask */
221    Addr physAddrMask() const
222    {
223        return mask(physAddrRange());
224    }
225
226    /** Returns true if the system of a specific thread context implements the
227     * Security Extensions
228     */
229    static bool haveSecurity(ThreadContext *tc);
230
231    /** Returns true if the system of a specific thread context implements the
232     * virtualization Extensions
233     */
234    static bool haveVirtualization(ThreadContext *tc);
235
236    /** Returns true if the system of a specific thread context implements the
237     * Large Physical Address Extension
238     */
239    static bool haveLPAE(ThreadContext *tc);
240
241    /** Returns true if the register width of the highest implemented exception
242     * level for the system of a specific thread context is 64 bits (ARMv8)
243     */
244    static bool highestELIs64(ThreadContext *tc);
245
246    /** Returns the highest implemented exception level for the system of a
247     * specific thread context
248     */
249    static ExceptionLevel highestEL(ThreadContext *tc);
250
251    /** Returns the reset address if the highest implemented exception level for
252     * the system of a specific thread context is 64 bits (ARMv8)
253     */
254    static Addr resetAddr64(ThreadContext *tc);
255
256    /** Returns the supported physical address range in bits for the system of a
257     * specific thread context
258     */
259    static uint8_t physAddrRange(ThreadContext *tc);
260
261    /** Returns the physical address mask for the system of a specific thread
262     * context
263     */
264    static Addr physAddrMask(ThreadContext *tc);
265
266    /** Returns true if ASID is 16 bits for the system of a specific thread
267     * context while in AArch64 (ARMv8) */
268    static bool haveLargeAsid64(ThreadContext *tc);
269};
270
271class GenericArmSystem : public ArmSystem
272{
273  public:
274    typedef GenericArmSystemParams Params;
275    const Params *
276    params() const
277    {
278        return dynamic_cast<const Params *>(_params);
279    }
280
281    GenericArmSystem(Params *p) : ArmSystem(p) {};
282    virtual ~GenericArmSystem() {};
283
284    /**
285     * Initialise the system
286     */
287    virtual void initState();
288};
289
290#endif
291