system.hh revision 8527
12567SN/A/* 27650SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37650SAli.Saidi@ARM.com * All rights reserved 47650SAli.Saidi@ARM.com * 57650SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67650SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77650SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87650SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97650SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107650SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117650SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127650SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137650SAli.Saidi@ARM.com * 142567SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152567SN/A * All rights reserved. 162567SN/A * 172567SN/A * Redistribution and use in source and binary forms, with or without 182567SN/A * modification, are permitted provided that the following conditions are 192567SN/A * met: redistributions of source code must retain the above copyright 202567SN/A * notice, this list of conditions and the following disclaimer; 212567SN/A * redistributions in binary form must reproduce the above copyright 222567SN/A * notice, this list of conditions and the following disclaimer in the 232567SN/A * documentation and/or other materials provided with the distribution; 242567SN/A * neither the name of the copyright holders nor the names of its 252567SN/A * contributors may be used to endorse or promote products derived from 262567SN/A * this software without specific prior written permission. 272567SN/A * 282567SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292567SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302567SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312567SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322567SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332567SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342567SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352567SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362567SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372567SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382567SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 412567SN/A */ 422567SN/A 436757SAli.Saidi@ARM.com#ifndef __ARCH_ARM_SYSTEM_HH__ 446757SAli.Saidi@ARM.com#define __ARCH_ARM_SYSTEM_HH__ 452567SN/A 462567SN/A#include <string> 472567SN/A#include <vector> 482567SN/A 498229Snate@binkert.org#include "kern/linux/events.hh" 506757SAli.Saidi@ARM.com#include "params/ArmSystem.hh" 512567SN/A#include "sim/sim_object.hh" 522567SN/A#include "sim/system.hh" 532567SN/A 546757SAli.Saidi@ARM.comclass ArmSystem : public System 552567SN/A{ 568285SPrakash.Ramrakhyani@arm.com protected: 577650SAli.Saidi@ARM.com /** 587650SAli.Saidi@ARM.com * PC based event to skip the dprink() call and emulate its 597650SAli.Saidi@ARM.com * functionality 607650SAli.Saidi@ARM.com */ 617650SAli.Saidi@ARM.com Linux::DebugPrintkEvent *debugPrintkEvent; 627650SAli.Saidi@ARM.com 638286SAli.Saidi@ARM.com /** 648286SAli.Saidi@ARM.com * Pointer to the bootloader object 658286SAli.Saidi@ARM.com */ 668286SAli.Saidi@ARM.com ObjectFile *bootldr; 678286SAli.Saidi@ARM.com 682567SN/A public: 696757SAli.Saidi@ARM.com typedef ArmSystemParams Params; 708286SAli.Saidi@ARM.com const Params * 718286SAli.Saidi@ARM.com params() const 728286SAli.Saidi@ARM.com { 738286SAli.Saidi@ARM.com return dynamic_cast<const Params *>(_params); 748286SAli.Saidi@ARM.com } 758286SAli.Saidi@ARM.com 766757SAli.Saidi@ARM.com ArmSystem(Params *p); 776757SAli.Saidi@ARM.com ~ArmSystem(); 788286SAli.Saidi@ARM.com 798286SAli.Saidi@ARM.com void initState(); 808286SAli.Saidi@ARM.com 818527SAli.Saidi@ARM.com /** Check if an address should be uncacheable until all caches are enabled. 828527SAli.Saidi@ARM.com * This exits because coherence on some addresses at boot is maintained via 838527SAli.Saidi@ARM.com * sw coherence until the caches are enbaled. Since we don't support sw 848527SAli.Saidi@ARM.com * coherence operations in gem5, this is a method that allows a system 858527SAli.Saidi@ARM.com * type to designate certain addresses that should remain uncachebale 868527SAli.Saidi@ARM.com * for a while. 878527SAli.Saidi@ARM.com */ 888527SAli.Saidi@ARM.com virtual bool adderBootUncacheable(Addr a) { return false; } 898527SAli.Saidi@ARM.com 903553SN/A virtual Addr fixFuncEventAddr(Addr addr) 913553SN/A { 927693SAli.Saidi@ARM.com // Remove the low bit that thumb symbols have set 937693SAli.Saidi@ARM.com // but that aren't actually odd aligned 947693SAli.Saidi@ARM.com if (addr & 0x1) 957720Sgblack@eecs.umich.edu return addr & ~1; 963553SN/A return addr; 973553SN/A } 982567SN/A}; 992567SN/A 1002567SN/A#endif 1012567SN/A 102