system.hh revision 13531 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class BaseGic;
58class ThreadContext;
59
60class ArmSystem : public System
61{
62  protected:
63    /**
64     * PC based event to skip the dprink() call and emulate its
65     * functionality
66     */
67    Linux::DebugPrintkEvent *debugPrintkEvent;
68
69    /** Bootloaders */
70    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
71
72    /**
73     * Pointer to the bootloader object
74     */
75    ObjectFile *bootldr;
76
77    /**
78     * True if this system implements the Security Extensions
79     */
80    const bool _haveSecurity;
81
82    /**
83     * True if this system implements the Large Physical Address Extension
84     */
85    const bool _haveLPAE;
86
87    /**
88     * True if this system implements the virtualization Extensions
89     */
90    const bool _haveVirtualization;
91
92    /**
93     * True if this system implements the Crypto Extension
94     */
95    const bool _haveCrypto;
96
97    /**
98     * Pointer to the Generic Timer wrapper.
99     */
100    GenericTimer *_genericTimer;
101    BaseGic *_gic;
102
103    /**
104     * Reset address (ARMv8)
105     */
106    const Addr _resetAddr;
107
108    /**
109     * True if the register width of the highest implemented exception level is
110     * 64 bits (ARMv8)
111     */
112    bool _highestELIs64;
113
114    /**
115     * Supported physical address range in bits if the highest implemented
116     * exception level is 64 bits (ARMv8)
117     */
118    const uint8_t _physAddrRange64;
119
120    /**
121     * True if ASID is 16 bits in AArch64 (ARMv8)
122     */
123    const bool _haveLargeAsid64;
124
125    /**
126     * Range for memory-mapped m5 pseudo ops. The range will be
127     * invalid/empty if disabled.
128     */
129    const AddrRange _m5opRange;
130
131    /**
132     * True if the Semihosting interface is enabled.
133     */
134    ArmSemihosting *const semihosting;
135
136  protected:
137    /**
138     * Get a boot loader that matches the kernel.
139     *
140     * @param obj Kernel binary
141     * @return Pointer to boot loader ObjectFile or nullptr if there
142     *         is no matching boot loader.
143     */
144    ObjectFile *getBootLoader(ObjectFile *const obj);
145
146  public:
147    typedef ArmSystemParams Params;
148    const Params *
149    params() const
150    {
151        return dynamic_cast<const Params *>(_params);
152    }
153
154    ArmSystem(Params *p);
155    ~ArmSystem();
156
157    /**
158     * Initialise the system
159     */
160    virtual void initState();
161
162    virtual Addr fixFuncEventAddr(Addr addr)
163    {
164        // Remove the low bit that thumb symbols have set
165        // but that aren't actually odd aligned
166        if (addr & 0x1)
167            return addr & ~1;
168        return addr;
169    }
170
171    /** true if this a multiprocessor system */
172    bool multiProc;
173
174    /** Returns true if this system implements the Security Extensions */
175    bool haveSecurity() const { return _haveSecurity; }
176
177    /** Returns true if this system implements the Large Physical Address
178     * Extension */
179    bool haveLPAE() const { return _haveLPAE; }
180
181    /** Returns true if this system implements the virtualization
182      * Extensions
183      */
184    bool haveVirtualization() const { return _haveVirtualization; }
185
186    /** Returns true if this system implements the Crypto
187      * Extension
188      */
189    bool haveCrypto() const { return _haveCrypto; }
190
191    /** Sets the pointer to the Generic Timer. */
192    void setGenericTimer(GenericTimer *generic_timer)
193    {
194        _genericTimer = generic_timer;
195    }
196
197    /** Sets the pointer to the GIC. */
198    void setGIC(BaseGic *gic)
199    {
200        _gic = gic;
201    }
202
203    /** Get a pointer to the system's generic timer model */
204    GenericTimer *getGenericTimer() const { return _genericTimer; }
205
206    /** Get a pointer to the system's GIC */
207    BaseGic *getGIC() const { return _gic; }
208
209    /** Returns true if the register width of the highest implemented exception
210     * level is 64 bits (ARMv8) */
211    bool highestELIs64() const { return _highestELIs64; }
212
213    /** Returns the highest implemented exception level */
214    ExceptionLevel highestEL() const
215    {
216        if (_haveSecurity)
217            return EL3;
218        if (_haveVirtualization)
219            return EL2;
220        return EL1;
221    }
222
223    /** Returns the reset address if the highest implemented exception level is
224     * 64 bits (ARMv8) */
225    Addr resetAddr() const { return _resetAddr; }
226
227    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
228    bool haveLargeAsid64() const { return _haveLargeAsid64; }
229
230    /** Returns the supported physical address range in bits if the highest
231     * implemented exception level is 64 bits (ARMv8) */
232    uint8_t physAddrRange64() const { return _physAddrRange64; }
233
234    /** Returns the supported physical address range in bits */
235    uint8_t physAddrRange() const
236    {
237        if (_highestELIs64)
238            return _physAddrRange64;
239        if (_haveLPAE)
240            return 40;
241        return 32;
242    }
243
244    /** Returns the physical address mask */
245    Addr physAddrMask() const
246    {
247        return mask(physAddrRange());
248    }
249
250    /**
251     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
252     * an invalid/empty range if disabled.
253     */
254    const AddrRange &m5opRange() const { return _m5opRange; }
255
256    /** Is Arm Semihosting support enabled? */
257    bool haveSemihosting() const { return semihosting != nullptr; }
258
259    /**
260     * Returns a valid ArmSystem pointer if using ARM ISA, it fails
261     * otherwise.
262     */
263    static ArmSystem* getArmSystem(ThreadContext *tc);
264
265    /** Returns true if the system of a specific thread context implements the
266     * Security Extensions
267     */
268    static bool haveSecurity(ThreadContext *tc);
269
270    /** Returns true if the system of a specific thread context implements the
271     * virtualization Extensions
272     */
273    static bool haveVirtualization(ThreadContext *tc);
274
275    /** Returns true if the system of a specific thread context implements the
276     * Large Physical Address Extension
277     */
278    static bool haveLPAE(ThreadContext *tc);
279
280    /** Returns true if the register width of the highest implemented exception
281     * level for the system of a specific thread context is 64 bits (ARMv8)
282     */
283    static bool highestELIs64(ThreadContext *tc);
284
285    /** Returns the highest implemented exception level for the system of a
286     * specific thread context
287     */
288    static ExceptionLevel highestEL(ThreadContext *tc);
289
290    /** Return true if the system implements a specific exception level */
291    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
292
293    /** Returns the reset address if the highest implemented exception level
294     * for the system of a specific thread context is 64 bits (ARMv8)
295     */
296    static Addr resetAddr(ThreadContext *tc);
297
298    /** Returns the supported physical address range in bits for the system of a
299     * specific thread context
300     */
301    static uint8_t physAddrRange(ThreadContext *tc);
302
303    /** Returns the physical address mask for the system of a specific thread
304     * context
305     */
306    static Addr physAddrMask(ThreadContext *tc);
307
308    /** Returns true if ASID is 16 bits for the system of a specific thread
309     * context while in AArch64 (ARMv8) */
310    static bool haveLargeAsid64(ThreadContext *tc);
311
312    /** Is Arm Semihosting support enabled? */
313    static bool haveSemihosting(ThreadContext *tc);
314
315    /** Make a Semihosting call from aarch64 */
316    static uint64_t callSemihosting64(ThreadContext *tc,
317                                      uint32_t op, uint64_t param);
318
319    /** Make a Semihosting call from aarch32 */
320    static uint32_t callSemihosting32(ThreadContext *tc,
321                                      uint32_t op, uint32_t param);
322};
323
324class GenericArmSystem : public ArmSystem
325{
326  public:
327    typedef GenericArmSystemParams Params;
328    const Params *
329    params() const
330    {
331        return dynamic_cast<const Params *>(_params);
332    }
333
334    GenericArmSystem(Params *p) : ArmSystem(p) {};
335    virtual ~GenericArmSystem() {};
336
337    /**
338     * Initialise the system
339     */
340    virtual void initState();
341};
342
343#endif
344