system.hh revision 11168
12567SN/A/* 210037SARM gem5 Developers * Copyright (c) 2010, 2012-2013 ARM Limited 37650SAli.Saidi@ARM.com * All rights reserved 47650SAli.Saidi@ARM.com * 57650SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67650SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77650SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87650SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97650SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107650SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117650SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127650SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137650SAli.Saidi@ARM.com * 142567SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152567SN/A * All rights reserved. 162567SN/A * 172567SN/A * Redistribution and use in source and binary forms, with or without 182567SN/A * modification, are permitted provided that the following conditions are 192567SN/A * met: redistributions of source code must retain the above copyright 202567SN/A * notice, this list of conditions and the following disclaimer; 212567SN/A * redistributions in binary form must reproduce the above copyright 222567SN/A * notice, this list of conditions and the following disclaimer in the 232567SN/A * documentation and/or other materials provided with the distribution; 242567SN/A * neither the name of the copyright holders nor the names of its 252567SN/A * contributors may be used to endorse or promote products derived from 262567SN/A * this software without specific prior written permission. 272567SN/A * 282567SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292567SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302567SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312567SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322567SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332567SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342567SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352567SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362567SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372567SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382567SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 412567SN/A */ 422567SN/A 436757SAli.Saidi@ARM.com#ifndef __ARCH_ARM_SYSTEM_HH__ 446757SAli.Saidi@ARM.com#define __ARCH_ARM_SYSTEM_HH__ 452567SN/A 462567SN/A#include <string> 472567SN/A#include <vector> 482567SN/A 498229Snate@binkert.org#include "kern/linux/events.hh" 506757SAli.Saidi@ARM.com#include "params/ArmSystem.hh" 5110810Sbr@bsdpad.com#include "params/GenericArmSystem.hh" 522567SN/A#include "sim/sim_object.hh" 532567SN/A#include "sim/system.hh" 542567SN/A 5510844Sandreas.sandberg@arm.comclass GenericTimer; 5610037SARM gem5 Developersclass ThreadContext; 5710037SARM gem5 Developers 586757SAli.Saidi@ARM.comclass ArmSystem : public System 592567SN/A{ 608285SPrakash.Ramrakhyani@arm.com protected: 617650SAli.Saidi@ARM.com /** 627650SAli.Saidi@ARM.com * PC based event to skip the dprink() call and emulate its 637650SAli.Saidi@ARM.com * functionality 647650SAli.Saidi@ARM.com */ 657650SAli.Saidi@ARM.com Linux::DebugPrintkEvent *debugPrintkEvent; 667650SAli.Saidi@ARM.com 678286SAli.Saidi@ARM.com /** 688286SAli.Saidi@ARM.com * Pointer to the bootloader object 698286SAli.Saidi@ARM.com */ 708286SAli.Saidi@ARM.com ObjectFile *bootldr; 718286SAli.Saidi@ARM.com 7210037SARM gem5 Developers /** 7310037SARM gem5 Developers * True if this system implements the Security Extensions 7410037SARM gem5 Developers */ 7510037SARM gem5 Developers const bool _haveSecurity; 7610037SARM gem5 Developers 7710037SARM gem5 Developers /** 7810037SARM gem5 Developers * True if this system implements the Large Physical Address Extension 7910037SARM gem5 Developers */ 8010037SARM gem5 Developers const bool _haveLPAE; 8110037SARM gem5 Developers 8210037SARM gem5 Developers /** 8310037SARM gem5 Developers * True if this system implements the virtualization Extensions 8410037SARM gem5 Developers */ 8510037SARM gem5 Developers const bool _haveVirtualization; 8610037SARM gem5 Developers 8710037SARM gem5 Developers /** 8810037SARM gem5 Developers * Pointer to the Generic Timer wrapper. 8910037SARM gem5 Developers */ 9010037SARM gem5 Developers GenericTimer *_genericTimer; 9110037SARM gem5 Developers 9210037SARM gem5 Developers /** 9310037SARM gem5 Developers * True if the register width of the highest implemented exception level is 9410037SARM gem5 Developers * 64 bits (ARMv8) 9510037SARM gem5 Developers */ 9610037SARM gem5 Developers bool _highestELIs64; 9710037SARM gem5 Developers 9810037SARM gem5 Developers /** 9910037SARM gem5 Developers * Reset address if the highest implemented exception level is 64 bits 10010037SARM gem5 Developers * (ARMv8) 10110037SARM gem5 Developers */ 10210037SARM gem5 Developers const Addr _resetAddr64; 10310037SARM gem5 Developers 10410037SARM gem5 Developers /** 10510037SARM gem5 Developers * Supported physical address range in bits if the highest implemented 10610037SARM gem5 Developers * exception level is 64 bits (ARMv8) 10710037SARM gem5 Developers */ 10810037SARM gem5 Developers const uint8_t _physAddrRange64; 10910037SARM gem5 Developers 11010037SARM gem5 Developers /** 11110037SARM gem5 Developers * True if ASID is 16 bits in AArch64 (ARMv8) 11210037SARM gem5 Developers */ 11310037SARM gem5 Developers const bool _haveLargeAsid64; 11410037SARM gem5 Developers 1152567SN/A public: 1166757SAli.Saidi@ARM.com typedef ArmSystemParams Params; 1178286SAli.Saidi@ARM.com const Params * 1188286SAli.Saidi@ARM.com params() const 1198286SAli.Saidi@ARM.com { 1208286SAli.Saidi@ARM.com return dynamic_cast<const Params *>(_params); 1218286SAli.Saidi@ARM.com } 1228286SAli.Saidi@ARM.com 1236757SAli.Saidi@ARM.com ArmSystem(Params *p); 1246757SAli.Saidi@ARM.com ~ArmSystem(); 1258286SAli.Saidi@ARM.com 1268706Sandreas.hansson@arm.com /** 1278706Sandreas.hansson@arm.com * Initialise the system 1288706Sandreas.hansson@arm.com */ 1298706Sandreas.hansson@arm.com virtual void initState(); 1308286SAli.Saidi@ARM.com 1313553SN/A virtual Addr fixFuncEventAddr(Addr addr) 1323553SN/A { 1337693SAli.Saidi@ARM.com // Remove the low bit that thumb symbols have set 1347693SAli.Saidi@ARM.com // but that aren't actually odd aligned 1357693SAli.Saidi@ARM.com if (addr & 0x1) 1367720Sgblack@eecs.umich.edu return addr & ~1; 1373553SN/A return addr; 1383553SN/A } 1399050Schander.sudanthi@arm.com 1409050Schander.sudanthi@arm.com /** true if this a multiprocessor system */ 1419050Schander.sudanthi@arm.com bool multiProc; 14210037SARM gem5 Developers 14310037SARM gem5 Developers /** Returns true if this system implements the Security Extensions */ 14410037SARM gem5 Developers bool haveSecurity() const { return _haveSecurity; } 14510037SARM gem5 Developers 14610037SARM gem5 Developers /** Returns true if this system implements the Large Physical Address 14710037SARM gem5 Developers * Extension */ 14810037SARM gem5 Developers bool haveLPAE() const { return _haveLPAE; } 14910037SARM gem5 Developers 15010037SARM gem5 Developers /** Returns true if this system implements the virtualization 15110037SARM gem5 Developers * Extensions 15210037SARM gem5 Developers */ 15310037SARM gem5 Developers bool haveVirtualization() const { return _haveVirtualization; } 15410037SARM gem5 Developers 15510037SARM gem5 Developers /** Sets the pointer to the Generic Timer. */ 15610037SARM gem5 Developers void setGenericTimer(GenericTimer *generic_timer) 15710037SARM gem5 Developers { 15810037SARM gem5 Developers _genericTimer = generic_timer; 15910037SARM gem5 Developers } 16010037SARM gem5 Developers 16110844Sandreas.sandberg@arm.com /** Get a pointer to the system's generic timer model */ 16210844Sandreas.sandberg@arm.com GenericTimer *getGenericTimer() const { return _genericTimer; } 16310037SARM gem5 Developers 16410037SARM gem5 Developers /** Returns true if the register width of the highest implemented exception 16510037SARM gem5 Developers * level is 64 bits (ARMv8) */ 16610037SARM gem5 Developers bool highestELIs64() const { return _highestELIs64; } 16710037SARM gem5 Developers 16810037SARM gem5 Developers /** Returns the highest implemented exception level */ 16910037SARM gem5 Developers ExceptionLevel highestEL() const 17010037SARM gem5 Developers { 17110037SARM gem5 Developers if (_haveSecurity) 17210037SARM gem5 Developers return EL3; 17310037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 17410037SARM gem5 Developers // if (_haveVirtualization) 17510037SARM gem5 Developers // return EL2; 17610037SARM gem5 Developers return EL1; 17710037SARM gem5 Developers } 17810037SARM gem5 Developers 17910037SARM gem5 Developers /** Returns the reset address if the highest implemented exception level is 18010037SARM gem5 Developers * 64 bits (ARMv8) */ 18110037SARM gem5 Developers Addr resetAddr64() const { return _resetAddr64; } 18210037SARM gem5 Developers 18310037SARM gem5 Developers /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */ 18410037SARM gem5 Developers bool haveLargeAsid64() const { return _haveLargeAsid64; } 18510037SARM gem5 Developers 18610037SARM gem5 Developers /** Returns the supported physical address range in bits if the highest 18710037SARM gem5 Developers * implemented exception level is 64 bits (ARMv8) */ 18810037SARM gem5 Developers uint8_t physAddrRange64() const { return _physAddrRange64; } 18910037SARM gem5 Developers 19010037SARM gem5 Developers /** Returns the supported physical address range in bits */ 19110037SARM gem5 Developers uint8_t physAddrRange() const 19210037SARM gem5 Developers { 19310037SARM gem5 Developers if (_highestELIs64) 19410037SARM gem5 Developers return _physAddrRange64; 19510037SARM gem5 Developers if (_haveLPAE) 19610037SARM gem5 Developers return 40; 19710037SARM gem5 Developers return 32; 19810037SARM gem5 Developers } 19910037SARM gem5 Developers 20010037SARM gem5 Developers /** Returns the physical address mask */ 20110037SARM gem5 Developers Addr physAddrMask() const 20210037SARM gem5 Developers { 20310037SARM gem5 Developers return mask(physAddrRange()); 20410037SARM gem5 Developers } 20510037SARM gem5 Developers 20610037SARM gem5 Developers /** Returns true if the system of a specific thread context implements the 20710037SARM gem5 Developers * Security Extensions 20810037SARM gem5 Developers */ 20910037SARM gem5 Developers static bool haveSecurity(ThreadContext *tc); 21010037SARM gem5 Developers 21110037SARM gem5 Developers /** Returns true if the system of a specific thread context implements the 21210037SARM gem5 Developers * virtualization Extensions 21310037SARM gem5 Developers */ 21410037SARM gem5 Developers static bool haveVirtualization(ThreadContext *tc); 21510037SARM gem5 Developers 21610037SARM gem5 Developers /** Returns true if the system of a specific thread context implements the 21710037SARM gem5 Developers * Large Physical Address Extension 21810037SARM gem5 Developers */ 21910037SARM gem5 Developers static bool haveLPAE(ThreadContext *tc); 22010037SARM gem5 Developers 22110037SARM gem5 Developers /** Returns true if the register width of the highest implemented exception 22210037SARM gem5 Developers * level for the system of a specific thread context is 64 bits (ARMv8) 22310037SARM gem5 Developers */ 22410037SARM gem5 Developers static bool highestELIs64(ThreadContext *tc); 22510037SARM gem5 Developers 22610037SARM gem5 Developers /** Returns the highest implemented exception level for the system of a 22710037SARM gem5 Developers * specific thread context 22810037SARM gem5 Developers */ 22910037SARM gem5 Developers static ExceptionLevel highestEL(ThreadContext *tc); 23010037SARM gem5 Developers 23110037SARM gem5 Developers /** Returns the reset address if the highest implemented exception level for 23210037SARM gem5 Developers * the system of a specific thread context is 64 bits (ARMv8) 23310037SARM gem5 Developers */ 23410037SARM gem5 Developers static Addr resetAddr64(ThreadContext *tc); 23510037SARM gem5 Developers 23610037SARM gem5 Developers /** Returns the supported physical address range in bits for the system of a 23710037SARM gem5 Developers * specific thread context 23810037SARM gem5 Developers */ 23910037SARM gem5 Developers static uint8_t physAddrRange(ThreadContext *tc); 24010037SARM gem5 Developers 24110037SARM gem5 Developers /** Returns the physical address mask for the system of a specific thread 24210037SARM gem5 Developers * context 24310037SARM gem5 Developers */ 24410037SARM gem5 Developers static Addr physAddrMask(ThreadContext *tc); 24510037SARM gem5 Developers 24610037SARM gem5 Developers /** Returns true if ASID is 16 bits for the system of a specific thread 24710037SARM gem5 Developers * context while in AArch64 (ARMv8) */ 24810037SARM gem5 Developers static bool haveLargeAsid64(ThreadContext *tc); 24910810Sbr@bsdpad.com}; 25010037SARM gem5 Developers 25110810Sbr@bsdpad.comclass GenericArmSystem : public ArmSystem 25210810Sbr@bsdpad.com{ 25310810Sbr@bsdpad.com public: 25410810Sbr@bsdpad.com typedef GenericArmSystemParams Params; 25510810Sbr@bsdpad.com const Params * 25610810Sbr@bsdpad.com params() const 25710810Sbr@bsdpad.com { 25810810Sbr@bsdpad.com return dynamic_cast<const Params *>(_params); 25910810Sbr@bsdpad.com } 26010810Sbr@bsdpad.com 26110810Sbr@bsdpad.com GenericArmSystem(Params *p) : ArmSystem(p) {}; 26210810Sbr@bsdpad.com virtual ~GenericArmSystem() {}; 26310810Sbr@bsdpad.com 26410810Sbr@bsdpad.com /** 26510810Sbr@bsdpad.com * Initialise the system 26610810Sbr@bsdpad.com */ 26710810Sbr@bsdpad.com virtual void initState(); 2682567SN/A}; 2692567SN/A 2702567SN/A#endif 271