system.cc revision 8997
111570SCurtis.Dunham@arm.com/* 211570SCurtis.Dunham@arm.com * Copyright (c) 2010 ARM Limited 38721SN/A * All rights reserved 48721SN/A * 56112SN/A * The license below extends only to copyright in the software and shall 611570SCurtis.Dunham@arm.com * not be construed as granting a license to any other intellectual 711570SCurtis.Dunham@arm.com * property including but not limited to intellectual property relating 811570SCurtis.Dunham@arm.com * to a hardware implementation of the functionality of the software 911570SCurtis.Dunham@arm.com * licensed hereunder. You may use the software subject to the license 1011219Snilay@cs.wisc.edu * terms below provided that you ensure that this notice is replicated 116112SN/A * unmodified and in its entirety in all distributions of the software, 126112SN/A * modified or unmodified, in source code or in binary form. 136112SN/A * 146112SN/A * Copyright (c) 2002-2006 The Regents of The University of Michigan 156112SN/A * All rights reserved. 166112SN/A * 176112SN/A * Redistribution and use in source and binary forms, with or without 186112SN/A * modification, are permitted provided that the following conditions are 196112SN/A * met: redistributions of source code must retain the above copyright 206112SN/A * notice, this list of conditions and the following disclaimer; 216112SN/A * redistributions in binary form must reproduce the above copyright 226112SN/A * notice, this list of conditions and the following disclaimer in the 236112SN/A * documentation and/or other materials provided with the distribution; 246112SN/A * neither the name of the copyright holders nor the names of its 256112SN/A * contributors may be used to endorse or promote products derived from 266112SN/A * this software without specific prior written permission. 276112SN/A * 286112SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296112SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306112SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316112SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326112SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336112SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346112SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510451Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610451Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376112SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810451Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396112SN/A * 406112SN/A * Authors: Ali Saidi 416112SN/A */ 426112SN/A 436112SN/A#include <iostream> 4410451Snilay@cs.wisc.edu 4510451Snilay@cs.wisc.edu#include "arch/arm/system.hh" 466112SN/A#include "base/loader/object_file.hh" 4710451Snilay@cs.wisc.edu#include "base/loader/symtab.hh" 486112SN/A#include "cpu/thread_context.hh" 496112SN/A#include "mem/physical.hh" 506112SN/A#include "mem/fs_translating_port_proxy.hh" 5110451Snilay@cs.wisc.edu 5210451Snilay@cs.wisc.eduusing namespace std; 536112SN/Ausing namespace Linux; 5410451Snilay@cs.wisc.edu 556112SN/AArmSystem::ArmSystem(Params *p) 566112SN/A : System(p), bootldr(NULL) 576112SN/A{ 5810451Snilay@cs.wisc.edu if (p->boot_loader != "") { 5910451Snilay@cs.wisc.edu bootldr = createObjectFile(p->boot_loader); 606112SN/A 6110451Snilay@cs.wisc.edu if (!bootldr) 626112SN/A fatal("Could not read bootloader: %s\n", p->boot_loader); 6310451Snilay@cs.wisc.edu 6410451Snilay@cs.wisc.edu bootldr->loadGlobalSymbols(debugSymbolTable); 656112SN/A 6610451Snilay@cs.wisc.edu } 676112SN/A debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk"); 6810451Snilay@cs.wisc.edu} 696112SN/A 7010451Snilay@cs.wisc.eduvoid 7110451Snilay@cs.wisc.eduArmSystem::initState() 726112SN/A{ 7310451Snilay@cs.wisc.edu // Moved from the constructor to here since it relies on the 746112SN/A // address map being resolved in the interconnect 7510451Snilay@cs.wisc.edu 766112SN/A // Call the initialisation of the super class 7710451Snilay@cs.wisc.edu System::initState(); 7810451Snilay@cs.wisc.edu 7910451Snilay@cs.wisc.edu const Params* p = params(); 8010451Snilay@cs.wisc.edu 816112SN/A if (bootldr) { 8210451Snilay@cs.wisc.edu bootldr->loadSections(physProxy); 836112SN/A 846112SN/A uint8_t jump_to_bl[] = 859150SAli.Saidi@ARM.com { 86 0x07, 0xf0, 0xa0, 0xe1 // branch to r7 87 }; 88 physProxy.writeBlob(0x0, jump_to_bl, sizeof(jump_to_bl)); 89 90 inform("Using bootloader at address %#x\n", bootldr->entryPoint()); 91 92 // Put the address of the boot loader into r7 so we know 93 // where to branch to after the reset fault 94 // All other values needed by the boot loader to know what to do 95 if (!p->gic_cpu_addr || !p->flags_addr) 96 fatal("gic_cpu_addr && flags_addr must be set with bootloader\n"); 97 98 for (int i = 0; i < threadContexts.size(); i++) { 99 threadContexts[i]->setIntReg(3, kernelEntry & loadAddrMask); 100 threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); 101 threadContexts[i]->setIntReg(5, params()->flags_addr); 102 threadContexts[i]->setIntReg(7, bootldr->entryPoint()); 103 } 104 } else { 105 // Set the initial PC to be at start of the kernel code 106 threadContexts[0]->pcState(kernelEntry & loadAddrMask); 107 } 108 109 for (int i = 0; i < threadContexts.size(); i++) { 110 if (p->midr_regval) { 111 threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR, 112 p->midr_regval); 113 } 114 } 115} 116 117ArmSystem::~ArmSystem() 118{ 119 if (debugPrintkEvent) 120 delete debugPrintkEvent; 121} 122 123 124ArmSystem * 125ArmSystemParams::create() 126{ 127 return new ArmSystem(this); 128} 129