system.cc revision 13759:9941fca869a9
1/* 2 * Copyright (c) 2010, 2012-2013, 2015,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#include "arch/arm/system.hh" 44 45#include <iostream> 46 47#include "arch/arm/semihosting.hh" 48#include "base/loader/object_file.hh" 49#include "base/loader/symtab.hh" 50#include "cpu/thread_context.hh" 51#include "dev/arm/gic_v3.hh" 52#include "mem/fs_translating_port_proxy.hh" 53#include "mem/physical.hh" 54#include "sim/full_system.hh" 55 56using namespace std; 57using namespace Linux; 58 59ArmSystem::ArmSystem(Params *p) 60 : System(p), 61 bootLoaders(), bootldr(nullptr), 62 _haveSecurity(p->have_security), 63 _haveLPAE(p->have_lpae), 64 _haveVirtualization(p->have_virtualization), 65 _haveCrypto(p->have_crypto), 66 _genericTimer(nullptr), 67 _gic(nullptr), 68 _resetAddr(p->auto_reset_addr ? 69 (kernelEntry & loadAddrMask) + loadAddrOffset : 70 p->reset_addr), 71 _highestELIs64(p->highest_el_is_64), 72 _physAddrRange64(p->phys_addr_range_64), 73 _haveLargeAsid64(p->have_large_asid_64), 74 _haveSVE(p->have_sve), 75 _sveVL(p->sve_vl), 76 _m5opRange(p->m5ops_base ? 77 RangeSize(p->m5ops_base, 0x10000) : 78 AddrRange(1, 0)), // Create an empty range if disabled 79 semihosting(p->semihosting), 80 multiProc(p->multi_proc) 81{ 82 // Check if the physical address range is valid 83 if (_highestELIs64 && ( 84 _physAddrRange64 < 32 || 85 _physAddrRange64 > 48 || 86 (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) { 87 fatal("Invalid physical address range (%d)\n", _physAddrRange64); 88 } 89 90 bootLoaders.reserve(p->boot_loader.size()); 91 for (const auto &bl : p->boot_loader) { 92 std::unique_ptr<ObjectFile> obj; 93 obj.reset(createObjectFile(bl)); 94 95 fatal_if(!obj, "Could not read bootloader: %s\n", bl); 96 bootLoaders.emplace_back(std::move(obj)); 97 } 98 99 if (kernel) { 100 bootldr = getBootLoader(kernel); 101 } else if (!bootLoaders.empty()) { 102 // No kernel specified, default to the first boot loader 103 bootldr = bootLoaders[0].get(); 104 } 105 106 if (!bootLoaders.empty() && !bootldr) 107 fatal("Can't find a matching boot loader / kernel combination!"); 108 109 if (bootldr) { 110 bootldr->loadGlobalSymbols(debugSymbolTable); 111 112 warn_if(bootldr->entryPoint() != _resetAddr, 113 "Bootloader entry point %#x overriding reset address %#x", 114 bootldr->entryPoint(), _resetAddr); 115 const_cast<Addr&>(_resetAddr) = bootldr->entryPoint(); 116 117 if ((bootldr->getArch() == ObjectFile::Arm64) && !_highestELIs64) { 118 warn("Highest ARM exception-level set to AArch32 but bootloader " 119 "is for AArch64. Assuming you wanted these to match.\n"); 120 _highestELIs64 = true; 121 } else if ((bootldr->getArch() == ObjectFile::Arm) && _highestELIs64) { 122 warn("Highest ARM exception-level set to AArch64 but bootloader " 123 "is for AArch32. Assuming you wanted these to match.\n"); 124 _highestELIs64 = false; 125 } 126 } 127 128 debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk"); 129} 130 131void 132ArmSystem::initState() 133{ 134 // Moved from the constructor to here since it relies on the 135 // address map being resolved in the interconnect 136 137 // Call the initialisation of the super class 138 System::initState(); 139 140 const Params* p = params(); 141 142 if (bootldr) { 143 bool isGICv3System = dynamic_cast<Gicv3 *>(getGIC()) != nullptr; 144 bootldr->loadSections(physProxy); 145 146 inform("Using bootloader at address %#x\n", bootldr->entryPoint()); 147 148 // Put the address of the boot loader into r7 so we know 149 // where to branch to after the reset fault 150 // All other values needed by the boot loader to know what to do 151 if (!p->flags_addr) 152 fatal("flags_addr must be set with bootloader\n"); 153 154 if (!p->gic_cpu_addr && !isGICv3System) 155 fatal("gic_cpu_addr must be set with bootloader\n"); 156 157 for (int i = 0; i < threadContexts.size(); i++) { 158 if (!_highestELIs64) 159 threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) + 160 loadAddrOffset); 161 if (!isGICv3System) 162 threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); 163 threadContexts[i]->setIntReg(5, params()->flags_addr); 164 } 165 inform("Using kernel entry physical address at %#x\n", 166 (kernelEntry & loadAddrMask) + loadAddrOffset); 167 } else { 168 // Set the initial PC to be at start of the kernel code 169 if (!_highestELIs64) 170 threadContexts[0]->pcState((kernelEntry & loadAddrMask) + 171 loadAddrOffset); 172 } 173} 174 175ArmSystem* 176ArmSystem::getArmSystem(ThreadContext *tc) 177{ 178 ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr()); 179 assert(a_sys); 180 return a_sys; 181} 182 183bool 184ArmSystem::haveSecurity(ThreadContext *tc) 185{ 186 return FullSystem? getArmSystem(tc)->haveSecurity() : false; 187} 188 189 190ArmSystem::~ArmSystem() 191{ 192 if (debugPrintkEvent) 193 delete debugPrintkEvent; 194} 195 196ObjectFile * 197ArmSystem::getBootLoader(ObjectFile *const obj) 198{ 199 for (auto &bl : bootLoaders) { 200 if (bl->getArch() == obj->getArch()) 201 return bl.get(); 202 } 203 204 return nullptr; 205} 206 207bool 208ArmSystem::haveLPAE(ThreadContext *tc) 209{ 210 return FullSystem? getArmSystem(tc)->haveLPAE() : false; 211} 212 213bool 214ArmSystem::haveVirtualization(ThreadContext *tc) 215{ 216 return FullSystem? getArmSystem(tc)->haveVirtualization() : false; 217} 218 219bool 220ArmSystem::highestELIs64(ThreadContext *tc) 221{ 222 return FullSystem? getArmSystem(tc)->highestELIs64() : true; 223} 224 225ExceptionLevel 226ArmSystem::highestEL(ThreadContext *tc) 227{ 228 return FullSystem? getArmSystem(tc)->highestEL() : EL1; 229} 230 231bool 232ArmSystem::haveEL(ThreadContext *tc, ExceptionLevel el) 233{ 234 switch (el) { 235 case EL0: 236 case EL1: 237 return true; 238 case EL2: 239 return haveVirtualization(tc); 240 case EL3: 241 return haveSecurity(tc); 242 default: 243 warn("Unimplemented Exception Level\n"); 244 return false; 245 } 246} 247 248Addr 249ArmSystem::resetAddr(ThreadContext *tc) 250{ 251 return getArmSystem(tc)->resetAddr(); 252} 253 254uint8_t 255ArmSystem::physAddrRange(ThreadContext *tc) 256{ 257 return getArmSystem(tc)->physAddrRange(); 258} 259 260Addr 261ArmSystem::physAddrMask(ThreadContext *tc) 262{ 263 return getArmSystem(tc)->physAddrMask(); 264} 265 266bool 267ArmSystem::haveLargeAsid64(ThreadContext *tc) 268{ 269 return getArmSystem(tc)->haveLargeAsid64(); 270} 271 272bool 273ArmSystem::haveSemihosting(ThreadContext *tc) 274{ 275 return FullSystem && getArmSystem(tc)->haveSemihosting(); 276} 277 278uint64_t 279ArmSystem::callSemihosting64(ThreadContext *tc, 280 uint32_t op, uint64_t param) 281{ 282 ArmSystem *sys = getArmSystem(tc); 283 return sys->semihosting->call64(tc, op, param); 284} 285 286uint32_t 287ArmSystem::callSemihosting32(ThreadContext *tc, 288 uint32_t op, uint32_t param) 289{ 290 ArmSystem *sys = getArmSystem(tc); 291 return sys->semihosting->call32(tc, op, param); 292} 293 294ArmSystem * 295ArmSystemParams::create() 296{ 297 return new ArmSystem(this); 298} 299 300void 301GenericArmSystem::initState() 302{ 303 // Moved from the constructor to here since it relies on the 304 // address map being resolved in the interconnect 305 306 // Call the initialisation of the super class 307 ArmSystem::initState(); 308} 309 310GenericArmSystem * 311GenericArmSystemParams::create() 312{ 313 314 return new GenericArmSystem(this); 315} 316