stage2_mmu.hh revision 10379 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/request.hh"
46#include "params/ArmStage2MMU.hh"
47#include "sim/eventq.hh"
48
49namespace ArmISA {
50
51class Stage2MMU : public SimObject
52{
53  private:
54    TLB *_stage1Tlb;
55    /** The TLB that will cache the stage 2 look ups. */
56    TLB *_stage2Tlb;
57
58  public:
59    /** This translation class is used to trigger the data fetch once a timing
60        translation returns the translated physical address */
61    class Stage2Translation : public BaseTLB::Translation
62    {
63      private:
64        uint8_t   *data;
65        int       numBytes;
66        Request   req;
67        Event     *event;
68        Stage2MMU &parent;
69        Addr      oVAddr;
70
71      public:
72        Fault fault;
73
74        Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
75                          Addr _oVAddr);
76
77        void
78        markDelayed() {}
79
80        void
81        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
82               BaseTLB::Mode mode);
83
84        void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
85        {
86            numBytes = size;
87            req.setVirt(0, vaddr, size, flags, masterId, 0);
88        }
89
90        Fault translateTiming(ThreadContext *tc)
91        {
92            return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
93        }
94    };
95
96    typedef ArmStage2MMUParams Params;
97    Stage2MMU(const Params *p);
98
99    Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
100        uint8_t *data, int numBytes, Request::Flags flags, int masterId,
101        bool isFunctional);
102    Fault readDataTimed(ThreadContext *tc, Addr descAddr,
103        Stage2Translation *translation, int numBytes, Request::Flags flags,
104        int masterId);
105
106    TLB* stage1Tlb() const { return _stage1Tlb; }
107    TLB* stage2Tlb() const { return _stage2Tlb; }
108};
109
110
111
112} // namespace ArmISA
113
114#endif //__ARCH_ARM_STAGE2_MMU_HH__
115
116