stage2_mmu.cc revision 10379:c00f6d7e2681 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#include "arch/arm/faults.hh"
41#include "arch/arm/stage2_mmu.hh"
42#include "arch/arm/system.hh"
43#include "arch/arm/tlb.hh"
44#include "cpu/base.hh"
45#include "cpu/thread_context.hh"
46#include "debug/Checkpoint.hh"
47#include "debug/TLB.hh"
48#include "debug/TLBVerbose.hh"
49
50using namespace ArmISA;
51
52Stage2MMU::Stage2MMU(const Params *p)
53    : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb)
54{
55    stage1Tlb()->setMMU(this);
56    stage2Tlb()->setMMU(this);
57}
58
59Fault
60Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
61    uint8_t *data, int numBytes, Request::Flags flags, int masterId,
62    bool isFunctional)
63{
64    Fault fault;
65
66    // translate to physical address using the second stage MMU
67    Request req = Request();
68    req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
69    if (isFunctional) {
70        fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read);
71    } else {
72        fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read);
73    }
74
75    // Now do the access.
76    if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) {
77        Packet pkt = Packet(&req, MemCmd::ReadReq);
78        pkt.dataStatic(data);
79        if (isFunctional) {
80            stage1Tlb()->getWalkerPort().sendFunctional(&pkt);
81        } else {
82            stage1Tlb()->getWalkerPort().sendAtomic(&pkt);
83        }
84        assert(!pkt.isError());
85    }
86
87    // If there was a fault annotate it with the flag saying the foult occured
88    // while doing a translation for a stage 1 page table walk.
89    if (fault != NoFault) {
90        ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
91        armFault->annotate(ArmFault::S1PTW, true);
92        armFault->annotate(ArmFault::OVA, oVAddr);
93    }
94    return fault;
95}
96
97Fault
98Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
99    Stage2Translation *translation, int numBytes, Request::Flags flags,
100    int masterId)
101{
102    Fault fault;
103    // translate to physical address using the second stage MMU
104    translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId);
105    fault = translation->translateTiming(tc);
106    return fault;
107}
108
109Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
110        uint8_t *_data, Event *_event, Addr _oVAddr)
111    : data(_data), event(_event), parent(_parent), oVAddr(_oVAddr),
112    fault(NoFault)
113{
114}
115
116void
117Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
118                                     ThreadContext *tc, BaseTLB::Mode mode)
119{
120    fault = _fault;
121
122    // If there was a fault annotate it with the flag saying the foult occured
123    // while doing a translation for a stage 1 page table walk.
124    if (fault != NoFault) {
125        ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
126        armFault->annotate(ArmFault::S1PTW, true);
127        armFault->annotate(ArmFault::OVA, oVAddr);
128    }
129
130    if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
131        DmaPort& port = parent.stage1Tlb()->getWalkerPort();
132        port.dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
133                       event, data, tc->getCpuPtr()->clockPeriod(),
134                       req->getFlags());
135    } else {
136        // We can't do the DMA access as there's been a problem, so tell the
137        // event we're done
138        event->process();
139    }
140}
141
142ArmISA::Stage2MMU *
143ArmStage2MMUParams::create()
144{
145    return new ArmISA::Stage2MMU(this);
146}
147