stage2_lookup.hh revision 12429:beefb9f5f551 
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 *          Giacomo Gabrielli
39 */
40
41#ifndef __ARCH_ARM_STAGE2_LOOKUP_HH__
42#define __ARCH_ARM_STAGE2_LOOKUP_HH__
43
44#include <list>
45
46#include "arch/arm/system.hh"
47#include "arch/arm/table_walker.hh"
48#include "arch/arm/tlb.hh"
49#include "mem/request.hh"
50
51class ThreadContext;
52
53namespace ArmISA {
54class Translation;
55class TLB;
56
57
58class Stage2LookUp : public BaseTLB::Translation
59{
60  private:
61    TLB                     *stage1Tlb;
62    TLB               *stage2Tlb;
63    TlbEntry                stage1Te;
64    RequestPtr              s1Req;
65    TLB::Translation        *transState;
66    BaseTLB::Mode           mode;
67    bool                    timing;
68    bool                    functional;
69    TLB::ArmTranslationType tranType;
70    TlbEntry                *stage2Te;
71    Request                 req;
72    Fault                   fault;
73    bool                    complete;
74    bool                    selfDelete;
75
76  public:
77    Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, RequestPtr _req,
78        TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
79        bool _functional, TLB::ArmTranslationType _tranType) :
80        stage1Tlb(s1Tlb), stage2Tlb(s2Tlb), stage1Te(s1Te), s1Req(_req),
81        transState(_transState), mode(_mode), timing(_timing),
82        functional(_functional), tranType(_tranType), stage2Te(nullptr),
83        fault(NoFault), complete(false), selfDelete(false)
84    {
85        req.setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
86                    s1Req->getFlags(), s1Req->masterId(), 0);
87    }
88
89    Fault getTe(ThreadContext *tc, TlbEntry *destTe);
90
91    void mergeTe(RequestPtr req, BaseTLB::Mode mode);
92
93    void setSelfDelete() { selfDelete = true; }
94
95    bool isComplete() const { return complete; }
96
97    void markDelayed() {}
98
99    void finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
100                BaseTLB::Mode mode);
101};
102
103
104} // namespace ArmISA
105
106#endif //__ARCH_ARM_STAGE2_LOOKUP_HH__
107
108