remote_gdb.cc revision 8782:10c9297e14d5
12SN/A/* 21762SN/A * Copyright (c) 2010 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3775SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392439SN/A * 402439SN/A * Authors: Nathan Binkert 41603SN/A * William Wang 422986Sgblack@eecs.umich.edu */ 43603SN/A 444762Snate@binkert.org/* 452520SN/A * Copyright (c) 1990, 1993 The Regents of the University of California 464762Snate@binkert.org * All rights reserved 472378SN/A * 486658Snate@binkert.org * This software was developed by the Computer Systems Engineering group 492378SN/A * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 50722SN/A * contributed to Berkeley. 512521SN/A * 522378SN/A * All advertising materials mentioning features or use of this software 53312SN/A * must display the following acknowledgement: 541634SN/A * This product includes software developed by the University of 552680Sktlim@umich.edu * California, Lawrence Berkeley Laboratories. 561634SN/A * 572521SN/A * Redistribution and use in source and binary forms, with or without 582378SN/A * modification, are permitted provided that the following conditions 592378SN/A * are met: 60803SN/A * 1. Redistributions of source code must retain the above copyright 613960Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer. 622378SN/A * 2. Redistributions in binary form must reproduce the above copyright 636658Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 642SN/A * documentation and/or other materials provided with the distribution. 652SN/A * 3. All advertising materials mentioning features or use of this software 662SN/A * must display the following acknowledgement: 67603SN/A * This product includes software developed by the University of 682901Ssaidi@eecs.umich.edu * California, Berkeley and its contributors. 692902Ssaidi@eecs.umich.edu * 4. Neither the name of the University nor the names of its contributors 702902Ssaidi@eecs.umich.edu * may be used to endorse or promote products derived from this software 714762Snate@binkert.org * without specific prior written permission. 724762Snate@binkert.org * 734762Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 744762Snate@binkert.org * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 754762Snate@binkert.org * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 764762Snate@binkert.org * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 772901Ssaidi@eecs.umich.edu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 782901Ssaidi@eecs.umich.edu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 792901Ssaidi@eecs.umich.edu * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 802901Ssaidi@eecs.umich.edu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 812901Ssaidi@eecs.umich.edu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 824762Snate@binkert.org * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 832901Ssaidi@eecs.umich.edu * SUCH DAMAGE. 842521SN/A * 852SN/A * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94 862SN/A */ 872680Sktlim@umich.edu 885714Shsul@eecs.umich.edu/*- 891806SN/A * Copyright (c) 2001 The NetBSD Foundation, Inc. 906221Snate@binkert.org * All rights reserved. 915713Shsul@eecs.umich.edu * 925713Shsul@eecs.umich.edu * This code is derived from software contributed to The NetBSD Foundation 935713Shsul@eecs.umich.edu * by Jason R. Thorpe. 945713Shsul@eecs.umich.edu * 955714Shsul@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 961806SN/A * modification, are permitted provided that the following conditions 976227Snate@binkert.org * are met: 985714Shsul@eecs.umich.edu * 1. Redistributions of source code must retain the above copyright 991806SN/A * notice, this list of conditions and the following disclaimer. 100180SN/A * 2. Redistributions in binary form must reproduce the above copyright 1016029Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 1026029Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution. 1036029Ssteve.reinhardt@amd.com * 3. All advertising materials mentioning features or use of this software 1046029Ssteve.reinhardt@amd.com * must display the following acknowledgement: 1052378SN/A * This product includes software developed by the NetBSD 1062378SN/A * Foundation, Inc. and its contributors. 1072378SN/A * 4. Neither the name of The NetBSD Foundation nor the names of its 1082378SN/A * contributors may be used to endorse or promote products derived 1092520SN/A * from this software without specific prior written permission. 1102520SN/A * 1112520SN/A * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 1122521SN/A * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 1132520SN/A * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 1141885SN/A * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 1151070SN/A * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 116954SN/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 1171070SN/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 1181070SN/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 1191070SN/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 1201070SN/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 1211070SN/A * POSSIBILITY OF SUCH DAMAGE. 1221070SN/A */ 1231070SN/A 1241070SN/A/* 1251070SN/A * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $ 1261070SN/A * 1271070SN/A * Taken from NetBSD 1281070SN/A * 1297580SAli.Saidi@arm.com * "Stub" to allow remote cpu to debug over a serial line using gdb. 1307580SAli.Saidi@arm.com */ 1317580SAli.Saidi@arm.com 1327580SAli.Saidi@arm.com#include <sys/signal.h> 1337580SAli.Saidi@arm.com#include <unistd.h> 1347580SAli.Saidi@arm.com 1357580SAli.Saidi@arm.com#include <string> 1367580SAli.Saidi@arm.com 1372378SN/A#include "arch/arm/pagetable.hh" 1382378SN/A#include "arch/arm/registers.hh" 1392378SN/A#include "arch/arm/remote_gdb.hh" 1402378SN/A#include "arch/arm/utility.hh" 1414997Sgblack@eecs.umich.edu#include "arch/arm/vtophys.hh" 1424997Sgblack@eecs.umich.edu#include "base/intmath.hh" 1434997Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 1444997Sgblack@eecs.umich.edu#include "base/socket.hh" 1454997Sgblack@eecs.umich.edu#include "base/trace.hh" 1464997Sgblack@eecs.umich.edu#include "cpu/decode.hh" 1474997Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 1484997Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 1494997Sgblack@eecs.umich.edu#include "cpu/thread_state.hh" 1505795Ssaidi@eecs.umich.edu#include "debug/GDBAcc.hh" 1515795Ssaidi@eecs.umich.edu#include "debug/GDBMisc.hh" 1525795Ssaidi@eecs.umich.edu#include "mem/page_table.hh" 1535795Ssaidi@eecs.umich.edu#include "mem/physical.hh" 1545795Ssaidi@eecs.umich.edu#include "mem/port.hh" 1555795Ssaidi@eecs.umich.edu#include "sim/full_system.hh" 1562378SN/A#include "sim/system.hh" 1572378SN/A 1582378SN/Ausing namespace std; 1591885SN/Ausing namespace ArmISA; 1604762Snate@binkert.org 1612901Ssaidi@eecs.umich.eduRemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) 1622424SN/A : BaseRemoteGDB(_system, tc, NUMREGS) 1631885SN/A{ 1641885SN/A} 1651885SN/A 1661885SN/A/* 1671885SN/A * Determine if the mapping at va..(va+len) is valid. 1682158SN/A */ 1691885SN/Abool 1701885SN/ARemoteGDB::acc(Addr va, size_t len) 1711885SN/A{ 1721885SN/A if (FullSystem) { 1731885SN/A Addr last_va; 1741885SN/A va = truncPage(va); 1752989Ssaidi@eecs.umich.edu last_va = roundPage(va + len); 1761885SN/A 1771913SN/A do { 1781885SN/A if (virtvalid(context, va)) { 1791885SN/A return true; 1801885SN/A } 1811885SN/A va += PageBytes; 1821885SN/A } while (va < last_va); 1831885SN/A 1841885SN/A DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); 1851885SN/A return true; 1861885SN/A } else { 1871885SN/A TlbEntry entry; 1881885SN/A //Check to make sure the first byte is mapped into the processes address 1892989Ssaidi@eecs.umich.edu //space. 1901885SN/A if (context->getProcessPtr()->pTable->lookup(va, entry)) 1911885SN/A return true; 1921885SN/A return false; 1931885SN/A } 1942378SN/A} 19577SN/A 1966658Snate@binkert.org/* 1971070SN/A * Translate the kernel debugger register format into the GDB register 1983960Sgblack@eecs.umich.edu * format. 1991070SN/A */ 2001070SN/Avoid 2014762Snate@binkert.orgRemoteGDB::getregs() 2021070SN/A{ 2032158SN/A DPRINTF(GDBAcc, "getregs in remotegdb \n"); 2042158SN/A 2051070SN/A memset(gdbregs.regs, 0, gdbregs.bytes()); 2062158SN/A 2071070SN/A // R0-R15 supervisor mode 2082SN/A // arm registers are 32 bits wide, gdb registers are 64 bits wide 2092SN/A // two arm registers are packed into one gdb register (little endian) 2101129SN/A gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 | 2111129SN/A context->readIntReg(INTREG_R0); 2122158SN/A gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 | 2132158SN/A context->readIntReg(INTREG_R2); 2141070SN/A gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 | 2152378SN/A context->readIntReg(INTREG_R4); 2162378SN/A gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 | 2171070SN/A context->readIntReg(INTREG_R6); 2181070SN/A gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 | 2191070SN/A context->readIntReg(INTREG_R8); 2201070SN/A gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32| 2211070SN/A context->readIntReg(INTREG_R10); 2221070SN/A gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 | 2231070SN/A context->readIntReg(INTREG_R12); 2241070SN/A gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 | 2251070SN/A context->readIntReg(INTREG_LR); 2261070SN/A 2271070SN/A // CPSR 2281070SN/A gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR); 2291070SN/A 2301070SN/A // vfpv3/neon floating point registers (32 double or 64 float) 2311070SN/A 2321070SN/A gdbregs.regs[REG_F0] = 2331070SN/A static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 | 2341070SN/A gdbregs.regs[REG_CPSR]; 2352378SN/A 2362378SN/A for (int i = 1; i < (NumFloatArchRegs>>1); ++i) { 2372378SN/A gdbregs.regs[i + REG_F0] = 2382378SN/A static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 | 2392378SN/A context->readFloatRegBits(2*i-1); 2402378SN/A } 2415718Shsul@eecs.umich.edu 2425713Shsul@eecs.umich.edu // FPSCR 2431070SN/A gdbregs.regs[REG_FPSCR] = 2441070SN/A static_cast<uint64_t>(context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 | 2451070SN/A context->readFloatRegBits(NumFloatArchRegs - 1); 2462SN/A} 24777SN/A 2482SN/A/* 2492SN/A * Translate the GDB register format into the kernel debugger register 2502SN/A * format. 2512SN/A */ 2522SN/Avoid 2532SN/ARemoteGDB::setregs() 2542SN/A{ 2552SN/A 2562SN/A DPRINTF(GDBAcc, "setregs in remotegdb \n"); 2572SN/A 2582158SN/A // R0-R15 supervisor mode 2592158SN/A // arm registers are 32 bits wide, gdb registers are 64 bits wide 2602SN/A // two arm registers are packed into one gdb register (little endian) 2612SN/A context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0)); 2622SN/A context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32)); 263 context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0)); 264 context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32)); 265 context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0)); 266 context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32)); 267 context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0)); 268 context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32)); 269 context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0)); 270 context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32)); 271 context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0)); 272 context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32)); 273 context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0)); 274 context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32)); 275 context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0)); 276 context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32)); 277 278 //CPSR 279 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]); 280 281 //vfpv3/neon floating point registers (32 double or 64 float) 282 context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32); 283 284 for (int i = 1; i < NumFloatArchRegs; ++i) { 285 if(i%2){ 286 int j = (i+1)/2; 287 context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0)); 288 } 289 else{ 290 int j = i/2; 291 context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32); 292 } 293 } 294 295 //FPSCR 296 context->setMiscRegNoEffect(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32); 297} 298 299void 300RemoteGDB::clearSingleStep() 301{ 302 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", 303 takenBkpt, notTakenBkpt); 304 305 if (takenBkpt != 0) 306 clearTempBreakpoint(takenBkpt); 307 308 if (notTakenBkpt != 0) 309 clearTempBreakpoint(notTakenBkpt); 310} 311 312void 313RemoteGDB::setSingleStep() 314{ 315 PCState pc = context->pcState(); 316 PCState bpc; 317 bool set_bt = false; 318 319 // User was stopped at pc, e.g. the instruction at pc was not 320 // executed. 321 MachInst inst = read<MachInst>(pc.pc()); 322 StaticInstPtr si = context->getDecoderPtr()->decode(inst, pc.pc()); 323 if (si->hasBranchTarget(pc, context, bpc)) { 324 // Don't bother setting a breakpoint on the taken branch if it 325 // is the same as the next pc 326 if (bpc.pc() != pc.npc()) 327 set_bt = true; 328 } 329 330 DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n", 331 takenBkpt, notTakenBkpt); 332 333 setTempBreakpoint(notTakenBkpt = pc.npc()); 334 335 if (set_bt) 336 setTempBreakpoint(takenBkpt = bpc.pc()); 337} 338 339// Write bytes to kernel address space for debugger. 340bool 341RemoteGDB::write(Addr vaddr, size_t size, const char *data) 342{ 343 return BaseRemoteGDB::write(vaddr, size, data); 344} 345 346