registers.hh revision 12109
16019SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2011, 2014, 2016 ARM Limited 37649Sminkyu.jeong@arm.com * All rights reserved 47649Sminkyu.jeong@arm.com * 57649Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67649Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77649Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87649Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97649Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107649Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117649Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127649Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137649Sminkyu.jeong@arm.com * 146019SN/A * Copyright (c) 2007-2008 The Florida State University 156019SN/A * All rights reserved. 166019SN/A * 176019SN/A * Redistribution and use in source and binary forms, with or without 186019SN/A * modification, are permitted provided that the following conditions are 196019SN/A * met: redistributions of source code must retain the above copyright 206019SN/A * notice, this list of conditions and the following disclaimer; 216019SN/A * redistributions in binary form must reproduce the above copyright 226019SN/A * notice, this list of conditions and the following disclaimer in the 236019SN/A * documentation and/or other materials provided with the distribution; 246019SN/A * neither the name of the copyright holders nor the names of its 256019SN/A * contributors may be used to endorse or promote products derived from 266019SN/A * this software without specific prior written permission. 276019SN/A * 286019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019SN/A * 406019SN/A * Authors: Stephen Hines 416019SN/A */ 426019SN/A 436329Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_REGISTERS_HH__ 446329Sgblack@eecs.umich.edu#define __ARCH_ARM_REGISTERS_HH__ 456019SN/A 4612109SRekai.GonzalezAlberquilla@arm.com#include "arch/arm/ccregs.hh" 478961Sgblack@eecs.umich.edu#include "arch/arm/generated/max_inst_regs.hh" 488229Snate@binkert.org#include "arch/arm/intregs.hh" 496329Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5012109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh" 516328SN/A 526329Sgblack@eecs.umich.edunamespace ArmISA { 536328SN/A 547848SAli.Saidi@ARM.com 557848SAli.Saidi@ARM.com// For a predicated instruction, we need all the 567848SAli.Saidi@ARM.com// destination registers to also be sources 577848SAli.Saidi@ARM.comconst int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 587848SAli.Saidi@ARM.com ArmISAInst::MaxInstSrcRegs; 596329Sgblack@eecs.umich.eduusing ArmISAInst::MaxInstDestRegs; 609046SAli.Saidi@ARM.comusing ArmISAInst::MaxMiscDestRegs; 616328SN/A 626329Sgblack@eecs.umich.edutypedef uint64_t IntReg; 636328SN/A 646329Sgblack@eecs.umich.edu// floating point register file entry type 656329Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits; 666329Sgblack@eecs.umich.edutypedef float FloatReg; 676328SN/A 6812109SRekai.GonzalezAlberquilla@arm.com// Number of VecElem per Vector Register, computed based on the vector length 6912109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecElemPerVecReg = 4; 7012109SRekai.GonzalezAlberquilla@arm.comusing VecElem = uint32_t; 7112109SRekai.GonzalezAlberquilla@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 7212109SRekai.GonzalezAlberquilla@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 7312109SRekai.GonzalezAlberquilla@arm.comusing VecRegContainer = VecReg::Container; 7412109SRekai.GonzalezAlberquilla@arm.com 756329Sgblack@eecs.umich.edu// cop-0/cop-1 system control register 766329Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 776328SN/A 7810338SCurtis.Dunham@arm.com// condition code register; must be at least 32 bits for FpCondCodes 7910338SCurtis.Dunham@arm.comtypedef uint64_t CCReg; 809920Syasuko.eckert@amd.com 816329Sgblack@eecs.umich.edu// Constants Related to the number of registers 826717Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_ARCH_INTREGS; 837177Sgblack@eecs.umich.edu// The number of single precision floating point registers 8410037SARM gem5 Developersconst int NumFloatV7ArchRegs = 64; 8510037SARM gem5 Developersconst int NumFloatV8ArchRegs = 128; 8610037SARM gem5 Developersconst int NumFloatSpecialRegs = 32; 8712109SRekai.GonzalezAlberquilla@arm.comconst int NumVecV7ArchRegs = 64; 8812109SRekai.GonzalezAlberquilla@arm.comconst int NumVecV8ArchRegs = 32; 8912109SRekai.GonzalezAlberquilla@arm.comconst int NumVecSpecialRegs = 8; 906328SN/A 916717Sgblack@eecs.umich.educonst int NumIntRegs = NUM_INTREGS; 9210037SARM gem5 Developersconst int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 9312109SRekai.GonzalezAlberquilla@arm.comconst int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; 9410338SCurtis.Dunham@arm.comconst int NumCCRegs = NUM_CCREGS; 956329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS; 966328SN/A 9710338SCurtis.Dunham@arm.com#define ISA_HAS_CC_REGS 9810338SCurtis.Dunham@arm.com 9912109SRekai.GonzalezAlberquilla@arm.comconst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumMiscRegs; 1006328SN/A 1016329Sgblack@eecs.umich.edu// semantically meaningful register indices 1026329Sgblack@eecs.umich.educonst int ReturnValueReg = 0; 1036329Sgblack@eecs.umich.educonst int ReturnValueReg1 = 1; 1046329Sgblack@eecs.umich.educonst int ReturnValueReg2 = 2; 1057650SAli.Saidi@ARM.comconst int NumArgumentRegs = 4; 10610037SARM gem5 Developersconst int NumArgumentRegs64 = 8; 1076329Sgblack@eecs.umich.educonst int ArgumentReg0 = 0; 1086329Sgblack@eecs.umich.educonst int ArgumentReg1 = 1; 1096329Sgblack@eecs.umich.educonst int ArgumentReg2 = 2; 1106329Sgblack@eecs.umich.educonst int ArgumentReg3 = 3; 1116329Sgblack@eecs.umich.educonst int FramePointerReg = 11; 1126717Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_SP; 1136717Sgblack@eecs.umich.educonst int ReturnAddressReg = INTREG_LR; 1146717Sgblack@eecs.umich.educonst int PCReg = INTREG_PC; 1156328SN/A 1166717Sgblack@eecs.umich.educonst int ZeroReg = INTREG_ZERO; 1176328SN/A 1186329Sgblack@eecs.umich.educonst int SyscallNumReg = ReturnValueReg; 1196329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = ReturnValueReg; 1206329Sgblack@eecs.umich.educonst int SyscallSuccessReg = ReturnValueReg; 1216328SN/A 1226329Sgblack@eecs.umich.edutypedef union { 1236329Sgblack@eecs.umich.edu IntReg intreg; 1246329Sgblack@eecs.umich.edu FloatReg fpreg; 12510338SCurtis.Dunham@arm.com CCReg ccreg; 1266329Sgblack@eecs.umich.edu MiscReg ctrlreg; 1276329Sgblack@eecs.umich.edu} AnyReg; 1286329Sgblack@eecs.umich.edu 1296328SN/A} // namespace ArmISA 1306019SN/A 1316019SN/A#endif 132