process.hh revision 13121:4741df518ab8 
1/*
2* Copyright (c) 2012, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARM_PROCESS_HH__
44#define __ARM_PROCESS_HH__
45
46#include <string>
47#include <vector>
48
49#include "arch/arm/intregs.hh"
50#include "base/loader/object_file.hh"
51#include "mem/page_table.hh"
52#include "sim/process.hh"
53
54class ObjectFile;
55
56class ArmProcess : public Process
57{
58  protected:
59    ObjectFile::Arch arch;
60    ArmProcess(ProcessParams * params, ObjectFile *objFile,
61               ObjectFile::Arch _arch);
62    template<class IntType>
63    void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
64
65    template<class IntType>
66    IntType armHwcap() const
67    {
68        return static_cast<IntType>(armHwcapImpl());
69    }
70
71    /**
72     * AT_HWCAP is 32-bit wide on AArch64 as well so we can
73     * safely return an uint32_t */
74    virtual uint32_t armHwcapImpl() const = 0;
75};
76
77class ArmProcess32 : public ArmProcess
78{
79  protected:
80    ArmProcess32(ProcessParams * params, ObjectFile *objFile,
81                 ObjectFile::Arch _arch);
82
83    void initState();
84
85    /** AArch32 AT_HWCAP */
86    uint32_t armHwcapImpl() const override;
87
88  public:
89
90    ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
91    ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
92    void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
93    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
94};
95
96class ArmProcess64 : public ArmProcess
97{
98  protected:
99    ArmProcess64(ProcessParams * params, ObjectFile *objFile,
100                 ObjectFile::Arch _arch);
101
102    void initState();
103
104    /** AArch64 AT_HWCAP */
105    uint32_t armHwcapImpl() const override;
106
107  public:
108
109    ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
110    ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
111    void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
112    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
113};
114
115#endif // __ARM_PROCESS_HH__
116
117